SU783792A1 - Device for normalizing binary numbers - Google Patents

Description

one

The invention relates to automation and computing and can be used to create high-performance computing systems.

A known shift logic circuit 1, consisting of several logic layer circuits, each of which contains logic-elements of type I, or 1.

The number t of levels into which the shift logic circuit is divided is an integer and must satisfy the relation .2 (N + 1 is the size of the normalized number).

Each of the levels will hold down the left-shift logical block, by which the binary number is shifted to the left by a certain number of bits.

A shifting device is known that allows the input information to be shifted in parallel to the required number of bits per cycle and contains a matrix of long-term memory types (flip-flops) and AND and OR 2 logic circuits,

The closest to the invention is a device for normalizing numbers, containing several series-connected logic levels, each of which contains a group-to-zero content analyzer, connected by inputs to the outputs of a gate circuit of the previous level, and outputs to inputs of an offset-value decoder; connected to the inputs of the encoder and gate circuit of a given level pj,

ten

K-bit N, which determines the number of zeros before the old non-zero bit of the normalized number, is divided into groups containing the number of bits K, K 2

K, K ,, ..., Kfn (K + K2 + K3 + K4l + ...).

The valve circuit of each logic level shifts the number to the left by an amount determined by the weighting coefficients and values of the bits of the corresponding group.

As the number of the normalized number increases, the number of logical levels increases, which leads to an increase (in hardware costs and in the time required for the normalization operation.

A disadvantage of this device is the relatively high hardware costs and the dependence of the execution time of the normalization operation on the size of the normalized number. The purpose of the invention is to simplify the device. It is achieved by the fact that the device for normalizing binary numbers includes switches and decoders, the information inputs of the first switch are connected to the first input of the device, the information inputs of the second switch are connected to the outputs of the first switch, contains an order register, two encoders, an adder, the first group of inputs which is connected to the first and second device taps, the transfer output of each tetrad of the adder (where n is the width of the normalized numbers) is connected to the corresponding input of the first an encoder, the outputs of which are connected to the inputs of the first encoder, connected to the outputs of the first group of inputs of the register of the order and to the control inputs of the first switch, the outputs of the three most significant bits of which are connected to the inputs of the second decoder, connected to the inputs of the second encoder, outputs of which connected to the second group of inputs of the register of the order and with the controlling inputs of the second switch. The block diagram of the device shown in the drawing. The device contains an adder 1, the first and second decoders 2 and 3, the first and second encoders 4 and 5, the first and second switches 6 and 7, the register is 8 times. The normalized number A is divided into N tetrads with a size n, starting with the most significant bit. In the case of an incomplete tetrad tetrade, it is supplemented with zeros. The number A is the first term that arrives at the first group of inputs of the adder 1. The upper digits of the normalized number arrive at the lower digits (4 N) - the digit of the adder, and the lower digits of the normalized number to the old digit of the adder. The second term is a binary number consisting of (4N) units — the 1 4N bits of the adder 1 entering the second group of inputs of the adder are also divided into N tetrads, starting with the higher order. Thus, the transfer between tetrads, which occurs during compaction, spreads in the direction from the lower tetrads of the adder to the highest relative to the tetrads of the normalized number — from the older to the younger. When entering the adder 1 of the p-bit normalized number A and (4N) - units of the second term, the output of the adder forms an N-digit number, the bits of which are transfers between the adders' tetrads. The first transfer is formed in the adder tetrad, which receives the highest nonzero bit of the normalized number. In this case, in all subsequent higher tetrads of the adder, transfers are formed independently of the zeros in the corresponding tetrads of the normalized number. The zeroes in M are the digits of the number at the output of adder 1 correspond to the tetrads of the normalized number, consisting of all zeros and located before the first significant tetrad of the normalized number. The first decoder 2, in accordance with the digit input from its adder 1, generates a sampling signal from the first 1-flipper, where the numbers of the tetrads of the normalized number are written, starting from zero. At the output of the first encoder 4, in accordance with the H-bit code, the number of the first significant tetrad of the normalized number is generated. The outputs of the first port 4 are connected to the first group of 8 order register inputs and the control inputs of the first switch b. The number of the first significant tetrad enters the control inputs of the first switch b, providing a shift of the first KOivttiyTaTopa arriving at the information inputs of the normalized number by 4 K bits to the left, where K is the number of the first significant tetrad of the normalized number. At the same time, K is written in m - 2 most significant bits of a t-bit register of 8 orders (a t-bit number determines the number of zeros before the most significant non-zero bit of the normalized number A). Writing the number K in m 2 most significant bits of the register of order 8 corresponds to writing the value of the shift to the left by 4 K, which is in the first switch 6. Clashed to 4 K to the left and normalized number A goes to the inputs of the second commutator 7. Max -1 is the maximum number of zeros before the highest nonzero bit of the shifted. Minimum number A is three. The upper three bits of the first switch 6 are connected to the inputs of the second decoder 3, the outputs of which are connected to the inputs of the second encoder 5. The second decoder 3 generates sampling signals from the second encoder 5 of the number of the higher nonzero bit of the shifted number A according to the form flL-CH ; la, daz-, Ajc a; la2la -,

In the second encoder 5, the numbers of the upper four bits of the number A are written, starting with zero. From the outputs of the second encoder 5, the number of the higher nonzero bit K (a two-bit digit number) is fed to the control inputs of the second switch 7, providing a shift of the number A to the left by K, and therefore the final normalization of the number A, and the second group of inputs of the register 8 dca. The two-digit number K is written B lower two bits of the t-bit register of 8 orders, in which after that the order of the normalized number A j will be formed.

As the width of the initial normalized number A increases, it increases by the corresponding number of bits. The length of all (except for the second decoder 3) device nodes for normalizing binary numbers.

The increase in hardware costs associated with an increase in the size of the initial normalized number in the proposed device is much less than in the prototype. The duration of the normalization operation is constant, does not depend on the size of the normalized number, and is determined by the formula of the form.

The normalization time. + Et, where t4.- is the summation time in the adder;

t «- the average delay time in the nodes of the device.

As an example, consider a device for the normalization of a 40-bit binary number, using 155 series chips.

As shown by calculations, when implementing a device, the savings in hardware costs (in the number of chips used), compared with the device selected as a prototype, reaches 30% ().

In the case of the normalization of the p-bit with the subsequent use

In the older bits of the mantissa, the normalized number (E-in) savings in hardware costs of the proposed device as compared with the prototype become BETTER more significant (for example, with and With 12,).

Claims (3)

1. Japanese Patent 48-23866, 0 cl. G 06 F 7/54, 1973. 2. The patent of Great Britain No. 1323825, class, G 06 F 7/00, 1973. 3. USSR author's certificate No. 397908, cl. G 06. F 7/38 ,. 1972 (prototype).