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Code No: R22023

R10
II B.Tech II Semester, Regular Examinations, April 2012 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, BME, EIE, ECC)

SET - 1

Time: 3 hours Answer any FIVE Questions All Questions carry Equal Marks ~~~~~~~~~~~~~~~~~~~~~~ 1.

Max. Marks: 75

a) Assume an arbitrary number system having a radix of 5 and 0, 1, 2, L and M as its independent digits. Determine: i) The decimal equivalent of (2LM.L1) ii) The octal equivalent of (21L.M2) iii) The hexagonal equivalent of (LM1.L2)

iv) The total number of possible four-digit combinations in this arbitrary number system. b) What is an excess-3 BCD code? Which short coming of the 8421 BCD code is overcome in the excess-3 BCD code? Illustrate with the help of an example.

2.

a) i) Simplify F ( A, B, C , D, E ) = ABC D + ABCD + ABC D + ABCDE + ABC D E + ABC DE ii) Prove that AB + C + D [D + (E + F )G ] = D (AB + C ) + D G (E + F ) b) With the help of the generalized form of the Hamming code, explain how the number of parity bits required to transmit a given number of data bits

3.

a) Write a simplified max-term Boolean expression for 0, 4, 5, 6, 7, 10, 14 using the Karnaugh mapping method.

b) Minimize the following function using the Quine-McCluskey method. Y = (1, 2, 5, 8, 9, 10, 12, 13, 16, 18, 24, 25, 26, 28, 29, 31) (6M+9M)

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(8M+7M)

(8M+7M)

4.

a) Discuss the functional principle of 4-bit ripple carry adder what is its major disadvantage? b) Draw the logic diagram of a three-digit Excess-3 adder and briefly describe its functional principle? (8M+7M)

5.

a) Design a two-level positive logic decimal-to-BCD priority encoder for decimal inputs from 0 to 4. b) Implement the following logic function using MUX with three select inputs? (8M+7M)

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Code No: R22023

R10

SET - 1

6.

a) Obtain the programming table for three-digit binary to gray code conversion using PLA b) How does a programmable logic device differ from a fixed logic device? What are the primary advantages of using programmable logic devices? (8M+7M)

7.

a) Design a synchronous counter that counts as 000, 010, 101, 110, 000, 010 Ensure that the un used states of 001, 011, 100 and 111 go to 000 on the next clock pulse. Use J-K flip-flops. b) Obtain conversion from D flip-flop to J-K flip-flop (9M+6M)

8.

Derive a circuit that realizes the FSM defined by the state assigned table below using JK flipflops PS A B C D E NS, Z X=0 X=1 B,0 E,0 E,0 D,0 D,1 A,0 C,1 E,0 B,0 D,0 (15M)

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Code No: R22023

R10
II B.Tech II Semester, Regular Examinations, April 2012 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, BME, EIE, ECC)

SET - 2

Time: 3 hours Answer any FIVE Questions All Questions carry Equal Marks ~~~~~~~~~~~~~~~~~~~~~~ 1.

Max. Marks: 75

a) Perform the following operations using r-1s complement arithmetic: i) (+43)10 (53)10. ii) (3F85)16 (1E73)16 b) Prove that16-bit 2s complement arithmetic cannot be used to add +18150 and +14618, while it can be used to add 18150 and 14618. (8M+7M) a) What do you understand by canonical and expanded forms of Boolean expressions? Illustrate with examples. b) What is the Hamming distance? Discuss with the help of examples, what is the role of the Hamming distance in deciding the error detection and correction capability of a code meant for the purpose? (8M+7M) a) i) Simplify the Boolean function given by f ( X , Y , Z ) = X .Z + X .Z for the dont care condition expressed X .Y + X .Y .Z + X .Y .Z as ii) Simplify the Boolean function given by f ( A, B, C ) = ( A + B + C ) (A + B + C ) ( A + B + C ) for the dont care condition expressed as

2.

3.

(A + B )(A + B + C )

b) Minimizing a given Boolean expression using the QuineMcCluskey tabular method yields the following prime implicants: 00, 11, 110 and 000. Draw the corresponding Karnaugh map. (9M+6M) 4. a) How can a 4-bit parallel adder (ripple carry) be converted to a parallel subtractor using XOR gates. (Hint: use two's complement subtraction.) b) Draw the logic diagram of a three-digit BCD adder and briefly describe its functional principle. (6M+9M) a) How could a 1-of-4 multiplexer plus one other gate be used for the implementation of full adder? b) Design a combinational circuit that converts a decimal digit from 2,4,2,1 code to 8, 4,-2,1code. (6M+9M)

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Code No: R22023

R10

SET - 2

6.

a) Obtain the programming table for the SUM output of the full adder to implement with PLA b) What do you understand by the following as regards programmable logic devices? i) Combinational and registered outputs; ii) Configurable output logic cell; iii) reprogrammable PLD; (4M+11M)

7.

a) Obtain the count sequence of i) a MOD-10 Ring counter ii) a MOD-10 Johnson counter Determine the number of flip-flops required to construct the above counters. b) Draw and explain the operation of universal shift register a) Convert the following Mealy machine into a corresponding Moore machine? PS NS, Z X=0 X=1 A C,0 B,0 B A,1 D,0 C B,1 A,1 D D,1 C,0 b) Design the circuit for the above table?

8.

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(8M+7M)

(8M+7M)

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Code No: R22023

R10

SET - 3

Time: 3 hours

II B.Tech II Semester, Regular Examinations, April 2012 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, BME, EIE, ECC) Max. Marks: 75 Answer any FIVE Questions All Questions carry Equal Marks ~~~~~~~~~~~~~~~~~~~~~~

1. a) Perform the following operations using 2s complement arithmetic: i) (+43)10 (53)10. ii) (3E91)16 (1F93)16 b) Represent the unsigned decimal numbers 351 and 986 in BCD, and then show the steps necessary to form their sum. (8M+7M)

2. a) It is proposed to construct an eight-input NAND gate using only two-input AND gates and two-input NAND gates. Draw the logic arrangement that uses the minimum number of logic gates.

b) What is a parity bit? Define even and odd parity. What is the limitation of the parity code when it comes to detection and correction of bit errors?

3. a) Use Karnaugh maps to show that AC + A C and A C + AC are factors of A BC D + AB C D and find a suitable third and final factor.

b) Using the QuineMcCluskey tabular method, find the minimum sum of products for (1, 2, 3, 9, 13, 14 ) + (0,7, 10, 15)

4. a) Draw the truth table of a full subtractor circuit. Write a min-term Boolean expression for DIFFERENCE and BORROW outputs in terms of minuend variable, subtrahend variable and BORROW-IN. Minimize the expressions and implement the min hardware. b) Briefly describe the concept of look-ahead carry generation with respect to its use in adder circuits. (8M+7M)

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(8M+7M)

(8M+7M)

5. a) What is a de-multiplexer and how does it differ from a decoder? Can a decoder be used as a de-multiplexer? b) Implement the following logic function using MUX with three select inputs? F (a, b, c, d ) = a + bcd + ad + c 1 of 2 (8M+7M)

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Code No: R22023

R10

SET - 3

6. a) Distinguish between a programmable logic array (PLA) device and a programmable array logic (PAL) device in terms of architecture and capability to implement Boolean functions. b) Realize the following switching functions with PROM F1 (A,B,C,D) = m(0,1,3,4,5,6,7,12,13) F1 (A,B,C,D) = m(5,6,7,10,11,13,14,15) (8M+7M)

7. a) Draw the truth table and briefly describe its operation of the following types of flip-flop: i) A positive edge-triggered J-K flip-flop with active HIGH J and K inputs and active LOW PRESET and CLEAR inputs;

ii) A negative edge-triggered J-K flip-flop with active LOW J and K inputs and active LOW PRESET and CLEAR inputs.

b) Enumerate the differences between transition table and state table?

8. a) Explain the capabilities and limitations of finite state machines b) Convert the following Mealy machine into a corresponding Moore machine.

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NS, Z X=0 X=1 B,0 E,0 E,0 D,0 D,1 A,0 C,1 E,0 B,0 D,0

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(9M+6M)

(8M+7M)

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Code No: R22023

R10

SET - 4

Time: 3 hours

II B.Tech II Semester, Regular Examinations, April 2012 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, BME, EIE, ECC) Max. Marks: 75 Answer any FIVE Questions All Questions carry Equal Marks ~~~~~~~~~~~~~~~~~~~~~~

1.

a) Solve i) (AD012)16 = (X)5 ii) (5.204)10 = (X)3 b) Add the maximum positive integer to the minimum negative integer, both represented in i) 16-bit 1s complement binary notation. Express the answer in 1s complement binary ii) 16-bit 2s complement binary notation. Express the answer in 2s complement binary (8M+7M) a) Write both sum-of-products and product-of-sums Boolean expressions for i) a two-input AND gate, ii) a two-input NAND-gate, iii) a two-input EX-OR gate and iv) a two-input NOR gate from their respective truth tables. b) i) Simplify ii) Prove that [AB + C + D ] [D + (E + F )G ] = D (AB + C ) + D G (E + F )

2.

F ( A, B, C , D, E ) = ABCD + ABC D + ABCD + ABC D + ABCDE + ABC D E + ABC DE

3.

A logic system has three inputs A, B and C and two outputs Y1 and Y2. The output functions Y1 and Y2 are expressed by Y1 = A BC + BC + A C + AB C + ABC and Y2 = A B + AC + ABC Determine the minimized output logic functions using the QuineMcCluskey tabular method (15M) a) Draw the circuit diagram of a 4-bit adder-subtractor and briefly describe its functional principle. b) Briefly describe the concept of look-ahead carry generation with respect to its use in adder circuits. (8M+7M) a) Draw the logic diagram and truth tables for the following: i) An eight-line to three-line priority encoder with active LOW inputs and outputs and an active LOW ENABLE input. ii) A four-line to16-line decoder with active HIGH inputs and active LOW outputs and an active LOW ENABLE input; b) Implement the three-variable Boolean function using an 8-to-1multiplexer and a 4-to1multiplexer? F ( A, B, C ) = A C + AB C + ABC (8M+7M)

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(8M+7M)

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Code No: R22023

R10

SET - 4

6.

a) Design four-digit Excess-3 code converter using PROM with the help of programming table b) Realize the following switching functions with PAL with the help of programming table F1 (A,B,C,D) = m(0,1,3,4,5,6,7,12,13) (6M+9M) a) How can presettable counters be used to construct counters with variable modulus? b) Obtain the count sequence of i) a MOD-10 Ring counter ii) a MOD-10 Johnson counter Determine the number of flip-flops required to construct the above counters. (7M+8M)

7.

8.

Convert the following Mealy machine into a corresponding Moore machine and realize using JK Flip-flop (15M) PS NS, Z X=0 X=1 A C,0 B,0 B A,1 D,0 C B,1 A,1 D D,1 C,0

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