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Lec 13

Computer Organization

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Parivesh Jain
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35 views

Lec 13

Computer Organization

Uploaded by

Parivesh Jain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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27-Nov-06

27-Nov-06 (1)

27-Nov-06 (2)

Execution of Add (R3),R1


Fetch the instruction
Fetch the first operand
(R3)
Perform the addition
Load result to R1

CSC2510 - Computer
Organization
Lecture 13: Revision
Processor Unit
Philip Leong

What should MDRin be?

27-Nov-06 (3)

27-Nov-06 (4)

Execution

Execution
Internal processor
bus

Step 1: PC loaded into MAR, read request to memory, MUX gives 4,


added to B (PC) and stored in Z
Step 2: Z moved to PC while waiting for memory
Step 3: Word fetched from memory and loaded into IR
Step 4: figure out what the instruction should do and set control
circuitry for steps 4-7. R3 transferred to MAR and memory read
operation initiated
Step 5: contents of R1 moved to Y
Step 6: read operation completed and is in MDR as well as B input
of ALU. SelectY as second input of ALU and add performed
Step 7: result is transferred to R1, End causes a goto step 1

Step

Action

PCout , MAR in , Read, Select4,Add, Zin

Zout , PCin , Y in , WMF C

Control signals
PC

Address
lines
MAR

Instruction

MDR out , IR in

decoder and

R3out , MAR in , Read

control logic

Memory
bus

R1out , Y in , WMF C

MDR out , SelectY, Add, Zin

Zout , R1in , End

MDR
Data
lines

IR

Figure 7.6. Control sequencefor execution of the instruction Add (R3),R1.

Y
R0

Constant 4

Select

Memory-bus
data lines

MDRoutE

ALU
control
lines

Which steps are the instruction fetch?

Internal processo
bus

MUX
Add

MDRout

Sub

MDR

R( n - 1)

ALU
Carry-in
XOR

TEMP
MDR inE

MDRin

Figure 7.4. Connection and control signals forgister


re MDR.

27-Nov-06 (5)

Branch Instructions

Step Action
1

Steps 1-3, instruction fetch


Step 4: add the offset to the
PC
Step 5: update the PC

PCout , MAR in , Read, Select4,Add, Z in

Zout , PCin , Yin , WMF C

MDR out , IR in

Offset-field-of-IRout, Add, Z in

Z out, PCin , End

Now do you understand why


the branch offset is calculated
from the next address to be
executed?
For conditional e.g. branch < 0,
step 4 is replaced with
Offset-field-of-IRout, Add, Zin,
If N=0 then End

27-Nov-06 (6)

Multiple Buses
One disadvantage of our single bus scheme is that only
one data item can be transferred over the bus per cycle
A solution is multiple internal buses
All registers combined into a register file with 3 ports
Why are there 2 outputs?
What is the input for?
What does 3 port mean?

Buses A and B allow simultaneous transfer of the two


operands for the ALU
ALU is able to just pass one of its operands to R e.g. R=A

Incrementer unit computes PC+4, means we dont need


the ALU for this
ALU still has a 4 input for other instructions such as
postincrement

27-Nov-06

27-Nov-06 (7)

Three bus datapath


Bus A

Bus B

27-Nov-06 (8)

Hardwired Control

Bus C
Incrementer

What does this do?


(WMFC means wait for
memory function completed)
What are the advantages and
disadvantages over a single
bus?

How do we generate the


control signals?

PC

Hardwired control
Microprogrammed control

Register
file

A
ALU

Step Action
Instruction
decoder

PCout, R=B, MAR in , Read, IncPC

WMFC

MDR outB , R=B, IR in

R4outA , R5outB , SelectA, Add, R6in , End

CLK

IR

MDR

Decoder/
encoder

IR

Condition
codes

Control signals

MAR

Memory bus
data lines

Control step
counter

External
inputs

Sequences using a counter


and produces control
signals at the right time
Control signals are
functions of the IR, external
inputs and condition codes
Can you give an example
for each?

Clock

A hardwired control is
called a finite state
machine

Constant 4

MUX

Address
lines

27-Nov-06 (9)

27-Nov-06 (10)

Microprogrammed
Control Unit

Microprogrammed Control

Micro instruction

PCout

MAR in

Read

MDRout

IRin

Yin

Select

Add

Zin

Z out

R1out

R1in

R3out

WMFC

End

The control signals are stored in a memory as sequences of control


words which are the individual bits of the control signals
Microinstructions are executed in a manner similar to machine code

PCin

A microprogram counter is
used to read control words
sequentially from control store
Every time new instruction
loaded into the IR, output of
Starting Address Generator
loaded into the uPC
uPC automatically
incremented by clock causing
successive microinstructions to
be read from the control store
Control signals delivered to
various parts of the processor
in the correct sequence
This scheme is not able to
change its sequence as a
result of other inputs such as
the condition code e.g. Branch
<0

IR

Starting
address
generator

Clock

PC

Control
store

Figure 7.16. Basic organization of a microprogrammed control

27-Nov-06 (11)

Microprogrammed
Control Unit
0

PCout , MAR

Z out , PC in , Y in , WMF C

MDR out , IR in

in

27-Nov-06 (12)

Scheme to allow
Conditional Branching
Starting and branch
address generator

Address Microinstruction
, Read, Select4, Add, Z in

3
Branch to starting addressof appropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25

If N=0, then branch to microinstruction 0

26

Offset-field-of-IR

27

Z out , PC in , End

out

, SelectY, Add, Z in

Figure 7.17. Microroutine for the instruction Branch<0.

CW

Loads new address into


uPC when instructed
Has condition codes and
external inputs which can
affect uPC

External
inputs
IR

Starting and
branch address
generator

Condition
codes

uPC incremented every


cycle except
When new instruction
loaded into IR, uPC loaded
with starting address of the
microroutine
For taken branches, uPC
updated to branch address
For End microinstruction,
uPC set to 0

Clock

PC

Control
store

CW

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