UNIT 4.

PROCESSOR
Some Fundamental Concepts
 Processor fetches one instruction at a time and perform the operation
specified.
 Instructions are fetched from successive memory locations until a
branch or a jump instruction is encountered.
 Processor keeps track of the address of the memory location
containing the next instruction to be fetched using Program Counter
(PC).
 Instruction Register (IR)
 Suppose each instruction comprises 4 bytes, and that is stored in one
memory word. To execute an instruction, the process will do following
Processor Organization Internal processor
bus

Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic
MDR HAS Memory
TWO INPUTS bus
AND TWO
MDR
OUTPUTS Data
lines IR

Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

Memory-bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure 7.4. Connection and control signals for register MDR.

Internal processor
b us
Register Transfer
Riin

Ri

Ri out

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
• Writing the word into a memory location follows the desired address is loaded into MAR. Then, the
data to be written are loaded in to MDR, and a Write command is issued.
Internal processor
bus
Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP

Z
Execution of Branch Instructions
Control sequence for an unconditional branch instruction is as follows:
1) PCout, MARin, Read, Select4, Add, Zin
2) Zout, PCin, Yin, WMFC
3) MDRout, IRin
4) Offset-field-of-IRout, Add, Zin
5) Zout, PCin, End
Execution of branch instruction contd..
The processing starts, as usual, the fetch phase ends in step3.
• In step 4, the offset-value is extracted from IR by instruction-decoding circuit.
• Since the updated value of PC is already available in register Y, the offset X is gated onto the
bus, and an addition operation is performed.
• In step 5, the result, which is the branch-address, is loaded into the PC.
• The offset X used in a branch instruction is usually the difference between the branch target-
address and the address immediately following the branch instruction. (For example, if the
branch instruction is at location 1000 and branch target-address is 1200, then the value of X
must be 196, since the PC will be containing the address 1004 after fetching the instruction at
location 1000).
• In case of conditional branch, we need to check the status of the condition-codes before
loading a new value into the PC.
e.g.: Offset-field-of-IRout, Add, Zin, If N=0 then End
If N=0, processor returns to step 1 immediately after step 4. If N=1, step 5 is performed to load
a new value into PC.
Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

PC

Register
file

Constant 4

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory bus Address

data lines lines

Figure 7.8. Three-bus organization of the datapath.

Multiple bus organization
 In case of single bus organization only one data item can be
transferred over the bus in a clock cycle.
 To reduce number of steps needed, most commercial
processors provide multiple internal paths that enable several
transfers to take place in parallel.
 In three-bus structure all general purpose registers are
combined into a single block called the register file.
 The register file is said to have three ports
 Two output-ports allow the contents of 2 different registers to be
simultaneously placed on buses A & B.
 Third input-port allows data on bus C to be loaded into a third
register during the same clock-cycle.
 Buses A and B are used to transfer source-operands to A & B
inputs of ALU during arithmetic or logic operations.
 Result is transferred to destination over bus C.
 Incrementer-unit is used to increment PC by 4.
Multiple-Bus Organization
 Add R4, R5, R6

Step Action

1 PCout , R=B, MAR in , Read, IncPC

2 WMFC
3 MDR outB , R=B, IR in
4 R4outA , R5outB , SelectA, Add, R6 in , End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
Hardwired Control
 To execute instructions, the processor must have some
means of generating the control signals needed in the proper
sequence.
 Two categories:
 hardwired control and microprogrammed control
 Hardwired system can operate at high speed; but with little
flexibility.
 Consider the sequence of control signals given in figure 7.6
 Each step is completed in one clock period.
 A counter can be used to keep track of control steps.
 Each state or count of this counter corresponds to one control
step.
 The required control signals are determined by the following
information:
 Contents of the control step counter.
 Contents of the instruction register.
 Contents of condition code flags
 External input signals such as MFC and interrupt requests
Control Unit Organization
CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Figure 7.10. Control unit organization.

Detailed Block Description
CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS 1
External
INS 2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

 Decoder/encoder block is a combinational-circuit that
generates required control-outputs depending on state of all
its inputs.
 Step-decoder provides a separate signal line for each step in
the control sequence.
 Similarly, output of instruction-decoder consists of a separate
line for each machine instruction.
 For any instruction loaded in IR, one of the output-lines INS1
through INSm is set to 1, and all other lines are set to 0.
 The input signals to encoder-block are combined to generate
the individual control-signals Yin, PCout, Add, End and so on.
Generating Zin
 Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
 For example, Zin=T1+T6.ADD+T4.BR ;
 This signal is asserted during time-slot T1 for all instructions,
 during T6 for an Add instruction
 during T4 for unconditional branch instruction
 When RUN=1, counter is incremented by 1 at the end of
every clock cycle. When RUN=0, counter stops counting.
 Sequence of operations carried out by this machine is
determined by wiring of logic elements, hence the name
“hardwired”.