VHDL Assignment No 1

1. Design and simulate a 4 input NOR Gate program using dataflow modeling in
VHDL.

Program:
entity norgate4 is
port(a,b,c ,d: in bit;
y: out bit);
end norgate4;
architecture data of norgate4 is
begin
y<= not(a or b or c or d);
end data;
Wave output :

2. Design and simulate a 4 input NAND Gate program using dataflow modeling
in
VHDL.

Program:
entity nandgate4 is
port(a,b,c ,d: in bit;

y: out bit);
end nandgate4;
architecture data of nandgate4 is
begin
y<= not(a and b and c and d);
end data;

Wave output :

3.Design and simulate a 3 input AND Gate program using dataflow modeling in
VHDL.

Program:
entity andgate3 is
port(a, b,c: in bit;
y: out bit);
end andgate3;
architecture data of andgate3 is
begin
y<=a and b and c;

end data;
Wave output :

4. Design and simulate a 3 input XOR Gate program using dataflow modeling in
VHDL.

Program:
entity xorgate3 is
port(a,b,c : in bit;
y: out bit);
end xorgate3;
architecture data of xorgate3 is
begin
y<= a xor b xor c;
end data;
Wave output :

5. Design and simulate a 2 input EX-NOR Gate program using dataflow

modeling in
VHDL.

Program:
entity xnorgate is
port(a,b : in bit;
y : out bit);
end xnorgate;
architecture data of xnorgate is
begin
y<= a xnor b;
end data;

Wave output :

6. Design and simulate a 3 input OR Gate program using dataflow modeling in

VHDL.

Program:
entity orgate3 is

port(a, b,c: in bit;

y: out bit);
end orgate3;
architecture data of orgate3 is
begin
y<=a or b or c;
end data;
Wave output :

7. Design and simulate a 3 input NAND Gate program using dataflow modeling
in
VHDL.

Program:
entity nandgate3 is
port(a,b,c : in bit;
y : out bit);
end nandgate3;
architecture data of nandgate3 is
begin
y<= not(a and b and c);

end data;

Wave output :

8. Design and simulate a 3 input NOR Gate program using dataflow modeling in
VHDL.

Program:
entity norgate3 is
port(a,b,c : in bit;
y: out bit);
end norgate3;
architecture data of norgate3 is
begin
y<= not(a or b or c);
end data;

Wave output :

9. Design and simulate a half adder in VHDL using dataflow-modeling style.

Program:

entity ha is
port(a,b : in bit;
sum,carry: out bit);
end ha;
architecture data of ha is
begin
sum<= a xor b;
carry<= a and b;
end data;

Wave output :

10. Design and simulate a full adder in VHDL using dataflow-modeling style.

Program:

entity fa is
port(a,b,c : in bit;
sum,carry: out bit);

end fa;
architecture data of fa is
begin
sum<=a xor b xor c;
carry<= (a and b)or(b and c)or(c and a);
end data;

Wave output :

11. Design and simulate a 2-1 Mux in VHDL using dataflow-modeling style.

Program:

entity mux2_1 is
port(a,b,s : in bit;
y : out bit);
end mux2_1;
architecture data of mux2_1 is
begin
y<=(a and (not s)) or (b and s);
end data;

Wave output :

12. Design and simulate a 4-1 Mux in VHDL using dataflow-modeling style.

Program:
entity mux_4 is
port(a,b,c,d,s1,s2 : in bit;
y: out bit);
end mux_4;
architecture data of mux_4 is
begin
y<= ((a and (not s1) and (not s2)) or (b and s1 and (not s2)) or (c and (not s1) and
s2) or ( d and s1 and s2));
end data;
Wave output :

13. Design and simulate an 8-1 Mux in VHDL using dataflow-modeling style.

Program:
entity mux_8 is
port(a,b,c,d,e,f,g,h,s1,s2,s3 : in bit;
y: out bit);
end mux_8;
architecture data of mux_8 is
begin
y<= ((a and (not s1) and (not s2) and (not s3)) or (b and s1 and (not s2) and (not
s3)) or (c and (not s1) and s2 and (not s3) ) or ( d and s1 and s2 and (not s3)) or (e
and (not s1) and (not s2) and s3) or (f and s1 and (not s2) and s3) or (g and (not s1)
and s2 and s3) or (h and s1 and s2 and s3));
end data;

Wave output :

14. Design and simulate a 16-1 Mux in VHDL using dataflow-modeling style.

Program:
library ieee;

use ieee.std_logic_1164.all;
entity mux16_1 is
port(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p : in std_logic;
s : in std_logic_vector(3 downto 0);
out_put : out std_logic);
end mux16_1;
architecture data of mux16_1 is
signal w,x,y,z: std_logic;
begin
w<= not s(0);
x<= not s(1);
y<= not s(2);
z<= not s(3);
out_put <= ((a and w and x and y and z) or (b and s(0) and x and y and z)
or (c and w and s(1) and y and z) or (d and s(0) and s(1) and y and z)
or (e and w and x and s(2) and z) or (f and s(0) and x and s(2) and z)
or (g and w and s(1) and s(2) and z) or (h and s(0) and s(1)and s(2) and z)
or (i and w and x and y and s(3)) or (j and s(0) and x and y and s(3))
or (k and w and s(1) and y and s(3)) or (l and s(0) and s(1)and y and s(3))
or (m and w and x and s(2) and s(3)) or (n and s(0) and x and s(2) and s(3))
or (o and w and s(1) and w and s(2) and s(3)) or (p and s(0)and s(1) and w and
s(2)));
end data;
Wave output :

15. Design and simulate a 1 to 2 De- Mux in VHDL using dataflow modeling
style.

Program:

entity demux1_2 is
port(a,s : in bit;
x,y : out bit);
end demux1_2;
architecture data of demux1_2 is
begin

x<=(a and (not s));

y<=(a and s);
end data;
Wave output :

16. Design and simulate a 2-to-4-line decoder/demultiplexer in VHDL using

data flow modeling style.

Program:
entity demux2_4 is
port(a : in bit;
s : in bit_vector(2 downto 0);
w,x,y,z : out bit);
end demux2_4;
architecture data of demux2_4 is
signal n,p: bit;
begin
n<= (not s(0));
p<= (not s(1));
w<=(a and n and p);
x<=(a and s(0) and p);
y<=(a and n and s(1));

z<=(a and s(0) and s(1));

end data;
Wave output :

17. Design and simulate a 3-to-8-line decoder/demultiplexer in VHDL using

data flow modeling style.

Program:
entity demux3_8 is
port(a : in bit;
s : in bit_vector(2 downto 0);
r,t,u,v,w,x,y,z : out bit);
end demux3_8;
architecture data of demux3_8 is
signal n,o,p: bit;
begin
n<= (not s(0));
o<= (not s(1));
p<= (not s(2));
r<=(a and n and o and p);
t<=(a and s(0) and o and p);

u<=(a and n and s(1) and p);

v<=(a and s(0) and s(1) and p);
w<=(a and n and o and s(2));
x<=(a and s(0) and o and s(2));
y<=(a and n and s(1) and s(2));
z<=(a and s(0) and s(1) and s(2));
end data;

Wave output :

18. Design and simulate a Master Slave J-K Flip Flop in VHDL using dataflowmodeling
style.

Program:
entity mastr_slaveflp is
port(j,k,q,clk : in bit;
f1: out bit);
end mastr_slaveflp;
architecture data of mastr_slaveflp is

begin
f1<=((not k and q) or (j and not q)) and (not clk);
end data;
Wave output :

19. Realize a circuit for the following function in VHDL using data flow modeling.
F1= _m (0, 3, 5, 6, 9, 10, 12, 15)

Program:
entity circuitreal is
port(a,b,c,d: in bit;
y: out bit);
end circuitreal;
architecture data of circuitreal is
signal s0,s1,s2,s3 : bit;
begin
s0<= not a;
s1<= not b;
s2<= not c;
s3<= not d;
y<= (s0 and s1 and s2 and s3) or (s0 and s1 and c and d) or ( s0 and b and
s2 and d) or (s0 and b and c and s3)
or (a and b and s2 and s3) or (a and b and c and d) or (a and s1 and s2 and

d) or (a and s1 and c and s3);

end data;
Wave output :

20. Design a circuit with two outputs has to implement the following functions.
F(A,B,C,D)= _m (0, 2,4,6,7,9)+D(10,11)
G (A,B,C,D)= _m (2,4,9,10,15)+D(0,13,14)

Program:
entity cct_rlwt_dnc is
port(a,b,c,d: in bit;
f,g: out bit);
end cct_rlwt_dnc;
architecture data of cct_rlwt_dnc is
signal s0,s1,s2,s3 : bit;
begin
s0<= not a;
s1<= not b;
s2<= not c;
s3<= not d;

f<= (s0 and s3) or (s0 and b and c) or ( a and s1 and d);
g<= (s0 and s2 and s3) or (a and s2 and d)or (a and b and c) or (s1 and c and s3);
end data;

Wave output :

21. Design and simulate a half -Subtractor in VHDL using dataflow-modeling

style.

Program:

entity hs is
port(a,b : in bit;
df,carry: out bit);
end hs;
architecture data of hs is
begin
df<=a xor b;
carry<= (not a) and b;

end data;
Wave output :

22. Design and simulate a Full -Subtractor in VHDL using dataflow-modeling

style.

Program:
entity fs is
port(a,b,c : in bit;
df,carry : out bit);
end fs;
architecture data of fs is
begin
df<=a xor b xor c;
carry<= ((not a) and (b or c)) or (b and c);
end data;

Wave output :

23. Design a BCD to 7-Segment Decoder in VHDL using dataflow-modeling style.

Program:

entity bcd_7segment is
port(a,b,c,d: in bit;
t,u,v,w,x,y,z: out bit);
end bcd_7segment;
architecture data of bcd_7segment is
signal s0,s1,s2,s3 : bit;
begin
s0<= not a;
s1<= not b;
s2<= not c;
s3<= not d;
t<=(s1 and s3) or (b and d) or (c and d) or a;
u<=(s1 or (s2 and s3) or (c and d));
v<=(b or s2 or d);
w<=(s1 and s3) or (c and s3) or (s1 and c) or (b and s2 and d);

x<=(s1 and s3) or (c and s3);

y<=a or (s2 and s3) or (b and s2) or (b and s3);
z<=a or (b and s2) or (s1 and c) or (c and s3);
end data;
Wave output :

24. Realize a circuit for the following function in VHDL using data flow modeling.
F1= _m (0, 3, 5, 6, 9, 10, 12, 15)+ D (2,14)

Program:
f1: out bit);
end cct_rlwt_dnc2;
architecture data of cct_rlwt_dnc2 is
signal s0,s1,s2,s3 : bit;
begin
s0<= not a(3);
s1<= not a(2);
s2<= not a(1);

s3<= not a(0);

f1<= (a(1) and s3) or (s0 and s1 and a(1)) or (s0 and s1 and s3) or (a(3) and a(2)
and a(1))
or (a(3) and a(2) and s3) or (s0 and a(2) and s2 and a(0)) or (a(3) and s1 and s2 and
a(0));
end data;

Wave output :

25. Realize a circuit for the following function in VHDL using data flow modeling.
F1= _m (0, 1, 2, 3, 11, 12, 14, 15)

Program:
entity cct_rlwt_dnc3 is
port(a: in bit_vector(3 downto 0);
f1: out bit);
end cct_rlwt_dnc3;
architecture data of cct_rlwt_dnc3 is
signal s0,s1,s2,s3 : bit;
begin

s0<= not a(3);

s1<= not a(2);
s2<= not a(1);
s3<= not a(0);
f1<= (s0 and s1) or (a(3) and a(1) and a(0)) or (a(3) and a(2) and a(0));
end data;

Wave output :

26. Realize a BCD to Excess 3 code converter using minimum number of NAND
gates in
VHDL using Dataflow Modeling.

Program:

Wave output :

27. Realize a Excess 3 to BCD code converter using minimum number of NAND
gates in
VHDL using Dataflow Modeling.

Program:

Wave output :

28. Realize a 2-bit Comparator using gates in VHDL in Dataflow.

Program:
entity comparator_2bit is
port(a,b : in bit_vector(1 downto 0);
agb,aeb,alb: out bit);
end comparator_2bit ;
architecture data of comparator_2bit is
signal s0,s1,s2,s3: bit;
begin
s0<=not a(1);
s1<=not a(0);
s2<=not b(1);
s3<=not b(0);
agb<=(a(0) and s2 and s3) or (a(1) and s2) or (a(1) and a(0) and s3);
aeb<=(s0 and s1 and s2 and s3) or (s0 and a(0) and s2 and b(0)) or (a(1) and s1
and b(1) and s3);
alb<=(s0 and b(1)) or (s0 and s2 and b(0)) or (s1 and b(0) and b(1));
end data;
Wave output :

29. Realize a 4-bit Comparator using gates in VHDL using Dataflow.

Program:
entity comptr4bit is
port(a0,a1,a2,a3,b0,b1,b2,b3 : in bit;
alb,agb,aeb: out bit);
end comptr4bit;
architecture data of comptr4bit is
signal x0,x1,x2,x3: bit;
begin
x3<=(not a3 and b3) nor (a3 and not b3);
x2<=(not a2 and b2) nor (a2 and not b2);
x1<=(not a1 and b1) nor (a1 and not b1);
x0<=(not a0 and b0) nor (a0 and not b0);
alb<=(not a3 and b3) or (x3 and not a2 and b2) or (x3 and x2 and not a1
and b1) or (x3 and x2 and x1 and a0 and not b0);
agb<=(a3 and not b3) or (x3 and a2 and not b2) or (x3 and x2 and a1 and
not b1) or (x3 and x2 and x1 and not a0 and b0);

aeb<=x3 and x2 and x1 and x0;

end data;

Wave output :

30. Realize a 4 to 1 Mux using WITH SELECT Statement in VHDL.

Program:
library ieee;
use ieee.std_logic_1164.all;
entity mux4_1with is
port(a,b,c,d : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux4_1with;
architecture data of mux4_1with is

begin
with s select
y<= a when "00",
b when "01",
c when "10",
d when others;
end data;

Wave output :

31. Realize a 4- to 1 Mux using WHEN -ELSE Statement in VHDL.

Program:
entity mux4_1when is
port(a,b,c,d : in bit;
s : in bit_vector(1 downto 0);
y : out bit);

end mux4_1when;
architecture data of mux4_1when is
begin
y<= a when (s="00") else
b when (s="01") else
c when (s="10") else
d;
end data;

Wave output :

32. Realize a BCD to 7 Segment Converter using WITH SELECT Statement in

VHDL.

Program:
entity bcd_7segmentwith is
port(s : in bit_vector(3 downto 0);
y: out bit_vector(6 downto 0));
end bcd_7segmentwith;

architecture data of bcd_7segmentwith is

begin
with s select
y<="1111110" when "0000",
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"0011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1110011" when "1001",
"0000000" when others;
end data;
Wave output :

33. Realize a BCD to 7 Segment Converter using WHEN -ELSE Statement in

VHDL.

Program:
entity bcd_7segmentwhen is
port(s : in bit_vector(3 downto 0);

y: out bit_vector(6 downto 0));

end bcd_7segmentwhen;
architecture data of bcd_7segmentwhen is
begin
y<="1111110" when (s ="0000") else
"0110000" when (s="0001") else
"1101101" when (s="0010") else
"1111001" when (s="0011") else
"0110011" when (s="0100") else
"1011011" when (s="0101") else
"0011111" when (s="0110") else
"1110000" when (s="0111") else
"1111111" when (s="1000") else
"1110011" when (s="1001") else
"0000000";
end data;
Wave output :

34. Realize a Toggle Flip Flop in VHDL using Dataflow Modeling.

Program:
entity t_filpflop is
port(t,q : in bit;

f1: out bit);

end t_filpflop;
architecture data of t_filpflop is
begin
f1<=(t xor q) and clk;
end data;

Wave output :

35. Realize a Delay Flip flop in VHDL using Dataflow Modeling.

Program:
entity d_filpflop is
port(d,clk : in bit;
f1: out bit);
end d_filpflop;
architecture data of d_filpflop is
begin
f1<=d and clk;
end data;
Wave output :

36. Realize a Priority Encoder using Dataflow in VHDL.

Program:

Wave output :

37. Realize a 4-bit binary Full adder with fast carry

Program:
entity fastcarry is
port(a1,a2,a3,a4,b1,b2,b3,b4,cin : in bit;
s1,s2,s3,s4,cout: out bit);
end fastcarry;
architecture data of fastcarry is
signal cb,a1ndb1,a2ndb2,a3ndb3,a4ndb4,a1nrb1,a2nrb2,a3nrb3,a4nrb4: bit;
begin
cb<=not cin;
a1ndb1<=a1 nand b1;
a1nrb1<=a1 nor b1;
a2ndb2<=a2 nand b2;

a2nrb2<=a2 nor b2;

a3ndb3<=a3 nand b3;
a3nrb3<=a3 nor b3;
a4ndb4<=a4 nand b4;
a4nrb4<=a4 nor b4;
s1<=(cin) xor (not a1nrb1 and a1ndb1);
s2<=((cb and a1ndb1) nor a1nrb1) xor (not a2nrb2 and a2ndb2);
s3<=(not ((cb and a1ndb1 and a2ndb2) or (a2ndb2 and a1nrb1) or
(a2nrb2))) xor (not a3nrb3 and a3ndb3);
s4<=(not((cb and a1ndb1 and a2ndb2 and a3ndb3) or (a2ndb2 and a3ndb3
and a1nrb1) or (a3ndb3))) xor (not a2nrb2 and a2ndb2);
cout<=(not ((cb and a1ndb1 and a2ndb2 and a3ndb3 and a4ndb4) or
(a2ndb2 and a3ndb3 and a4ndb4 and a1nrb1) or (a3ndb3 and a4ndb4 and
a2nrb2) or (a4ndb4 and a3nrb3) or(a4nrb4)));
end data;

Wave output :

38. Design and implement in VHDL a Four variable majority function.

Program:
entity majorityfn is
port(a,b,c,d : in bit;
y: out bit);
end majorityfn;
architecture data of majorityfn is
begin
y<= (a and b) or (c and d) or (b and d) or (a and d) or (b and c) or (a and c);
end data;
Wave output :

39. Design and Realize the below problem in VHDL.

Program:
entity traffic is
port(a,b : in bit;
red,yellow,green: out bit);
end traffic;
architecture data of traffic is
begin
red<=not a;
yellow<=b;

green<=a and not b;

end data;
Wave output :