AVR ARCHITECTURE &

ASSEMBLY
General
purpose
registers

Special On-chip
function Flash
registers (Program)
Memory

Execution
Engine
WHY USE ASSEMBLY PROGRAMMING?
 Full access to hardware features
 Compiler limits a programmers access to the hardware
features that the compiler writer decided to implement
 Writing time critical portions of code
 Allows tight control over what the CPU is doing on every clock
cycle
 Debugging
 It in not uncommon when trying to debug odd system behavior
to have to look at disassembled code

Refs: Beginners Introduction to the Assembly Language of

ATMEL-AVR-Microprocessors (Gerhard Schmidt)
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WHY LEARN THE ATMEGA128 HARDWARE
ARCHITECTURE?
 Helps give intuition to why the assembly instructions
were created the way the were
 Help understand what special feature may be available
for you to make use of.

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ATMEGA128 ARCHITECTURE OVERVIEW

 8 bit processor
 size of bus is 8 bits

http://class.ece.iastate.edu/cpre288
 size of registers is 8
bits
 RISC architecture
 Harvard architecture
 separate data and
instruction memory
 133 instructions

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ATMEGA128 BLOCK DIAGRAM
CPU

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ATMEGA128: RISC CPU ARCHITECTURE
 What is RISC?
 Reduced Instruction Set Computer (with respect to
CISC, Complex Instruction set Computer)
 Typical RISC
 Load/Store based: ALU to memory transaction via
registers
 Most instruction are the same length
 Typically fewer instructions than a CISC
architecture
 Typically many more registers than CISC since Data
must be moved into a register before it can be
operated on
 Low number of instructions typically makes
hardware design simpler (as compared to CISC)
Ref: http://www.seas.upenn.edu/~palsetia/cit595s07/RISCvsCISC.pdf (Diana Palsetia) 
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ATMEGA128 CPU CORE SUMMARY
Most instructions are 16-bit or 32-bit
 Takes one or two cycles to fetch

Simple two-stage pipeline

 Most instructions take one or two cycles

Registers are 8-bit and addresses are 16-bit

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ATMEGA128 BLOCK DIAGRAM

Program
Memory

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ATMEGA128 BLOCK DIAGRAM

Data
Memory

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ATMEGA128: HARVARD ARCHITECTURE

Program Data
Memory Memory
64K
(128KB) CPU (4KB) 4K rows
rows

16‐bits 8‐bits
 Program memory
 Flash based: Program persists even if power turned off (non-volatile)
 16-bits wide, instructions are 16-bit (typical) or 32-bit wide.
 Data Memory
 SRAM based: Data disappears if power is turned off (volatile)
 8-bits wide: all data and registers are stored as 8-bit chunks.

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http://class.ece.iastate.edu/cpre288
ATMEGA128: LOGICAL DATA MEMORY ORGANIZATION

CPU
Data
32 8-bit Memory
4K
Registers (4KB) rows

ALU

 Registers: 8‐bits
 8-bits wide
 Directly accessible by ALU
 Data Memory:
 8-bit wide
 Must use a register to source data to ALU/store the result of ALU

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ATMEGA128: MEMORY MAP ORGANIZATION
General
CPU Reg
I/O Reg
Ext: I/O
Reg

4KB 4K
(Internal rows
 Address layout: SRAM)
 First 32 rows (0 – 0x1F) are gen purpose registers
 Next 64 rows (0x20-0x5F) are I/O registers 8‐bits
 Next 160 rows (0x60-0xFF) are Extended I/O registers
 Next 4096 rows (0x0100 – 0x10FF ) are Internal SRAM

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General Purpose Registers
8-bits

R0

R1

R2

R26
X
R27

R28
Y
R29

R30
Z
R31
GENERAL PURPOSE REGISTER FILE

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ATMEGA128: GP REGISTERS (CONT.)
 32 8-bit general purpose registers
 Used for accessing SRAM
 Used for storing function parameters
 Used for instructions to execute operations on
 What is an 8-bit register.
 Basically just 8 D-Flip-flops connected together

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Bit 1 Bit 0

2

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ATMEGA128: GP REGISTERS (CONT.)
 R16 – R31 are the only registers that can have immediate
values loaded (e.g. LDI R17, 5)

 Register pairs R27:R26, R29:R28, R31:R30 can be used as

16-bit pointers (short versions of these registers are X, Y,
Z)

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ATMEGA128: GP REGISTERS
 16-bit Data stored across adjacent registers
 Used for accessing SRAM
 Used for storing function parameters
 Used for instructions to execute operations on
 32-bit data stored across adjacent registers.

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SREG: Status Register

I T H S V N Z C

Bit 7 – I: Global Interrupt Enable

Bit 6 – T: Bit Copy Storage
Bit 5 – H: Half Carry Flag
Bit 4 – S: Sign Bit, S = N ⊕ V
Bit 3 – V: Two’s Complement Overflow Flag
Bit 2 – N: Negative Flag
Bit 1 – Z: Zero Flag
Bit 0 – C: Carry Flag
STATUS REGISTER (SREG)

Describes the status of the CPU

I: Global Interrupt Enable, enable/disable interrupts
to the CPU
T: Bit Copy Storage, for moving a single bit between
registers
H: Half Carry Flag, To indicate a half carry in BCD
arithmetic

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STATUS REGISTER (CONT.)

S: Sign Bit, Whether the actual result is negative or

not with signed type operation
V: Two’s Complement Overflow Flag, whether a
overflow happened or not with signed operands
N: Negative Flag, whether the result is negative or not
with signed operands

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STATUS REGISTER (CONT.)

Z: Zero flag, whether the result is zero or not

C: Carry Flag, whether a carry is generated for
unsigned operands

H, S, N, V, Z, C bits are regarding the last

arithmetic/logic operation

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SPECIAL FUNCTION REGISTERS (SFR)
 SREG
 MCUCR

 Stack Pointer (SP) – SPH:SPL

 ADCSR

 PINF

 OCR1A
SREG: Status Register

I T H S V N Z C

Bit 7 – I: Global Interrupt Enable

Bit 6 – T: Bit Copy Storage
Bit 5 – H: Half Carry Flag
Bit 4 – S: Sign Bit, S = N ⊕ V
Bit 3 – V: Two’s Complement Overflow Flag
Bit 2 – N: Negative Flag
Bit 1 – Z: Zero Flag
Bit 0 – C: Carry Flag
SAMPLE INSTRUCTIONS
 ADD Rd, Rr Add two Registers Rd ← Rd + Rr
Z,C,N,V,H #1

 ADC Rd, Rr Add with Carry two Registers Rd ←

Rd + Rr + C Z,C,N,V,H #1

 ADIW RdL,K Add Immediate to Word RdH:RdL ←

RdH:RdL + K Z,C,N,V,S #2
INSTRUCTIONS TO MOVE DATA
 MOV Rd, Rr Move Between Registers Rd ← Rr
#1

 LD Rd, X Load Indirect Rd ← (X) #2

 LDI Rd, K Load Immediate Rd ← K #1

 LD Rd, X+ Load Indirect and Post-Inc. Rd ←

(X), X ← X + 1 #2
PORT PROGRAMMING

LDI R16, $FF ; Select Direction as Output on all pins

OUT DDRB, R16 ; Set value in DDRB

LDI R16, $FF ; Set Initial value to high on all pins

OUT PORTB, R16 ; Set PORTB value, Port B pins
should be high
LDI R16, $00 ; Select Direction as Input on all pins
OUT DDRA, R16 ; Set value in DDRA

IN R16, PORTA ; Port A read into R16

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CONTROL INSTRUCTIONS
R17 R2
if (X == Y) X = X+Y;

CP R17, R2 ; compare X & Y

BRNE SKIPADD ; Z=1 iff X==Y
ADD R17, R2 ; X = X+Y
SKIPADD: ADD R1, R2 ; some junk
if (X == Y) X = X+Y;
R17 R2
else X = X-Y;

CP R17, R2 ; compare X & Y

BREQ THENPART ; Z=1 iff X==Y
SUB R17, R2 ; X = X-Y – ELSEPART
JMP SKIPTHENPART ;do not do THENPART
;as well
THENPART: ADD R17, R2 ; X=X+Y
SKIPTHENPART:
WHILE/FOR LOOP
R17 R2 R1
for (i=0; i < 100; i++) X = X+Y;

CLR R17 ;i=0

LOOP: ADD R2, R1 ; X=X+Y
INC R17 ;i=i+1
CPI R17, 100 ; i-100
BRMI LOOP ; branch on -ve
CAN WE DO BETTER?
R17 R2 R1
for (i=0; i < 100; i++)X = X+Y;

LDI R17, 100 ; i = 100

LOOP: ADD R2, R1 ; X=X+Y
DEC R17 ;i=i-1
BRNE LOOP ; branch on not zero
ARRAYS
char A[100];
for (i=0; i < 100; i++)A[i] = A[i]+1;
R17 R16

LDI R26, 0x01 ;XL – LB of starting

address for A
LDI R27, 0x00 ;XH – MB of starting
address for A
LDI R17, 100 ; i = 100
LOOP: LD R16, X ; A[i]
INC R16 ; A[i]=A[i]+1
ST X, R16
INC R26 ; next A[i]
DEC R17 ;i=i-1
BRNE LOOP ; branch on not zero
ARRAYS
char A[100];
for (i=0; i < 100; i++)A[i] = A[i]+1;
R17 R16

LDI R26, 0x01 ;XL – LB of starting

address for A
LDI R27, 0x00 ;XH – MB of starting
address for A
LDI R17, 100 ; i = 100
LOOP: LD R16, X ; A[i]
INC R16 ; A[i]=A[i]+1
ST X+, R16
INC R26 ; next A[i]
DEC R17 ;i=i-1
BRNE LOOP ; branch on not zero
ARRAY ACCESS: LOAD/STORE WITH
DISPLACEMENT

 LDD R1, X+8

X
Memory

+8 (displacement)

R1
SUB Rd, Rr Subtract without Rd ←Rd - Rr
Carry
SUBI Rd, K Subtract Imm Rd← Rd - K

SBC Rd, Rr Subtract with Carry Rd ←Rd - Rr - C

AND Rd, Rr Logical AND Rd ←Rd · Rr

ANDI Rd, K Logical AND with Imm Rd ←Rd · K

OR Rd, Rr Logical OR Rd ← Rd v Rr

EOR Rd, Rr Exclusive OR Rd ← Rd ^Rr

COM Rd One's Complement Rd ← $FF - Rd

NEG Rd Two's Complement Rd ← $00 - Rd

SBR Rd,K Set Bit(s) in Register Rd ←Rd v K

CBR Rd,K Clear Bit(s) in Register Rd ← Rd · ($FF - K)

CLR Rd CLR Rd Rd ← Rd ^ Rd

INC Rd Increment Rd ←d + 1

TST Rd Test for Zero or Minus Rd ← Rd · Rd

CPC Rd,Rr Compare with Carry Rd - Rr - C

CPI Rd,K Compare with Imm Rd - K

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2

SBRC Rr, b Skip if Bit in Register if (Rr(b)=0) PC ← PC + 2

Cleared
SBRS Rr, b Skip if Bit in Register Set if (Rr(b)=1) PC ← PC + 2
RJMP k RJMP k PC ← PC + k + 1

SBIC P, b Skip if Bit in I/O Register if(I/O(P,b)=0) PC ¬ PC + 2

Cleared
IJMP Indirect Jump to (Z) PC ← Z

RCALL k Relative Call Subroutine PC ← PC + k + 1

RET Subroutine Return PC ← STACK

RETI Interrupt Return PC ← STACK

BRPL k Branch if Plus if (N = 0) then PC ← PC +

k+1
BRIE k Branch if Interrupt if (I = 1) then PC ← PC + k
Enabled +1
LDS Rd, k Load Direct from Rd ← (k)
SRAM
LD Rd, X Load Indirect Rd ← (X)

LDD Rd, Y+q Load Indirect with Rd ← (Y + q)

Displacement
LD Rd, X+ Load Indirect and Post- Rd ← (X), X ← X + 1
Increment
LD Rd, -X Load Indirect and Pre- X ← X - 1, Rd ← (X)
Decrement
STD Y+q,Rr STD Y+q,Rr (Y + q) ← Rr

ST Z+, Rr Store Indirect and Post- (Z)← Rr, Z ← Z + 1

Increment
PUSH Rr Push Register on Stack STACK ← Rr

POP Rd Pop Register from Stack Rd ← STACK

IN Rd, P In Port Rd ← P

OUT P, Rr Out Port P ← Rr

LPM Load Program Memory R0 ← (Z)

BYTE Reserve byte to a variable

CSEG Code Segment

DB Define constant byte(s)

DEF Define a symbolic name on a register

DSEG Data Segment

DW Define constant word(s)

EQU Set a symbol equal to an expression

ESEG EEPROM Segment

INCLUDE Read source from another file

ORG Set program origin

SET Set a symbol to an expression

MACRO Begin macro

ENDMACRO End macro

ASSEMBLER DIRECTIVES
.DSEG
var1: .BYTE 1 ; reserve 1 byte to var1
table: .BYTE tab_size ; reserve tab_size bytes
.CSEG
ldi r30, low(var1) ; Load Z register low
ldi r31, high(var1) ; Load Z register high
ld r1, Z ; Load VAR1 into register 1
char A[100];
for (i=0; i < 100; i++)A[i] = A[i]+1;

.DSEG
StartA: .BYTE 100 ;100 bytes for Array A
.CSEG
LDI R26, low(StartA) ;XL – LB of starting address for
A
LDI R27, high(StartA);XH – MB of starting address for
A
LDI R17, 100 ; i = 100
LOOP: LD R16, X ; A[i]
SUBI R16, -1 ; A[i]=A[i]+1
ST X+, R16
SUBI R17, 1 ;i=i-1
BRNE LOOP ; branch on not zero
.ESEG
StartA: .DB 1,1,1,1,1,1,1,1,….,1 ;100 bytes
for Array A defined in EEPROM

.DEF temp=R16
.CSEG
.ORG 0x1200
StartA: .DB 1,1,1,1,1,1,1,1,….,1 ;100 bytes
for Array A defined in flash/text memory
MACROS
.MACRO SUBI16 ; Start macro definition
subi r16,low(@0) ; Subtract low byte
sbci r17,high(@0) ; Subtract high byte
.ENDMACRO ; End macro definition

.EQU io_offset = 0x23

.EQU porta = io_offset + 2
.CSEG ; Start code segment
clr r2 ; Clear register 2
out porta,r2 ; Write to Port A
SUBI16 StartA
GCC MEMORY LAYOUT