Chapter Two

–Lecture 3
oThe Control
Unit
CONTROL UNIT
 Generate relevant timing and control signals to all operations
in the computer.
– The control signals generated by the control unit cause the opening and
closing of logic gates, resulting in the transfer of data to and from
registers and the operation of the ALU.
 Control units are implemented in one of two ways the hardwired
and Micro programmed Control unit.
 Hardwired - is made up of sequential and combinational circuits to
generate the control signals.
 Its input logic signals, governed by the current machine
instruction, are transferred into a set of output control signals. 2
TIMING AND
CONTROL
Control unit of Basic Computer
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter 3
(SC) Clock
TIMING AND CONTROL
 Step 1: at T0 (start time)?
Where do we fetch the next instruction
from

 The Program Counter register (PC) holds the

address of the next instruction to be executed.

 The PC is transferred to the Address Register (AR)

which is connected to the Address Bus.
T0 : AR = PC
Timing and Control
• Step 2: How do we obtain the instruction from
memory at T1?
– The data stored at the selected address is transferred onto the
Data Bus and then to the Data Register (DR) in the CPU.
– The instruction data is transferred immediately to the
Instruction Register (IR)
T1 : DR = M[AR] , IR = DR , PC = PC + 1
Memory
Data bus
INC
M[AR] DR LD PC

IR LD
CPU bus
AR LD
Address bus
Timing and Control
• Step 3: How do we decode the instruction intention (ie.
NOTE:
meaning, operational definition) at T2?
All instructions share the
– The OpCode,
steps T0, T1 Mode
and T2.and Address field bits all serve as inputs
toHowever,
the Control Logic on
depending Gates that select the specific instruction
semantics
what each specific
instruction requires, the
• Direct addressing
control logic for higher time
• Indirect
steps is moreaddressing
complicated,
•requiring
CPU register
moreaddressing
inputs.
• Input
• Output

T2 : {D0,...,D7} = DEC( IR(12-14) ),

AR = IR(0-11),
I = IR(15)
FETCH AND
DECODE
T0: AR PC (S0S1S2=010, T0=1)
• Fetch and Decode T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
T1
S2
T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock 7
Common bus
Basic Computer Organization & Design 8 Instrction Cycle

DETERMINE THE TYPE OF INSTRUCTION

Start
SC  0

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference) =>opcode ≠ 111

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
Computer Organization Computer Architectures Lab
MR Instructions

MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1

- The execution of MR instruction starts with T4

AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand 9
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
Basic Computer Organization & Design 10

MEMORY REFERENCE INSTRUCTIONS

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

BSA: AR = 135 135 21

136 Subroutine PC = 136 Subroutine
D5T4: M[AR]  PC,
AR  AR + 1
D5T5: PC  AR, SC  0

1 BUN 135 1 BUN 135

Memory Memory

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 11 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

 ISZ: Increment and Skip-if-Zero

Since it is not possible to increment a word inside the memory

directly, it is necessary to read to DR, increment DR and back
to the memory.

 This is done by the following sequence of microoperations.

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1),SC 
0

Computer Organization Computer Architectures Lab

12 CHAPTER 3

CENTRAL
PROCESSING UNT
STRUCTURE
ECEg3148 12/09/2024
13 Lecture Outline
• CPU Instruction Set
Architectures
•Instruction Formats

 Three address instructions

 Two address instructions
 One address instructions
 Zero address instructions

12/09/2024
An Instruction Set
 An Instruction Sets.
 Serves as an interface between software and hardware.
 Provides a mechanism by which the software tells the
hardware what should be done.
 Instruction Set Design
 One important design factor is the number of
operands contained in each instruction
 Has a significant impact on the word size and complexity of
theE.CPU
 Joanne DeGroat, OSU
Instruction Set Design
 Consider how many operands we need for an ADD
instruction
 If we want to add the contents of two memory locations
together, then we need to be able to handle at least two
memory addresses
 Where does the result of the add go? We need a third
operand to specify the destination

 If all of these operands are memory addresses, we

need a really long instruction!
 Joanne E. DeGroat, OSU
 The number of address fields in the instruction
CPU Architectures
Classifying Instruction Set Architectures
 The type of internal storage in the CPU is the
most basic differentiation. The major choices are a
stack, an accumulator, or a set of registers.
– Stack Computer Architecture
– AC Computer Architecture
– General Purpose Register Computer Architecture

Input Bus Input Bus

General Other
Purpose Stack
ALU
ALU
AC Registers ALU
Registers
Registers

Stack Architecture Output Bus Output Bus

AC Architecture
GPR Architecture

 Joanne E. DeGroat, OSU

Operand Locations in Four ISA Classes
GPR

 Joanne E. DeGroat, OSU

Code Sequence C = A + B for Four Instruction Sets

Stack Accumulator GPR GPR

0 address 1 address (register-memory) Register – Register
2 address 3 address
Push A Load A Mov R1, A Mov R1,A
Push B Add B Add R1, B Mov R2, B
Add Store C Mov C, R1 Add R3, R1, R2
Pop C Mov C, R3

memory
 Joanne E. DeGroat, OSU memory
acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2
NUMBER OF ADDRESSES
19

The number of address fields in the instruction format

depends on the internal organization of CPU
Single accumulator organization:
ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
POP M[X]  TOS

 Joanne E. DeGroat, OSU 12/09/2024

Three-Address Instructions:
20

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B]
*/
ADD R2, C, D /* R2  M[C] + M[D]
*/
MUL X, R1, R2 /* M[X]  R1 * R2
*/

- Results in short programs

- Instruction becomes long (many bits)

 Joanne E. DeGroat, OSU 12/09/2024

TWO-ADDRESS INSTRUCTIONS
21

Program to evaluate X = (A + B)*(C + D) :

MOV R1, A /* R1  M[A] */
ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
 Joanne E. DeGroat, OSU
ONE-ADDRESS INSTRUCTIONS
22

- Use an implied AC register for all data manipulation

Program to evaluate X = (A + B) * (C + D) :
 LOAD A /* AC  M[A] */
 ADD B /* AC  AC + M[B] */
 STORE T /* M[T]  AC */
 LOAD C /* AC  M[C] */
 ADD D /* AC  AC + M[D] */
 MUL T /* AC  AC * M[T] */
 STORE X /* M[X]  AC */

 Joanne E. DeGroat, OSU

Stack Architecture
Zero-address Instructions
23

 Stack is a part of memory

 There is a pointer maintained to the top of the stack
 Stack is “last in, first out” (LIFO)
 Operation: “PUSH A” means put M[A] into top of stack
 Operation: “ADD” means add the contents of the top of the stack to the
contents of the next on the stack, remove these two contents, and put the
result in the top of the stack
 Operation: “POP X” means put the contents of the top of stack to memory
location M[X], and remove the item from the top of the stack .

 Joanne E. DeGroat, OSU ECE265 12/09/2024

Stack Architectures
 Instruction set: add, sub, mult, div, . .
.push A, pop A
Example: A*B - (A+C*B)
push A
push B
A C B B*C A+B*C result
mul A B A*B
A*B A C A A*B
A
push A A*B A A*B
A*B
push C
push B
mul
add
sub

 Joanne E. DeGroat, OSU

Exercise
25

Write the stack architecture code to execute the

following program.

Program to evaluate X = (A + B) * (C + D) :

 Joanne E. DeGroat, OSU ECE265 12/09/2024

Home Exercise - 1

 Understand the pro’s and con’s

of the three, two, one and zero
address instruction formats.

 Joanne E. DeGroat, OSU

Home Exercise - 2
27

 Assume a given microprocessor supports 2-

address, 1-address & 0-address instructions. It has
also the following specification.
 20 bit instruction
 512 word memory
 Two 2-address instruction & 150 1-address
instructions.
 How many possible 0-address instructions can be
included?

 Joanne E. DeGroat, OSU ECE265 12/09/2024