ECE 2300

Digital Logic & Computer Organization

Spring 2018

Single Cycle Microprocessor

Lecture 15: 1
Announcements
• HW 6 released (with a practice question)

• Lab 5 prelab (A) due tomorrow

Lecture 15: 2
SRAM vs. DRAM
• SRAM advantages and disadvantages
– Usually on the same chip with microprocessor
– Fast access (+)
– High power (−)
– Relatively high area & cost per bit (−)

• DRAM: main memory is stored in DRAM cells

– Typically off-chip
– Single transistor storage cell (+)
• Higher density lower cost/bit
• Lower power/bit
– Slow (−)
• Need periodic refresh to retain data
Lecture 15: 3
Course Roadmap (Part 1)
• Boolean algebra
• Combinational logic and minimization
• Logic functions
• CMOS gates
• Binary arithmetic and ALUs
• Latches and flip-flops
• Counters
• Verilog
• Finite state machines
• Hazards, timing, clocking
• Memories
Lecture 15: 4
Organization of a Computer
Part 2: Computer Organization

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Lecture 15: !18
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Let’s Build a Microprocessor!
0 0
1 1
+2 0
Z 2
3
Z’
4
MP
1 N
5
SE(OFF,0) Adder N’
C 6
MP V 7
BS
DR Fm … F0
SA RF DataA
Inst. RAM

SB M_address
Decoder

IMM LD
DataB ALU Data
PC

MB SA Data_in 0
FS
0 RAM
SB 1 1
MD DR
LD D_in SE VCZN
MW MB MW MD
BS IMM

Lecture 15: 6
The Basic Processing Cycle
Operation
RF
DataA
Data Out
LD ALU
SA DataB
SB
DR
D_in

• Read data from two registers

• Perform an operation
• Place the result into a register

• All three steps performed in 1 clock cycle

Lecture 15: 7
Register File (RF)
• Collection of 2k n-bit registers RF
• Control inputs
n
SA – Source address A LD DataA
k n
SB – Source address B SA DataB
k
SB
DR – Destination address k
DR
LD – Load destination register n
D_in
with D_in
• Data inputs Clk
D_in – Input data
• Data outputs
DataA – Output data A
DataB – Output data B

Lecture 15: 8
Example RF Organization
Decoder Reg 0
MUX
EN
0 n
DR0 I0 Y0 D DataA
1
DR1 I1 Y1
Reg 1 2
LD EN Y2
EN 3
Y3
D SA1 SA0
n
D_in Reg 2 MUX
EN 0 n
D 1 DataB
2
Reg 3
3
EN
D SB1 SB0

Example with 4 registers. Typically have 32 or more.

Lecture 15: 9
Instruction Execution
“add”
RF DataA
Data Out
1 LD
01 DataB ALU
SA
10 SB
00 DR
D_in

ADD R0, R1, R2

operation
destination source
register registers

Lecture 15: 10
Instruction Execution
Operation
RF DataA
Data Out
LD
SA
DataB ALU ADD R0, R1, R2
SB
DR
D_in

CLOCK
Operation “add”
SA 01
SB 10
DataA [R1]
DataB [R2]
Data Out [R1]+[R2]
DR 00
LD Lecture 15: 11
Instruction Execution
Operation
RF DataA
Data Out
LD
SA
DataB ALU ADD R0, R1, R2
SB SUB R3, R2, R1
DR
D_in

CLOCK
Operation “add” “sub”
SA 01 10
SB 10 01
DataA [R1] [R2]
DataB [R2] [R1]
Data Out [R1]+[R2] [R2]−[R1]
DR 00 11
LD Lecture 15: 12
Operations With Constants
Operation
RF DataA
Data Out
LD ALU
DataB
SA 0 ADDI R3, R3, 1
SB 1
DR
D_in SE
MB
IMM

• Constants are called immediate values

• Sign extend (SE) IMM to the width of DataA to
perform correct two’s complement operation
– Why? May not have enough bits in instruction (later)
– Assume IMM is 4 bits and DataA is 8 bits wide
0101 00000101
1110 11111110 Lecture 15: 13
Reading and Writing Memory
Operation
RF DataA
M_address
LD ALU
DataB Data_in RAM 0
SA 0
SB 1 1
DR
D_in SE
MB MW MD
IMM

• Most data are held in memory (RAM)

• Must be moved into a register in order to operate
on it
• Data will also move out of registers into memory
– To make room for other data
– To move it to permanent storage (e.g., disk)
Lecture 15: 14
Reading Memory (“Load”)
“add”
RF DataA
M_address
1 LD
01 DataB ALU RAM
SA 0 Data_in 0
xx SB 1 1
11 DR
D_in SE
MB = 1 MW = 0 MD =1
IMM = 4

Example: LOAD R3, 4(R1) // R3 <= M[R1 + 4]

Step 1: Form the memory address by adding the

value in R1 (base) with the immediate 4 (offset)
Step 2: Read the data at that address in RAM
and place it in R3
Lecture 15: 15
Writing Memory (“Store”)
“add”
RF DataA
M_address
0 LD
00 DataB ALU RAM
SA 0 Data_in 0
10 SB 1 1
xx DR
D_in SE
MB = 1 MW = 1 MD =x
IMM = 0

Example: STORE R2, 0(R0) // M[R0] <= R2

Step 1: Form the memory address by adding
the value in R0 with the immediate 0

Step 2: Write the value in R2 into the RAM at

that address
Lecture 15: 16
Control Unit
• Regulates the interaction between data and
operations on data (i.e., datapath)

• Series of control words control the datapath to

perform a sequence of operations

• The sequence of operations performed by the

CU may be affected by the ALU Condition Codes
– Z: Zero
– N: Negative
– Also V: Overflow and C: Carry out

Lecture 15: 17
Datapath + Control Unit
Fm … F0
DR RF DataA
SA M_address
SB LD
IMM DataB ALU RAM
SA 0 Data_in 0
MB SB 1
V FS
1
C DR
MD D_in VCZN
N SE
LD MB MW MD
Z MW
CU IMM

Control Word→ DR SA SB IMM MB FS MD LD MW

memory write
k-bit register immediate function
addresses value select load register

register/immediate ALU/memory
select select
Lecture 15: 18
Sequence of Operations
Fm … F0
DR RF DataA
SA M_address
SB LD
IMM DataB ALU RAM
SA 0 Data_in 0
MB SB 1
V FS
1
C DR
MD D_in VCZN
N SE
LD MB MW MD
Z MW
CU IMM

DR SA SB IMM MB FS MD LD MW

R2 <= R0 + R1 10 00 01 x 0 ADD 0 1 0

R1 <= M[R2] 01 10 xx 0 1 ADD 1 1 0

M[R2] <= R0 xx 10 00 0 1 ADD x 0 1

Lecture 15: 19
Sequential (Shift and Add) Multiplication
• Unsigned multiplication: A2A1A0 by B2B1B0
A 2A 1A 0 R1 <= M[0] // load A from M[0]
B 2B 1B 0 R2 <= M[1] // load B from M[1]
(A2A1A0)ÎB0 R3 <= 0 // initialize R3 (P) = 0
(A2A1A0) ÎB1
(A2A1A0) ÎB2 (*) R4 <= R2 & 1 // R4 = lsb(B)
P4 P3 P2 P1 P0 R2 <= SRL(R2) // shift B right
if (R4) R3 <= R3+R1 // if lsb(B)=1, P=P+A
P = AxB R1 <= SLL(R1) // shift A left
if (R2) goto (*) // repeat until B=0
Assumptions:
(1) A, B are initially in
memory; M[2] <= R3 // store P to M[2]
(2) P will also be put Pseudo code
back to memory

Lecture 15: 20
Next Time

More Single-Cycle Microprocessor

Lecture 15: 21