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FINALTERM EXAMINATION
CS501- Advance Computer Architecture (Session - 1)
Marks: 75
Mc100201523
Syed Muhsan Abbas

You can test easily in handbook just search red answer

Please upload hurry ly if you have better solution thanks .

Question No: 1 ( Marks: 1 ) - Please choose one

Which one of the following is the memory organization of SRC processor?
 28 * 8 bits
 216 * 8 bits
 232 * 8 bits
 264 * 8 bits
Question No: 2 ( Marks: 1 ) - Please choose one
Type A format of SRC uses -----------instructions
 two
 three
 four
 five
Question No: 3 ( Marks: 1 ) - Please choose one
The instruction ---------------will load
the register R3 with the contents of the memory
location M [PC+56]
 Add R3, 56
 lar R3, 56
 ldr R3, 56
 str R3, 56
Question No: 4 ( Marks: 1 ) - Please choose one
Which format of the instruction is called the accumulator?
 3-address instructions
 3-address instructions
 2-address instructions
 1-address instructions
 0-address instructions
Question No: 5 ( Marks: 1 ) - Please choose one
Which one of the following are the code size
and the Number of memory
bytes respectively for a 2-address instruction?
 4 bytes, 7 bytes
 7 bytes, 16 bytes
 10 bytes, 19 bytes
 13 bytes, 22 bytes

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Question No: 6 ( Marks: 1 ) - Please choose one

Which operator is used to name registers, or part of registers, in the Register
Transfer Language?
 :=
 &
 %
 ©
Question No: 7 ( Marks: 1 ) - Please choose one
The transmission of data in which each character is self-contained units with its
own start and stop bits is -----------
 Asynchronous
 Synchronous
 Parallel
 All of the given options
Question No: 8 ( Marks: 1 ) - Please choose one
Circuitry that is used to move data is called -------------
 Bus
 Port
 Disk
 Memory
Question No: 9 ( Marks: 1 ) - Please choose one
Which one of the following is NOT a technique used when the CPU wants to
exchange data with a peripheral device?
 Direct Memory Access (DMA).
 Interrupt driven I/O
 Programmed I/O
 Virtual Memory
Question No: 10 ( Marks: 1 ) - Please choose one
Every time you press a key, an interrupt is generated.
This is an example of
 Hardware interrupt
 Software interrupt
 Exception
 All of the given
Question No: 11 ( Marks: 1 ) - Please choose one
The interrupts which are pre-programmed and the processor automatically finds
the address of the ISR using interrupt vector table are
 Maskable
 Non-maskable
 Non-vectored
 Vectored
Question No: 12 ( Marks: 1 ) - Please choose one
Which is the last instruction of the ISR that is to be executed when the ISR
terminates?
 IRET

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 IRQ
 INT
 NMI
Question No: 13 ( Marks: 1 ) - Please choose one
If NMI and INTR both interrupts occur simultaneously, then which one has the
precedence over the other

 NMI
 INTR
 IRET
 All of the given
Question No: 14 ( Marks: 1 ) - Please choose one
Identify the following type of serial communication error condition:
The prior character that was received was not still read by the CPU and is
over written by a new received character.
 Framing error
 Parity error
 Overrun error
 Under-run error
Question No: 15 ( Marks: 1 ) - Please choose one
----------the device usually means reading its status register every so often until
the device's status changes to indicate that it has completed the request.
 Executing
 Interrupting
 Masking
 Polling
Question No: 16 ( Marks: 1 ) - Please choose one
Which I/O technique will be used by a sound card that may need to access data
stored in the computer's RAM?
 Programmed I/O
 Interrupt driven I/O
 Direct memory access(DMA)
 Polling
Question No: 17 ( Marks: 1 ) - Please choose one
For increased and better performance we use _____ which are usually made of glass.
 Coaxial Cables
 Twisted Pair Cables
 Fiber Optic Cables
 Shielded Twisted Pair Cables
Question No: 18 ( Marks: 1 ) - Please choose one
In _____ if we find some call party busy we can have provision of call waiting.
 Delay System
 Loss System
 Single Server Model
 None of the given

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Question No: 19 ( Marks: 1 ) - Please choose one

In ____ technique memory is divided into segments of variable sizes depending upon
the requirements.
 Paging
 Segmentation
 Fragmentation
 None of the given
Question No: 20 ( Marks: 1 ) - Please choose one
For a request of data if the requested data is not present in the cache, it is called a _____
 Cache Miss
 Spatial Locality
 Temporal Locality
 Cache Hit
Question No: 21 ( Marks: 1 ) - Please choose one
An entire _____ memory can be erased in one or a few seconds which is much faster
than EPROM.
 PROM
 Cache
 EEPROM
 Flash Memory
Question No: 22 ( Marks: 1 ) - Please choose one
________chips have quartz windows and by applying ultraviolet light data can be
erased from them.
 PROM
 Flash Memory
 EPROM
 EEPROM
Question No: 23 ( Marks: 1 ) - Please choose one
The _______signal coming from the CPU tells the memory that some interaction is
required between the CPU and memory.
 REQUEST
 COMPLETE
None of the given
Question No: 24 ( Marks: 1 ) - Please choose one
______ is a combination of arithmetic, logic and shifter unit along with some
multiplexers and control unit.
 Barrel Rotator
 Control Unit
 Flip Flop
 ALU
Question No: 25 ( Marks: 1 ) - Please choose one
1. In Multiple Interrupt Line, a number of interrupt lines are provided between the
____________________ module.
 CPU and the I/O

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 CPU and Memory

 Memory and I/O
 None of the given
Question No: 26 ( Marks: 1 ) - Please choose one
The data movement instructions ___________ data within the machine and to
or from input/output devices.
 Store
 Load
 Move
 None of given
Question No: 27 ( Marks: 1 ) - Please choose one
CRC has ------------ overhead as compared to Hamming code.
 Equal
 Greater
 Lesser
 None of the given
Question No: 28 ( Marks: 1 ) - Please choose one
The ________ is w-bit wide and contains a data word, directly connected to the data
bus which is b-bit wide memory address register (MAR) .
 Instruction Register(IR)
 memory address register (MAR)
 memory Buffer Register(MBR)
 Program counter (PC)
Question No: 29 ( Marks: 1 ) - Please choose one
In_______technique, a particular block of data from main memory can be placed in
only one location into the cache memory .
 Set Associative Mapping
 Direct Mapping
 Associative Mapping
 Block Placement
Question No: 30 ( Marks: 1 ) - Please choose one
_______ indicate the availability of page in main memory.
 Access Control Bits
 Used Bits
 Presence Bits
 None of the given
Question No: 31 ( Marks: 1 )
What are the hardware interrupts in a computer system?Mention its utility.

Hardware interrupts:
Hardware interrupts are generated by external events specific to peripheral devices. Most
processors have at least one line dedicated to interrupt requests. When a device signals on
this specific line, the processor halts its activity and executes an interrupt service routine.
Such interrupts are always asynchronous with respect to instruction execution, and are

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not associated with any particular instruction. They do not prevent instruction completion
as exceptions like an arithmetic overflows does. Thus, the control unit only needs to
check for such interrupts at the start of every new instruction. Additionally, the CPU
needs to know the identification and priority of the device sending the interrupt request.
There are two types of hardware interrupt:
Maskable Interrupts
Non-maskable Interrupts
Maskable Interrupts:
• These interrupts are applied to the INTR pin of the processor.
• These can be blocked by resetting the flag bit for the interrupts.
Non-maskable Interrupts:
• These interrupts are detected using the NMI pin of the processor.
• These can not be blocked or masked.
• Reserved for catastrophic event in the system

Question No: 32 ( Marks: 1 )

Consider a LAN, using bus topology. If we replace the bus with a switch, what change
will occur in such a configuration?

For full duplex operation, it is necessary to use
switches in a LAN. If there are loops in the 
wiring between two (or more) switch ports, 
problems will occur and the network will not 
function properly.

Question No: 33 ( Marks: 2 )

Where do you find the utility of hardware interrupts in a computer system?
A hardware interrupt causes the processor to save its state of execution and begin execution of
an interrupt handle

Question No: 34 ( Marks: 2 )

Differentiate between CPU register and Cache Memory.

A CPU cache is a cache used by the central processing unit of a computer to reduce the average
time to access memory. The cache is a smaller, faster memory which stores copies of the data
from the most frequently used main memory locations. As long as most memory accesses are to
cached memory locations, the average latency of memory accesses will be closer to the cache
latency than to the latency of main memory.

a processor register is a small amount of storage available on the CPU whose contents can be
accessed more quickly than storage available elsewhere. Most, but not all, modern computer
architectures operate on the principle of moving data from main memory into registers, operating

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on them, then moving the result back into main memory—a so-called load-store architecture. A
common property of computer programs is locality of reference: the same values are often
accessed repeatedly; and holding these frequently used values in registers improves program
execution performance.
Source(s):
http://en.wikipedia.org/wiki/CPU_cache
http://en.wikipedia.org/wiki/Processor_r…

Question No: 35 ( Marks: 3 )

Name three important schemes that are commonly used for error control.

There are three schemes commonly used for error control.

1. Parity code
2. Hamming code
3. CRC mechanism
1. Parity code
Along with the information bits, we add up another bit, which is called the parity bit. The
objective is the total number of 1’s as even or odd. If the parity at the receiving end is
different, an error is indicated. Once error is found, CPU may request to repeat that data.
The concept of parity bit could be enhanced. In such a case, we would like to increase the
distance between different code words. Consider a code word consists of four bits, 0000,
and second code word consists of 1111. The distance between two codes is four. So the
distance between the two codes would be the number of bits in which they differ from
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each other. So the concept of introducing redundancy is increase this distance. Larger the
distance, higher will be the capacity of the code. For single parity, the distance is two, we
can only detect the parity. But if the distance is three, we could also correct these single
errors.
If D= minimum distance between two code words then D-1 errors could be detected and
D/2 errors could be corrected.
2. Hamming code
Hamming code is an example of block code. We have an encoder which could be a
program or a hardware device. We feed k inputs to it. These are k information input bits.
We also feed some extra bits. Let r be the number of redundant bits. So at output we have
r+k = m bits. As an example, for parity bit, we have k=7 and r=1 and m=8. So for 7 bits
we get eight output bits.
For any positive integer m<=3, a Hamming code with following parameters exists:
• Code Length:
n=2m-1
• Number of information symbols:
k = 2m-1-m
• Number of parity-check symbols:

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n–k=m
3. CRC
The basic principle for CRC is very simple. We divide a particular code word and make it
divisible by a prime number, and if it is divisible by a prime number then it is a valid
code word.
CRC does not support error correction but the CRC bits generated can be used to detect
multi-bit errors. At the transmitter, we generate extra CRC bits, which are appended to
the data word and sent along. The receiving entity can check for errors by re computing
the CRC and comparing it with the one that was transmitted.
CRC has lesser overhead as compared to Hamming code. It is practically quite simple to
implement and easy to use.
RAID
The main advantage of having an array of disks is that we could have a simultaneous I/O
request. Latency could also be reduced..
RAID Level 0

Question No: 36 ( Marks: 3 )

What do you understand by the term data synchronization ?
Explain briefly the following schemes of data synchronization in your own words
Synchronous transmission
Asynchronous transmission
There are three basic schemes which can be
used for synchronization of an I/O data
transmission:
Synchronous transmission
Semi-synchronous transmission
Asynchronous transmission
Synchronous transmission:
This can be understood by looking at the
waveforms shown in Figure A.
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M stands for the bus master and S stands for the slave device on the bus. The master and
the slave are assumed to be permanently connected together, so that there is no need for
the selection of the particular slave device out of the many devices that may be present in
the system. It is also assumed that the slave device can perform the transfer at the speed
of the master, so no handshaking signals are needed.
At the start of the transfer operation, the master activates the Read signal, which indicates
to the slave that it should respond with data. The data is provided by the slave, and the
master uses the Enable signal to latch it. All
activity takes place synchronously with the
system clock (not shown in the figure). A
familiar example of synchronous transfer is a register-to-register transfer within a CPU.
Semi-synchronous transmission:

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Figure B explains this type of transfer. All activity is still synchronous with the system
clock, but in some situations, the slave device
may not be able to provide the data to the
master within the allotted time. The additional
time needed by the slave, can be provided by
adding an integral number of clock periods to
the master’s cycle time.
The slave indicates its readiness by activating
the complete signal. Upon receiving this
signal, the master activates the Enable signal
to latch the data provided by the slave.
Transfers between the CPU and the main
memory are examples of semi-synchronous
transfer.
Asynchronous transmission:
This type of transfer does not require a
common clock. The master and the slave
operate at different speeds. Handshaking
signals are necessary in this case, and are used
to coordinate the data transfer between the
master and the slave as shown in the Figure C.
When the master wants to initiate a data
transfer, it activates its Ready signal. The
slave detects this signal, and if it can provide
data to the master, it does so and also activates
its Acknowledge signal. Upon receiving the
Acknowledge signal, the master uses the
Enable signal to latch the incoming data .The
master then deactivates its Ready line, and in
response to it, the slave removes its data and
deactivates its Acknowledge line.
In all the three cases discussed above, the
waveforms correspond to an “input” or a “read”
Figure A
Figure A
Figure B
Figure C
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Last Modified: 17-Feb-07 Page 239
operation. A similar explanation will apply to an “output” or a “write” operation. It
should also be noted that the latching of the incoming data can be done by the master
either by using the rising edge of the Enable signal or by using its falling-edge. This will
depend on the way the intermediate circuitry between the master and the slave is
designed.

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Question No: 37 ( Marks: 3 )

Differenciate between Spatial Locality And Temporal Locality .

Temporal Locality: Concept that a resource will be referenced at one point in time will be
referenced again. Cache miss traffic decreases fast when cache size increases and temporal
locality determines sensitivity to cache size.
Spatial Locality: Concept that likelihood of referencing a resource is higher if a resource near it
was referenced. Cache miss traffic does not increase much when line size increases. Spatial
locality determines sensivity to line size.
~BR
Mukkaysh Srivastav
Temporal Locality: Concept that a resource will be referenced at one point in time will be
referenced again. Cache miss traffic decreases fast when cache size increases and temporal
locality determines sensitivity to cache size.
Spatial Locality: Concept that likelihood of referencing a resource is higher if a resource near it
was referenced. Cache miss traffic does not increase much when line size increases. Spatial
locality determines sensivity to line size.
~BR
Mukkaysh Srivastav

Read
more: http://wiki.answers.com/Q/What_is_the_distinction_between_spatial_locality_and_tem
poral_locality#ixzz1l6tZx0L3

Question No: 38 ( Marks: 5 )

Given a 16-bit parallel output port attached with the FALCON-A CPU as shown in the
figure. The
port is mapped onto address DEh of the FALCON-A s I/O space. Sixteen LED branches
are
used to display the data being received from the FALCON-A s data bus. Every LED
branch is
wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED
on; a 0
turns it off.
Which LEDs will be ON when the instruction
out r2, 222
executes on the CPU? Assume r2 contains 1234h.

Solution:
Since r2 contains 1234h, the bit pattern corresponding to this value will be sent out to the
output port at address 222 (or DEh). This is the address of the output port in this
13 Dependingon the way the assembler is written, the syntax of the out instruction may allow only the
decimal form of the port address, or only the hexadecimal form, or both. Our version of the assembler for
the FALCON-A allows the decimal form only. It also requires that the port address be aligned on 16-bit
“word boundaries”, which means that every port address should be divisible by 2.
Advanced Computer Architecture-CS501

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example. Writing the bit pattern in binary will help us determine the LEDs which will be
ON.
Now 1234h gives us the following bit associations with the data bus
0001001000110100
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB at address DEh LSB at address DFh
Note that the 8-bit register which uses lines D15 .. D8 of the FALCON-A’s data bus is
actually mapped onto address DEh of the I/O space. This is because the architect of the
FALCON-A had chosen a “byte-wide” (i.e., x8) organization of the address space, a 16-
bit data bus width, and the “big-endian” data format at the ISA design stage.
Additionally, data bus lines D15...D8 will transfer the data byte of higher significance
(MSB) using address DEh, and D7...D0 will transfer the data byte of lower significance
(LSB) using address DFh. Thus the LEDs at L12, L9, L5, L4 and L2 will turn on.

Question No: 39 ( Marks: 5 )

Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines
a) How many sets are there in the cache?
b) How many bits of address are required to select a set in cache?

Example 11
Consider a 2-way set-associative cache with 64KB capacity and 16 byte lines.
a. How many sets are there in the cache?
b. How many bits of address are required to select a set in the cache?
c. Repeat the above two calculations for a 4-way set-associative cache with
same size.
Solution
a. A 64KB cache with 16 byte lines contains 4096 lines of data. In a 2-way set
associative cache, each set contains 2 lines, so there are 2048 sets in the cache.
b. Log2(2048)=11. Hence 11 bits of the address are required to select the set.
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c. The cache with 64KB capacity and 16 byte line has 4096 lines of data. For a 4-
way set associative cache, each set contains 4 lines, so the number of sets in the
cache would be 1024 and Log 2 (1024) =10. Therefore 10 bits of the address are
required to select a set in the cache.

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Question No: 40 ( Marks: 10 )

Describe the following features of FALCON-A Assembler
Symbol Table

I/O Ports
I/O Ports: I/O ports are labeled as “14” in Figure 6. These ports are available
for the user to enter input operation values and visualize output operation
values whenever an I/O operation takes place in the program. The input
value for an input operation is given by the user before an instruction
executes. The output values are visible in the I/O port area once the
instruction has successfully executed.

List File

List File: Labeled as “3”, in Figure 1, the List File feature gives a detailed
insight of the FALCON-A listing file, which is produced as a result of the
execution of the 1st and 2nd-pass. It shows the Program Counter value in
hexadecimal and decimal formats along with the machine code generated for
every line of assembly code. These values are printed when the 2nd-pass is
completed.

Single Step

Single Step: “Single Step” lets the user execute the program, one instruction
at a time. The next instruction is not executed unless the user does a “single
step” again. By default, the instruction to be executed will be the one next in
the sequence. It changes if the user specifies a different PC value using the
Change PC option (explained below).
Change PC: This option lets the user change the value of PC
(Program Counter). By changing the PC the user can execute the
instruction to which the specified PC points

Error Log

Error Log: The Error Log is labeled as “4” in Figure 1. It informs the user
about the errors and their respective details, which occurs in any of the

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passes of the assembler.

Question No: 41 ( Marks: 10 )
How many platters are required for a 40GB disk if there are 1024

bytes/sector, 2048 sectors per track and 4096 tracks per platter

How many platters are required for a 40GB disk if there are 1024
bytes/sector, 2048 sectors per track and 4096 tracks per platter
Solution
The capacity of one platter
= 1024 x 2048 x 4096
= 8GB
For a 40GB hard disk, we need 40/8
= 5 such platters.

How many platters are required for a 80GB disk if there are 1024

bytes/sector, 2048 sectors per track and 4096 tracks per platter

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