MODULE-6

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 2

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 3
INTRODUCTION TO SEQUENTIAL LOGIC
Classification of Digital Logic Circuits

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 4

INTRODUCTION TO SEQUENTIAL LOGIC
 Digital electronics is classified into combinational logic and
sequential logic.

 In combinational logic circuits, the outputs at any instant of time

depend only on the input signals present at that time.

 For a change in input, the output occurs immediately.

Combinational Circuit- Block Diagram

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 5

INTRODUCTION TO SEQUENTIAL LOGIC
 There are many applications in which digital outputs are required
to be generated in accordance with the sequence in which the
input signals are received.

 The requirement can’t be satisfied with combinational circuits.

 In sequential logic circuits, it consists of combinational circuits to

which storage elements are connected to form a feedback path.

 The storage elements are devices capable of storing binary

information either 1 or 0.

 The information stored in the memory elements at any given time

defines the present state of the sequential circuit.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 6
INTRODUCTION TO SEQUENTIAL LOGIC

 The present state and the external circuit determine the output
and the next state of sequential circuits.

 Thus in sequential circuits, the output variables depend not only on

the present input variables but also on the past history of input
variables.

Sequential Circuit- Block Diagram

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 7

INTRODUCTION TO SEQUENTIAL LOGIC
Combinational vs Sequential Circuit

S.No Combinational logic Sequential logic

The output variable, at all times The output variable depends not only on
1 depends on the combination of the present input but also depend upon the
input variables. past history of inputs.

Memory unit is required to store the past

2 Memory unit is not required
history of input variables.

3 Faster in speed Slower than combinational circuits.

4 Easy to design Comparatively difficult to design.

5 Eg. MUX, Decoder, Parallel adder Eg. Counter, Shift Register, Serial adder

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 8

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 9
LATCHES
 Latches and Flip-Flops are the basic building blocks of the most
sequential circuits.
 Latches are used for a sequential device that checks all of its inputs
continuously and changes its outputs accordingly at any time
independent of clocking signal.
 Enable signal is provided with the latch. When enable signal is
active output changes occur as the input changes.
 But when enable signal is not activated input changes do not affect
the output.
 Flip-Flop is used for a sequential device that normally samples its
inputs and changes its outputs only at times determined by
clocking signal.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 10
LATCHES
SR Latch using NOR

 The simplest type of latch is the set-reset (SR) latch. It can be

constructed from either two NOR gates or two NAND gates.
 The two NOR gates are cross-coupled so that the output of NOR
gate 1 is connected to one of the inputs of NOR gate 2 and vice
versa.
 The latch has two outputs Q and Q’ and two inputs, set and reset.
 Before going to analyze the SR latch, we recall that a logic 1 at any
input of a NOR gate forces its output to a logic 0.
 Let us understand the operation of this circuit for various input/
output possibilities.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 11
LATCHES
SR Latch using NOR

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 12

LATCHES
SR Latch using NOR

Case 1: S= 0 and R= 0 Case 1: S= 0 and R= 0

(Initially, Q= 1 and Q’= 0) (Initially, Q= 0 and Q’= 1)

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 13

LATCHES
SR Latch using NOR

Case 2: S= 0 and R= 1 Case 3: S= 1 and R= 0

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 14

LATCHES
SR Latch using NOR
Case 4: S= 1 and R= 1
 When R and S both are at logic 1, they force the outputs of both
NOR gates to the low state, i.e., (Q=0 and Q’=0).

 So, we call this an indeterminate or prohibited state, and represent

this condition in the truth table as an asterisk (*).

 This condition also violates the basic definition of a latch that

requires Q to be complement of Q’.

 Thus in normal operation this condition must be avoided by

making sure that 1’s are not applied to both the inputs
simultaneously.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 15
LATCHES
SR Latch using NOR

Present state Next state

S R State
Qn Qn+1
0 0 0 0
No Change (NC)
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 x
Indeterminate*
1 1 1 x
Truth table
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 16
LATCHES
SR Latch using NAND
 The SR latch can also be implemented using NAND gates. The
inputs of this Latch are S and R.

 To understand how this circuit functions, recall that a low on any

input to a NAND gate forces its output high.

Logic Symbol SR latch using NAND gates

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 17

LATCHES
SR Latch using NAND

S R Qn Qn+1 State
0 0 0 x
Indeterminate*
0 0 1 x
0 1 0 1
Set
0 1 1 1
1 0 0 0
Reset
1 0 1 0
1 1 0 0
No Change (NC)
1 1 1 1

Truth table

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 18

LATCHES
Gated Latch using NAND

 In the SR latch, the output changes occur immediately

after the input changes i.e, the latch is sensitive to its S
and R inputs all the time.

 A latch that is sensitive to the inputs only when an enable

input is active. Such a latch with enable input is known as
gated SR latch.

 The circuit behaves like SR latch when EN= 1. It retains

its previous state when EN= 0.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 19

LATCHES
Gated Latch using NAND

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 20

LATCHES
Gated Latch using NAND

EN S R Qn Qn+1 State
1 0 0 0 0
No Change (NC)
1 0 0 1 1
1 0 1 0 0
Reset
1 0 1 1 0
1 1 0 0 1
Set
1 1 0 1 1
1 1 1 0 x Indeterminate
1 1 1 1 x *
0 x x 0 0
No Change (NC)
0 x x 1 1

Truth table

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 21

LATCHES
Gated Latch using NAND

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 22

LATCHES
D - Latch using NAND
 In SR latch, when both inputs are same (00 or 11), the output either
does not change or it is invalid.

 In many practical applications, these input conditions are not

required.

 These input conditions can be avoided by making them

complement of each other.

 Therefore, only two input conditions exists, either S=0 and R=1 or
S=1 and R=0.

 This modified SR latch is known as D latch.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 23
LATCHES
D - Latch using NAND

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 24

LATCHES
D - Latch using NAND

EN D Qn Qn+1 State

1 0 x 0 Reset
1 1 x 1 Set
0 x x Qn No Change (NC)

Truth table

Input and output waveforms

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 25

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 26
FLIP-FLOPS
Triggering of Flip flops
 The state of a Flip-Flop is switched by a momentary change in the input
signal.
 This momentary change is called a trigger and the transition it causes is
said to trigger the Flip-Flop.
 Clocked Flip-Flops are triggered by pulses. A clock pulse starts from an
initial value of 0, goes momentarily to 1 and after a short time, returns to
its initial 0 value.
 Level Triggering: In the level triggering the output state is allowed to
change according to inputs when active (either positive or negative) is
maintained at the enable input.
 Latches are controlled by enable signal, and they are level triggered,
either positive level triggered or negative level triggered.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 27

FLIP-FLOPS
Triggering of Flip flops
 There are two types of level triggered latches:
 (i). Positive level triggered: The output of the latch responds to
the input changes only when the enable input is 1(HIGH).

 (ii). Negative level triggered: The output of the latch responds

to the input changes only when the enable input is 0 (LOW).

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 28

FLIP-FLOPS
Triggering of Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 29

FLIP-FLOPS
Triggering of Flip flops
 Edge Triggering: In the edge triggering the output responds to the
changes in the input only at the positive or negative edges of the
clock pulse at the clock input.

 Flip-Flops are different from latches. Flip-Flops are pulse or clock

edge triggered instead of level triggered.

 (i). Positive edge triggering: Here the output responds to the

changes in the input only at the positive edge of the clock pulse at
the clock input.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 30

FLIP-FLOPS
Triggering of Flip flops
 (ii). Negative edge triggering: Here the output responds to the
changes in the input only at the negative edge of the clock pulse at
the clock input.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 31

FLIP-FLOPS
Flip flops
 The basic 1-bit digital memory circuit is known as a flip-flop. Flip-
Flops are synchronous bistable devices (has two outputs Q and Q’).

 In this case, the term synchronous means that the output changes
state only at a specified point on the triggering input called the
clock (CLK), i.e., changes in the output occur in synchronization
with the clock. It can have only two states, either the 1 state or the
0 state.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 32

FLIP-FLOPS
Flip flops
 Flip-flops can be obtained by using NAND or NOR gates.

 If Q is 1 i.e., Set, then Q' is 0; if Q is 0 i.e., Reset, then Q' is 1. That

means Q and Q' cannot be at the same state simultaneously.

 There are different types of flip-flops depending on how their

inputs and clock pulses cause transition between two states.

 We will discuss four different types of flip-flops SR, D, JK, and T.

 Basically D, J-K, and T are three different modifications of the S-R

flip-flop.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 33

FLIP-FLOPS
SR Flip flops

 The S and R inputs of the S-R Flip-Flop are called

synchronous inputs because data on these inputs are
transferred to the Flip-Flop's output only on the
triggering edge of the clock pulse.

 The circuit is similar to SR latch except enable signal is

replaced by clock pulse (CLK).

 On the positive edge of the clock pulse, the circuit

responds to the S and R inputs.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 34

FLIP-FLOPS
SR Flip flops
 When S is HIGH and R is LOW, the Q output goes HIGH on
the triggering edge of the clock pulse, and the Flip-Flop is
SET.

 When S is LOW and R is HIGH, the Q output goes LOW on

the triggering edge of the clock pulse, and the Flip-Flop is
RESET.

 When both S and R are LOW, the output does not change
from its prior state.

 An invalid condition exists when both S and R are HIGH.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 35
FLIP-FLOPS
SR Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 36

FLIP-FLOPS
SR Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 37

FLIP-FLOPS
SR Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 38

FLIP-FLOPS
SR Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 39

FLIP-FLOPS
D Flip flops

 Like in D latch, in D Flip-Flop the basic SR Flip-Flop is used with

complemented inputs.

 The D Flip-Flop is similar to D-latch except clock pulse is used

instead of enable input.

 To eliminate the undesirable condition of the indeterminate state

in the RS Flip-Flop is to ensure that inputs S and R are never equal
to 1 at the same time. This is done by D Flip-Flop.

 The D (delay or data) Flip-Flop has one input called delay input
and clock pulse input.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 40

FLIP-FLOPS
D Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 41

FLIP-FLOPS
D Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 42

FLIP-FLOPS
D Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 43

FLIP-FLOPS
JK Flip flops
 JK means Jack Kilby, Texas Instrument (TI) Engineer, who invented
IC in 1958.

 JK Flip-Flop has two inputs J(set) and K(reset). A JK Flip-Flop can

be obtained from the clocked SR Flip-Flop by augmenting two
AND gates.

 The data input J and the output Q’ are applied to the first AND
gate and its output (JQ’) is applied to the S input of SR Flip-Flop.

 Similarly, the data input K and the output Q is applied to the

second AND gate and its output (KQ) is applied to the R input of
SR Flip-Flop.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 44
FLIP-FLOPS
JK Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 45

FLIP-FLOPS
JK Flip flops
Case1: J= K= 0
When J=K= 0, both AND gates are disabled. Therefore clock pulse have no
effect, hence the Flip-Flop output is same as the previous output.

Case2: J= 0, K= 1
When J= 0 and K= 1, AND gate 1 is disabled i.e., S= 0 and R= 1. This
condition will reset the Flip-Flop to 0.

Case3: J= 1, K= 0
When J= 1 and K= 0, AND gate 2 is disabled i.e., S= 1 and R= 0. Therefore
the Flip-Flop will set on the application of a clock pulse.

Case4: J= K= 1
When J=K= 1, it is possible to set or reset the Flip-Flop. If Q is High, AND
gate 2 passes on a reset pulse to the next clock. When Q is low, AND gate 1 passes
on a set pulse to the next clock. Either way, Q changes to the complement of the last
state i.e., toggle. Toggle means to switch to the opposite state.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 46
FLIP-FLOPS
JK Flip flops
 The function of JK flip flop using SR flip flop and AND gate can
also be performed by adding extra input terminal to input
terminals of NAND gates. Figure (b) shows the modified circuit of
JK flip flop which has only NAND gates.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 47

FLIP-FLOPS
JK Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 48

FLIP-FLOPS
JK Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 49

FLIP-FLOPS
JK Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 50

FLIP-FLOPS
T Flip flops
 The T (Toggle) Flip-Flop is a modification of the JK Flip-Flop. It is
obtained from JK Flip-Flop by connecting both inputs J and K
together, i.e., single input.

 Regardless of the present state, the Flip-Flop complements its

output when the clock pulse occurs while input T= 1.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 51

FLIP-FLOPS
T Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 52

FLIP-FLOPS
T Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 53

FLIP-FLOPS
T Flip flops

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 54

FLIP-FLOPS
Flip flops Summary

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 55

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 56
SHIFT REGISTERS
SHIFT REGISTERS
 A register is simply a group of Flip-Flops that can be used
to store a binary number. There must be one Flip-Flop
for each bit in the binary number. For instance, a register
used to store an 8-bit binary number must have 8 Flip-
Flops.

 The Flip-Flops must be connected such that the binary

number can be entered (shifted) into the register and
possibly shifted out. A group of Flip-Flops connected to
provide either or both of these functions is called a shift
register.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 57
SHIFT REGISTERS
SHIFT REGISTER

 The bits in a binary number (data) can be removed from

one place to another in either of two ways.

 The first method involves shifting the data one bit at a

time in a serial fashion, beginning with either the most
significant bit (MSB) or the least significant bit (LSB). This
technique is referred to as serial shifting.

 The second method involves shifting all the data bits

simultaneously and is referred to as parallel shifting.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 58

SHIFT REGISTERS
SHIFT REGISTER TYPES
 There are two ways to shift into a register (serial or
parallel) and similarly two ways to shift the data out of
the register.

 This leads to the construction of four basic register types:

 Serial in- serial out,
 Serial in- parallel out,
 Parallel in- serial out,
 Parallel in- parallel out.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 59

SHIFT REGISTERS
SHIFT REGISTER TYPES

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 60

SHIFT REGISTERS
Serial-In Serial-Out (SISO) Shift register

 The serial in/serial out shift register accepts data serially,

i.e., one bit at a time on a single line. It produces the
stored information on its output also in serial form.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 61

SHIFT REGISTERS
Serial-In Serial-Out (SISO) Shift register Example
(If 1010 is applied) – Serial In

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 62

SHIFT REGISTERS
Serial-In Serial-Out (SISO) Shift register Example
(If 1010 is applied) – Serial In

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 63

SHIFT REGISTERS
Serial-In Serial-Out (SISO) Shift register Example
(If 1010 is applied) – Serial Out

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 64

SHIFT REGISTERS
Serial-In Serial-Out (SISO) Shift register Example
(If 1010 is applied) – Serial Out

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 65

SHIFT REGISTERS
Serial-In Parallel-Out (SIPO) Shift register

 In this shift register, data bits are entered into the register
in the same as serial-in serial-out shift register. But the
output is taken in parallel. Once the data are stored, each
bit appears on its respective output line and all bits are
available simultaneously instead of on a bit-by-bit.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 66

SHIFT REGISTERS
Serial-In Parallel-Out (SIPO) Shift register
Example (1111) Serial in

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 67

SHIFT REGISTERS
Serial-In Parallel-Out (SIPO) Shift register
Example (1111) Serial in

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 68

SHIFT REGISTERS
Parallel-In Parallel-Out (PIPO) Shift register

 In this type, there is simultaneous entry of all data bits

and the bits appear on parallel outputs simultaneously.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 69

SHIFT REGISTERS
Parallel-In Serial-Out (PISO) Shift register

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 70

SHIFT REGISTERS
Parallel-In Serial-Out (PISO) Shift register

 In this type, the bits are entered in parallel i.e.,

simultaneously into their respective stages on parallel
lines.

 There are four data input lines, X0, X1, X2 and X3 for
entering data in parallel into the register.

 SHIFT/ LOAD input is the control input, which allows

four bits of data to load in parallel into the register.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 71

SHIFT REGISTERS
Parallel-In Serial-Out (PISO) Shift register

 When SHIFT/LOAD is LOW, gates G1, G2, G3 and G4 are

enabled, allowing each data bit to be applied to the D
input of its respective Flip-Flop.

 When a clock pulse is applied, the Flip-Flops with D = 1

will set and those with D = 0 will reset, thereby storing all
four bits simultaneously.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 72

SHIFT REGISTERS
Parallel-In Serial-Out (PISO) Shift register

 When SHIFT/LOAD is HIGH, gates G1, G2, G3 and G4

are disabled and gates G5, G6 and G7 are enabled,
allowing the data bits to shift right from one stage to the
next.

 The OR gates allow either the normal shifting operation

or the parallel data-entry operation, depending on which
AND gates are enabled by the level on the SHIFT/LOAD
input.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 73

COUNTERS
SHIFT REGISTER COUNTERS

 A shift register counter is basically a shift register with the

serial output connected back to the serial input to
produce special sequences.

 Two of the most common types of shift register counters

are:
Johnson counter (Shift Counter),
Ring counter

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 74

COUNTERS
JOHNSON COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 75

COUNTERS
JOHNSON COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 76

COUNTERS
JOHNSON COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 77

COUNTERS
RING COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 78

COUNTERS
RING COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 79

COUNTERS
RING COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 80

SHIFT REGISTERS
Applications of Shift register

 Serial to parallel converters

 Keyboard encoders
 Universal Asynchronous Receiver Transmitter (UART)
 Pulse extender
 Data processing (Multiplication)
 Delay line memory

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 81

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 82
COUNTERS
TYPES OF COUNTER
 Flip-Flops can be connected together to perform counting
operations. Such a group of Flip- Flops is a counter.

 The number of Flip-Flops used and the way in which they are
connected determine the number of states (called the
modulus) and also the specific sequence of states that the
counter goes through during each complete cycle.

 Counters are classified into two broad categories according to

the way they are clocked:
Asynchronous counters,
Synchronous counters.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 83
COUNTERS
TYPES OF COUNTER

 In asynchronous (ripple) counters, the first Flip-Flop is clocked

by the external clock pulse and then each successive Flip-Flop
is clocked by the output of the preceding Flip-Flop.

 In synchronous counters, the clock input is connected to all

of the Flip-Flops so that they are clocked simultaneously.

 Within each of these two categories, counters are classified

primarily by the type of sequence, the number of states, or
the number of Flip-Flops in the counter.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 84

COUNTERS
SYNC. Vs ASYNC. COUNTER
S.No Asynchronous (ripple) counter Synchronous counter
1 All the Flip-Flops are not clocked All the Flip-Flops are clocked
simultaneously. simultaneously.
2 The delay times of all Flip-Flops There is minimum propagation delay.
are added. Therefore there is
considerable propagation delay.
3 Speed of operation is low Speed of operation is high.
4 Logic circuit is very simple even Design involves complex logic circuit as
for more number of states. number of state increases.
5 Minimum numbers of logic The number of logic devices is more than
devices are needed. ripple counters.
6 Cheaper than synchronous Costlier than ripple counters.
counters.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 85

COUNTERS
2-BIT SYNC. UP COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 86

COUNTERS
2-BIT SYNC. UP COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 87

COUNTERS
3-BIT SYNC. UP COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 88

COUNTERS
3-BIT SYNC. UP COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 89

COUNTERS
3-BIT SYNC. UP COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 90

COUNTERS
4-BIT SYNC. UP COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 91

COUNTERS
4-BIT SYNC. UP COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 92

COUNTERS
3-BIT UP/DOWN COUNTER

 An up/down counter is a bidirectional counter, capable

of progressing in either direction through a certain
sequence.

 A 3-bit binary counter that advances upward through its

sequence (0, 1, 2, 3, 4, 5, 6, 7) and then can be reversed so
that it goes through the sequence in the opposite
direction (7, 6, 5, 4, 3, 2, 1,0) is an illustration of up/down
sequential operation.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 93

COUNTERS
3-BIT UP/DOWN COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 94

COUNTERS
3-BIT UP/DOWN COUNTER

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 95

COUNTERS
2-BIT ASYNC. UP COUNTER

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 96

COUNTERS
2-BIT ASYNC. UP COUNTER

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 97

COUNTERS
3-BIT ASYNC. UP COUNTER

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 98

COUNTERS
3-BIT ASYNC. UP COUNTER

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 99

COUNTERS
4-BIT ASYNC. UP COUNTER

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 100

COUNTERS
4-BIT ASYNC. UP COUNTER

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 101

COUNTERS
4-BIT ASYNC. DOWN COUNTER

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 102

COUNTERS
4-BIT ASYNC. DOWN COUNTER

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 103

COUNTERS
SYNC. MOD COUNTER DESIGN
 The counter can be designed using any types of Flip flop. But
in general T-Flip flop is used to design counter.

 The use of MOD counter in to counter value for specific

number of times.

 For example, MOD-5 Counter means it can counter the

values from 0 to 4 and it get reset. So, it count in the
sequence of 000,001,0110,011,100,000,001,etc.,

 The number of flip flop required to design MOD counter is

depends on the number of count it performs.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 104
COUNTERS
SYNC. MOD COUNTER DESIGN

1. Determine the number of Flip-Flop needed

2. Choose the type of Flip Flop and its excitation table

3. Determine Transition table

4. K-Map simplification procedures for driving expressions

5. Draw the logic diagram

UNIT-V : LECTURE-32 ECE103 – DIGITAL LOGIC DESIGN 105

COUNTERS
Example:1 Design of MOD-6 Counter using JK Flip flop

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 106

COUNTERS
Example:1 Design of MOD-6 Counter using JK Flip flop

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 107

COUNTERS
Example:1 Design of MOD-6 Counter using JK Flip flop

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 108

COUNTERS
Example:1 Design of MOD-6 Counter using JK Flip flop

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 109

COUNTERS
Example:2 Design of MOD-6 Counter using T Flip flop

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 110

COUNTERS
Example:2 Design of MOD-6 Counter using T Flip flop

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 111

COUNTERS
Example:2 Design of MOD-6 Counter using T Flip flop

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 112

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 113
MEALY MODEL

 There are two types of finite state machines that generate

output Mealy Machine & Moore machine

 A Mealy Machine is an FSM whose output depends on

the present state as well as the present input

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 114

MEALY MODEL
MEALY MODEL

 A sequence detector is a sequential circuit that outputs 1

when a particular pattern of bits sequentially arrives at its
data input.

 Our example will detect the bit pattern “1001”:

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 115

MEALY MODEL
MEALY MODEL – SEQUENCE DETECTOR

1101 sequence detector

11011 sequence detector

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 116

MEALY MODEL
STEPS TO DESIGN MEALY MODEL - SEQUENCE DETECTOR

1. Draw the state diagram

2. Construct state table
3. Construct state table with state values
4. Determine excitation table
5. Construct the transition table
6. K-Map simplification procedures for driving expressions
7. Draw the logic diagram
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 117
MEALY MODEL – EXAMPLE-1
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “101”
1. Draw the state diagram

1/0 1/1
0/0

A B C
1/0 0/0

0/0

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 118

MEALY MODEL – EXAMPLE-1
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “101”
2. Construct state table
Present Next
State Input State Output
A 0 A 0
A 1 B 0
B 0 C 0
B 1 B 0
C 0 A 0
C 1 B 1

NOTE: For state C when input X=1 then it move to state B and produce the
output as 1. For all other cases the output remains 0.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 119
MEALY MODEL – EXAMPLE-1
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “101”
3. Construct state table with state values
Present Next
State Input State Output
Q1 Q0 X Q1 Q0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 0 1 1

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 120

MEALY MODEL – EXAMPLE-1
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “101”
4. Determine excitation table (D-Flip Flop)

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 121

MEALY MODEL – EXAMPLE-1
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “101”
5. Construct the transition table
Present Next Flip-Flop
State Input State inputs Output
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 0 1 0 1 1
NOTE: Number of flip flops required for the design is calculated based on number of
state. In this case number state is 3, so we need 2 flip flop for the design (22=4).
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 122
MEALY MODEL – EXAMPLE-1
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “101”
6. K-Map simplification procedures for driving expressions
Q0X Q0X
00 01 11 10 00 01 11 10
Q1 Q1
0 0 0 0 1 0 0 1 1 0
1 0 0 X X 1 0 1 X X
D1 = Q0X’
D0 = X
NOTE: In K-Map, we Q0X
must assume don’t care 00 01 11 10
“x” values for the Q1
remaining unknown states. 0 0 0 0 0
In this case “11” state is Z = Q1X
unknown state and its
output is “X” irrespective
1 0 1 X X
of input is 0 or 1.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 123
MEALY MODEL – EXAMPLE-1
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “101”
7. Draw the logic diagram

D1 = Q0X’
D0 = X
Z = Q1X

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 124

MEALY MODEL – EXAMPLE-2
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “1001”
1. Draw the state diagram

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 125

MEALY MODEL – EXAMPLE-2
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “1001”
2. Construct state table

NOTE: For state D when input X=1 then it move to state B and produce the
output as 1. For all other cases the output remains 0.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 126
MEALY MODEL – EXAMPLE-2
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “1001”
3. Construct state table with state values

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 127

MEALY MODEL – EXAMPLE-2
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “1001”
4. Determine excitation table

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 128

MEALY MODEL – EXAMPLE-2
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “1001”
5. Construct the transition table

NOTE: Number of flip flops required for the design is calculated based on number of
states. In this case number state is 4, so we need 2 flip flop for the design (22=4).
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 129
MEALY MODEL – EXAMPLE-2
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “1001”
6. K-Map simplification procedures for driving expressions

Q0X Q0X
00 01 11 10 00 01 11 10
Q1 Q1
0 0 0 0 1 0 X X X X
1 X X X X 1 0 1 1 1

J1 = Q0X’ K1 = X + Q0

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 130

MEALY MODEL – EXAMPLE-2
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “1001”

Q0X Q0X
00 01 11 10 00 01 11 10
Q1 Q1
0 0 1 X X 0 X X 0 1

1 1 1 X X 1 X X 0 1

J0 = Q1+X K0 = X’
Q0X
00 01 11 10
Q1
0 0 0 0 0
Z = Q1Q0X
1 0 0 1 0
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 131
MEALY MODEL – EXAMPLE-2
STEPS TO DESIGN MEALY MODEL – SEQUENCE DETECTOR “1001”
7. Draw the logic diagram

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 132

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 133
MOORE MODEL

 Moore machine is an FSM whose outputs depend on

only the present state.

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 134

MOORE MODEL
STEPS TO DESIGN MOORE MODEL - SEQUENCE DETECTOR

1. Draw the state diagram

2. Construct state table
3. Construct state table with state values
4. Determine excitation table
5. Construct the transition table
6. K-Map simplification procedures for driving expressions
7. Draw the logic diagram
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 135
MOORE MODEL – EXAMPLE-1
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “101”
1. Draw the state diagram

1 1
0

A B C D
0 1 0 0 0 1 1

0
0

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 136

MOORE MODEL – EXAMPLE-1
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “101”
2. Construct state table
Present Next
State Input State Output
A 0 A 0
A 1 B 0
B 0 C 0
B 1 B 0
C 0 A 0
C 1 D 0
D 0 C 1
D 1 B 1

NOTE: In the given state table, the output will be 1 whenever its present
state is “D” irrespective of input X(0 or 1). For all other states output
remains 0.
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 137
MOORE MODEL – EXAMPLE-1
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “101”
3. Construct state table with state values
Present Next
State Input State Output
Q1 Q0 X Q1 Q0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 1 0 1
1 1 1 0 1 1

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 138

MOORE MODEL – EXAMPLE-1
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “101”
4. Determine excitation table

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 139

MOORE MODEL – EXAMPLE-1
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “101”
5. Construct the transition table
Present Next Flip-Flop
State Input State inputs Output
Q1 Q0 X Q1 Q0 D1 D0 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 1 1 1 1 0
1 1 0 1 0 1 0 1
1 1 1 0 1 0 1 1
NOTE: Number of flip flops required for the design is calculated based on number of
state. In this case number state is 4, so we need 2 flip flop for the design (22=4).
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 140
MOORE MODEL – EXAMPLE-1
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “101”
6. K-Map simplification procedures for driving expressions
Q0X Q0X
00 01 11 10 00 01 11 10
Q1 Q1
0 0 0 0 1 0 0 1 1 0
1 0 1 0 1 1 0 1 1 0
D1 = Q0X’+Q1Q0’X
D0 = X
Q0X
NOTE: In Moore model, 00 01 11 10
the output expression (Z)
Q1
depends only on present 0 0 0 0 0
state values (Q1 & Q0) Z = Q1Q0
not on the input (X). 1 0 0 1 1
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 141
MOORE MODEL – EXAMPLE-1
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “101”
7. Draw the logic diagram

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 142

MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
1. Draw the state diagram

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 143

MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
2. Construct state table
Present State Input Next State Output
A 0 A 0
A 1 B 0
B 0 C 0
B 1 B 0
C 0 D 0
C 1 B 0
D 0 A 0
D 1 E 0
E 0 C 1
E 1 B 1
NOTE: In the given state table, the output will be 1 whenever its present
state is “E” irrespective of input X (0 or 1).
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 144
MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
3. Construct state table with state values
Present State Input Next State Output
Q2 Q1 Q0 X Q2 Q1 Q0 Z
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 0 1 0
0 1 1 0 0 0 0 0
0 1 1 1 1 0 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 0 1 1
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 145
MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
4. Determine excitation table

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 146

MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
5. Construct the transition table
Present State Input Next State Flip-Flop Inputs Output
Q2 Q1 Q0 X Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Z
0 0 0 0 0 0 0 0 X 0 X 0 X 0
0 0 0 1 0 0 1 0 X 0 X 1 X 0
0 0 1 0 0 1 0 0 X 1 X X 1 0
0 0 1 1 0 0 1 0 X 0 X X 0 0
0 1 0 0 0 1 1 0 X X 0 1 X 0
0 1 0 1 0 0 1 0 X X 1 1 X 0
0 1 1 0 0 0 0 0 X X 1 X 1 0
0 1 1 1 1 0 0 1 X X 1 X 1 0
1 0 0 0 0 1 0 X 1 1 X O X 1
1 0 0 1 0 0 1 X 1 0 X 1 X 1
NOTE: Number of flip flops required for the design is calculated based on number of
state. In this case number state is 5, so we need 3 flip flop for the design (23=8).
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 147
MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
6. K-Map simplification procedures for driving expressions
Q0X Q0X
Q2Q1 00 01 11 10 Q2Q1 00 01 11 10
00 0 0 0 0 00 X X X X
01 0 0 1 0 01 X X X X
11 X X X X 11 X X X X
10 X X X X 10 1 1 X X
J2 = Q1Q0X K2 = 1

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 148

MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
6. K-Map simplification procedures for driving expressions
Q0X Q0X
Q2Q1 00 01 11 10 Q2Q1 00 01 11 10
00 0 0 0 1 00 X X X X
01 X X X X 01 0 1 1 1
11 X X X X 11 X X X X
10 1 0 X X 10 X X X X
J1 = Q2X’+Q0X’ K1 = X+Q0

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 149

MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
6. K-Map simplification procedures for driving expressions
Q0X Q0X
Q2Q1 00 01 11 10 Q2Q1 00 01 11 10
00 0 1 X X 00 X X 0 1
01 1 1 X X 01 X X 1 1
11 X X X X 11 X X X X
10 0 1 X X 10 X X X X
J0 = X+Q1 K0 = X’+Q1

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 150

MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
6. K-Map simplification procedures for driving expressions

Q0X
Q2Q1 00 01 11 10
00 0 0 0 0
01 0 0 0 0
11 X X X X

NOTE: In Moore model,

10 1 1 X X
the output expression (Z)
depends only on present Z = Q2
state values (Q2) not on
the input (X).
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 151
MOORE MODEL – EXAMPLE-2
STEPS TO DESIGN MOORE MODEL – SEQUENCE DETECTOR “1001”
7. Draw the logic diagram
Z

Q2 Q2’ Q1 Q1’ Q0 Q0’

J2 clk K2 J1 clk K1 J0 clk K0

HIGH
clk

X’
X
MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 152