V.

PRAKASH
Asst. Professor, SENSE,
VIT Chennai

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 1

Design of Sequential Logic Circuits
Latches, Flip-Flops-SR, D, JK & T, Buffer Registers, Shift
Registers-SISO, SIPO, PISO,PIPO, Design of synchronous
sequentialcircuits: State table and state diagrams, Design of
counters: Modulo-n, Johnson, Ring, Up/Down,
Asynchronous counter. Modeling of sequential logic circuits
using Verilog HDL.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 2

3

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 3

TYPES OF DIGITAL SYSTEM

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 4

COMBINATIONAL LOGIC CIRCUITS

 Combinational logic circuits are designed by combining the basic logic gates
output is determined from the present combination of inputs

 A combinational logic circuit can be described by ‘m’ Boolean functions and

each output can be expressed in terms of ‘n’ input variables.

Block diagram of a combinational logic circuit

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 5
SEQUENTIAL LOGIC CIRCUITS
 In many applications, digital outputs are required to be generated in
accordance with the sequence in which the input signals are received, this
requirement can’t be satisfied with combinational circuits.

 In sequential logic circuits, it consists of combinational circuits to which memory

elements are connected to form a feedback path.

 The memory elements are devices (Flip-Flop) capable of storing binary

information either 1 or 0.

 The information stored in the memory elements at any given time defines the
present state of the sequential circuit.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 6
SEQUENTIAL LOGIC CIRCUITS
 The present state and the external circuit determine the output and the next
state of sequential circuits.

 Thus in sequential circuits, the output variables depend not only on the
present input variables but also on the past history of input variables.

Block diagram of a Sequential logic circuit

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 7
APPLICATIONS OF SEQUENTIAL LOGIC CIRCUIT
 Major application of sequential circuits is to build up the memory unit, from
small memory card to a huge computer memory

 Other applications of sequential logic circuits includes:

 Counters
 Shift registers
 Analog to digital and digital to analog converters
 Used as registers inside microprocessors and controllers
 Applied in programmable devices such as CPLD, PLD, and FPGA
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 8
9

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 9

LATCH
 Latches and Flip-Flops are the basic building blocks of the most sequential
circuits.

 Latches checks all of its inputs continuously and changes its outputs
accordingly at any time independent of clocking signal.

 Enable signal is provided with the latch circuit, when enable signal is active
output changes occur as the input changes else it do not affect the output.

 Flip-Flop is used for a sequential device that normally samples its inputs and
changes its outputs only at times determined by clocking signal.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 10

SR-LATCH USING NAND GATE
 The simplest type of latch is the set-reset (SR) latch, it can be constructed
from either two NOR gates or two NAND gates.

 The two NAND gates are cross-coupled so that the output of NAND gate 1 is
connected to one of the inputs of NAND gate 2 and vice versa. The latch has
two stable outputs Q and Q’ and two inputs, set and reset.

Logic Symbol SR latch using NAND gates

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 11
SR-LATCH USING NAND GATE
 To analyse the SR latch, recall that a logic 0 at any input of a NAND gate
forces its output to a logic 1.
Case 1: S= 0 and R= 0 Case 3: S= 1 and R= 0
(Initially, Q= 1 and Q’= 0) (Initially, Q= 1 and Q’= 0)

Case 2: S= 0 and R= 1 Case 4: S= 1 and R= 1

(Initially, Q= 0 and Q’= 1) (Initially, Q= 0 and Q’= 1)

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 12

SR-LATCH USING NAND GATE

Present state Next state

S R State
Qn Q’n Qn+1 Q’n+1
0 0 0 1 X X
Indeterminate*
0 0 1 0 X X
0 1 0 1 1 0
Set
0 1 1 0 1 0
1 0 0 1 0 1
Reset
1 0 1 0 0 1
1 1 0 1 0 1
No Change (NC)
1 1 1 0 1 0
Truth Table
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 13
SR-LATCH USING NOR GATE
 The SR latch can also be implemented using NOR gates.

 To understand how this circuit functions, recall that a HIGH on any input to a
NOR gate forces its output LOW.

Logic Symbol SR latch using NOR gates

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 14

SR-LATCH USING NOR GATE

Present state Next state

S R State
Qn Q’n Qn+1 Q’n+1
0 0 0 1 0 1
No Change (NC)
0 0 1 0 1 0
0 1 0 1 0 1
Reset
0 1 1 0 0 1
1 0 0 1 1 0
Set
1 0 1 0 1 0
1 1 0 1 x x
Indeterminate*
1 1 1 0 x x
Truth Table
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 15
GATED SR-LATCH USING NAND GATE
 In the SR latch, the output changes occur immediately after the input changes
i.e, the latch is sensitive to its S and R inputs all the time.

 A latch that is sensitive to the inputs only when an enable input is active is
known as gated SR latch. The circuit behaves like SR latch when EN= 1. It
retains its previous state when EN= 0.

Logic Symbol Gated SR latch using NAND gates

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 16
GATED SR-LATCH USING NAND GATE

Present state Next state

E S R State
Qn Q’n Qn+1 Q’n+1
1 0 0 0 1 0 1
No Change
1 0 0 1 0 1 0
1 0 1 0 1 0 1
Reset
1 0 1 1 0 0 1
1 1 0 0 1 1 0
Set
1 1 0 1 0 1 0
1 1 1 0 1 X X
Indeterminate*
1 1 1 1 0 X X
0 X X 0 1 0 1
No Change
0 X X 1 0 1 0

Truth Table Output waveform

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 17

18

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 18

TRIGGERING OF FLIP-FLOPS
 The state of a Flip-Flop is switched by a momentary change in the input
signal is called a trigger and it causes the transition in the Flip-Flop.

 Level Triggering: The output state is allowed to change according to inputs

when active (either positive or negative) is maintained at enable input.

 Latches are controlled by enable signal, and they are level triggered.
(i). High level triggered: The output of the latch responds to the input changes
only when the enable input is 1(HIGH).
(ii). Low level triggered: The output of the latch responds to the input changes
only when the enable input is 0 (LOW).
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 19
TRIGGERING OF FLIP-FLOPS
 Edge Triggering: The output responds to the changes in the input only at the
positive or negative edges of the clock pulse at the clock input.

 Flip-flops are triggered by clock pulses, it from an initial value of 0, goes

momentarily to 1 and after a short time, returns to its initial 0 value.

 Flip-Flops are different from latches because pulse or clock edge triggered
instead of level triggered.
(i). Positive edge triggering: Here the output responds to the changes in the input only
at the positive edge of the clock pulse at the clock input.
(ii). Negative edge triggering: Here the output responds to the changes in the input
only at the negative edge of the clock pulse at the clock input.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 20
TRIGGERING OF FLIP-FLOPS

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 21

FLIP-FLOPS
 Flip-flops can be constructed using NAND or NOR gates.

 The basic 1-bit digital memory circuit is known as a flip-flop. Flip-Flops are
synchronous bistable devices (has two outputs Q and Q’).

 If Q is 1 i.e., Set, then Q' is 0; if Q is 0 i.e., Reset, then Q' is 1 which signify
that the output Q and Q' are always complementary to each other.

 The term synchronous means that the output changes state only at a specified
point on the triggering input called the clock (CLK)

 There are different types of flip-flops depending on how their inputs and
clock pulses cause transition between two states.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 22
SR FLIP-FLOPS
 There are four types of flip-flops namely SR, D, JK, and T. Basically D, JK,
and T are three different modifications of the S-R flip-flop.

 When S is HIGH and R is LOW, the Q output goes HIGH on the triggering
edge of the clock pulse, and the Flip-Flop is SET.

 When S is LOW and R is HIGH, the Q output goes LOW on the triggering
edge of the clock pulse, and the Flip-Flop is RESET.

 When both S, R are LOW, the output does not change from its prior state.

 An invalid condition exists when both S and R are HIGH.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 23
SR FLIP-FLOPS

Logic Symbol

Logic diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 24

SR FLIP-FLOPS

Present state Next state K-Map

CLK S R State
Qn Q’n Qn+1 Q’n+1
0 0 0 1 0 1
↑ No Change
0 0 1 0 1 0
0 1 0 1 0 1
↑ Reset
0 1 1 0 0 1
1 0 0 1 1 0
↑ Set
1 0 1 0 1 0 Characteristic equation
1 1 0 1 X X
↑ Indeterminate* Qn+1=S + R’Qn
1 1 1 0 X X
X X 0 1 0 1 A characteristic equation is the simplified
↓ No Change
X X 1 0 1 0 expression derived from the truth table of the
specified flip flop to represent its behavior
Truth table under different combinations of inputs.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 25

SR FLIP-FLOPS

Present state Next state Inputs

Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Excitation table

The excitation table used to find the Flip-Flop input Input and output waveform
conditions that will cause the required transition, when the
present state (Qn) and the next state (Qn+1) are known.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 26

SR FLIP-FLOPS

VERILOG HDL CODE (Behavioural):

TEST BENCH:
module SR_FF(Q,QB,S,R,CLK);
module SR_FF_TB;
input S,R,CLK;
reg S, R, CLK;
output Q,QB;
wire Q, QB;
reg Q,QB;
SR_FF uut (.Q(Q), .QB(QB), .S(S), .R(R), .CLK(CLK));
always @(posedge CLK)
always #100 CLK=~CLK;
begin
initial
case({S,R})
begin
2'b00:Q=Q;
CLK=1;
2'b01:Q=0;
#200 S=1; R=0;
2'b10:Q=1;
#200 S=0; R=0;
2'b11:Q=1'bx;
#200 S=0; R=1;
endcase
#200 S=1; R=1;
QB=~Q;
end
end
endmodule
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 27

D FLIP-FLOPS

 The D Flip-Flop is similar to D-latch except clock pulse is used instead of

enable input.

 In D Flip-Flop the basic SR Flip-Flop is used with complemented inputs.

 To eliminate the undesirable condition of the indeterminate state in the SR

Flip-Flop is to ensure that inputs S and R are never equal to 1 at the same
time. This is done by D Flip-Flop.

 The D (delay or data) Flip-Flop has one input called delay input and clock
pulse input.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 28
D FLIP-FLOPS

Logic Symbol

Logic diagram

D Flip-flop using SR

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 29

D FLIP-FLOPS

Present state Next state K-Map

CLK D State
Qn Q’n Qn+1 Q’n+1
0 0 1 0 1
↑ Reset Characteristic equation
0 1 0 0 1
1 0 1 1 0 Qn+1= D
↑ Set
1 1 0 1 0
X 0 1 0 1
↓ No Change
X 1 0 1 0
Truth table

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 30

D FLIP-FLOP

Present state Next state Inputs

Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Input and output waveform
Excitation table

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 31

D FLIP-FLOPS

TEST BENCH:
VERILOG HDL CODE (Behavioural): module D_FF_TB;
module D_FF(Q,QB,D,CLK); reg D,CLK;
input D,CLK; wire Q, QB;
output Q,QB; D_FF uut (.Q(Q), .QB(QB), .D(D), .CLK(CLK));
reg Q,QB; always #100 CLK=~CLK;
always @(posedge CLK) initial
begin begin
Q=D; CLK=1;
QB=~Q; #200 D=1;
end #200 D=0;
endmodule end
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 32

JK FLIP-FLOP
 JK means Jack Kilby, Texas Instrument (TI) Engineer, who invented IC in 1958.

 JK Flip-Flop has two inputs J(set) and K(reset). A JK Flip-Flop can be

obtained from the clocked SR Flip-Flop by augmenting two AND gates.

 The data input J and the output Q’ are applied to the first AND gate and its
output (JQ’) is applied to the S input of SR Flip-Flop.

 Similarly, the data input K and the output Q is applied to the second AND
gate and its output (KQ) is applied to the R input of SR Flip-Flop.

 The function of JK flip flop using SR flip flop and AND gate can also be
performed by adding extra input terminal to input terminals of NAND gates.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 33
JK FLIP-FLOP

Logic Symbol

Logic diagram

JK Flip-flop using SR
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 34
JK FLIP-FLOP

Present state Next state

CLK J K State K-Map
Qn Q’n Qn+1 Q’n+1
0 0 0 1 0 1
↑ No Change
0 0 1 0 1 0
0 1 0 1 0 1
↑ Reset
0 1 1 0 0 1
1 0 0 1 1 0
↑ Set
1 0 1 0 1 0
1 1 0 1 1 0 Characteristic equation
↑ Toggle
1 1 1 0 0 1 Qn+1 = JQn’ + K’Qn
X X 0 1 0 1
↓ No Change
X X 1 0 1 0
Truth table

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 35

JK FLIP-FLOP

Present state Next state Inputs

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Excitation table Input and output waveform

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 36

JK FLIP-FLOPS

VERILOG HDL CODE (Behavioural):

TEST BENCH:
module JK_FF(Q,QB,J,K,CLK);
module JK_FF_TB;
input J,K,CLK;
reg J, K, CLK;
output Q,QB;
wire Q, QB;
reg Q,QB;
JK_FF uut (.Q(Q), .QB(QB), .J(J), .K(K), .CLK(CLK));
always @(posedge CLK)
always #100 CLK=~CLK;
begin
initial
case({J,K})
begin
2'b00:Q=Q;
CLK=1;
2'b01:Q=0;
#200 J=1;K=0;
2'b10:Q=1;
#200 J=0; K=0;
2'b11:Q=~Q;
#200 J=0; K=1;
endcase
#200 J=1; K=1;
QB=~Q;
end
end
endmodule
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 37

T FLIP-FLOP
 The T (Toggle) Flip-Flop is a modification of the JK Flip-Flop. It is obtained
from JK Flip-Flop by connecting both inputs J and K together, i.e., single input.

 Regardless of the present state, the Flip-Flop complements its output when the
clock pulse occurs while input T= 1.

Logic Symbol
T Flip-flop using JK
Logic diagram
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 38
T FLIP-FLOP

Present state Next state K-Map

CLK T State
Qn Q’n Qn+1 Q’n+1
0 0 1 0 1
↑ No Change Characteristic equation
0 1 0 1 0
1 0 1 1 0 Qn+1= TQn’ + T’Qn
↑ Toggle
1 1 0 0 1
X 0 1 0 1
↓ No Change
X 1 0 1 0
Truth table

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 39

T FLIP-FLOP

Present state Next state Inputs

Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0 Input and output waveform
Excitation table

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 40

T FLIP-FLOPS

TEST BENCH:
VERILOG HDL CODE (Behavioural): module T_FF_TB;
module T_FF(Q,QB,T,CLK); reg T,CLK;
input T,CLK; wire Q, QB;
output Q,QB; T_FF uut (.Q(Q), .QB(QB), .T(T), .CLK(CLK));
reg Q,QB; always #100 CLK=~CLK;
always @(posedge CLK) initial
begin begin
case(T) CLK=1;
1'b0:Q=Q; #200 T=0;
1'b1:Q=~Q; #200 T=1;
endcase #200 T=0;
QB=~Q; #200 T=1;
end end
endmodule endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 41

42

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 42

TYPES OF COUNTER
 Counter is a sequential logic circuit used to performs counting operation
(either incrementing or decrementing) by connecting group of Flip- Flops.

 The number of Flip-Flops used and the way in which they are connected
determine the number of states (called the modulus) and also the specific
sequence of states that the counter goes through during each complete cycle.

 Counters are classified into two types according to the way they are clocked:
 Synchronous counters : clock input is connected to all of the Flip-Flops so that they
are clocked simultaneously
 Asynchronous counters : clocked by the external clock pulse and then each
successive Flip-Flop is clocked by the output of the preceding Flip-Flop.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 43
SYNCHRONOUS vs ASYNCHRONOUS COUNTER
S.No Asynchronous (ripple) counter Synchronous counter
1 All the Flip-Flops are not clocked simultaneously. All the Flip-Flops are clocked simultaneously.
2 The delay times of all Flip-Flops are added. There is minimum propagation delay.
Therefore there is considerable propagation
delay.
3 Speed of operation is low Speed of operation is high.
4 Logic circuit is very simple even for more number Design involves complex logic circuit as number
of states. of state increases.
5 Cheaper than synchronous counters. Costlier than ripple counters.
6 Example: Example:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 44

3-BIT SYNCHRONOUS UP COUNTER

Logic diagram Timing diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 45

4-BIT SYNCHRONOUS UP COUNTER

Logic diagram Timing diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 46

4-BIT SYNCHRONOUS UP COUNTER
VERILOG HDL CODE (Behavioural):
TEST BENCH:
module UP_COUNTER(COUNT, CLK, RESET);
module UP_COUNTER_TB;
input CLK, RESET; reg CLK, RESET;
output [3 : 0] COUNT; wire [3:0] COUNT;
reg [3:0] COUNT = 0; // Instantiate the Unit Under Test (UUT)
UP_COUNTER uut (.COUNT(COUNT), .CLK(CLK), .RESET(RESET));
always @(posedge CLK or posedge RESET)
initial CLK = 0;
begin always #10 CLK = ~CLK;
if(RESET==1) initial
begin
COUNT<=0;
RESET = 0;
else #400;
COUNT <= COUNT + 1; RESET = 1;
end
end
endmodule
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 47

4-BIT SYNCHRONOUS UP COUNTER

OUTPUT WAVEFORM:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 48

4-BIT SYNCHRONOUS DOWN COUNTER

Logic diagram Timing diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 49

4-BIT SYNCHRONOUS DOWN COUNTER
VERILOG HDL CODE (Behavioural):
TEST BENCH:
module DOWN_COUNTER(COUNT, CLK, RESET);
module DOWN_COUNTER_TB;
input CLK, RESET; reg CLK, RESET;
output [3 : 0] COUNT; wire [3:0] COUNT;
reg [3:0] COUNT = 0; // Instantiate the Unit Under Test (UUT)
DOWN_COUNTER uut (.COUNT(COUNT), .CLK(CLK),
always @(posedge CLK or posedge RESET)
.RESET(RESET));
begin initial CLK = 0;
if(RESET==1) always #10 CLK = ~CLK;
initial
COUNT<=0;
begin
else RESET = 0;
COUNT <= COUNT - 1; #400;
RESET = 1;
end
end
endmodule endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 50

4-BIT SYNCHRONOUS DOWN COUNTER

OUTPUT WAVEFORM:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 51

3-BIT SYNCHRONOUS UP/DOWN COUNTER

Logic diagram Timing diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 52

3-BIT SYNCHRONOUS UP/DOWN COUNTER
VERILOG HDL CODE (Behavioural):
module UP_DOWN_COUNTER(COUNT, CLK, UP_DOWN, RESET);
input CLK, UP_DOWN, RESET;
output [2 : 0] COUNT;
reg [2:0] COUNT = 0;
always @(posedge CLK or posedge RESET)
begin
if(RESET==1)
COUNT<=0;
else
if(UP_DOWN == 1) //Up mode selected
if(COUNT == 7)
COUNT <= 0;
else
COUNT <= COUNT + 1; //Increment Counter
else //Down mode selected
if(COUNT == 0)
COUNT <= 7;
else
COUNT <= COUNT - 1; //Decrement counter
end
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 53

3-BIT SYNCHRONOUS UP/DOWN COUNTER
TEST BENCH:
module UP_DOWN_COUNTER_TB;
reg CLK, RESET;
reg UP_DOWN;
wire [2:0] COUNT;
// Instantiate the Unit Under Test (UUT)
UP_DOWN_COUNTER uut (.COUNT(COUNT),.CLK(CLK), .UP_DOWN(UP_DOWN), .RESET(RESET));
initial CLK = 0;
always #10 CLK = ~CLK;
initial
begin
RESET = 0; UP_DOWN = 1;
#200;
UP_DOWN = 0;
#200;
end
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 54

3-BIT SYNCHRONOUS UP/DOWN COUNTER

OUTPUT WAVEFORM:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 55

SYNC. MOD COUNTER DESIGN

 The counter can be designed using any types of Flip flop. But in general
T-Flip flop is used to design counter.

 The use of MOD counter in to counter value for specific number of times.

 For example, MOD-5 Counter means it can counter the values from 0 to 4
and it get reset. So, it count in the sequence of
000,001,0110,011,100,000,001,etc.,

 The number of flip flop required to design MOD counter is depends on the
number of count it performs.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 56
SYNC. MOD COUNTER DESIGN

 Steps involved in Synchronous MOD counter design

1. Determine the number of Flip-Flop needed

2. Choose the type of Flip Flop and its excitation table

3. Determine Transition table

4. K-Map simplification procedures for driving expressions

5. Draw the logic diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 57
EXAMPLE:1 DESIGN OF MOD-6 COUNTER USING JK FLIP FLOP

 Step-1: Find number of Flip-flips required to build the counter

Flip-flops required are 2n ≥N-1
Here N-1=5, therefore n=3

 Step-2: Excitation table for JK Flip-flop

Present state Next state Inputs
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 58
EXAMPLE:1 DESIGN OF MOD-6 COUNTER USING JK FLIP FLOP

 Step-3: Determine the transition table

Present State Next State Flip-flop inputs
QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0 X X 1
1 1 0 X X X X X X X X X
1 1 1 X X X X X X X X X

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 59

EXAMPLE:1 DESIGN OF MOD-6 COUNTER USING JK FLIP FLOP
 Step-4: K-Map simplification for Flip-flop inputs
For JA For JB For JC

JA= QBQC JB= QA’QC JC = 1

For KA For KB For KC

KA= QC KB= QC KC = 1
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 60
EXAMPLE:1 DESIGN OF MOD-6 COUNTER USING JK FLIP FLOP

 Step-5: Draw logic diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 61

EXAMPLE:1 DESIGN OF MOD-6 COUNTER USING JK FLIP FLOP

VERILOG HDL CODE (Behavioural): TEST BENCH:

module MOD6_COUNTER(COUNT, CLK, RESET);
module MOD6_COUNTER_TB;
input CLK, RESET;
reg CLK, RESET;
output [2 : 0] COUNT;
wire [2:0] COUNT;
reg [2:0] COUNT = 0;
always @(posedge CLK or posedge RESET) // Instantiate the Unit Under Test (UUT)
begin MOD6_COUNTER uut (.COUNT(COUNT), .CLK(CLK), .RESET(RESET));
if(RESET==1) initial CLK = 0;
COUNT<=0; always #10 CLK = ~CLK;
else initial
if(COUNT == 5) begin
COUNT <= 0; RESET = 0;
else #400;
RESET = 1;
COUNT <= COUNT + 1; end
end
endmodule
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 62

EXAMPLE:2 DESIGN OF MOD-6 COUNTER USING T FLIP FLOP

 Step-1: Find number of Flip-flips required to build the counter

Flip-flops required are 2n ≥N-1
Here N-1=5, therefore n=3

 Step-2: Excitation table for T Flip-flop

Present state Next state Inputs
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 63
EXAMPLE:2 DESIGN OF MOD-6 COUNTER USING T FLIP FLOP

 Step-3: Determine the transition table

Present State Next State Flip-Flop inputs
QA QB QC QA+1 QB+1 QC+1 TA TB TC
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 0 0 0 1 0 1
1 1 0 X X X X X X
1 1 1 X X X X X X

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 64

EXAMPLE:2 DESIGN OF MOD-6 COUNTER USING T FLIP FLOP
 Step-4: K-Map simplification for Flip-flop inputs
For TA For TB For TC

TA= QAQC+QBQC TB= QA’QC TC = 1

 Step-5: Draw logic diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 65

EXAMPLE:3 DESIGN OF MOD-8 UP/DOWN COUNTER USING T FLIP FLOP

 Step-1: Find number of Flip-flips required to build the counter

Flip-flops required are 2n ≥N-1 State Transition Diagram
Here N-1=7, therefore n=3

 Step-2: Excitation table for T Flip-flop

Present state Next state Inputs
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
• When M=0 ,then the counter will perform up counting.
1 1 0 • When M=1 ,then the counter will perform down counting.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 66

EXAMPLE:3 DESIGN OF MOD-8 UP/DOWN COUNTER USING T FLIP FLOP
 Step-3: Determine the transition table
Present State Next State Flip-Flop inputs
M Q3 Q2 Q1 Q*3 Q*2 Q*1 T3 T2 T1
0 0 0 0 0 0 1 0 0 1
0 0 0 1 0 1 0 0 1 1
0 0 1 0 0 1 1 0 0 1
0 0 1 1 1 0 0 1 1 1
0 1 0 0 1 0 1 0 0 1
0 1 0 1 1 1 0 0 1 1
0 1 1 0 1 1 1 0 0 1
0 1 1 1 0 0 0 1 1 1
1 0 0 0 1 1 1 1 1 1
1 0 0 1 0 0 0 0 0 1
1 0 1 0 0 0 1 0 1 1
1 0 1 1 0 1 0 0 0 1
1 1 0 0 0 1 1 1 1 1
1 1 0 1 1 0 0 0 0 1
1 1 1 0 1 0 1 0 1 1
1 1 1 1 1 1 0 0 0 1

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 67

EXAMPLE:3 DESIGN OF MOD-8 UP/DOWN COUNTER USING T FLIP FLOP
 Step-4: K-Map simplification for Flip-flop inputs

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 68

EXAMPLE:3 DESIGN OF MOD-8 UP/DOWN COUNTER USING T FLIP FLOP
 Step-5: Draw logic diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 69

2-BIT ASYNCHRONOUS UP COUNTER

 In 2-bit asynchronous binary counter, the clock (CLK) is applied to the clock
input of first Flop-Flop(FF) which is always the least significant bit (LSB).

 The second Flip-Flop is triggered by the QA, but changes only when FF is
triggered by a negative-going pulse of the QA.

 Because of the inherent propagation delay time through a FF, input clock
pulse (CLK) and a transition of the QA never occur at exactly the same time.

 Therefore, the two Flip-Flops are never simultaneously triggered, so the

counter operation is asynchronous.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 70
2-BIT ASYNCHRONOUS UP COUNTER

Logic diagram Timing diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 71

2-BIT ASYNCHRONOUS UP COUNTER - OPERATION

Condition Operation
Initially let both the FFs
• QBQA = 00 initially
be in the reset state
• As soon as the 1st negative clock edge is applied, FF-A will toggle and QA will be equal to 1.
After 1st negative clock • QA is connected to clock input of FF-B, since QA has changed from 0 to 1, it is treated as the positive clock
edge edge by FF-B. There is no change in QB because FF-B is a negative edge triggered FF.
• QBQA = 01 after the first clock pulse.
• On the arrival of 2nd negative clock edge, FF-A toggles again and QA = 0.
After 2nd negative
• The change in QA acts as a negative clock edge for FF-B, so it will also toggle and QB will be 1.
clock edge • QBQA = 10 after the second clock pulse.
• On the arrival of 3rd negative clock edge, FF-A toggles again and QA become 1 from 0.
After 3rd negative
• Since this is a positive edge, FF-B does not respond so QB does not change and continues to be equal to 1.
clock edge • QBQA = 11 after the third clock pulse.
• On the arrival of 4th negative clock edge, FF-A toggles again and QA becomes 0 from 1.
After 4th negative
• This negative change in QA acts as clock pulse for FF-B, hence it toggles to change QB from 1 to 0.
clock edge • QBQA = 00 after the fourth clock pulse.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 72

3-BIT ASYNCHRONOUS UP COUNTER

Logic diagram Timing diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 73

4-BIT ASYNCHRONOUS UP COUNTER

Logic diagram Timing diagram

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 74

4-BIT ASYNCHRONOUS UP COUNTER

VERILOG HDL CODE (Behavioural):

module counter( clk, count );
TEST BENCH:
input clk;
output[3:0] count; module counter_tb;
reg[3:0] count; reg clk;
wire clk; wire [3:0] count;
Initial count = 4'b0000;
always @( negedge clk ) // Instantiate the Unit Under Test (UUT)
count[0] <= ~count[0]; counter uut (.count(count), .clk(clk));
always @( negedge count[0] ) initial clk = 0;
count[1] <= ~count[1];
always @( negedge count[1] ) always #10 clk = ~clk;
count[2] <= ~count[2]; endmodule
always @( negedge count[2] )
count[3] <= ~count[3];
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 75

4-BIT ASYNCHRONOUS UP COUNTER

OUTPUT WAVEFORM:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 76

4-BIT ASYNCHRONOUS DOWN COUNTER

Logic diagram

Timing diagram
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 77
78

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 78

SHIFT REGISTERS
 A register is simply a group of Flip-Flops that can be used to store a binary
number and there must be one Flip-Flop for each bit in the binary number.

 The Flip-Flops must be connected such that the binary number can be entered
(shifted) into the register and possibly shifted out.

 A group of Flip-Flops connected to provide either or both of these functions is

called a shift register.

 The bits in a binary number (data) can be removed from one place to
another in either of two ways.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 79

SHIFT REGISTERS - TYPES
 Serial shifting: Shifting the data one bit at a time in a serial fashion,
beginning with either MSB or the LSB

 parallel shifting: Shifting all the data bits simultaneously

 There are two ways to shift into a register (serial or parallel) and similarly
two ways to shift the data out of the register.

 This leads to the construction of four basic register types:

 Serial In- Serial Out (SISO)
 Serial In- Parallel Out (SIPO)
 Parallel In- Serial Out (PISO)
 Parallel In- Parallel out(PIPO)
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 80
SHIFT REGISTERS - TYPES

Serial-in Serial-out

Parallel-in Serial-out Parallel-in Parallel-out

Serial-in Parallel-out
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 81
SISO SHIFT REGISTERS
 The serial in/serial out shift register accepts data serially, i.e., one bit at a
time on a single line. It produces the stored information on its output also in
serial form.

Serial-in Serial-out shift register

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 82

SISO SHIFT REGISTERS – EXAMPLE (If 1010 is applied)

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 83

SISO SHIFT REGISTERS
VERILOG HDL CODE (Behavioural): TEST BENCH:
module tb_siso;
module siso(si,so,clk);
reg si, clk;
input si,clk; wire so;
output so; siso s1(si,so,clk);
initial
reg so; begin
reg [3:0] temp; clk=1'b1;
si=0;
always@(posedge clk)
#10 si=1;
begin #10 si=0;
so=temp[3]; #10 si=1;
end
temp[0]=si;
always
temp[3:1]=temp[2:0]; begin
end #5 clk=~clk;
end
endmodule endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 84

SISO SHIFT REGISTERS
OUTPUT WAVEFORM:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 85

SIPO SHIFT REGISTERS
 In this shift register, data bits are entered into the register in the same as
serial-in serial-out shift register. But the output is taken in parallel.
 Once the data are stored, each bit appears on its respective output line and
all bits are available simultaneously instead of on a bit-by-bit.

Serial-in Parallel-out shift register

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 86
SIPO SHIFT REGISTERS – EXAMPLE (If 1111 is applied)

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 87

SIPO SHIFT REGISTERS
VERILOG HDL CODE (Behavioural):
TEST BENCH:
module sipo(si,clk,po);
module tb_sipo;
input si,clk; reg si,clk;
output [3:0] po; wire [3:0]po;
reg [3:0] po; sipo s1(si,clk,po);
initial clk=1'b1;
reg [3:0] temp; always #5 clk=~clk;
always @ (posedge clk) initial
begin begin
si=0;
temp[3:1]<=temp[2:0];
#10 si=1;
temp[0]<=si; #10 si=0;
po<=temp; #10 si=1;
end
end
endmodule
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 88

SIPO SHIFT REGISTERS
OUTPUT WAVEFORM:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 89

PIPO SHIFT REGISTERS
 In this type, there is simultaneous entry of all data bits and the bits appear
on parallel outputs simultaneously.

Parallel-in Parallel-out shift register

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 90
PIPO SHIFT REGISTERS

TEST BENCH:
VERILOG HDL CODE (Behavioural): module tb_pipo;
reg clk;
module pipo(pi,clk,po);
reg [3:0] pi;
input [3:0] pi; wire [3:0] po;
input clk; pipo p1(pi,clk,po);
initial clk=1'b1;
output [3:0] po;
always #5 clk=~clk;
reg [3:0] po; initial
always @ (posedge clk) begin
pi=4'b1001;
begin
#10 pi=4'b1100;
po<=pi; #10 pi=4'b0000;
end #10 pi=4'b1010;
endmodule end
endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 91

PIPO SHIFT REGISTERS
OUTPUT WAVEFORM:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 92

PISO SHIFT REGISTERS
 In this type, the input bits (X0, X1, X2 and X3) are entering data in parallel
into the register i.e., simultaneously into their respective stages.

 SHIFT/ LOAD input is the control input, when SHIFT/LOAD is LOW, gates G1,
G2, G3 and G4 are enabled, allowing each data bit to be applied to the D
input of its respective Flip-Flop.

 When a clock pulse is applied, the Flip-Flops with D = 1 will set and those
with D = 0 will reset, thereby storing all four bits simultaneously.

 When SHIFT/LOAD is HIGH, gates G1, G2, G3 and G4 are disabled and
gates G5, G6 and G7 are enabled, allowing the data bits to shift right from
one stage to the next.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 93
PISO SHIFT REGISTERS
 The OR gates allow either the normal shifting or the parallel data-entry operation,
depending on which AND gates are enabled by the SHIFT/LOAD input.

Parallel-in Serial-out shift register

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 94
PISO SHIFT REGISTERS

VERILOG HDL CODE (Behavioural):

TEST BENCH:
module piso(shift_load,clk,pi,so);
module tb_piso;
input shift_load, clk;
input [3:0] pi; reg shift_load,clk;
output so; reg [3:0] pi;
reg so, [3:0] temp; wire so;
always @ (posedge clk) piso p1(shift_load,clk,pi,so);
begin initial clk=1'b1;
if(shift_load==0) always #10 clk=~clk;
temp[3:0]<=pi[3:0]; initial begin
else pi=4'b1101;
begin shift_load = 1'b0;
so<=temp[3]; #20 shift_load = 1'b1;
temp[3:1]<=temp[2:0];
#120 pi=4'b1001; shift_load = 1'b0;
temp[0]<=0;
#20 shift_load = 1'b1;
end
end end
endmodule endmodule

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 95

PISO SHIFT REGISTERS
OUTPUT WAVEFORM:

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 96

SHIFT REGISTER COUNTER - RING
 A shift register counter is basically a shift register with the serial output
connected back to the serial input to produce special sequences.

 The ring counter is a cascaded connection of flip flops, in which the output of
last flip flop is connected to input of first flip flop.

 The input is shifted between the flip-flops in a ring shape which is why it is
known as a Ring counter.

 A typical 4-bit ring counter is made of D-flip flops connected in cascade with
the non-complemented output of the last stage connected as an input to the
first stage.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 97
SHIFT REGISTER COUNTER - RING
 Ring counter’s state needs to be set before the operation, since there are no
external inputs except the clock signal.

 For example, to set its state to initial state 1000 manually by setting the first
stage flip-flop and clearing the rest of the stages to obtain the state 1000.

 Whenever the first clock edge hits the counter the outputs of each stage shifts
to the next succeeding stage and the output of the last will shift to the first
stage making the state 0100.

 For next two consecutive clock cycles, each stage will update its state
according to its input and produces 0010 and 0001.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 98
SHIFT REGISTER COUNTER - RING
 Now upon next clock cycle, ‘1’ from the last stage will shift back to the first
stage making the initial state 1000 and it starts again from the first state.
 Ring counters can also be used for counting or rotating data around a
continuous loop, to detect or recognise various patterns.

Ring counter
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 99
SHIFT REGISTER COUNTER - RING

CLK Q0 Q1 Q2 Q3
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 0 0 1 0
8 0 0 0 1
Truth table Timing sequence

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 100

SHIFT REGISTER COUNTER – JOHNSON

 It is a modified design of ring counter, where the inverted output from the
last flip-flop is connected to the input of the first flip-flop.

 It is also known as an inverse feedback counter or twisted ring counter.

 When compared to the ring counter, it uses only half of the number of flip-
flops. So, the MOD will be 2n, if there are n flip-flops.

 A “n-stage” Johnson counter will circulate a single data bit giving sequence
of 2n different states and can be considered as a “mod-2n counter”.

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 101

SHIFT REGISTER COUNTER – JOHNSON
 This inversion of Q before it is fed back to input D causes the counter to
“count” in a different way from normal ring counter.

 The Johnson counter counts up and then down as the initial logic “1” passes
through it to the right replacing the preceding logic “0”.

 A 4-bit Johnson ring counter passes blocks of four logic “0” and then four
logic “1” thereby producing an 8-bit pattern.

 As the inverted output Q is connected to the input D this 8-bit pattern

continually repeats. For example, “1000”, “1100”, “1110”, “1111”, “0111”,
“0011”, “0001”, “0000”.
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 102
SHIFT REGISTER COUNTER – JOHNSON
 Johnson Counters can also be used to divide the frequency of the clock signal
by varying their feedback connections hence it be used as frequency divider.

 Also used as a 3 phase square wave generator, as a synchronous decade

counter, generate signals to control stepper motors etc.,

Johnson counter
MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 103
SHIFT REGISTER COUNTER - JOHNSON

CLK Q0 Q1 Q2 Q3
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0
Truth table Timing sequence

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 104

SHIFT REGISTER - APPLICATIONS

 Serial to parallel converters

 Keyboard encoders

 Universal Asynchronous Receiver Transmitter (UART)

 Pulse extender

 Data processing (Multiplication)

 Delay line memory

MODULE-5 BECE102L-DIGITAL SYSTEM DESIGN 105