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220 viewsVdocuments - MX - Sap 2 Simple As Possible Computer PDF
Uploaded by
Paula Camille PalinoCopyright
© © All Rights Reserved
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/ 22
SAP-2
SAP+I is 4 computer because it stores a program and data
before calculations begin; then it automatically carries out
the program instructions without human intervention. And
yet, SAP-I isa primitive computing machine. It compares
to a modern computer the way a Neanderthal human would
‘compare to a modern person, Something is missing, some-
thing found in every modern compute,
SAP.2 is the next step in the evolution toward modern
‘computers because it includes jump instuctions. These new
instructions force the computer to repeat or skip part of a
program. As you will discover, jump instructions open up
whole new world of computing power,
11-1 BIDIRECTIONAL REGISTERS
To reduce the wiring capacitance of SAP-2, we will run
only one set of wires between each register and the bus
Figure 11-Ia shows the idea. The input and output pins are
shorted; only one group of wires is connected to the bus
oes this shorting the input and output pins ever cause
trouble? No. During a computer run, either LOAD of
ENABLE may be active, but not both atthe sume time. An
active LOAD means that a binary word flows from the bus
to the register input; during a load operation, the output
lines are floating. On the other hand, an active ENABLE
means that a binary word flows from the register fo the
bus; in this case, the input lines float
‘The IC manufacturer can internally connect the input and
‘output pins of a three-state register. This not only reduces
the wiring capacitance; it also reduces the number of LiO
pins. For instance, Fig. 11-1b has four VO pins instead of
eight
Figure 11-Le isthe symbol for a three-state register with
internally connected input and output pins. The double
headed arrow reminds us thatthe pth is bidirectional: data
fan move either way
11-2 ARCHITECTURE
Figure 11-2 shows the architecture of SAP-2. All register
outputs to the W bus are three-state; those not connected
to the bus are two-state. As before, the contaller-sequencer
sends control signals (not shown) to each register. These
‘control signals load, enable, or otherwise prepare the register
for the next postive clock edge. A brief description of each
box is given now.
Input Ports
‘SAP-2 has two input ports, numbered 1 and 2. A hexade-
cimal keyboard encoder is connected to port 1. It allows
us to enter hexadecimal instructions and data through port,
1. Notice that the bexadccimal keyboard encoder sends &
READY signal to bit 0 of port 2. This signal indicates when
the data in port 1 is valid
Also notice the SERIAL IN signal going to pin 7 of port
2. A later example will show you how to convert serial
input data to parallel data,
Program Counter
This time, the program counter has 16 bits; therefore, it
can count from
PC = 0000 0000 0000 0000
0
Pe = ini win ant
This is equivalent to O000H to FFFFH, or decimal 0 to
65,538.
A low CER signal resets the PC before each computer
run; so the data processing starts with the instruction stored
in memory location 0000H.
173cw sidectons
te
Fig. 11-1 Bidirectional register.
MAR and Memory
During the fetch cycle, the MAR receives 16-bit addresses
from the program counter. The two-state MAR output then
addresses the ested memory location. The memory has a
2K ROM with addresses of O000H to OTFFH. This ROM
contains @ program called a monitor that initializes the
‘computer on power-up, interprets the keyboard inputs, and
so forth, The rest of the memory is a 62K RAM with
audesses from O800H to FFFFH.
Memory Data Register
‘The memory data register (MDR) is an 8-bit buer register.
Its output sets up the RAM. The memory data register
receives data from the bus before a write operation, and it
sends data to the bus after a read operation
Instruction Register
Because SAP-2 has more instructions than SAP-1, we will
use 8 bits forthe op code rather than 4. An 8-bit op code
‘can accommodate 256 instructions. SAP-2 has only 42
174 Digital computer
lectronice
instructions, so there will be no problem coding them with
B bits. Using an 8-bit op code also allows upward compat
ibility with the 8080/8085 instruction set because it is based
‘on an S-bit op code. As mentioned earlier, all SAP
instructions are identical with 8080/8085 instructions
Controller-Sequencer
‘The controller sequencer produces the control words or
microinstuctions that Coordinate and diret the rest of the
computer. Because SAP-2 has a bigger instruction set, the
controller-sequencer has more hardware. Although the CON
word is bigger, the idea is the same: the control word oF
microinstruction determines how the registers react to the
next positive clock edge.
Accumulator
‘The two-state output of the accumulator goes to the ALU;
the three-state output to the W bus. Therefore, the 8-bit
‘word in the accumulator continuously drives the ALU, but,
this same word appears on the bus only when E, is activewou
ACKNOWLEDGE —ed Hexadecimal _
‘oo
WS
tno SJ fas
ey TD) scoumucaron
TNS
Ww
reapy 1° Input
1) ee [ TZ) ww BY nse
senmn tof r7
«KEY KS
me
me KG] Ke
FY RY
w
oak Ls
wery Sek
&
won KE out LNT een
GQ Bs
= . as) ee Prmor
a fe zcrnonteoae
Ww
Fig. 1-2 SAP.2 block architecture.
ALU and Flags
Standard ALUs are commercially available as integrated
circuits. These ALUs have 4 of more contol its that
determine the arithmetic or logic operation performed on
words A and B. The ALU wsed in SAP-2 includes arithmetic
and logic operations
In this book « flag is « flip-op that keeps track of a
changing. condition during. @ computer run. The SAP-2
computer has two fags. ‘The sign flag is set when the
accumulator contents become negative during the execution
of some instrctions. The zero flag is set when the accu
:mulator contents become zero
‘TMP, B, and C Registers
Instead of using the B register to bold the data being added
or subtracted from the accumulator, a temporary (TMP)
register is used, This allows us more freedom in using the
B register. Besides the TMP and B registers, SAP-2 includes.
C register. This gives us more flexibility in moving data
during a computer run,
chapter 11 sap2 175Output Ports
SAP-2 has two output ports, numbered 3 and 4. The
contents of the accumulator can be loaded into port 3,
‘which drives a hexadecimal display. This allows us to see
the processed data
“The contents ofthe accumulator ean also be sent (0 port
4. Notice that pin 7 of port 4 sends an ACKNOWLEDGE,
signal tothe hexadecimal encoder. This ACKNOWLEDGE
signal and the READY signal are part of a concept called
handshaking, to be discussed Ister.
Also notice the SERIAL OUT signal from pin 0 of port
44; one of the examples will show you how to convert
parallel data in the accumulator into serial output data
11-3 MEMORY-REFERENCE
INSTRUCTIONS
‘The SAP2 fetch cycle is the same as before. T) is the
addres state, Tis the increment state, and T isthe memory
state. All SAP-2 instructions therefore use the memory
during the fetch cycle because @ program instruction is,
transferred from the memory to the instruction register.
‘During the execution cycle, however, the memory may
cor may not be used; it depends on the type of instruction
that has been fetched. A’ memory-reference instruction
(MRI) is one thet uses the memory during the execution
eydle.
‘The SAP.2 computer has an instruction set with 42
instructions. What follows is description of the memory-
reference instructions.
LDA and STA
LDA has the same meaning as before: [oad the accumulator
with the addressed memory data. The only difference is
that more memory locations can be accessed in SAP-2
because the addresses are from 0000H to FFFFH. For
example, LDA 2000H means to load the accumulator with
the contents of memory location 2000H,
To distinguish the different parts of an instruction, the
mnemonic is sometimes called the op code and the rest of.
‘the instruction is known asthe operand. With LDA 2000H,
LLDA is the op code and 2000H is the operand. Therefore,
“op code” has a double meaning in microprocessor work:
it may stand for the mnemonic or for the binary code used
to represent the mnemonic. The intended meaning is clear
from the context.
STA is a mnemonic for store the accumulator. Every
SSTA instruction needs an address. STA TFFFH means 10
store the accumulator contents at memory location TFFFH.
ig
A= SAH
the execution of STA TFFFH stores SAH at address 7FFFH.
176 digital computer Electronics
MvI
MVI is the mnemonic for move immediate. It tells the
computer to load a designated register with the byte that
‘immediately follows the ap code. For instance,
MVE A,37H
tells the computer to load the accumulator with 37H. After
this instruction has been executed, the binary contents of
‘the accumulator are
A= 00110111
You can use MVI with the A, B, and C registers. The
formats for these instructions are
MVI A,byte
MVI Bobyte
MVI.C.byte
Op Codes
Table 11-1 shows the op codes for the SAP-2 instruction
set, These are the 8080/8085 op codes. As you can see,
3A is the op code for LDA, 32 is the op code for STA,
ce. Refer to this table in the remainder of this chapter.
EXAMPLE 11-1
Show the mnemonies for a program that loads the accu
mutator with 49H, the B register with 44H, and the C
register with 4BH; then have the program store the accu
mulator data at memory location 6285H.
SOLUTION
Here's one program that will work
Mnemonics
MVIAA9H
MVIB4AH
MVIC4BH
STA 62851
HLT
The first three instructions load 49H, 4AH, and 4BH into
the A,B, and Cregisters. STA 6285H stores the accumulator
contents at 6285H
Note the use of HLT in this program, It has the same
meaning as before: halt the data processing,TABLE 11-1. SAP-2 OP CODES
Instruction Op Code Instruction Op Code
ADD B 80 MOV B,A a
ADD C 81 MOV B.C 41
ANAB AQ MOVGA 4F
ANAC AL MOVCB 48
ANI byte Ee MVIAbyte 3.
CALL address CD. MVIBibytc 06.
CMA 2F MVIC byte OE.
DcR A 3D NOP. 0
DCR B 05 ORAB BO
DcRC 0D RAC BI
HLT 16 ORL byte FS
IN byte DB OUT byte D3
INRA 3c RAL 7
INRB 04 RAR IF
INRC oc RET °
IM aadess FA STAaddwss 32
IMP address C3 SUBB 0
INZ address 2 SUBC 91
IZ adatess CA XRAB AB
LDA address = 3A XRAC Ao
MOV A.B 8 XRI byte BE
MOV A.C n
EXAMPLE 11-2
‘Translate the foregoing program into 8080/8085 machine
language using the op codes of Table 1-1, Start with
adress 2000H.
SOLUTION
Address Contents Symbolic
20008 3EH MVIA,9H
2001H 49H
2002H 06H MVIB4AH
2003H 4AH
2004H oEH MVIC4BH
2005H. 4BH
2006H 32H STA 6285H
2007H 89H
2008H_ oH
200981 6H BLT
‘There are a couple of new idea inthis machine-language
rogram. With the
MVIA,s91t
instruction, notice thatthe op code goes into the ist adress
and the byte into the second address. This is true ofall 2-
byte instructions: op code into the first available memory
location and byte into the next.
‘The instruction
STA 6285H
is a 3-byte instruction (1 byte for the op code and 2 forthe
address). The op code for STA is 32H. This byte goes into
the fist available memory location, which is 2006H. The
address 628SH has 2 bytes, The lower byte 85H goes into
the next memory location, and the upper byte 62H into the
next location
Why does the address get programmed with the lower
byte first and the upper byte second? This is @ peculiarity
of the original 8080 design. To keep upward compatibility,
the 8085 and some other microprocessors use the same
scheme: lower byte into lower memory, upper byte into
upper memory
The last instruction HLT has an op code of 76H, stored
in memory locaton 2009H,
In summary, the MVI instructions are 2-byte instructions,
the STA is a 3byte instruction, and the HLT is a I-byte
instruction
11-4 REGISTER INSTRUCTIONS
Memory-reference instructions are relatively slow because
they require more than one memory access during the
instrction eycle, Furthermore, we often want to move data
directly from one register to another without having to 20
through the memory. What follows are some of the SAP-
2 register instructions, designed to move data from one
register to another in the shortest possible time.
mov
MOV is the mnemonic for move. It tells the computer 10
‘move data from one register to another. For instance,
MOV A.B
tells the computer to move the data in the B register to the
accumulator. The operation is nondestructive, meaning that
the data in B is copied but not erased. For example, if
A= MH and B= 9DH
then the execution of MOV A,B results in
Chapter 11 sap2 177‘You can move data between the A, B, and C registers
The formats for all MOV instructions are
MOV A.B
MOV A.C
MOV B.A
MOV B.C
MOVC.A
MOV CB
“These instructions are the fastest in the SAP-2 instruction
set, requiring only one machine cycle.
ADD and SUB
[ADD stands for add the data in the designated register to
the accumulator. For instance,
ADD B
means to add the contents of the B register to the accu-
smulator, IF
ry
Oa and B= DH
then the execution of ADD B results in
A = 06H
‘SUB means subtract the data in the designated
register from the accumulator. SUB C will subtract the
contents of the C register from the accumulator.
‘The formats forthe ADD and SUB instructions are
ADDB
ppc
SUBB
SUBC
INR and DCR
Many times we want to increment or decrement the contents
of one of the registers, INR isthe mnemonic for increment;
it tells the computer to increment the designated register.
DCR is the mnemonic for decrement, and it instructs the
‘computer to decrement the designated register. The formats
for these instructions are
INRA
INRB
INRC
DCRA
DCRB
perc
As an example, if
B = SoH
and © = SAH
178 digital Computer Electronics
then the execution of INR B results in
sm
and the execution of a DCR C produces
c= 89H
EXAMPLE 11-3
‘Show the mnemonics for adding decimal 23 and 45. The
answer is to be stored at memory location S600H. Also,
the answer ineremented by Is tobe stored in the C register
SOLUTION =
AAs shown in Appendix 2, decimal 23 and 45 are equivalent
to ITH and 2DH, Here is a program that will do the job
Mnemonics
MVIA,ITH
MVIB.2DH
ADD B
STA S600H
INRA
MOVCA
HLT
EXAMPLE 11-4
To hand-assemble a program means to translate @ source
program into a machine-language program by hand rather
than machine. Hand-assemble the program of the preceding
‘example starting at address 20001,
SOLUTION
Address Contents Symbolic
2000H 3EH MVIA,ITH
201K v7H
2002H 6H MVIB,2DH
2003H 20H
2004H 80H ADD B.
200511 2H STA S600H
2006H OH
20078 SoH
2008H. 3cH INRA
2009H aFH MOV CA
2008H 76H HLT
Notice that the ADD, INR, MOV, and HLT instructions
are byte instructions; the MVI instructions are 2-byte
instrctions, and the STA is a 3-byte11-5 JUMP AND CALL
INSTRUCTIONS
SAP-2 has four jump instructions; these can change the
program sequence. In other words, instead of fetching the
next instruction in the usual way, the computer may jump
‘or branch to another part of the program.
aMP
‘To begin with, IMP is the mnemonic for jump; i els the
‘computer to get the next instruction from the designated
‘memory location. Every JMP instruction includes an address
that is loaded into the program counter. For instance,
IMP 300011
tells the computer to get the next instruction from memory
location 3000H.
200) | — 20008 |
200s sm 20004
seco so
Fig. 11-3 (a) Unconditional jump; () conditional jump.
Here is what happens. Suppose JMP 3000H is stored at
2O0SH, as shown in Fig. 11-34. At the end of the fetch
‘cle, the program counter contains
During the execution cycle, the IMP 3000H loads the
program counter with the designated address:
PC = 3000H
When the next fetch cycle begins, the next instruction
comes from 3000H rather than 2006H (see Fig. 11-34).
mM.
‘SAP-2 has two flags called the sign flag and the zero flag.
During the execution of some instructions, these lags will
be set or reset, depending on what happens to the accu
‘mulator contents. If the accumulator contents become
negative, the sign flag will be se; otherwise, the sign flag
is cleared. Symbolically,
0
s-{
ere § sands for sin ag Te sign wll remain st
Cr cl stl anther operation tt ote fag.
IM ise mone op mins compu wil
jump o «digs es sd nly ithe gn agi
te Av an example, appose a Mt SUKI i soe at
2105, Ath naton hos been eed,
ita=o
ifa
