Scribd
Upload
159 views

ES Model Question Paper With Solution Key

The document contains a model question paper for an Embedded Systems course. It includes questions on various embedded systems topics: 1. Top-down vs bottom-up design approaches for embedded systems. 2. The difference between Harvard and von Neumann architectures. 3. Scheduling periodic real-time tasks and calculating CPU utilization. 4. Interrupt handling and context switching in an embedded system. 5. I/O using interrupts vs busy-wait and sequence diagrams depicting the interactions. 6. Programming a PIC microcontroller for tasks like timer interrupts and I/O.

Uploaded by

vidhya_bineesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
159 views

ES Model Question Paper With Solution Key

The document contains a model question paper for an Embedded Systems course. It includes questions on various embedded systems topics: 1. Top-down vs bottom-up design approaches for embedded systems. 2. The difference between Harvard and von Neumann architectures. 3. Scheduling periodic real-time tasks and calculating CPU utilization. 4. Interrupt handling and context switching in an embedded system. 5. I/O using interrupts vs busy-wait and sequence diagrams depicting the interactions. 6. Programming a PIC microcontroller for tasks like timer interrupts and I/O.

Uploaded by

vidhya_bineesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 10

Model Question Paper

13.703 Embedded Systems

1. Compare and Contrast top- down and bottom –up design for embedded systems.
In a bottom‐up design, we begin with individual components that could comprise a
system and work our way up to eventual completes a full system. In contrast, in a top‐down
design, we begin with an abstract notion of a device and work our way down to the components
that comprise the system. Of course, both methods are similar from the standpoint that the net
result is a finished product. However, they both obviously achieve this result in completely
different ways. Furthermore, both methods are related since it would be very difficult to do a
good top down design without any knowledge of underlying components and vice versa.

2. What is the difference between the Harvard and von Neumann architectures?
The difference between the van Neumann and Harvard style architectures is that a van
Neumann style machine has shared program and data memory while a Harvard style machine has
separate program and data memory.

3. Draw a UML sequence diagram that shows a four-cycle handshake between a bus master and
a device.

4. What factors provide a lower bound on the period at which the system timer interrupts for
preemptive context switching?
A combination of:
a. System scheduler overhead
b. Context switch overhead
Provide the lower bound on the timer interrupt period.

5. What factors provide an upper bound on the period at which the system timer interrupts for
preemptive context switching?
A combination of:
c. Deadlines of the processes
d. Periods of the processes
e. Execution time of the processes
Provide the upper bound on the timer interrupt period
6. Draw the pin diagram of PIC16F873
7. You are given these periodic tasks:

Task Period (ms) Execution


time (ms)

P1 5 1

P2 10 2

P3 10 2

P4 15 3

a. Show a cyclostatic schedule for the tasks.

b. Compute the CPU utilization for the system.

8. Write a program that continuously get 8-bit data from P0 and sends it to P1 while
simultaneously creating a square wave of 200 μs period on pin P2.1. Use timer 0 to create the
square wave. Assume that XTAL = 11.0592 MHz.

Solution:
We will use timer 0 in mode 2 (auto reload).
TH0 = 100/1.085 us = 92

9. Discuss the watch Dog Timer of PIC16F873.


10. Draw a UML sequence diagram for a vectored interrupt-driven read of a device. The diagram should
include the background program, the interrupt vector table, the handler, and the device. Or
Draw a UML sequence diagram for an interrupt-driven write of a device. The diagram should
include the background program, the handler, and the device.

11. Draw a UML sequence diagram for a busy-wait read of a device. The diagram should include the program
running on the CPU and the device. Or
Draw a UML sequence diagram for a busy-wait write of a device. The diagram should include the program running
on the CPU and the device.

12. Draw a UML sequence diagram for copying characters from an input to an output device using busy-wait I/O.
The diagram should include the two devices and the two busy-wait I/O handlers.

13. Draw a UML sequence diagram for copying characters from an input to an output device using interrupt-driven I/O.
The diagram should include the two devices and the two I/O handlers.
14. Draw a UML sequence diagram of a higher-priority interrupt that happens during a lower-priority interrupt handler.
The diagram should include the device, the two handlers, and the background program.

15. Draw a UML sequence diagram of a lower-priority interrupt that happens during a higher-priority interrupt
handler.The diagram should include the device, the two handlers, and the background program.

16. Three devices are attached to a microprocessor: Device 1 has highest priority and device 3 has lowest priority.
Each device’s interrupt handler takes 5 time units to execute. Show what interrupt handler (if any) is executing
at each time given the sequence of device interrupts displayed below.

Solution:
17. For the periodic processes given below, find a valid schedule
Process Time Deadline
P1 2 30
P2 5 40
P3 7 120
P4 5 60
P5 1 15
a. using standard RMS
solution:
L.C.M =120
P1 lasts 2 and has deadlines at: 30, 60, 90, 120
P2 lasts 5 and has deadlines at: 40, 80, 120
P3 lasts 7 and has deadlines at: 120
P4 lasts 5 and has deadlines at: 60, 120
P5 lasts 1 and has deadlines at: 15, 30, 45, 60, 75, 90, 105,120

Time Running Process Status


0 P5
1 P1
2 P1
3 P2
4 P2
5 P2
6 P2
7 P2
8 P3
9 P3
10 P3
11 P3
12 P3
13 P3
14 P3
15 P5
16 P4
17 P4
18 P4
19 P4
20 P4
21
22
23
24
25
26
27
28
29
30 P5
31 P1
32 P1
33
34
35
36
37
38
39
40 P2
41 P2
42 P2
43 P2
44 P2
45 P5
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 P5
61 P1
62 P1
63 P4
64 P4
65 P4
66 P4
67 P4
68
69
70
71
72
73
74
75 P5
76
77
78
79
80 P2
81 P2
82 P2
83 P2
84 P2
85
86
87
88
89
90 P5
91 P1
92 P1
93
94
95
96
97
98
99
100
101
102
103
104
105 P5
106
107
108
109
110
111
112
113
114
115
116
117
118
119

b.adding one unit of overhead for each context switch


SOLUTION:
P1 lasts 2 and has deadlines at: 30, 60, 90, 120
P2 lasts 5 and has deadlines at: 40, 80, 120
P3 lasts 7 and has deadlines at: 120
P4 lasts 5 and has deadlines at: 60, 120
P5 lasts 1 and has deadlines at: 15, 30, 45, 60, 75, 90, 105,120
Time Running Process Status
0 P5
1 switch
2 P1
3 P1
4 switch
5 P2
6 P2
7 P2
8 P2
9 P2
10 switch
11
12
13
14
15 P5
16 switch
17 P4
18 P4
19 P4
20 P4
21 P4
22 switch
23
24
25
26
27
28
29
30 P5
31 switch
32 P1
33 P1
34 switch
35 P3
36 P3
37 P3
38 P3
39 P3
40 P3
41 P3
42 switch
43
44
45 P5
46 switch
47 P2
48 P2
49 P2
50 P2
51 P2
52 switch
53
54
55
56
57
58
59
60 P5
61 switch
62 P1
63 P1
64 switch
65 P4
66 P4
67 P4
68 P4
69 P4
70 switch
71
72
73
74
75 P5
76 switch
77
78
79
80 P2
81 P2
82 P2
83 P2
84 P2
85 switch
86
87
88
89
90 P5
91 switch
92 P1
93 P1
94 switch
95
96
97
98
99
100
101
102
103
104
105 P5
106 switch
107
108
109
110
111
112
113
114
115
116
117
118
119

18. Explain 4 cycle handshaking of CPU bus.

You might also like