Aim:

The aim of this topic is to enable students to appreciate the functions and uses of
combinational logic circuits to the electronic and related industries.

After completing this section, you should be able to

 Draw and explain the half and full adder.
 Define and design an encoder and decoder using logic gates.
 Explain and design the 7 – segment display decoder/driver
 Define and design a multiplexer/ Demultiplexer
 Define parity and explain the functions of parity generators
 Explain the terms associated with signal converters ADC/DAC
 Describe with aid of circuit diagrams the operation of typical ADC/DAC

Half and Full Adders

Adders are important in computers and also in other types of digital systems in which
numerical data are processed. An understanding of the basic adder operation is fundamental
to the study of digital systems.

The Half-Adder
Recall the basic rules for binary addition leant earlier.
0+0=0
0+1=1
1+0=1
1 + 1 = 10
The operations are performed by a logic circuit called a half-adder.
The half-adder accepts two binary digits on its inputs and produces two binary digits on its
outputs—a sum bit and a carry bit.

The block diagram below depicts a Half Adder

From the operation of the half-adder shown on the truth table above, expressions can be
derived for the sum and the output carry as functions of the inputs. Notice that the output
carry (Cout) is a 1 only when both A and B are 1s; therefore, Cout can be expressed as the
AND of the input variables. Cout =AB

Now observe that the sum output is a 1 only if the input variables, A and B, are not equal.
The sum can therefore be expressed as the exclusive-OR of the input variables.
A and B
From deduction above, the logic implementation required for the half-adder function can be
developed. The output carry is produced with an AND gate with A and B on the inputs, and
the sum output is generated with an exclusive-OR gate.
Remember that the exclusive-OR can be implemented with AND gates, an OR gate, and
inverters.(see the logic diagram below)

The Full-Adder
The second category of adder is the full-adder.
The full-adder accepts two input bits and an input carry and generates a sum output
and an output carry.
The basic difference between a full-adder and a half-adder is that the full-adder accepts an
input carry. A logic symbol for a full-adder and the truth table shows the operation of a full-
adder.
The full-adder must add the two input bits and the input carry. From the half-adder you know
that the sum of the input bits A and B is the exclusive-OR of those two variables, AOB. For
the input carry (Cin) to be added to the input bits, it must be exclusive-ORed with A0B,
yielding the equation for the sum output of the full-adder.

This means that to implement the full-adder sum function, two 2-input exclusive-OR gates
can be used. The first must generate the term AoB, and the second has as its inputs the output
of the first XOR gate and the input carry,
The logic required to form the sum of three bits as as shown below

The full adder logic is shown shaded

The output carry is a 1 when both inputs to the first XOR gate are 1s or when both inputs to
the second XOR gate are 1s. The output carry of the full-adder is therefore produced by input
A ANDed with input B and A_B ANDed with Cin. These two terms are ORed, as expressed
in Equation below. This function is implemented and combined with the sum logic to form a
complete full-adder circuit, as shown

Full adder implementation can be represented as below

To add two binary numbers, a full-adder (FA) is required for each bit in the numbers. So for
2-bit numbers, two adders are needed; for 4-bit numbers, four adders are used; and so on. The
carry output of each adder is connected to the carry input of the next higher-order adder, as
shown below for a 2-bit adder. Notice that either a half-adder can be used for the least
significant position or the carry input of a full-adder can be made 0 (grounded) because there
is no carry input to the least significant bit position.

This set up can be replicated to add a nibble,ie 4 bits at once

DECODERS

A decoder is a digital circuit that detects the presence of a specified combination of bits
(code) on its inputs and indicates the presence of that code by a specified output level. In its
general form, a decoder has n input lines to handle n bits and from one to 2n output lines to
indicate the presence of one or more n-bit combinations. The basic principles can be
extended to other types of decoders.

The 4-Bit Decoder

In order to decode all possible combinations of four bits, sixteen decoding gates are required
(24= 16). This type of decoder is commonly called either a 4-line-to-16-line decoder because
there are four inputs and sixteen outputs or a 1-of-16 decoder because for any given code on
the inputs, one of the sixteen outputs is activated. A list of the sixteen binary codes and their
corresponding decoding functions is given in Table below.
If an active-LOW output is required for each decoded number, the entire decoder can be
implemented with NAND gates and inverters. In order to decode each of the sixteen binary
codes, sixteen NAND gates are required (AND gates can be used to produce active-HIGH
outputs).
A logic symbol for a 4-line-to-16-line (1-of-16) decoder with active-LOW outputs is shown
in Figure. The BIN/DEC label indicates that a binary input makes the corresponding decimal
output active. The input labels 8, 4, 2, and 1 represent the binary weights of the input bits .

The BCD-to-Decimal Decoder

The BCD-to-decimal decoder converts each BCD code (8421 code) into one of ten possible
decimal digit indications. It is frequently referred as a 4-line-to-10-line decoder or a 1-of-10
decoder.
The method of implementation is the same as for the 1-of-16 decoder previously discussed,
except that only ten decoding gates are required because the BCD code represents only the
ten decimal digits 0 through 9. A list of the ten BCD codes and their corresponding decoding
functions is given in Table. Each of these decoding functions is implemented with NAND
gates to provide active-LOW outputs. If an active-HIGH output is required,
AND gates are used for decoding. The logic is identical to that of the first ten decoding gates
in the 1-of-16 decoder.
The BCD-to-7-Segment Decoder
The BCD-to-7-segment decoder accepts the BCD code on its inputs and provides outputs to
drive 7-segment display devices to produce a decimal readout. The logic diagram for a basic
7-segment decoder is shown in Figure below.

ENCODERS

An encoder is a combinational logic circuit that essentially performs a “reverse” decoder

function. An encoder accepts an active level on one of its inputs representing a digit, such as
a decimal or octal digit, and converts it to a coded output, such as BCD or binary. Encoders
can also be devised to encode various symbols and alphabetic characters. The process of
converting from familiar symbols or numbers to a coded format is called encoding.
The Decimal-to-BCD Encoder
This type of encoder has ten inputs—one for each decimal digit—and four outputs
corresponding to the BCD code, as shown in Figure below. This is a basic 10-line-to-4-line
encoder.

The BCD (8421) code is listed in Table below. From this table you can determine the
relationship between each BCD bit and the decimal digits in order to analyze the logic. For
instance, the most significant bit of the BCD code, A3, is always a 1 for decimal digit 8 or
9. An OR expression for bit A3 in terms of the decimal digits can therefore be written as
A3 = 8 + 9
Bit A2 is always a 1 for decimal digit 4, 5, 6 or 7 and can be expressed as an OR function as
follows:
A2 = 4 + 5 + 6 + 7
Bit A1 is always a 1 for decimal digit 2, 3, 6, or 7 and can be expressed as
A1 = 2 + 3 + 6 + 7
Finally, A0 is always a 1 for decimal digit 1, 3, 5, 7, or 9. The expression for A0 is
A0 = 1 + 3 + 5 + 7 + 9
Now let’s implement the logic circuitry required for encoding each decimal digit to a
BCD code by using the logic expressions just developed. It is simply a matter of ORing the
appropriate decimal digit input lines to form each BCD output. The basic encoder logic
resulting from these expressions is shown in Figure 6–37.

The basic operation of the circuit in Figure above is as follows: When a HIGH appears on
one of the decimal digit input lines, the appropriate levels occur on the four BCD output
lines. For instance, if input line 9 is HIGH (assuming all other input lines are LOW), this
condition will produce a HIGH on outputs A0 and A3 and LOWs on outputs A1 and A2,
which is the BCD code (1001) for decimal 9.

The Decimal-to-BCD Priority Encoder

This type of encoder performs the same basic encoding function as previously discussed.
A priority encoder also offers additional flexibility in that it can be used in applications that
require priority detection. The priority function means that the encoder will produce a
BCD output corresponding to the highest-order decimal digit input that is active and will
ignore any other lower-order active inputs. For instance, if the 6 and the 3 inputs are both
active, the BCD output is 0110 (which represents decimal 6).

MULTIPLEXER

A multiplexer (MUX) is a device that allows digital information from several sources to be
routed onto a single line for transmission over that line to a common destination. The basic
multiplexer has several data-input lines and a single output line. It also has data-select inputs,
which permit digital data on any one of the inputs to be switched to the output line.
Multiplexers are also known as data selectors.
A logic symbol for a 4-input multiplexer (MUX) is shown in Figure below. Notice that there
are two data-select lines because with two select bits, any one of the four data-input lines can
be selected.

In Figure above, a 2-bit code on the data-select (S) inputs will allow the data on the selected
data input to pass through to the data output. If a binary 0 (S1 = 0 and S0 = 0) is applied to the
data-select lines, the data on input D0 appear on the data-output line.
If a binary 1 (S1 = 0 and S0 = 1) is applied to the data-select lines, the data on input
D1 appear on the data output. If a binary 2 (S1 = 1 and S0 = 0) is applied, the data on D2
appear on the output. If a binary 3 (S1 = 1 and S0 = 1) is applied, the data on
D3 are switched to the output line. A summary of this operation is given in Table below.
Now let’s look at the logic circuitry required to perform this multiplexing operation. The data
output is equal to the state of the selected data input. You can therefore, derive a logic
expression for the output in terms of the data input and the select inputs.
The data output is equal to D0 only if S1 = 0 and S0 = 0: Y = D0S1S0.
The data output is equal to D1 only if S1 = 0 and S0 = 1: Y = D1S1S0.
The data output is equal to D2 only if S1 = 1 and S0 = 0: Y = D2S1S0.
The data output is equal to D3 only if S1 = 1 and S0 = 1: Y = D3S1S0.

When these terms are ORed, the total expression for the data output is
Y = D0S1S0 + D1S1S0 + D2S1S0 + D3S1S0
The implementation of this equation requires four 3-input AND gates, a 4-input OR gate, and
two inverters to generate the complements of S1 and S0, as shown in Figure below.
Because data can be selected from any one of the input lines, this circuit is also referred to as
a data selector.

Logic diagram of a 4 input Multiplexer

DEMULTIPLEXER

A demultiplexer (DEMUX) basically reverses the multiplexing function. It takes digital

information from one line and distributes it to a given number of output lines. For this reason,
the demultiplexer is also known as a data distributor. As you will see, decoders canalso be
used as demultiplexers.
Figure below shows a 1-line-to-4-line demultiplexer (DEMUX) circuit. The data-input line
goes to all of the AND gates. The two data-select lines enable only one gate at a time,and the
data appearing on the data-input line will pass through the selected gate to the associated
data-output line.
A 1-line-to-4-line demultiplexer.

4-Line-to-16-Line Decoder as a Demultiplexer

We have already discussed a 4-line-to-16-line decoder . This device and other decoders can
also be used in demultiplexing applications. In demultiplexer applications, the input lines are
used as the data-select lines. One of the chip select inputs is used as the data input line, with
the other chip select input held LOW to enable the internal negative-AND gate.

PARITY GENERATORS AND CHECKERS

Errors can occur as digital codes are being transferred from one point to another within a
digital system or while codes are being transmitted from one system to another. The errors
take the form of undesired changes in the bits that make up the coded information; that is, a 1
can change to a 0, or a 0 to a 1, because of component malfunctions or electrical noise. In
most digital systems, the probability that even a single bit error will occur is very small, and
the likelihood that more than one will occur is even smaller.
Nevertheless, when an error occurs undetected, it can cause serious problems in a digital
system.
The parity method of error detection in which a parity bit is attached to a group of
information bits in order to make the total number of 1s either even or odd (depending on the
system). In addition to parity bits, several specific codes also provide inherent error detection.

Basic Parity Logic

In order to check for or to generate the proper parity in a given code, a basic principle can
be used:
The sum (disregarding carries) of an even number of 1s is always 0, and the sum of an
odd number of 1s is always 1.
Therefore, to determine if a given code has even parity or odd parity, all the bits in that
code are summed. As you know, the modulo-2 sum of two bits can be generated by an
exclusive-OR gate, as shown in Figure below(a); the modulo-2 sum of four bits can be
formed by three exclusive-OR gates connected as shown in Figure 6–55(b); and so on. When
the number of 1s on the inputs is even, the output X is 0 (LOW). When the number of 1s is
odd, the output X is 1 (HIGH).
Parity Checker
When this device is used as an even parity checker, the number of input bits should always be
even; and when a parity error occurs, the Even output goes LOW
and the Odd output goes HIGH. When it is used as an odd parity checker, the number
of input bits should always be odd; and when a parity error occurs, the Odd output goes
LOW and the Even output goes HIGH.

Parity Generator
If this device is used as an even parity generator, the parity bit is taken at the © Odd output
because this output is a 0 if there is an even number of input bits and it is a 1 if there is an odd
number. When used as an odd parity generator, the parity bit is taken at the © Even output
because it is a 0 when the number of inputs bits is odd.

A Data Transmission System with Error Detection

A simplified data transmission system is shown in Figure below to illustrate an application of
parity generators/checkers, as well as multiplexers and demultiplexers, and to illustrate the
need for data storage in some applications.
In this application, digital data from seven sources are multiplexed onto a single line for
transmission to a distant point. The seven data bits (D0 through D6) are applied to the
multiplexer data inputs and, at the same time, to the even parity generator inputs. The ©
Odd output of the parity generator is used as the even parity bit. This bit is 0 if the number
of 1s on the inputs A through I is even and is a 1 if the number of 1s on A through I is odd.
This bit is D7 of the transmitted code.
The data-select inputs are repeatedly cycled through a binary sequence, and each data bit,
beginning with D0, is serially passed through and onto the transmission line (Y). In this
example, the transmission line consists of four conductors: one carries the serial data and
three carry the timing signals (data selects). There are more sophisticated ways of sending the
timing information, but we are using this direct method to illustrate a basic principle.

At the demultiplexer end of the system, the data-select signals and the serial data stream are
applied to the demultiplexer. The data bits are distributed by the demultiplexer onto the
output lines in the order in which they occurred on the multiplexer inputs. That is, D0 comes
out on the D0 output, D1 comes out on the D1 output, and so on. The parity bit comes out on
the D7 output. These eight bits are temporarily stored and applied to the even parity checker.
Not all of the bits are present on the parity checker inputs until the parity bit D7 comes out
and is stored. At this time, the error gate is enabled by the data-select code 111.
If the parity is correct, a 0 appears on the © Even output, keeping the Error output at 0. If
the parity is incorrect, all 1s appear on the error gate inputs, and a 1 on the Error output
results.
SIGNAL CONVERTERS

After completing this section, you should be able to

 Explain what an operational amplifier is
 Explain how a flash ADC works
 Discuss dual-slope ADCs
 Describe the operation of a successive-approximation ADC

ANALOG TO DIGITAL CONVERSION

In order to process signals using digital techniques, the incoming analog signal must be
converted into digital form.
Analog-to-digital conversion is the process of converting the output of the sample and- hold
circuit to a series of binary codes that represent the amplitude of the analog input at each of
the sample times. The sample-and-hold process keeps the amplitude of the analog input
signal constant between sample pulses; therefore, the analog-to digital conversion can be
done using a constant value rather than having the analog signal change during a conversion
interval, which is the time between sample pulses.
Figure below illustrates the basic function of an analog-to-digital converter (ADC), which is a
circuit that performs analog-to-digital conversion. The sample intervals are indicated by
dashed lines.

Before getting into analog-to-digital converters (ADCs), let’s look briefly at an element that
is common to most types of ADCs and digital-to-analog converters (DACs). This element is
the operational amplifier, or op-amp for short.
An op-amp is a linear amplifier that has two inputs (inverting and noninverting) and one
output. It has a very high voltage gain and a very high input impedance, as well as a very low
output impedance. The op-amp symbol is shown in Figure below(a). When used as an
inverting amplifier, the op-amp is configured as shown in part (b). The feedback resistor,
Rf, and the input resistor, Ri, control the voltage gain according to the formula in Equation
12–2, where Vout/Vin is the closed-loop voltage gain (closed loop refers to the feedback
from output to input provided by Rf). The negative sign indicates inversion.

Vout/Vin= -Rf/Ri

In the inverting amplifier configuration, the inverting input of the op-amp is approximatelyat
ground potential (0 V) because feedback and the extremely high open-loop gain make the
differential voltage between the two inputs extremely small. Since the non inverting input is
grounded, the inverting input is at approximately 0 V, which is called virtual ground.
When the op-amp is used as a comparator, as shown (c), two voltages are applied to the
inputs. When these input voltages differ by a very small amount, the opamp is driven into one
of its two saturated output states, either HIGH or LOW, depending on which input voltage is
greater.

ANALOG TO DIGITAL CONVERTER

Successive-Approximation Analog-to-Digital Converter
One of the most widely used methods of analog-to-digital conversion is successive
approximation.
It has a much faster conversion time than the dual-slope conversion, but it is slower than the
one flash method. It also has a fixed conversion time that is the same for any value of the
analog input.
The figure shows a basic block diagram of a 4-bit successive approximation ADC.
It consists of a DAC (DACs are covered in next Section), a successive-approximation register
(SAR), and a comparator. The basic operation is as follows: The input bits of the DAC are
enabled (made equal to a 1) one at a time, starting with the most significant bit (MSB). As
each bit is enabled, the comparator produces an output that indicates whether the input signal
voltage is greater or less than the output of the DAC. If the DAC output is greater than the
input signal, the comparator’s output is LOW, causing the bit in the register to reset. If the
output is less than the input signal, the 1 bit is retained in the register. The system does this
with the MSB first, then the next most significant bit, then the next, and so on. After all the
bits of the DAC have been tried, the conversion cycle is complete.

In order to better understand the operation of the successive-approximation ADC, let’s take a
specific example of a 4-bit conversion. Figure below illustrates the step-by-step conversion of
a constant input voltage (5.1 V in this case). Let’s assume that the DAC has the following
output characteristics: Vout = 8 V for the 2>3 bit (MSB), Vout = 4 V for the
2>2 bit, Vout = 2 V for the 2>1 bit, and Vout = 1 V for the 2>0 bit (LSB).
Figure (a) shows the first step in the conversion cycle with the MSB = 1. The output of the
DAC is 8 V. Since this is greater than the input of 5.1 V, the output of the comparator is
LOW, causing the MSB in the SAR to be reset to a 0.
Figure (b) shows the second step in the conversion cycle with the 2>2 bit equal to a
1. The output of the DAC is 4 V. Since this is less than the input of 5.1 V, the output of the
comparator switches to a HIGH, causing this bit to be retained in the SAR.
Figure (c) shows the third step in the conversion cycle with the 21 bit equal to a 1.
The output of the DAC is 6 V because there is a 1 on the 22 bit input and on the 21 bit input;
4 V + 2 V = 6 V. Since this is greater than the input of 5.1 V, the output of the comparator
switches to a LOW, causing this bit to be reset to a 0.
Figure (d) shows the fourth and final step in the conversion cycle with the 20 bit equal to a 1.
The output of the DAC is 5 V because there is a 1 on the 22 bit input and on the 20 bit input;
4 V + 1 V = 5 V.
The four bits have all been tried, thus completing the conversion cycle. At this point the
binary code in the register is 0101, which is approximately the binary value of the input of
5.1 V. Additional bits will produce an even more accurate result. Another conversion cycle
now begins, and the basic process is repeated. The SAR is cleared at the beginning of each
cycle.

Dual-Slope Analog-to-Digital Converter-Ramp

A dual-slope ADC is common in digital voltmeters and other types of measurement

instruments.
A ramp generator (integrator) is used to produce the dual-slope characteristic. A block
diagram of a dual-slope ADC is shown in Figure below.
This figure illustrates dual-slope conversion. Start by assuming that the counter is
reset and the output of the integrator is zero. Now assume that a positive input voltage is
applied to the input through the switch (SW) as selected by the control logic. Since the
inverting input of A1 is at virtual ground, and assuming that Vin is constant for a period of
time, there will be constant current through the input resistor R and therefore through the
capacitor C. Capacitor C will charge linearly because the current is constant, and as a result,
there will be a negative-going linear voltage ramp on the output of A1, as illustrated in Figure
(a).
When the counter reaches a specified count (n), it will be reset (R), and the control logic will
switch the negative reference voltage (-VREF) to the input of A1, as shown in Figure
(b). At this point the capacitor is charged to a negative voltage (-V) proportional to the input
analog voltage.
Now the capacitor discharges linearly because of the constant current from the -VREF, as
shown in Figure (c). This linear discharge produces a positive-going ramp on the A1 output,
starting at -V and having a constant slope that is independent of the charge voltage.
As the capacitor discharges, the counter advances from its RESET state. The time it takes the
capacitor to discharge to zero depends on the initial voltage -V (proportional to Vin) because
the discharge rate (slope) is constant. When the integrator (A1) output voltage reaches zero,
the comparator (A2) switches to the LOW state and disables the clock to the counter. The
binary count is latched, thus completing one conversion cycle. The binary count is
proportional to Vin because the time it takes the capacitor to discharge depends only on -V,
and the counter records this interval of time.
DIGITAL TO ANALOG CONVERSION
Digital-to-analog conversion is an important part of a digital processing system. Once the
digital data has been processed, it is converted back to analog form. In this section, we will
examine the theory of operation of two basic types of digital-to-analog converters (DACs)

Binary-Weighted-Input Digital-to-Analog Converter

One method of digital-to-analog conversion uses a resistor network and learn about their
performance characteristics.with resistance values that represent the binary weights of the
input bits of the digital code. Figure below shows a 4-bit DAC of this type. Each of the input
resistors will either have current or have no current, depending on the input voltage level. If
the input voltage is zero (binary 0), the current is also zero. If the input voltage is HIGH
(binary 1), the amount of current depends on the input resistor value and is different for each
input resistor, as indicated in the figure.

Since there is practically no current into the op-amp inverting (-) input, all of the input
currents sum together and go through Rf. Since the inverting input is at 0 V (virtual ground),
the drop across Rf is equal to the output voltage, so Vout = IfRf.
The values of the input resistors are chosen to be inversely proportional to the binary weights
of the corresponding input bits. The lowest-value resistor (R) corresponds to the highest
binary-weighted input (2>3). The other resistors are multiples of R (that is, 2R, 4R, and 8R)
and correspond to the binary weights 2>2, 2>1, and 2>0, respectively. The input currents are
also proportional to the binary weights. Thus, the output voltage is proportional to the sum of
the binary weights because the sum of the input currents is through Rf.
Disadvantages of this type of DAC are the number of different resistor values and the fact
that the voltage levels must be exactly the same for all inputs. For example, an 8-bit converter
requires eight resistors, ranging from some value of R to 128R in binary-weighted steps. This
range of resistors requires tolerances of one part in 255 (less than 0.5%) to accurately convert
the input, making this type of DAC very difficult to mass-produce.
The general equation for a weighted resister DAC is therefore

MSB ]

The R/2R Ladder Digital-to-Analog Converter

Another method of digital-to-analog conversion is the R/2R ladder, as shown in Figure
for four bits. It overcomes one of the problems in the binary-weighted-input DAC in
that it requires only two resistor values.

Start by assuming that the D3 input is HIGH (+5 V) and the others are LOW (ground, 0 V).
This condition represents the binary number 1000. A circuit analysis will show that this
reduces to the equivalent form shown in Figure 12–30(a). Essentially no current goes
(b) Equivalent circuit for D3 = 0, D2 = 1, D1 = 0, D0 = 0

through the 2R equivalent resistance because the inverting input is at virtual ground. Thus,
all of the current (I = 5 V/2R) through R7 also goes through Rf, and the output voltage is -5
V.
The operational amplifier keeps the inverting (-) input near zero volts (L0 V) because of
negative feedback. Therefore, all current goes through Rf rather than into the inverting input.
Figure 12–30(b) shows the equivalent circuit when the D2 input is at +5 V and the others are
at ground. This condition represents 0100. If we thevenize looking from R8, we get 2.5 V in
series with R, as shown. This results in a current through Rf of I = 2.5 V/2R, which gives an
output voltage of -2.5 V. Keep in mind that there is no current into the opamp inverting input
and that there is no current through the equivalent resistance to ground because it has 0 V
across it, due to the virtual ground.
Figure(c) shows the equivalent circuit when the D1 input is at +5 V and the others are at
ground. This condition represents 0010. Again thevenizing looking from R8, you get
1.25 V in series with R as shown. This results in a current through Rf of I = 1.25 V/2R, which
gives an output voltage of -1.25 V.
In part (d), the equivalent circuit representing the case where D0 is at
+5 V and the other inputs are at ground is shown. This condition represents 0001.
Thevenizing from R8 gives an equivalent of 0.625 V in series with R as shown. The resulting
current through Rf is I = 0.625 V/2R, which gives an output voltage of -0.625 V.
Notice that each successively lower-weighted input produces an output voltage that is
halved, so that the output voltage is proportional to the binary weight of the input bits.

The General Equation therefore follows

Performance Characteristics of Digital-to-Analog Converters

The performance characteristics of a DAC include resolution, accuracy, linearity,

monotonicity, and settling time, each of which is discussed in the following list:

Resolution. The resolution of a DAC is the reciprocal of the number of discrete steps
in the output. This, of course, is dependent on the number of input bits. For example,
a 4-bit DAC has a resolution of one part in 24 - 1 (one part in fifteen). Expressed as
a percentage, this is (1/15)100 = 6.67%. The total number of discrete steps equals
2n - 1, where n is the number of bits. Resolution can also be expressed as the number
of bits that are converted.

Accuracy. Accuracy is derived from a comparison of the actual output of a DAC with
the expected output. It is expressed as a percentage of a full-scale, or maximum, output
voltage. For example, if a converter has a full-scale output of 10 V and the accuracy
is ;0.1%, then the maximum error for any output voltage is (10 V)(0.001) = 10 mV.
Ideally, the accuracy should be no worse than ;1/2 of a least significant bit. For an
8-bit converter, the least significant bit is 0.39% of full scale. The accuracy should be
approximately ;0.2%.
Linearity. A linear error is a deviation from the ideal straight-line output of a DAC.
A special case is an offset error, which is the amount of output voltage when the
input bits are all zeros.
Monotonicity. A DAC is monotonic if it does not take any reverse steps when it is
sequenced over its entire range of input bits.

Settling time. Settling time is normally defined as the time it takes a DAC to settle
within ;1/2 LSB of its final value when a change occurs in the input code.

Practice Questions

1. Draw and explain the half and full adder.

2. Define and design an encoder and decoder using logic gates.
3. Explain and design the 7 – segment display decoder/driver
4. Define and design a multiplexer/ Demultiplexer
5. Define parity and explain the functions of parity generators
6. Explain the terms associated with signal converters ADC/DAC
7. Describe with aid of circuit diagrams the operation of typical ADC/DAC