RTL - Synthesis

PRABHAVATHI P
A S S O C I AT E P R O F E S S O R ,
D E PA R T M E N T O F E C E , B N M I T
Synthesis and Physical Design

10/22/2021 SYNTHESIS & PD_PPR 2

Timing Analysis – Min and Max timing paths

10/22/2021 SYNTHESIS & PD_PPR 3

10/22/2021 SYNTHESIS & PD_PPR 4
Critical Path – Example 2

10/22/2021 SYNTHESIS & PD_PPR 5

Critical path
Example shows four paths:
• a to c through +: 2 ns
• a to d through + and *: 7ns
• b to d through + and *: 7ns
• b to d through *: 5 ns
• Longest path is thus 7 ns
• Fastest frequency = 1 / 7 ns = 142 MHz

10/22/2021 SYNTHESIS & PD_PPR 6

Synthesis and Physical design

10/22/2021 SYNTHESIS & PD_PPR 7

SR Latch and Flip flop
SR LATCH
SR FLIPFLOP
module SR_Latch ( s ,r ,enable ,reset ,q ,qb ); module srff (
input reset, clk, s, r ,
output reg q ; output q, qb);
output reg qb ; reg q ;
input s, r, enable, reset; always @ (negedge reset, posedge clk)
begin
always @ (enable or s or r or reset) if (!reset)
begin q <= 1'b0;
if (reset) else
begin begin
q = 0; case ({s,r})
qb = 1; 2'b00 : q <= q ;
end 2'b01 : q <= 1'b0 ;
else if (enable) 2'b10 : q <= 1'b1 ;
begin 2'b11 : q <=1'bx ;
if (s!=r) default : q<=1'bz ;
begin endcase
q = s; end
qb = r; end
end assign qb = ~q ;
else if (s==1 && r==1) begin endmodule
q = 1'bZ;
qb = 1'bZ;
end
end
end
endmodule

10/22/2021 SYNTHESIS & PD_PPR 8

SR Latch and Flip flop
SR LATCH SR FLIPFLOP

10/22/2021 SYNTHESIS & PD_PPR 9

Updown counter design & Testbench in Verilog
Binary synchronous counter – Updown module bcdsyncupdown_tb;
reg reset, clk,dir;
// Code your design here wire [3:0] q;
module bcdsynch_updowncounter(input dir,
input reset, clk , bcdsynch_updowncounter bcds(dir,reset, clk,q);
output [3:0] q) ;
initial
reg [3:0] q ; begin
always @ (posedge clk) reset = 0;dir=0;
begin clk = 0;
end
if(!reset) always #5 clk =~clk;
q<=4'b0000; initial
else begin
begin #40 reset = 1'b1;
#195 reset = 1'b0;
if (dir) #20 reset = 1'b1;
begin #100 dir =1'b1;
q<=q+1; #40 reset = 1'b1;
if (q==4'b1001) #195 reset = 1'b0;
q<=4'b0000; #20 reset = 1'b1;
end end
else initial
begin
begin #800; $finish;
q<=4'b1001; end
q<=q-1; initial
$monitor($time, " The count sequence for reset = %b and clk= %b is q = %b", reset, clk, q);
if (q==4'b0000) initial
q<=4'b1001; begin
end $dumpfile("bcds.vcd");
end $dumpvars(2,bcdsyncupdown_tb);
end
end endmodule
endmodule

10/22/2021 SYNTHESIS & PD_PPR 10

Simulation snapshot

10/22/2021 SYNTHESIS & PD_PPR 11

RTL of Updown Counter

10/22/2021 SYNTHESIS & PD_PPR 12

•SDC is a short form of "Synopsys Design Constraint".

•SDC is a common format for constraining the design which is

supported by almost all Synthesis, PnR and other tools.

•Generally, timing, power and area constraints of design are

SDC File provided through the SDC file and this file has extension .sdc.

•SDC file syntax is based on TCL format and all commands of

sdc file follow the TCL syntax.

•In sdc file '#' is used to comment a line and '\' is used to break
the line.

•SDC file can be generated by the synthesis tool and the same
can be used in for PnR.

10/22/2021 SYNTHESIS & PD_PPR 13

Common SDC constraints

10/22/2021 SYNTHESIS & PD_PPR 14

Synthesis Commands with Genus
legacy_genus:/> read_hdl /home/cadence/DATABASE/test/rcfiles/rtl/updowncounter.v
legacy_genus:/> set_attribute library /home/cadence/DATABASE/test/rcfiles/lib/slow_vdd1v0_basicCells.lib
legacy_genus:/> set_attribute lib_search_path /home/cadence/DATABASE/test/rcfiles/rtl/
legacy_genus:/> elaborate bcdsynch_updowncounter
legacy_genus:/> synthesize -to_mapped
legacy_genus:/> report timing > updownCt1
legacy_genus:/> report area > updownCa1
legacy_genus:/> report power > updownCp1

legacy_genus:/> set_attribute syn_opt_effort -medium

legacy_genus:/> report timing > updownCtm
legacy_genus:/> report area > updownCam
legacy_genus:/> report power > updownCpm

legacy_genus:/> write_sdf > Updowncsdf1

legacy_genus:/> write_sdc > updowncsdc
10/22/2021 SYNTHESIS & PD_PPR 15
Synthesis Commands in standard format
To set input and output delays:
To create clock:
set_input_delay -max 0.1 [get_ports "in1"] -clock [get_clocks "clk"]
create_clock -name CK -period 0.5 -waveform {0 0.25} clk set_input_delay -max 0.1 [get_ports "in1"] -clock [get_clocks "CK"]
synthesize -to_mapped -effort high set_output_delay -max 0.1 [get_ports "s"] -clock [get_clocks "CK"]
report timing set_attribute syn_opt_effort high
report timing
To set clock uncertainty:
set_clock_uncertainty 0.01 [get_ports "CK"] set_output_delay -max 0.01 [get_ports "s"] -clock [get_clocks "CK"]
set_attribute syn_opt_effort high
To set clock transitions: report timing
set_clock_transition -rise 0.1 [get_clocks "CK"]
set_clock_transition -fall 0.1 [get_clocks "CK"] set_input_delay -max 0.1 [get_ports "in1"] -clock [get_clocks "CK"]
set_clock_uncertainty 0.01 [get_ports "CK"] set_output_delay -max 0.01 [get_ports "s"] -clock [get_clocks "CK"]
set_clock_uncertainty 0.01 [get_ports "clk"] set_attribute syn_opt_effort high
report timing
gui_show
To set power constraint: To save SDC and netlist:
write_sdc > clasdc
report power write_hdl > cla_sync.v
set_max_dynamic_power 0.05mW set_max_dynamic_power 0.5pW
set_attribute syn_opt_effort high set_attribute syn_opt_effort high
report power
report power
set_max_leakage_power 0.005pW
To view RTL in gui set_attribute leakage_power_effort high

set_max_leakage_power 0.005pW
gui_show
To design with low power libraries:

set_attribute lp_power_optimization_weight
set_attribute lp_power_optimization_weight -quiet
set_attribute -quiet lp_power_optimization_weight
set_max_leakage_power 0.005pW
set_attribute syn_opt_effort high
report power

set_max_leakage_power 0.0005pW
set_attribute syn_opt_effort high
report power

report area
report area > claarea

10/22/2021 SYNTHESIS & PD_PPR 16

Logic Optimization

10/22/2021 SYNTHESIS & PD_PPR 17

4 bit Adder
module adder_4bit_tb;
module adder_4bit ( a ,b, sum ,carry ); reg [3:0] a,b ;
reg cin;
output reg [4:0] sum ; wire [3:0] sum;
wire carry;
output reg carry ; adder_4bit a1(a, b, cin,sum, carry);
initial
input [3:0] a , b; begin
a=4'd0;
integer i; b= 4'd0;
cin = 1'b0;
end
initial
reg [4:0]s; begin
#10 a=4'd1;
always @ (a or b ) #10 b= 4'd4;
#10 a=4'd5;
begin #10 b= 4'd3;
#10 a=4'd1;
s[0] = 0; #10 cin = 1'b1;
#10 b= 4'd9;
for (i=0;i<=3;i=i+1) begin #10 a=4'd11;
#10 b= 4'd10;
sum [i] = a[i] ^ b[i] ^ s[i] ; #10 cin = 1'b0;
#10 cin = 1'b1;
s[i+1] = (a[i] & b[i]) | (b[i] & s[i]) | (s[i] & a[i]); end
initial
end begin
$dumpfile("adder_4bit.vcd");
carry = s[4]; $dumpvars(2, adder_4bit_tb);
end
end initial
#300 $finish;
endmodule endmodule

10/22/2021 SYNTHESIS & PD_PPR 18

Synthesis of 4 bit
adder
Without optimization

10/22/2021 SYNTHESIS & PD_PPR 19

Synthesis of 4 bit
Adder
With Optimization

10/22/2021 SYNTHESIS & PD_PPR 20

Timing Debug: Timing histogram

10/22/2021 SYNTHESIS & PD_PPR 21

Timing report with constraints
============================================================ ============================================================
Generated by: Genus(TM) Synthesis Solution 20.11-s111_1 Generated by: Genus(TM) Synthesis Solution 20.11-s111_1
Generated on: Nov 02 2021 12:52:39 pm Generated on: Nov 02 2021 12:50:51 pm
Module: bcdupC Module: bcdupC
Technology library: slow_vdd1v0 1.0 Technology library: slow_vdd1v0 1.0
Operating conditions: PVT_0P9V_125C (balanced_tree) Operating conditions: PVT_0P9V_125C (balanced_tree)
Wireload mode: enclosed Wireload mode: enclosed
Area mode: timing library Area mode: timing library
============================================================ ============================================================

Pin Type Fanout Load Slew Delay Arrival Pin Type Fanout Load Slew Delay Arrival
(fF) (ps) (ps) (ps) (fF) (ps) (ps) (ps)
--------------------------------------------------------- ---------------------------------------------------------
(clock CK) launch 0 R (clock CK) launch 0 R
q_reg[0]/CK 0 +0 0 R q_reg[0]/CK 0 +0 0 R
q_reg[0]/Q DFFRX1 3 0.6 32 +270 270 R q_reg[0]/Q DFFRX1 3 0.6 32 +270 270 R
g1250/A +0 270 g1250/A +0 270
g1250/Y AND2X1 3 1.0 36 +130 400 R g1250/Y AND2X1 3 1.0 36 +130 400 R
g1247/B +0 400 g1247/B +0 400
g1247/Y OR2X1 4 1.6 46 +87 487 R g1247/Y OR2X1 4 1.6 46 +87 487 R
g1244/A1 +0 487 g1244/A1 +0 487
g1244/Y AOI22X1 1 0.4 104 +107 594 F g1244/Y AOI22X1 1 0.4 104 +107 594 F
g1239/A1 +0 594 g1239/A1 +0 594
g1239/Y OAI221X1 1 0.2 91 +115 709 R g1239/Y OAI221X1 1 0.2 91 +115 709 R
q_reg[1]/D DFFRX1 +0 709 q_reg[1]/D DFFRX1 +0 709
q_reg[1]/CK setup 0 +160 869 R q_reg[1]/CK setup 0 +160 869 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(clock CK) capture 500 R (clock CK) capture 2000 R
--------------------------------------------------------- ---------------------------------------------------------
Cost Group : 'CK' (path_group 'CK') Cost Group : 'CK' (path_group 'CK')
Timing slack : -369ps (TIMING VIOLATION) Timing slack : 1131ps
Start-point : q_reg[0]/CK Start-point : q_reg[0]/CK
End-point : q_reg[1]/D End-point : q_reg[1]/D

Excessive positive slack with clock period of 2ns and 50% duty cycle.

10/22/2021 SYNTHESIS & PD_PPR 22

8 Bit Carry lookahead adder ( Module and testbench)
module cla8bit_tb;
module cla(in1,in2,s,cy,ac,clk); reg [7:0]in1,in2;
reg[7:0]p,g,c; reg clk;
wire [7:0]s;
input [7:0]in1,in2; wire cy,ac;
cla8bit cla1(in1,in2,s,cy,ac,clk);
output[7:0]s; initial
begin
output cy,ac; in1= 8'd0;
in2 = 8'd0;
integer i; clk = 1'b0;
input clk; end
always #5 clk = ~clk;
always@(posedge clk)
initial
begin begin
#10 in1 = 8'd10;
c[0]=0; #10 in2 = 8'd99;
#10 in1 = 8'd55;
p=in1^in2; #10 in2 = 8'd09;
g=in1&in2; #10 in1 = 8'd99;
for(i=7;i>0;i=i-1) #10 in2 = 8'd99;
end
c[i]=g[i-1]|(p[i-1]&c[i-1]); initial
begin
end $dumpfile("cla8bit.vcd");
$dumpvars(2, cla8bit_tb);
assign s=p^c; end
assign cy=c[7]; initial
assign ac=c[4]; #200 $finish;
endmodule
endmodule
10/22/2021 SYNTHESIS & PD_PPR 23
8 bit Carry look
ahead adder

10/22/2021 SYNTHESIS & PD_PPR 24

RTL of 8 bit carry
lookahead adder

10/22/2021 SYNTHESIS & PD_PPR 25

Timing reports ( with and without constraints)
============================================================ ============================================================
Generated by: Genus(TM) Synthesis Solution 20.11- Generated by: Genus(TM) Synthesis Solution 20.11-s111_1
s111_1 Generated on: Nov 09 2021 02:18:53 pm
Generated on: Nov 09 2021 02:05:01 pm Module: adderCLA
Module: adderCLA Technology library: slow_vdd1v0 1.0
Technology library: slow_vdd1v0 1.0 Operating conditions: PVT_0P9V_125C (balanced_tree)
Operating conditions: PVT_0P9V_125C (balanced_tree) Wireload mode: enclosed
Wireload mode: enclosed Area mode: timing library
Area mode: timing library
============================================================
============================================================
Pin Type Fanout Load Slew Delay Arrival
(fF) (ps) (ps) (ps)
Pin TypeFanout Load Slew Delay Arrival
(fF) (ps) (ps) (ps) -------------------------------------------------------------
---------------------------------------------------------- (clock CK) launch 0 R
c_reg[1]/CK 0 +0 0 R c_reg[2]/CK 0 +0 0 R
c_reg[1]/Q DFFHQX1 3 0.8 27 +177 177 R c_reg[2]/Q DFFHQX1 2 0.8 27 +177 177 R
g509/A1 +0 177 g1386/B0 +0 177
g509/Y OAI21XL 1 0.4 94 +82 259 F g1386/Y OAI21X1 1 0.4 72 +74 250 F
g508/B0 +0 259 g1384/B0 +0 250
g508/Y OAI2BB1X1 1 0.3 37 +71 330 R g1384/Y OAI2BB1X1 1 0.3 33 +59 309 R
c_reg[2]/D DFFHQX1 +0 330 c_reg[3]/D <<< DFFHQX1 +0 309
c_reg[2]/CK setup 0 +123 453 R c_reg[3]/CK setup 0 +121 431 R
---------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Timing slack : UNCONSTRAINED (clock CK) capture 500 R
Start-point : c_reg[1]/CK -------------------------------------------------------------
End-point : c_reg[2]/D Cost Group : 'CK' (path_group 'CK')
Timing slack : 69ps
Start-point : c_reg[2]/CK
Optimized positive slack with clock period of 0.5ns End-point : c_reg[3]/D

10/22/2021 SYNTHESIS & PD_PPR 26

32 bit ALU with case statement
module alu_32bit_tb_case; module alu_32bit_case(y,a,b,f);
reg [31:0]a; input [31:0]a;
reg [31:0]b; input [31:0]b;
reg [2:0]f; input [2:0]f;
wire [31:0]y; output reg [31:0]y;
alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f)); always@(*)
initial begin
begin case(f)
a=32'h00000000; 3'b000:y=a&b; //AND Operation
b=32'hFFFFFFFF; 3'b001:y=a|b; //OR Operation
#10 f=3'b000; 3'b010:y=~(a&b); //NAND Operation
#10 f=3'b001; 3'b011:y=~(a|b); //NOR Operation
#10 f=3'b010; 3'b010:y=a+b; //Addition
#10 f=3'b100; 3'b011:y=a-b; //Subtraction
end 3'b100:y=a*b; //Multiply
initial default:y=32'bx;
#50 $finish; endcase
initial end
begin endmodule
$dumpfile("alu_case.vcd");
$dumpvars(2, alu_32bit_tb_case);
end
endmodule

10/22/2021 SYNTHESIS & PD_PPR 27

32 bit ALU with if statement
module alu_32bit_tb_if; module alu_32bit_if(y,clk,reset,a,b,f);
reg [31:0]a;
input [31:0]a;
reg [31:0]b;
reg [2:0]f;
input [31:0]b;
reg clk, reset; input [2:0]f;
input clk, reset;
wire [31:0]y; output reg [31:0]y;
alu_32bit_if test2(.y(y),.clk(clk), .reset(reset),.a(a),.b(b),.f(f)); always@(posedge clk, negedge reset)
initial begin clk = 1'b0;reset = 1'b1; end
always #5 clk = ~clk;
begin
initial if (!reset)
begin y= 0; else
a=32'h00000000; if(f==3'b000)
b=32'hFFFFFFFF; y=a&b; //AND Operation
else if (f==3'b001)
#10 f=3'b000;
#10 f=3'b001;
y=a|b; //OR Operation
#10 reset =1'b0; else if (f==3'b010)
#10 f=3'b000; y=a+b; //Addition
#10 f=3'b001; else if (f==3'b011)
#10 f=3'b010;
y=a-b; //Subtraction
#10 f=3'b100;
end
else if (f==3'b100)
initial y=a*b; //Multiply
#50 $finish; else
initial y=32'bx;
begin
end
$dumpfile("alu_case.vcd");
$dumpvars(2, alu_32bit_tb_if);
endmodule
end
endmodule

10/22/2021 SYNTHESIS & PD_PPR 28

Simulation

10/22/2021 SYNTHESIS & PD_PPR 29

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