Tessent Command Study Notes

1. set_logfile_handling: Specifies that the tool directs the transcription

information to a file; outputs a log file.

2. set_tsdb_output_directory: Set the output directory of tsdb and write the

required information into the directory of TSDB for use in subsequent steps.

3. open_tsdb: Makes the contents of the tsdb directory visible to the tool and
automatically opens the specified tsdb directory.

4. set_tool_options: This command sets some options in Tessent Shell; -

reapply_setting_after_re-elaboration {on|off}, when set_current_design is used
again on the current design, the design will be re-elaborated. When set to "on",
Tessent shell will retain some settings, such as add_clocks, add_black_boxes,
etc.; -allow_vhdl_2008 on|off, if there is a 2008 (version) structure in any
module, in order to load the 2008 version of the package, you must specify
Tessent shell.

5. set_design_macros: specifies one or more defined macros for use by

subsequent commands, that is, macro definition , for ease of use.

6. setenv: Specifies a shell environment variable in the tool environment; assigns a

new value to the environment variable, which only changes it in the current tool
session.

7. read_vhdl -format 2008 -f $f: Read one or more VHDL files into the specified or
default logic library ; -format 2008, optional, specifies the expected format of
the input file; -f, optional, tcl list, specifies the name of one or more ASCII files
pointing to the design files to be loaded. The called files are usually generated by
another tool, so this option requires the use of the file without converting it to
the format allowed by the read_vhdl command.

8. read_verilog: read one or more Verilog files into the specified or default logic
library; -format, optional, specifies the format of the input Verilog file; -
vcs_compatibility, optional, ignores syntax errors allowed by Synopsys
compilation.

9. read_cell_library: loads one or more cell library files into tools.

10. read_design: reloads the design after DFT insertion to perform analysis or
future DFT insertion processes; first use the read_verilog and read_vhdl
commands to read the design into the tool. In the design, once the DFT insertion
process is performed, the read_verilog and read_vhdl command lists require the
modified design to be reloaded into the tool and stored in design_name; for

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example: use the read_verilog and read_vhdl commands to read in the RTL code,
and then perform the Mbist insertion of the DFT. At this time, the RTL file has
been modified. When the logic test is inserted in the next step, the read_design
command is used to load the RTL file modified in the first step; -design_identifier,
optional, is used to specify the design_in of the design to be read in (each design
corresponds to a design_id, which is used to represent this design); –view
full|graybox|interface, determines the view of the design to be read in.

11. read_core_descriptions: Reads the specified TCD file; the TCD file is used to map
scan information from one level to the next level in order to run ATPG at a
higher level and relocate patterns for instances of the associated core (top read
submodule).

12. read_icl: read ICL files into internal ICL dbs.

13. set_current_design: specifies the top-level design for subsequent commands

until the next time the command is reset, in order to specify the top-level design
module.

14. add_black_boxes: treat instances of Verilog modules or cell libraries as black

boxes, and set constraint values on the output or bidirectional pins of the black
boxes; some blocks do not need to be scan chains and can be defined as black
boxes; -Auto, set netlist instances that do not have reference modules in the
netlist or cell library as black boxes.

15. set_design_level : specifies the level of the current design, including

chip|physical_block|sub_block. There is no default setting. This command must
be used to specify the level of the current design. The appropriate level must be
specified because this setting affects the create_dft_specification and
process_dft_specification commands, as well as DRC checks. If the design_level
is chip, TAPs (Test Access ports) will be inserted into the design, and all ports will
have a pad buffer. The physical_block is treated as a separate entity during
synthesis and laid out. When a physical block is instantiated in another physical
block, when synthesizing the parent physical block, the netlist view of the child
physical block does not need to be loaded into the tool, but the timing model of
the child physical block is used. The netlist of the sub_block usually exists as part
of the parent physical netlist. Scan insertion can be performed from the physical
block boundary, and scan chains can be inserted into the sub_block. (Since the
netlist of the sub_block is part of the parents physical block, why use sub_block?
It should be that the sub_block can be inserted separately)

16. set_system_mode: specifies the operating state you want the tool to enter,
setup, analyze, or insertion.

17. create_port: Creates a port on the specified design module. The default mode
after calling the tool is setup. After generating patterns, if you try to return to
setup mode, the tool will prompt you to save the patterns and issue an error:

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18. intercept_connection : A command that uses the get_dft_cell command to get a
cell with a specified function name, and uses it to intercept connections to pins,
ports, or nets. Add corresponding cells, such as Mux, AND, OR gates, to the
original connection to make the signal selectively connected.

 node
is either a port, pin or net name in the design, or a collection of port, pin or net
objects. Based on the type of the object and its attribute direction, for a pin or port,
intercepts the source or destionation connection of the object. If node is an inout pin
or port, or if node is a net corresponding to an inout pin or port, an error will occur.

 cell_function_name function_name
specifies the function of the cell used for interception, including and, buffer, inverter,
mux, or, clock_and, clock_buffer, clock_inverter, clock_mux, and clock_or.

 select select_source
specifies a node connected to the select input of the cell. The source must be a valid
pin, port, or net object, or a name, or a constant value of 0 or 1. If you want to insert
a gate and then connect additional pins later, you should use a constant value.

 leaf_instance_prefix prefix_name
Specifies the prefix to use when instantiating cells. If not specified, defaults to
"insertion_". The leaf instance name is a combination of prefix_name and
cell_function_name. When a collision is detected during instantiation (with the same
name), the tool automatically adds an "_" suffix to make the leaf name unique. Use a
special prefix if you want to easily find the inserted cells in synthesis or layout scripts
(using e.g. "get_cells prefix_name -hier").

19. get_instances: Returns a set of instances instantiated relative to the current

design that match the specified name_patterns list and are filtered by the
specified options; -silent, no error is reported if the set is empty; -of_modules,
only instances of the specified modules are returned.

20. create_connections: connect the pin, net, or port of the object.

21. set_simulation_options: This command controls the behavior during pattern

generation and simulation.

 set_Reset_dominate_clock OFFf|ON

Optional, used to determine whether the assertion of the set or reset port
dominates the clock value of flip-flops and latches when multiple ports are turned on
at the same time (multiple ports refer to clocks). When switch is on, the set or reset

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port is on (not both can be on at the same time), and the estimated value of the
state element (the value in the register or latch) depends on the set or reset port.
When the switch is off and multiple ports are turned on at the same time, the
estimated value depends on all the enabled ports. When the values of the enabled
ports are consistent, the state element is set to a consistent value, otherwise, the
state element is set to X. In addition, even if the switch is set, the state element is set
to X when set and reset are turned on at the same time.

-C6_mask_races OFf | ON

Enables pessimistic simulation on C6 violation state elements, masking the captured

value when data port transitions and clock capture occur in the same frame (data is
not captured, data should be captured in the next frame after clock capture). This
option allows changing the handling of cells with C6 violations when data and clock
ports have race transitions. By default, create_patterns turns on clock_off simulation,
and the tool assumes that the clock port transitions before the data port. If this
assumption is wrong, this option is recommended to mask cells with C6 violations to
prevent mismatches due to races. This feature is less pessimistic than
"add_cell_constraints -DRC C6" because the latter masks C6 violations even if no
races occur.

-MUX_Select_x_sim_x OFf | ON

Optional, specifies whether model_mux primitives in the design are consensus or

non-consensus. By default, the tool always models_mux as consensus (as long as
both data input ports are the same known value, and evaluates_mux is the known
value).

You can use the ON parameter to model the _mux primitive as non-consensus
(select line X -mux instance output X). Changing the _mux primitive to non-
consensus will reduce test coverage. And this switch can be used in any mode, but
when used in setup mode, the tool evaluates _mux instance as non-consensus mux
instances, which will cause additional DRC violations.

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