AMBA-AHB Protocol Interview Questions:

● Does HWDATA have to remain stable during an extended transfer?

● https://community.arm.com/support-forums/f/architectures-and-processors-
forum/6316/amba-ahb5-stable-between-clock-question

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● Must a read after a write to the same address return the newly written data?
● Can HWDATA change in the 2nd cycle of an ERROR response ?
● Arbitration: Can a master deassert HLOCK during a burst?
● Arbitration: Can a master perform transfers other than IDLE when the bus was granted to it,
but not requested by the master?
● Arbitration: If a master is currently granted the bus by default, how many cycles before
starting an non-IDLE transfer does it have to assert HBUSREQ?
● Arbitration: What is the relationship between the HLOCK signal and the HMASTLOCK
signal?
● Arbitration: When can the HGRANT signal change?
● Arbitration: Why is HADDR sometimes shown as an input to the arbiter?
● Can an arbiter be designed to always allow bursts to complete?
● Does the AHB Arbiter require address lines as input?
● General : When can Early Burst Termination occur
● General: Can HTRANS change whilst HREADY is low?
● General: Can a BUSY transfer occur at the end of a burst?
● General: Can a master change the address/control signals during a waited transfer?
● General: Does the address have to be aligned, even for IDLE transfers?
● General: How many masters can there be in an AHB system?
● General: Is HREADY an input or an output from slaves?
● General: Is a default slave really necessary?
● General: Is a dummy master really necessary?
● General: Is it legal for a master to change HADDR when a transfer is extended?
● General: Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a
burst?
● General: The specification recommends that only 16 wait states are used. What should you
do if more than 16 cycles are needed?
● General: What are the different bursts used for?
● General: What default state should be used for the HREADY and HRESP outputs from a
slave?
● General: What is a default slave?
● General: What is the difference between a dummy bus master and a default bus master?
● General: What is the recommended default value for HPROT?
● General: What sequences of transfers types (HTRANS) can occur on the bus?
● General: When a master rebuilds a burst which has been terminated early are there any
limitations on how it rebuilds the burst?
● General: Why is a burst not allowed to cross a 1 kilobyte boundary?
● How does the AHB handle LOCKed SPLITs?
● Is it legal for an AHB wrapping burst to be aligned with respect to the total number bytes in
the burst, such that it does not wrap?
● Split/Retry: Can a SPLIT or RETRY response be given at any point during a burst?
● Split/Retry: Can a slave assert HSPLITx in the same cycle that it gives a SPLIT response?
● Split/Retry: Can a slave use both SPLIT and RETRY responses?
● Split/Retry: What address should be on the bus during the IDLE cycle after a SPLIT or
RETRY?
● Split/Retry: What is the difference between SPLIT and RETRY responses?
● Split/Retry: What value should be used for HTRANS when an AHB master gets a RETRY
response from a slave in the middle of burst?
● Split/Retry: Will a master always lose the bus after a SPLIT response?
● When should a master assert and deassert the HLOCK signal for a locked transfer?
● When should a master deassert its HBUSREQ signal?
● When will the arbiter grant another master after a locked transfer?
● Why is there a 1KB restriction in AHB?
● When Should A Master Assert And Deassert The Hlock Signal For A Locked Transfer?
● Can An Arbiter Be Designed To Always Allow Bursts To Complete?
● Why Is Haddr Sometimes Shown As An Input To The Arbiter?
● What Is The Relationship Between The Hlock Signal And The Hmastlock
● When Should A Master Deassert Its Hbusreq Signal?
● When Will The Arbiter Grant Another Master After A Locked Transfer?
● Can A Master Deassert Hlock During A Burst?
● How AHB is pipelined architecture?
● What is the size of the max data that can be transferred in a single transfer?
● Okay, response is a single cycle? but error/split/retry is two cycles, why?
● Explain the concept of a two-cycle response?
● What if the slave gets the address out of range?
● How to connect multiple slaves to a single master?
● Explain the split-retry concept?
● What is the difference between HREADY and HREADY_OUT signals?
● What is the slave response for a BUSY transfer?
● What is the difference between WRAP4 and INCR4?
● How to terminate the INCR type transfer?
● What is the difference between BURST and Beat?
● How to calculate the size of the burst?
● Is HREADY is Input or output to/from the slave?
● What is the aligned and un-align concept?
● Explain wrapping calculation?
● Is early burst termination is done by Slave/Arbiter?
● Explain the LOCKED transfer?
● What is the default Master?
● How the slave will detect the end of INCR type burst transfer?