Course Code Digital Logic Design Course Type LTP

ECE2002 Credits 4
Course Objectives :
 To study the various number systems and simplify logical expressions using Boolean Algebra
 To use K-maps for reduction of Boolean functions
 To understand the design procedure of any combinational logic function
 To understand the basic principles of memory elements Latches and Flip flops
 To analyse and design a sequential logic circuit
 To design circits for FSM
 To use HDL for digital logic design
Course Outcomes:
Students who complete this course will be able
 To understand the basic principles of Boolean algebra
 To design and analyze combinational logic and sequential logic digital circuits
 To understand the basic number systems used in digital design
 To design and analyze finite state machines.
 To write and simulate a Verilog code for any digital design
Student Outcomes (SO) : a,b,c,k
Module
Module Description Hrs. SO
No.
1 Digital Logic Design Fundamentals : 9 a,b
Number Systems – Positional number systems, Number base conversions
between binary, octal , decimal and hexadecimal numbers – Unsigned and Signed
binary number systems.
Boolean Algebra : Basic definitions, theorems and properties of Boolean Algebra
- Boolean functions – canonical and standard forms –Digital logic gates –
Introduction to digital logic families (RTL , TTL,ECL and CML)
2 Combinational Logic Design : 10 a,b,c
Gate Level minimization – SOP and POS forms – The Karnaugh’s map method –
Four and Five variable functions – don’t care conditions.
Combinational Logic Functions: Analysis and design procedure – Non-arithmetic
logic functions – MUX, DEMUX, Code converters,Encoders, decoders,Parity
checker and generator. Arithmetic Circuits – Adders, subtractors, BCD adder and
Multiplier
3 Sequential Logic Circuits : Introduction – Synchronous sequential logic – 7 a,b,c
Latches & Flip-flops – SR, D, JK and T – characteristic equations & wave forms
– Analysis and design procedure – State diagram –state reduction – state
assignment
4 Registers, Counters & FSMs : Ripple counter and synchronous counter – 8 b,c
Design procedure for synchronous MOD counters – UP/DOWN counter- Johnson
& Ring Counters - Shift registers – SISO, SIPO,PISO,POPI.
Finite State Machine : Mealy and Moore machine – Design of sequence
detectors.
5 Hardware Description Language : Verilog HDL - Lexical Conventions -Ports 9 a,c,k
and Modules, Gate Level Modeling, Operators, Data Flow Modeling, Behavioral
level Modeling, Testbench.

Modeling of Combinational and Sequential Logic Circuits using Verilog HDL.

6. Guest Lecture on Contemporary Topics 2 j

Total 45
Mode of Teaching and Learning:
Flipped Class Room, Activity Based Teaching/Learning, Digital/Computer based models, wherever possible to
augment lecture for practice/tutorial and minimum 2 hours lectures by industry experts on contemporary
topics
Mode of Evaluation:
The assessment and evaluation components may consist of unannounced open book examinations, quizzes,
student’s portfolio generation and assessment, and any other innovative assessment practices followed by
faculty, in addition to the Continuous Assessment Tests and Term End Examination.
Text Book(s):
1. M. Morris R. Mano and Michael D. Ciletti , “Digital Design With an Introduction to the Verilog
HDL”,6th Edition, Prentice Hall of India Pvt. Ltd., 2014.
2. Stephen Brown and ZvonkoVranesic, “Fundamentals of Digital Logic with Verilog Design”, Third
Edition, McGraw-Hill Higher Education, 2013.

Reference Book(s):
1. Mandal ”Digital Electronics Principles & Application, McGraw Hill Edu,2013.
2. Comer “Digital Logic & State Machine Design, Oxford, 2012.
3. William Keitz, Digital Electronics-A Practical Approach with VHDL,Pearson,2013.

Indicative List of Experiments: SO –a,b,c,k

1. Design and Implementation of HA, FA, HA, FS
2. Code Converters (BCD to Gray, Gray to BCd and BCD to Excess-3)
3. a)Implementation of MUX/DEMUX using basic logic gates
b)Boolean function implementation using MUX IC
4. Design of data-path elements a) 4-bit Adder b) 2-bit Multiplier
5. a)Verification of Flip-flops b)Construction of a flip flop using gates (any one FF)
6. Design and implementation of MOD Counters
7. Simulation of Half Adder, Full Adder, Half subtractor and full subtractor
8. Simulation of Encoder/Decoder circuits
9. Simulation of N-bit Adder/ Multiplier/code converters
10. Design and simulation of Shift Registers
11. Design and simulation of different types of counters
Recommendation by the Board of Studies on
Approval by Academic council on
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