Course Code:21EC3C02 Course: Digital Electronics

Credits: 3 L:T:P:S : 3:0:2:0

CIE: 50% MarksSEE: 50% Marks
SEE Hours: 3Max. Marks: 100
Prerequisites if any Number Systems
Learning ➢ Design various logic gates and simplify Boolean equations.
Objectives ➢ Design various flip flops, shift registers and determining
outputs.
➢ Design different types of counters.
➢ Verifying the digital systems using Verilog HDL

Course Outcomes:
On successful completion of the course, the student will be able to:
COs Course Outcomes Bloom’s level
CO1 Apply algebraic and mapping techniques to minimize the Understand
hardware in implementation of combinational circuits.
CO2 Design, analyse and implement of sequential circuits with Analyze
timing diagram.
CO3 Design digital machines using state diagram and state table. Apply
CO4 Verify the design of combinational and sequential circuits Apply
using Verilog HDL

Mapping with POs and PSOs:

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
CO1 3 2 2 2 1 1 1 1 3 2 1
CO2 3 3 2 2 1 1 1 1 3 2 1
CO3 3 3 2 2 1 1 1 1 3 2 1
CO4 3 3 2 2 2 1 1 1 1 3 2 1
3 – Strong 2 – Medium 1 – Low

Course Structure
No. of No. of
Module 1 Lecture Tutorial
Hours Hours
1.1 Revision on Gates and Combinational Circuits, Sum of products and 4 -
products of sums, Minterms and Maxterms, Karnaugh map
Minimization, Implification using map entered variables and Quine-
McCluskey method of minimization
1.2 Design of Half and Full Adders, Half and Full Subtractors, Binary 2 -
Parallel Adder – Carry look ahead Adder, BCD Adder
1.3 Multiplexer, Demultiplexer, Magnitude Comparator, 1 -
1.4 Decoder, Encoder-Priority Encoder. 1 -
Module 2
2.1 SYNCHRONOUS SEQUENTIAL CIRCUITS: Flip flops – SR, JK, 1 -
T, D, and Master/Slave FF – operation and excitation tables.
2.2 Triggering of FF, Analysis, and design of clocked sequential circuits 1 -
2.3 Design – Moore/Mealy models, state minimization, state assignment, 2 -
circuit implementation
2.4 Design of Counters- Ripple Counters, Ring Counters, 1 -
2.5 Shift registers, Universal Shift Register. 1 -
2.6 ASYNCHRONOUS SEQUENTIAL CIRCUITS: Stable and 1 -
Unstable states, output specifications, cycles and races, state
reduction, race free assignments,
2.7 Hazards, Essential Hazards, Pulse mode sequential circuits, Design of 1 -
Hazard free circuits.
Module 3
3.1 Design Procedure, Design of sequence detector. 2 -
3.2 More complex design problems, Eliminations of redundant states and 1 -
techniques.
3.3 Basic memory structure – ROM, RAM, Programmable Logic 2 -
Devices, Programmable Logic Array (PLA) – Programmable Array
Logic (PAL) – Field Programmable Gate Arrays (FPGA).
3.4 Implementation of combinational logic circuits using PLA, PAL and 1 -
CLB.
3.5 Digital integrated circuits: Logic levels, propagation delay, power 2 -
dissipation, fan-out and fan-in, noise margin.
Module 4
4.1 Introduction to Verilog and Dataflow descriptions: Program structure, 3 -
Logic systems
4.2 Nets, Variables and Constants, Vectors and Operators, Arrays, 2 -
Logical operators, and expressions
4.3 Dataflow Design elements: Continuous assignments, delay 1 -
specification
4.4 expressions, rise, fall, and turn-off delays 1 -
4.5 Min, max, and typical delays. 1 -
Module 5
5.1 Behavioural Design elements: Structured procedures, initial and 1 -
always
5.2 blocking and non-blocking statements, 1 -
5.3 delay control, generate statement, event control 1 -
5.4 conditional statements, multiway branching, loops, sequential and 1 -
parallel blocks
5.5 Simulation, Test benches 1 -
5.6 Synthesis and Programs on combinational and sequential circuits, 1 -
5.7 Structural description 1 -
5.8 ASM charts 1 -
Total No. of Lecture Hours 40
Total No. of Tutorial Hours 0

Text Books:
1. Mano, Morris. “Digital logic.” Computer Design. Englewood Cliffs Prentice-Hall
(1979).
2. M. Morris Mano, Michael D. Ciletti, “Digital Design with an Introduction to the
Verilog HDL”, 5thEdition.
3. Samir Palnitkar, “Verilog HDL”, Published by Pearson Education 2003.
Reference Books:
1. Kumar, A. Anand. Fundamentals of Digital Circuits 2Nd Ed. PHI Learning Pvt. Ltd.,
2009.
2. Taub, Herbert, and Donald L. Schilling. Digital integrated electronics. New York:
McGraw-Hill, 1977.
3. Charles H. Roth, “Fundamentals of Logic Design”, Thomson books / Co. Publications,
5th Edition.
4. Digital Design (Verilog)-An Embedded Systems Approach Using Verilog, 1st Edition
- September 10, 2007.
5. James W. Bignel, Digital Electronics, Cengage learning, 5th Edition, 2007.
6. Comer “Digital Logic & State Machine Design, Oxford, 2012.
Digital Electronics Lab
Part A: Using Digital Trainer Kit
1 Verification of Basic gates and Simplification, Realization of Boolean expressions
using logic gates/Universal gates
2 Adders / Subtractors
3 MUX/DEMUX/Decoder and Encoders
4 F/F’s, Counters etc.,
Part B: Simulation, Synthesis and Implementation using Vivado and Artix 7/Zynq 7
Developmental Boards. Verifying and optimizing the design by analysing the CLB’s and
I/O’s for the given FPGA board.
1 Logic gates in Structural, Dataflow and Behavioural
2 Combinational Circuits-Adders, Subtractors, MUX, DEMUX and Encoders etc.,
3 Sequential Circuits -F/F’s, Counters