Esp32-C3 Technical Reference Manual en
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DooLooEsp32-C3 Technical Reference Manual en
Uploaded by
DooLooESP32C3
Technical Reference Manual
A RY
IN
IM
EL
PR
Pre-release v0.4
Espressif Systems
Copyright © 2021
www.espressif.com
Contents
Contents
1 ESPRISCV CPU 18
1.1 Overview 18
1.2 Features 18
1.3 Address Map 19
1.4 Configuration and Status Registers (CSRs) 19
1.4.1 Register Summary 19
1.4.2 Register Description 20
1.5 Interrupt Controller 28
RY
1.5.1 Features 28
1.5.2 Functional Description 28
1.5.3 Suggested Operation 30
1.5.3.1 Latency Aspects 30
1.5.3.2 Configuration Procedure 30
A
1.5.4 Register Summary 31
1.5.5 Register Description 32
1.6 Debug 35
1.6.1
1.6.2
Overview
Features
IN 35
36
1.6.3 Functional Description 36
1.6.4 Register Summary 36
IM
1.6.5 Register Description 36
1.7 Hardware Trigger 39
1.7.1 Features 39
1.7.2 Functional Description 39
1.7.3 Trigger Execution Flow 40
EL
1.7.4 Register Summary 40
1.7.5 Register Description 41
1.8 Memory Protection 45
1.8.1 Overview 45
1.8.2 Features 45
PR
1.8.3 Functional Description 45
1.8.4 Register Summary 46
1.8.5 Register Description 46
2 GDMA Controller (GDMA) 47
2.1 Overview 47
2.2 Features 47
2.3 Architecture 48
2.4 Functional Description 48
2.4.1 Linked List 49
2.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer 50
2.4.3 Memory-to-Memory Data Transfer 50
Espressif Systems 1 ESP32-C3 TRM (Pre-release v0.4)
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2.4.4 Enabling GDMA 50
2.4.5 Linked List Reading Process 51
2.4.6 EOF 52
2.4.7 Accessing Internal RAM 52
2.4.8 Arbitration 52
2.4.9 Bandwidth 53
2.5 GDMA Interrupts 53
2.6 Programming Procedures 54
2.6.1 Programming Procedures for GDMA’s Transmit Channel 54
2.6.2 Programming Procedures for GDMA’s Receive Channel 54
2.6.3 Programming Procedures for Memory-to-Memory Transfer 54
RY
2.7 Register Summary 56
2.8 Registers 60
3 System and Memory 77
3.1 Overview 77
3.2 Features 77
A
3.3 Functional Description 78
3.3.1 Address Mapping 78
3.3.2 Internal Memory 79
3.3.3 External Memory
3.3.3.1
IN
External Memory Address Mapping
81
81
3.3.3.2 Cache 82
3.3.3.3 Cache Operations 82
IM
3.3.4 GDMA Address Space 83
3.3.5 Modules/Peripherals 84
3.3.5.1 Module/Peripheral Address Mapping 84
4 eFuse Controller (EFUSE) 86
EL
4.1 Overview 86
4.2 Features 86
4.3 Functional Description 86
4.3.1 Structure 86
4.3.1.1 EFUSE_WR_DIS 90
PR
4.3.1.2 EFUSE_RD_DIS 90
4.3.1.3 Data Storage 90
4.3.2 Software Programming of Parameters 91
4.3.3 Software Reading of Parameters 93
4.3.4 eFuse VDDQ Timing 95
4.3.5 The Use of Parameters by Hardware Modules 95
4.3.6 Interrupts 95
4.4 Register Summary 96
4.5 Registers 100
5 IO MUX and GPIO Matrix (GPIO, IO MUX) 141
5.1 Overview 141
Espressif Systems 2 ESP32-C3 TRM (Pre-release v0.4)
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5.2 Features 141
5.3 Architectural Overview 141
5.4 Peripheral Input via GPIO Matrix 143
5.4.1 Overview 143
5.4.2 Signal Synchronization 144
5.4.3 Functional Description 144
5.4.4 Simple GPIO Input 145
5.5 Peripheral Output via GPIO Matrix 145
5.5.1 Overview 145
5.5.2 Functional Description 146
5.5.3 Simple GPIO Output 147
RY
5.5.4 Sigma Delta Modulated Output (SDM) 147
5.5.4.1 Functional Description 147
5.5.4.2 SDM Configuration 148
5.6 Direct Input and Output via IO MUX 148
5.6.1 Overview 148
5.6.2 Functional Description 148
A
5.7 Analog Functions of GPIO Pins 148
5.8 Pin Hold Feature 149
5.9 Power Supplies and Management of GPIO Pins 149
5.9.1
5.9.2
Power Supplies of GPIO Pins
Power Supply Management
IN 149
149
5.10 Peripheral Signal List 149
5.11 IO MUX Functions List 156
IM
5.12 Analog Functions List 157
5.13 Register Summary 157
5.13.1 GPIO Matrix Register Summary 157
5.13.2 IO MUX Register Summary 159
5.13.3 SDM Register Summary 160
EL
5.14 Registers 160
5.14.1 GPIO Matrix Registers 160
5.14.2 IO MUX Registers 168
5.14.3 SDM Output Registers 170
PR
6 Reset and Clock 172
6.1 Reset 172
6.1.1 Overview 172
6.1.2 Architectural Overview 172
6.1.3 Features 172
6.1.4 Functional Description 173
6.2 Clock 173
6.2.1 Overview 174
6.2.2 Architectural Overview 174
6.2.3 Features 174
6.2.4 Functional Description 175
6.2.4.1 CPU Clock 175
Espressif Systems 3 ESP32-C3 TRM (Pre-release v0.4)
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6.2.4.2 Peripheral Clock 175
®
6.2.4.3 Wi-Fi and Bluetooth LE Clock 177
6.2.4.4 RTC Clock 177
7 Chip Boot Control 178
7.1 Overview 178
7.2 Boot Mode Control 178
7.3 ROM Code Printing Control 179
8 Interrupt Matrix (INTMTRX) 181
8.1 Overview 181
RY
8.2 Features 181
8.3 Functional Description 181
8.3.1 Peripheral Interrupt Sources 181
8.3.2 CPU Interrupts 185
8.3.3 Allocate Peripheral Interrupt Source to CPU Interrupt 185
8.3.3.1 Allocate one peripheral interrupt source (Source_X) to CPU 185
A
8.3.3.2 Allocate multiple peripheral interrupt sources (Source_Xn) to CPU 185
8.3.3.3 Disable CPU peripheral interrupt source (Source_X) 185
8.3.4 Query Current Interrupt Status of Peripheral Interrupt Source 185
8.4
8.5
Register Summary
Registers
IN 186
190
9 System Timer (SYSTIMER) 196
IM
9.1 Overview 196
9.2 Features 196
9.3 Clock Source Selection 197
9.4 Functional Description 197
9.4.1 Counter 197
EL
9.4.2 Comparator and Alarm 198
9.4.3 Synchronization Operation 199
9.4.4 Interrupt 199
9.5 Programming Procedure 199
9.5.1 Read Current Count Value 199
PR
9.5.2 Configure One-Time Alarm in Target Mode 200
9.5.3 Configure Periodic Alarms in Period Mode 200
9.5.4 Update After Deep-sleep and Light-sleep 200
9.6 Register Summary 201
9.7 Registers 203
10 Timer Group (TIMG) 214
10.1 Overview 214
10.2 Functional Description 215
10.2.1 16-bit Prescaler and Clock Selection 215
10.2.2 54-bit Time-base Counter 215
10.2.3 Alarm Generation 216
Espressif Systems 4 ESP32-C3 TRM (Pre-release v0.4)
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10.2.4 Timer Reload 217
10.2.5 SLOW_CLK Frequency Calculation 217
10.2.6 Interrupts 217
10.3 Configuration and Usage 218
10.3.1 Timer as a Simple Clock 218
10.3.2 Timer as One-shot Alarm 218
10.3.3 Timer as Periodic Alarm 219
10.3.4 SLOW_CLK Frequency Calculation 219
10.4 Register Summary 220
10.5 Registers 221
11 Watchdog Timers (WDT)
RY
231
11.1 Overview 231
11.2 Digital Watchdog Timers 232
11.2.1 Features 232
11.2.2 Functional Description 232
11.2.2.1 Clock Source and 32-Bit Counter 233
A
11.2.2.2 Stages and Timeout Actions 233
11.2.2.3 Write Protection 234
11.2.2.4 Flash Boot Protection 234
11.3 Super Watchdog
11.3.1 Features
IN 234
235
11.3.2 Super Watchdog Controller 235
11.3.2.1 Structure 235
IM
11.3.2.2 Workflow 235
11.4 Interrupts 236
11.5 Registers 236
12 XTAL32K Watchdog Timers (XTWDT) 237
EL
12.1 Overview 237
12.2 Features 237
12.2.1 Interrupt and Wake-Up 237
12.2.2 BACKUP32K_CLK 237
12.3 Functional Description 237
PR
12.3.1 Workflow 238
12.3.2 BACKUP32K_CLK Working Principle 238
12.3.3 Configuring the Divisor Component of BACKUP32K_CLK 238
13 System Registers (SYSREG) 240
13.1 Overview 240
13.2 Features 240
13.3 Function Description 240
13.3.1 System and Memory Registers 240
13.3.1.1 Internal Memory 240
13.3.1.2 External Memory 241
13.3.1.3 RSA Memory 241
Espressif Systems 5 ESP32-C3 TRM (Pre-release v0.4)
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13.3.2 Clock Registers 242
13.3.3 Interrupt Signal Registers 242
13.3.4 Low-power Management Registers 242
13.3.5 Peripheral Clock Gating and Reset Registers 242
13.4 Register Summary 244
13.5 Registers 245
14 Debug Assist 257
14.1 Overview 257
14.2 Features 257
14.3 Functional Description 257
RY
14.3.1 Region Read/Write Monitoring 257
14.3.2 SP Monitoring 257
14.3.3 PC Logging 257
14.3.4 CPU/DMA Bus Access Logging 257
14.4 Recommended Operation 258
14.4.1 Region Monitoring and SP Monitoring Configuration Process 258
A
14.4.2 PC Logging Configuration Process 259
14.4.3 CPU/DMA Bus Access Logging Configuration Process 259
14.5 Register Summary 263
14.6 Registers
IN 265
15 SHA Accelerator (SHA) 282
15.1 Introduction 282
IM
15.2 Features 282
15.3 Working Modes 282
15.4 Function Description 283
15.4.1 Preprocessing 283
15.4.1.1 Padding the Message 283
EL
15.4.1.2 Parsing the Message 283
15.4.1.3 Setting the Initial Hash Value 284
15.4.2 Hash Operation 284
15.4.2.1 Typical SHA Mode Process 284
15.4.2.2 DMA-SHA Mode Process 285
PR
15.4.3 Message Digest 286
15.4.4 Interrupt 287
15.5 Register Summary 287
15.6 Registers 288
16 AES Accelerator (AES) 292
16.1 Introduction 292
16.2 Features 292
16.3 AES Working Modes 292
16.4 Typical AES Working Mode 294
16.4.1 Key, Plaintext, and Ciphertext 294
16.4.2 Endianness 294
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16.4.3 Operation Process 296
16.5 DMA-AES Working Mode 296
16.5.1 Key, Plaintext, and Ciphertext 297
16.5.2 Endianness 297
16.5.3 Standard Incrementing Function 298
16.5.4 Block Number 298
16.5.5 Initialization Vector 298
16.5.6 Block Operation Process 299
16.6 Memory Summary 299
16.7 Register Summary 300
16.8 Registers 301
RY
17 RSA Accelerator (RSA) 305
17.1 Introduction 305
17.2 Features 305
17.3 Functional Description 305
17.3.1 Large Number Modular Exponentiation 305
A
17.3.2 Large Number Modular Multiplication 307
17.3.3 Large Number Multiplication 307
17.3.4 Options for Acceleration 308
17.4
17.5
Memory Summary
Register Summary
IN 309
310
17.6 Registers 311
IM
18 HMAC Accelerator (HMAC) 315
18.1 Main Features 315
18.2 Functional Description 315
18.2.1 Upstream Mode 315
18.2.2 Downstream JTAG Enable Mode 316
EL
18.2.3 Downstream Digital Signature Mode 316
18.2.4 HMAC eFuse Configuration 316
18.2.5 HMAC Process (Detailed) 318
18.3 HMAC Algorithm Details 319
18.3.1 Padding Bits 319
PR
18.3.2 HMAC Algorithm Structure 320
18.4 Register Summary 322
18.5 Registers 324
19 Digital Signature (DS) 330
19.1 Overview 330
19.2 Features 330
19.3 Functional Description 330
19.3.1 Overview 330
19.3.2 Private Key Operands 331
19.3.3 Software Prerequisites 331
19.3.4 DS Operation at the Hardware Level 332
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19.3.5 DS Operation at the Software Level 333
19.4 Memory Summary 335
19.5 Register Summary 336
19.6 Registers 337
20 Clock Glitch Detection 339
20.1 Overview 339
20.2 Functional Description 339
20.2.1 Clock Glitch Detection 339
20.2.2 Reset 339
21 Random Number Generator (RNG)
RY
340
21.1 Introduction 340
21.2 Features 340
21.3 Functional Description 340
21.4 Programming Procedure 341
21.5 Register Summary 341
A
21.6 Register 341
22 UART Controller (UART) 342
22.1
22.2
Overview
Features
IN 342
342
22.3 UART Structure 343
22.4 Functional Description 344
IM
22.4.1 Clock and Reset 344
22.4.2 UART RAM 345
22.4.3 Baud Rate Generation and Detection 346
22.4.3.1 Baud Rate Generation 346
22.4.3.2 Baud Rate Detection 346
EL
22.4.4 UART Data Frame 347
22.4.5 RS485 348
22.4.5.1 Driver Control 348
22.4.5.2 Turnaround Delay 349
22.4.5.3 Bus Snooping 349
PR
22.4.6 IrDA 349
22.4.7 Wake-up 350
22.4.8 Flow Control 350
22.4.8.1 Hardware Flow Control 351
22.4.8.2 Software Flow Control 352
22.4.9 GDMA Mode 352
22.4.10 UART Interrupts 353
22.4.11 UHCI Interrupts 354
22.5 Programming Procedures 354
22.5.1 Register Type 354
22.5.1.1 Synchronous Registers 355
22.5.1.2 Static Registers 356
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22.5.1.3 Immediate Registers 356
22.5.2 Detailed Steps 356
22.5.2.1 Initializing URATn 357
22.5.2.2 Configuring URATn Communication 358
22.5.2.3 Enabling UARTn 358
22.6 Register Summary 359
22.7 Registers 361
23 I2C Controller (I2C) 397
23.1 Overview 397
23.2 Features 397
RY
23.3 I2C Architecture 398
23.4 Functional Description 400
23.4.1 Clock Configuration 400
23.4.2 SCL and SDA Noise Filtering 400
23.4.3 SCL Clock Stretching 401
23.4.4 Generating SCL Pulses in Idle State 401
A
23.4.5 Synchronization 401
23.4.6 Open-Drain Output 402
23.4.7 Timing Parameter Configuration 403
23.4.8 Timeout Control
23.4.9 Command Configuration
IN 404
405
23.4.10 TX/RX RAM Data Storage 406
23.4.11 Data Conversion 407
IM
23.4.12 Addressing Mode 407
23.4.13 R/W Bit Check in 10-bit Addressing Mode 407
23.4.14 To Start the I2C Controller 408
23.5 Programming Example 408
23.5.1 I2Cmaster Writes to I2Cslave with a 7-bit Address in One Command Sequence 408
EL
23.5.1.1 Introduction 408
23.5.1.2 Configuration Example 409
23.5.2 I2Cmaster Writes to I2Cslave with a 10-bit Address in One Command Sequence 410
23.5.2.1 Introduction 410
23.5.2.2 Configuration Example 410
PR
23.5.3 I2Cmaster Writes to I2Cslave with Two 7-bit Addresses in One Command Sequence 412
23.5.3.1 Introduction 412
23.5.3.2 Configuration Example 412
23.5.4 I2Cmaster Writes to I2Cslave with a 7-bit Address in Multiple Command Sequences 414
23.5.4.1 Introduction 414
23.5.4.2 Configuration Example 415
23.5.5 I2Cmaster Reads I2Cslave with a 7-bit Address in One Command Sequence 416
23.5.5.1 Introduction 416
23.5.5.2 Configuration Example 417
23.5.6 I2Cmaster Reads I2Cslave with a 10-bit Address in One Command Sequence 418
23.5.6.1 Introduction 418
23.5.6.2 Configuration Example 418
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23.5.7 I2Cmaster Reads I2Cslave with Two 7-bit Addresses in One Command Sequence 420
23.5.7.1 Introduction 420
23.5.7.2 Configuration Example 421
23.5.8 I2Cmaster Reads I2Cslave with a 7-bit Address in Multiple Command Sequences 423
23.5.8.1 Introduction 423
23.5.8.2 Configuration Example 424
23.6 Interrupts 425
23.7 Register Summary 427
23.8 Registers 429
24 USB Serial/JTAG Controller (USB_SERIAL_JTAG) 449
RY
24.1 Overview 449
24.2 Features 449
24.3 Functional Description 451
24.3.1 CDC-ACM USB Interface Functional Description 451
24.3.2 CDC-ACM Firmware Interface Functional Description 451
24.3.3 USB-to-JTAG Interface 452
A
24.3.4 JTAG Command Processor 452
24.3.5 USB-to-JTAG Interface: CMD_REP usage example 453
24.3.6 USB-to-JTAG Interface: Response Capture Unit 454
24.4 Recommended Operation
IN
24.3.7 USB-to-JTAG Interface: Control Transfer Requests 454
455
24.5 Register Summary 457
24.6 Registers 458
IM
25 Twowire Automotive Interface (TWAI) 472
25.1 Features 472
25.2 Functional Protocol 472
25.2.1 TWAI Properties 472
EL
25.2.2 TWAI Messages 473
25.2.2.1 Data Frames and Remote Frames 474
25.2.2.2 Error and Overload Frames 476
25.2.2.3 Interframe Space 477
25.2.3 TWAI Errors 478
PR
25.2.3.1 Error Types 478
25.2.3.2 Error States 478
25.2.3.3 Error Counters 479
25.2.4 TWAI Bit Timing 480
25.2.4.1 Nominal Bit 480
25.2.4.2 Hard Synchronization and Resynchronization 481
25.3 Architectural Overview 481
25.3.1 Registers Block 481
25.3.2 Bit Stream Processor 483
25.3.3 Error Management Logic 483
25.3.4 Bit Timing Logic 483
25.3.5 Acceptance Filter 483
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25.3.6 Receive FIFO 483
25.4 Functional Description 483
25.4.1 Modes 483
25.4.1.1 Reset Mode 484
25.4.1.2 Operation Mode 484
25.4.2 Bit Timing 484
25.4.3 Interrupt Management 485
25.4.3.1 Receive Interrupt (RXI) 485
25.4.3.2 Transmit Interrupt (TXI) 486
25.4.3.3 Error Warning Interrupt (EWI) 486
25.4.3.4 Data Overrun Interrupt (DOI) 486
RY
25.4.3.5 Error Passive Interrupt (TXI) 486
25.4.3.6 Arbitration Lost Interrupt (ALI) 487
25.4.3.7 Bus Error Interrupt (BEI) 487
25.4.3.8 Bus Status Interrupt (BSI) 487
25.4.4 Transmit and Receive Buffers 487
25.4.4.1 Overview of Buffers 487
A
25.4.4.2 Frame Information 488
25.4.4.3 Frame Identifier 488
25.4.4.4 Frame Data 489
25.4.5 Receive FIFO and Data Overruns
25.4.6 Acceptance Filter
IN 490
490
25.4.6.1 Single Filter Mode 491
25.4.6.2 Dual Filter Mode 491
IM
25.4.7 Error Management 492
25.4.7.1 Error Warning Limit 493
25.4.7.2 Error Passive 493
25.4.7.3 Bus-Off and Bus-Off Recovery 493
25.4.8 Error Code Capture 494
EL
25.4.9 Arbitration Lost Capture 495
25.5 Register Summary 497
25.6 Registers 498
26 LED PWM Controller (LEDC) 511
PR
26.1 Overview 511
26.2 Features 511
26.3 Functional Description 511
26.3.1 Architecture 511
26.3.2 Timers 512
26.3.2.1 Clock Source 512
26.3.2.2 Clock Divider Configuration 513
26.3.2.3 14-bit Counter 514
26.3.3 PWM Generators 514
26.3.4 Duty Cycle Fading 515
26.3.5 Interrupts 516
26.4 Register Summary 517
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26.5 Registers 519
27 Remote Control Peripheral (RMT) 526
27.1 Overview 526
27.2 Features 526
27.3 Functional Description 526
27.3.1 RMT Architecture 527
27.3.2 RMT RAM 527
27.3.3 Clock 529
27.3.4 Transmitter 529
27.3.4.1 Normal TX Mode 529
RY
27.3.4.2 Wrap TX Mode 529
27.3.4.3 TX Modulation 530
27.3.4.4 Continuous TX Mode 530
27.3.4.5 Simultaneous TX Mode 530
27.3.5 Receiver 531
27.3.5.1 Normal RX Mode 531
A
27.3.5.2 Wrap RX Mode 531
27.3.5.3 RX Filtering 532
27.3.5.4 RX Demodulation 532
27.3.6 Configuration Update
27.3.7 Interrupts
IN 532
533
27.4 Register Summary 534
27.5 Registers 535
IM
28 OnChip Sensor and Analog Signal Processing 550
28.1 Overview 550
28.2 SAR ADCs 550
28.2.1 Overview 550
EL
28.2.2 Features 550
28.2.3 Functional Description 550
28.2.3.1 Input Signals 552
28.2.3.2 ADC Conversion and Attenuation 552
28.2.3.3 DIG ADC Controller 552
PR
28.2.3.4 DIG ADC Clock 553
28.2.3.5 DMA Support 553
28.2.3.6 DIG ADC FSM 553
28.2.3.7 ADC Filters 556
28.2.3.8 Threshold Monitoring 557
28.2.3.9 SAR ADC2 Arbiter 557
28.3 Temperature Sensor 558
28.3.1 Overview 558
28.3.2 Features 558
28.3.3 Functional Description 558
28.4 Interrupts 559
28.5 Register Summary 559
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28.6 Register 560
29 Related Documentation and Resources 573
Glossary 574
Abbreviations for Peripherals 574
Abbreviations for Registers 574
Revision History 575
A RY
IN
IM
EL
PR
Espressif Systems 13 ESP32-C3 TRM (Pre-release v0.4)
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List of Tables
List of Tables
1-1 CPU Address Map 19
1-3 ID wise map of Interrupt Trap-Vector Addresses 29
1-6 NAPOT encoding for maddress 40
2-1 Selecting Peripherals via Register Configuration 50
2-2 Descriptor Field Alignment Requirements 52
2-3 Total Bandwidth Supported by GDMA 53
3-1 Address Mapping 79
3-2 Internal Memory Address Mapping 80
3-3 External Memory Address Mapping 81
RY
3-4 Module/Peripheral Address Mapping 84
4-1 Parameters in eFuse BLOCK0 87
4-2 Secure Key Purpose Values 89
4-3 Parameters in BLOCK1 to BLOCK10 89
4-4 Registers Information 93
A
4-5 Configuration of Default VDDQ Timing Parameters 95
5-1 Peripheral Signals via GPIO Matrix 151
5-2 IO MUX Pin Functions 156
5-3
5-4
Power-Up Glitches on Pins
Analog Functions of IO MUX Pins
IN 157
157
6-1 Reset Sources 173
6-2 CPU_CLK Clock Source 175
6-3 CPU Clock Frequency 175
IM
6-4 Peripheral Clocks 176
6-5 APB_CLK Clock Frequency 177
6-6 CRYPTO_CLK Frequency 177
7-1 Default Configuration of Strapping Pins 178
EL
7-2 Boot Mode Control 179
7-3 ROM Code Printing Control 180
8-1 CPU Peripheral Interrupt Configuration/Status Registers and Peripheral Interrupt Sources 183
9-1 UNITn Configuration Bits 198
9-2 Trigger Point 199
PR
9-3 Synchronization Operation 199
10-1 Alarm Generation When Up-Down Counter Increments 216
10-2 Alarm Generation When Up-Down Counter Decrements 216
13-1 Memory Controlling Bit 241
13-2 Clock Gating and Reset Bits 242
14-1 CPU Packet Format 261
14-2 DMA Packet Format 261
14-3 DMA Source 261
14-4 Written Data Format 261
15-1 SHA Accelerator Working Mode 282
15-2 SHA Hash Algorithm Selection 283
15-3 The Storage and Length of Message Digest from Different Algorithms 287
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List of Tables
16-1 AES Accelerator Working Mode 293
16-2 Key Length and Encryption/Decryption 293
16-3 Working Status under Typical AES Working Mode 294
16-4 Text Endianness Type for Typical AES 294
16-5 Key Endianness Type for AES-128 Encryption and Decryption 295
16-6 Key Endianness Type for AES-256 Encryption and Decryption 295
16-7 Block Cipher Mode 296
16-8 Working Status under DMA-AES Working mode 297
16-9 TEXT-PADDING 297
16-10 Text Endianness for DMA-AES 298
17-1 Acceleration Performance 309
RY
17-2 RSA Accelerator Memory Blocks 309
18-1 HMAC Purposes and Configuration Value 317
22-1 UARTn Synchronous Registers 355
22-2 UARTn Static Registers 356
23-1 I2C Synchronous Registers 401
24-1 Standard CDC-ACM Control Requests 451
A
24-2 CDC-ACM Settings with RTS and DTR 451
24-3 Commands of a Nibble 453
24-4 USB-to-JTAG Control Requests 454
24-5 JTAG Capabilities Descriptor
24-6 Reset SoC into Download Mode
IN 455
456
24-7 Reset SoC into Booting 456
25-1 Data Frames and Remote Frames in SFF and EFF 475
IM
25-2 Error Frame 476
25-3 Overload Frame 477
25-4 Interframe Space 478
25-5 Segments of a Nominal Bit Time 480
25-6 Bit Information of TWAI_BUS_TIMING_0_REG (0x18) 484
EL
25-7 Bit Information of TWAI_BUS_TIMING_1_REG (0x1c) 485
25-8 Buffer Layout for Standard Frame Format and Extended Frame Format 487
25-9 TX/RX Frame Information (SFF/EFF)�TWAI Address 0x40 488
25-10 TX/RX Identifier 1 (SFF); TWAI Address 0x44 488
25-11 TX/RX Identifier 2 (SFF); TWAI Address 0x48 489
PR
25-12 TX/RX Identifier 1 (EFF); TWAI Address 0x44 489
25-13 TX/RX Identifier 2 (EFF); TWAI Address 0x48 489
25-14 TX/RX Identifier 3 (EFF); TWAI Address 0x4c 489
25-15 TX/RX Identifier 4 (EFF); TWAI Address 0x50 489
25-16 Bit Information of TWAI_ERR_CODE_CAP_REG (0x30) 494
25-17 Bit Information of Bits SEG.4 - SEG.0 494
25-18 Bit Information of TWAI_ARB LOST CAP_REG (0x2c) 496
27-1 Configuration Update 532
28-1 SAR ADC Input Signals 552
28-2 Temperature Offset 559
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List of Figures
List of Figures
1-1 CPU Block Diagram 18
1-2 Debug System Overview 35
2-1 Modules with GDMA Feature and GDMA Channels 47
2-2 GDMA Engine Architecture 48
2-3 Structure of a Linked List 49
2-4 Relationship among Linked Lists 51
3-1 System Structure and Address Mapping 78
3-2 Cache Structure 82
3-3 Peripherals/modules that can work with GDMA 83
RY
4-1 Shift Register Circuit (first 32 output) 91
4-2 Shift Register Circuit (last 12 output) 91
5-1 Diagram of IO MUX and GPIO Matrix 142
5-2 Architecture of IO MUX and GPIO Matirx 142
5-3 Internal Structure of a Pad 143
A
5-4 GPIO Input Synchronized on APB Clock Rising Edge or on Falling Edge 144
5-5 Filter Timing of GPIO Input Signals 144
6-1 Reset Types 172
6-2
8-1
System Clock
Interrupt Matrix Structure
IN 174
181
9-1 System Timer Structure 196
9-2 System Timer Alarm Generation 197
10-1 Timer Units within Groups 214
IM
10-2 Timer Group Architecture 215
11-1 Watchdog Timers Overview 231
11-2 Watchdog Timers in ESP32-C3 232
11-3 Super Watchdog Controller Structure 235
EL
12-1 XTAL32K Watchdog Timer 237
18-1 HMAC SHA-256 Padding Diagram 320
18-2 HMAC Structure Schematic Diagram 320
19-1 Software Preparations and Hardware Working Process 331
20-1 XTAL_CLK Pulse Width 339
PR
21-1 Noise Source 340
22-1 UART Structure 343
22-2 UART Controllers Sharing RAM 345
22-3 UART Controllers Division 346
22-4 The Timing Diagram of Weak UART Signals Along Falling Edges 347
22-5 Structure of UART Data Frame 347
22-6 AT_CMD Character Structure 348
22-7 Driver Control Diagram in RS485 Mode 349
22-8 The Timing Diagram of Encoding and Decoding in SIR mode 350
22-9 IrDA Encoding and Decoding Diagram 350
22-10 Hardware Flow Control Diagram 351
22-11 Connection between Hardware Flow Control Signals 351
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List of Figures
22-12 Data Transfer in GDMA Mode 353
22-13 UART Programming Procedures 357
23-1 I2C Master Architecture 398
23-2 I2C Slave Architecture 398
23-3 I2C Protocol Timing (Cited from Fig.31 in The I2C-bus specification Version 2.1) 399
23-4 I2C Timing Parameters (Cited from Table 5 in The I2C-bus specification Version 2.1) 400
23-5 I2C Timing Diagram 403
23-6 Structure of I2C Command Registers 405
23-7 I2Cmaster Writing to I2Cslave with a 7-bit Address 408
23-8 I2Cmaster Writing to a Slave with a 10-bit Address 410
23-9 I2Cmaster Writing to I2Cslave with Two 7-bit Addresses 412
RY
23-10 I2Cmaster Writing to I2Cslave with a 7-bit Address in Multiple Sequences 414
23-11 I2Cmaster Reading I2Cslave with a 7-bit Address 416
23-12 I2Cmaster Reading I2Cslave with a 10-bit Address 418
23-13 I2Cmaster Reading N Bytes of Data from addrM of I2Cslave with a 7-bit Address 420
23-14 I2Cmaster Reading I2Cslave with a 7-bit Address in Segments 423
24-1 USB Serial/JTAG High Level Diagram 450
A
24-2 USB Serial/JTAG Block Diagram 450
25-1 Bit Fields in Data Frames and Remote Frames 474
25-2 Fields of an Error Frame 476
25-3 Fields of an Overload Frame
25-4 The Fields within an Interframe Space
IN 477
478
25-5 Layout of a Bit 480
25-6 TWAI Overview Diagram 482
IM
25-7 Acceptance Filter 491
25-8 Single Filter Mode 491
25-9 Dual Filter Mode 492
25-10 Error State Transition 493
25-11 Positions of Arbitration Lost Bits 496
EL
26-1 LED PWM Architecture 511
26-2 LED PWM Generator Diagram 512
26-3 Frequency Division When LEDC_CLK_DIV_TIMERx is a Non-Integer Value 513
26-4 LED_PWM Output Signal Diagram 515
26-5 Output Signal Diagram of Fading Duty Cycle 516
PR
27-1 RMT Architecture 527
27-2 Format of Pulse Code in RAM 527
28-1 SAR ADCs Function Overview 551
28-2 Diagram of DIG ADC FSM 554
28-3 APB_SARADC_SAR_PATT_TAB1_REG and Pattern Table Entry 0 - Entry 3 555
28-4 APB_SARADC_SAR_PATT_TAB2_REG and Pattern Table Entry 4 - Entry 7 555
28-5 Pattern Table Entry 555
28-6 cmd0 Configuration 556
28-7 cmd1 configuration 556
28-8 DMA Data Format 556
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1 ESPRISCV CPU
1.1 Overview
ESP-RISC-V CPU is a 32-bit core based upon RISC-V ISA comprising base integer (I), multiplication/division (M)
and compressed (C) standard extensions. The core has 4-stage, in-order, scalar pipeline optimized for area,
power and performance. CPU core complex has an interrupt-controller (INTC), debug module (DM) and system
bus (SYS BUS) interfaces for memory and peripheral access.
A RY
IN
IM
Figure 11. CPU Block Diagram
EL
1.2 Features
• Operating clock frequency up to 160 MHz
PR
• Zero wait cycle access to on-chip SRAM and Cache for program and data access over IRAM/DRAM
interface
• Interrupt controller (INTC) with up to 31 vectored interrupts with programmable priority and threshold levels
• Debug module (DM) compliant with RISC-V debug specification v0.13 with external debugger support over
an industry-standard JTAG/USB port
• Debugger direct system bus access (SBA) to memory and peripherals
• Hardware trigger compliant to RISC-V debug specification v0.13 with up to 8 breakpoints/watchpoints
• Physical memory protection (PMP) for up to 16 configurable regions
• 32-bit AHB system bus for peripheral access
• Configurable events for core performance metrics
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1.3 Address Map
Below table shows address map of various regions accessible by CPU for instruction, data, system bus
peripheral and debug.
Table 11. CPU Address Map
Name Description Starting Address Ending Address Access
IRAM Instruction Address Map 0x4000_0000 0x47FF_FFFF R/W
DRAM Data Address Map 0x3800_0000 0x3FFF_FFFF R/W
DM Debug Address Map 0x2000_0000 0x27FF_FFFF R/W
AHB AHB Address Map *default *default R/W
RY
*default : Address not matching any of the specified ranges (IRAM, DRAM, DM) are accessed using AHB
bus.
1.4 Configuration and Status Registers (CSRs)
A
1.4.1 Register Summary
Below is a list of CSRs available to the CPU. Except for the custom performance counter CSRs, all the
IN
implemented CSRs follow the standard mapping of bit fields as described in the RISC-V Instruction Set Manual,
Volume II: Privileged Architecture, Version 1.10. It must be noted that even among the standard CSRs, not all bit
fields have been implemented, limited by the subset of features implemented in the CPU. Refer to the next
section for detailed description of the subset of fields implemented under each of these CSRs.
IM
Name Description Address Access
Machine Information CSRs
mvendorid Machine Vendor ID 0xF11 RO
marchid Machine Architecture ID 0xF12 RO
EL
mimpid Machine Implementation ID 0xF13 RO
mhartid Machine Hart ID 0xF14 RO
Machine Trap Setup CSRs
mstatus Machine Mode Status 0x300 R/W
1
misa Machine ISA 0x301 R/W
PR
2
mtvec Machine Trap Vector 0x305 R/W
Machine Trap Handling CSRs
mscratch Machine Scratch 0x340 R/W
mepc Machine Trap Program Counter 0x341 R/W
3
mcause Machine Trap Cause 0x342 R/W
mtval Machine Trap Value 0x343 R/W
Physical Memory Protection (PMP) CSRs
pmpcfg0 Physical memory protection configuration 0x3A0 R/W
1 Although misa is specified as having both read and write access (R/W), its fields are hardwired and thus write has no effect. This is what
would be termed WARL (Write Any Read Legal) in RISC-V terminology
2 mtvec only provides configuration for trap handling in vectored mode with the base address aligned to 256 bytes
3 External interrupt IDs reflected in mcause include even those IDs which have been reserved by RISC-V standard for core internal sources.
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Name Description Address Access
pmpcfg1 Physical memory protection configuration 0x3A1 R/W
pmpcfg2 Physical memory protection configuration 0x3A2 R/W
pmpcfg3 Physical memory protection configuration 0x3A3 R/W
pmpaddr0 Physical memory protection address register 0x3B0 R/W
pmpaddr1 Physical memory protection address register 0x3B1 R/W
....
pmpaddr15 Physical memory protection address register 0x3BF R/W
Trigger Module CSRs (shared with Debug Mode)
tselect Trigger Select Register 0x7A0 R/W
tdata1 Trigger Abstract Data 1 0x7A1 R/W
RY
tdata2 Trigger Abstract Data 2 0x7A2 R/W
tcontrol Global Trigger Control 0x7A5 R/W
Debug Mode CSRs
dcsr Debug Control and Status 0x7B0 R/W
dpc Debug PC 0x7B1 R/W
A
dscratch0 Debug Scratch Register 0 0x7B2 R/W
dscratch1 Debug Scratch Register 1 0x7B3 R/W
4
Performance Counter CSRs (Custom)
mpcer
mpcmr
IN
Machine Performance Counter Event
Machine Performance Counter Mode
0x7E0
0x7E1
R/W
R/W
mpccr Machine Performance Counter Count 0x7E2 R/W
GPIO Access CSRs (Custom)
IM
gpio_oen GPIO Output Enable 0x803 R/W
gpio_in GPIO Input Value 0x804 RO
gpio_out GPIO Output Value 0x805 R/W
EL
Note that if write/set/clear operation is attempted on any of the CSRs which are read-only (RO), as indicated in
the above table, the CPU will generate illegal instruction exception.
1.4.2 Register Description
Register 1.1. mvendorid (0xF11)
PR
D
RI
O
ND
VE
M
31 0
0x00000612 Reset
MVENDORID Vendor ID. (RO)
4 These custom CSRs have been implemented in the address space reserved by RISC-V standard for custom use
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Register 1.2. marchid (0xF12)
ID
CH
AR
M
31 0
0x80000001 Reset
MARCHID Architecture ID. (RO)
Register 1.3. mimpid (0xF13)
RY
D
PI
IM
M
31 0
0x00000001 Reset
MIMPID Implementation ID. (RO)
A
Register 1.4. mhartid (0xF14)
IN RT
ID
HA
M
31 0
IM
0x00000000 Reset
MHARTID Hart ID. (RO)
EL
PR
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Register 1.5. mstatus (0x300)
d)
d)
ed
ed
ed
ve
e
rv
rv
rv
rv
r
E
se
se
se
se
se
PP
PI
IE
TW
(re
(re
(re
(re
(re
M
M
31 22 21 20 13 12 11 10 8 7 6 4 3 2 0
0x000 0 0x00 0x0 0x0 0 0x0 0 0x0 Reset
MIE Global machine mode interrupt enable. (R/W)
MPIE Previous MIE. (R/W)
MPP Machine previous privilege mode. (R/W)
Possible values:
RY
• 0x0: User mode
• 0x3: Machine mode
Note : Only lower bit is writable. Write to the higher bit is ignored as it is directly tied to the lower bit.
TW Timeout wait. (R/W)
A
If this bit is set, executing WFI (Wait-for-Interrupt) instruction in User mode will cause illegal instruc-
tion exception. IN
IM
EL
PR
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Register 1.6. misa (0x301)
d)
ve
r
se
XL
(re
W
M
M
Q
C
N
H
U
D
R
B
K
S
A
Y
E
Z
F
J
I
31 30 29 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x1 0x0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 Reset
MXL Machine XLEN = 1 (32-bit). (RO)
Z Reserved = 0. (RO)
Y Reserved = 0. (RO)
RY
X Non-standard extensions present = 0. (RO)
W Reserved = 0. (RO)
V Reserved = 0. (RO)
U User mode implemented = 1. (RO)
A
T Reserved = 0. (RO)
S Supervisor mode implemented = 0. (RO)
R Reserved = 0. (RO)
IN
Q Quad-precision floating-point extension = 0. (RO)
P Reserved = 0. (RO)
IM
O Reserved = 0. (RO)
N User-level interrupts supported = 0. (RO)
M Integer Multiply/Divide extension = 1. (RO)
EL
L Reserved = 0. (RO)
K Reserved = 0. (RO)
J Reserved = 0. (RO)
PR
I RV32I base ISA = 1. (RO)
H Hypervisor extension = 0. (RO)
G Additional standard extensions present = 0. (RO)
F Single-precision floating-point extension = 0. (RO)
E RV32E base ISA = 0. (RO)
D Double-precision floating-point extension = 0. (RO)
C Compressed Extension = 1. (RO)
B Reserved = 0. (RO)
A Atomic Extension = 0. (RO)
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Register 1.7. mtvec (0x305)
)
ed
rv
DE
SE
se
O
BA
(re
M
31 8 7 2 1 0
0x000000 0x00 0x1 Reset
MODE Only vectored mode 0x1 is available. (RO)
BASE Higher 24 bits of trap vector base address aligned to 256 bytes. (R/W)
RY
Register 1.8. mscratch (0x340)
H
TC
RA
SC
M
31 0
0x00000000 Reset
A
MSCRATCH Machine scratch register for custom use. (R/W)
IN
Register 1.9. mepc (0x341)
C
EP
IM M
31 0
0x00000000 Reset
MEPC Machine trap/exception program counter. (R/W)
This is automatically updated with address of the instruction which was about to be executed while
EL
CPU encountered the most recent trap.
PR
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Register 1.10. mcause (0x342)
de
Co
F lag
n
)
ed
io
pt
pt
rv
rru
ce
se
te
Ex
(re
In
31 30 5 4 0
0 0x0000000 0x00 Reset
Exception Code This field is automatically updated with unique ID of the most recent exception or
interrupt due to which CPU entered trap. (R/W)
Possible exception IDs are:
RY
• 0x1: PMP Instruction access fault
• 0x2: Illegal Instruction
• 0x3: Hardware Breakpoint/Watchpoint or EBREAK
• 0x5: PMP Load access fault
• 0x7: PMP Store access fault
• 0x8: ECALL from U mode
• 0xb: ECALL from M mode
A
Note : Exception ID 0x0 (instruction access misaligned) is not present because CPU always masks
the lowest bit of the address during instruction fetch.
IN
Interrupt Flag This flag is automatically updated when CPU enters trap. (R/W)
If this is found to be set, indicates that the latest trap occurred due to interrupt. For exceptions it
remains unset.
Note : The interrupt controller is using up IDs in range 1-31 for all external interrupt sources. This is
IM
different from the RISC-V standard which has reserved IDs in range 0-15 for core internal interrupt
sources.
EL
Register 1.11. mtval (0x343)
AL
TV
M
31 0
0x00000000 Reset
PR
MTVAL Machine trap value. (R/W)
This is automatically updated with an exception dependent data which may be useful for handling
that exception.
Data is to be interpreted depending upon exception IDs:
• 0x1: Faulting virtual address of instruction
• 0x2: Faulting instruction opcode
• 0x5: Faulting data address of load operation
• 0x7: Faulting data address of store operation
Note : The value of this register is not valid for other exception IDs and interrupts.
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Register 1.12. mpcer (0x7E0)
N
P H KE
ST A D
JM C TA
LO RE ON
IN AZ AR
RD
BR NC P
M
AN H_
O NC
_H AZ
)
RA O
ed
(B _C
LD _H
ST _U
E
rv
ID D
CL
se
ST
P
LE
A
JM
CY
(re
IN
31 11 10 9 8 7 6 5 4 3 2 1 0
0x000 0 0 0 0 0 0 0 0 0 0 0 Reset
INST_COMP Count Compressed Instructions. (R/W)
BRANCH_TAKEN Count Branches Taken. (R/W)
BRANCH Count Branches. (R/W)
RY
JMP_UNCOND Count Unconditional Jumps. (R/W)
STORE Count Stores. (R/W)
LOAD Count Loads. (R/W)
A
IDLE Count IDLE Cycles. (R/W)
JMP_HAZARD Count Jump Hazards. (R/W) IN
LD_HAZARD Count Load Hazards. (R/W)
INST Count Instructions. (R/W)
CYCLE Count Clock Cycles. (R/W)
IM
Note: Each bit selects a specific event for counter to increment. If more than one event is selected
and occurs simultaneously, then counter increments by one only.
EL
Register 1.13. mpcmr (0x7E1) T_ T
EN
UN _SA
d)
ve
CO NT
r
U
se
CO
(re
31 2 1 0
PR
0 1 1 Reset
COUNT_SAT Counter Saturation Control. (R/W)
Possible values:
• 0: Overflow on maximum value
• 1: Halt on maximum value
COUNT_EN Counter Enable Control. (R/W)
Possible values:
• 0: Disabled
• 1: Enabled
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Register 1.14. mpccr (0x7E2)
CR
PC
M
31 0
0x00000000 Reset
MPCCR Machine Performance Counter Value. (R/W)
Register 1.15. gpio_oen (0x803)
RY PI E ]
PI E ]
PI E ]
PI E ]
PI E ]
PI E ]
EN ]
]
G _O N[7
G _O [6
G _O N[5
G _O [ 4
G _O N[3
G _O N[2
_O [1
[0
O N
O N
O N
)
PI E
ed
G _O
rv
O
O
O
O
se
PI
(re
G
31 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 Reset
GPIO_OEN GPIO[n] Output Enable. (R/W)
A
Refer to IOMUX for GPIO pin index mapping to this register
• 0: GPIO Output Disable
• 1: GPIO Output Enable
IN
Register 1.16. gpio_in (0x804)
IM
G _IN ]
G _IN ]
G _IN ]
O [4]
G _IN ]
G _IN ]
O [1]
0]
O 7
O [6
O [5
O [3
O [2
d)
PI IN[
N[
G _IN
ve
_I
_
r
O
se
PI
PI
PI
PI
PI
PI
PI
(re
G
G
31 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 Reset
EL
GPIO_IN GPIO[n] Input Value. (RO)
Refer to IOMUX for GPIO pin index mapping to this register
PR
Register 1.17. gpio_out (0x805)
PI U ]
PI U ]
PI U ]
PI U ]
PI U ]
PI U ]
UT ]
]
G _O [7
G _O T[6
G _O T[5
G _O [4
G _O T[3
G _O [2
_O [1
[0
O T
O T
O T
O T
PI U
d)
G _O
e
rv
O
O
O
se
PI
(re
31 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 Reset
GPIO_OUT GPIO[n] Output Value. (R/W)
Refer to IOMUX for GPIO pin index mapping to this register
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1.5 Interrupt Controller
1.5.1 Features
The interrupt controller allows capturing, masking and dynamic prioritization of interrupt sources routed from
peripherals to the RISC-V CPU. It supports:
• Up to 31 asynchronous interrupts with unique IDs (1-31)
• Configurable via read/write to memory mapped registers
• 15 levels of priority, programmable for each interrupt
• Support for both level and edge type interrupt sources
RY
• Programmable global threshold for masking interrupts with lower priority
• Interrupts IDs mapped to trap-vector address offsets
1.5.2 Functional Description
A
Each interrupt ID has 5 properties associated with it:
1. Enable State (0-1):
• Determines if an interrupt is enabled to be captured and serviced by the CPU.
IN
• Programmed by writing the corresponding bit in INT_ENABLE_REG.
2. Type (0-1):
• Enables latching the state of an interrupt signal on its rising edge.
IM
• Programmed by writing the corresponding bit in INT_TYPE_REG.
• An interrupt for which type is kept 0 is referred as a ’level’ type interrupt.
• An interrupt for which type is set to 1 is referred as an ’edge’ type interrupt.
EL
3. Priority (1-15):
• Determines which interrupt, among multiple pending interrupts, the CPU will service first.
• Programmed by writing to the INT_PRIORITY_n_REG for a particular ID n in range (1-31).
• Enabled interrupts with priorities zero or less than the threshold value in INT_THRESH_REG are
PR
masked.
• Priority levels increase from 1 (lowest) to 15 (highest).
• Interrupts with same priority are statically prioritized by their IDs, lowest ID having highest priority.
4. Pending State (0-1):
• Reflects the captured state of an enabled and unmasked interrupt signal.
• For each interrupt ID, the corresponding bit in read-only INT_EIP_REG gives its pending state.
• A pending interrupt will cause CPU to enter trap if no other pending interrupt has higher priority.
• A pending interrupt is said to be ’claimed’ if it preempts the CPU and causes it to jump to the
corresponding trap vector address.
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• All pending interrupts which are yet to be serviced are termed as ’unclaimed’.
5. Clear State (0-1):
• Toggling this will clear the pending state of claimed edge-type interrupts only.
• Toggled by first setting and then clearing the corresponding bit in INT_CLEAR_REG.
• Pending state of a level type interrupt is unaffected by this and must be cleared from source.
• Pending state of an unclaimed edge type interrupt can be flushed, if required, by first clearing the
corresponding bit in INT_ENABLE_REG and then toggling same bit in INT_CLEAR_REG.
When CPU services a pending interrupt, it:
RY
• saves the address of the current un-executed instruction in mepc for resuming execution later.
• updates the value of mcause with the ID of the interrupt being serviced.
• copies the state of MIE into MPIE, and subsequently clears MIE, thereby disabling interrupts globally.
• enters trap by jumping to a word-aligned offset of the address stored in mtvec.
Table 1-3 shows the mapping of each interrupt ID with the corresponding trap-vector address. In short, the word
A
aligned trap address for an interrupt with a certain ID = i can be calculated as (mtvec + 4i).
Note : ID = 0 is unavailable and therefore cannot be used for capturing interrupts. This is because the
IN
corresponding trap vector address (mtvec + 0x00) is reserved for exceptions.
Table 13. ID wise map of Interrupt TrapVector Addresses
ID Address ID Address ID Address ID Address
IM
0 NA 8 mtvec + 0x20 16 mtvec + 0x40 24 mtvec + 0x60
1 mtvec + 0x04 9 mtvec + 0x24 17 mtvec + 0x44 25 mtvec + 0x64
2 mtvec + 0x08 10 mtvec + 0x28 18 mtvec + 0x48 26 mtvec + 0x68
3 mtvec + 0x0c 11 mtvec + 0x2c 19 mtvec + 0x4c 27 mtvec + 0x6c
4 mtvec + 0x10 12 mtvec + 0x30 20 mtvec + 0x50 28 mtvec + 0x70
EL
5 mtvec + 0x14 13 mtvec + 0x34 21 mtvec + 0x54 29 mtvec + 0x74
6 mtvec + 0x18 14 mtvec + 0x38 22 mtvec + 0x58 30 mtvec + 0x78
7 mtvec + 0x1c 15 mtvec + 0x3c 23 mtvec + 0x5c 31 mtvec + 0x7c
PR
After jumping to the trap-vector, the execution flow is dependent on software implementation, although it can be
presumed that the interrupt will get handled (and cleared) in some interrupt service routine (ISR) and later the
normal execution will resume once the CPU encounters MRET instruction.
Upon execution of MRET instruction, the CPU:
• copies the state of MPIE back into MIE, and subsequently clears MPIE. This means that if previously MPIE
was set, then, after MRET, MIE will be set, thereby enabling interrupts globally.
• jumps to the address stored in mepc and resumes execution.
It is possible to perform software assisted nesting of interrupts inside an ISR as explained in 1.5.3.
The below listed points outline the functional behavior of the controller:
• Only if an interrupt has non-zero priority, higher or equal to the value in the threshold register, will it be
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reflected in INT_EIP_REG.
• If an interrupt is visible in INT_EIP_REG and has yet to be serviced, then it’s possible to mask it (and thereby
prevent the CPU from servicing it) by either lowering the value of its priority or increasing the global
threshold.
• If an interrupt, visible in INT_EIP_REG, is to be flushed (and prevented from being serviced at all), then it
must be disabled (and cleared if it is of edge type).
1.5.3 Suggested Operation
1.5.3.1 Latency Aspects
RY
There is latency involved while configuring the Interrupt Controller.
In steady state operation, the Interrupt Controller has a fixed latency of 4 cycles. Steady state means that no
changes have been made to the Interrupt Controller registers recently. This implies that any interrupt that is
asserted to the controller will take exactly 4 cycles before the CPU starts processing the interrupt. This further
implies that CPU may execute up to 5 instructions before the preemption happens.
A
Whenever any of its registers are modified, the Interrupt Controller enters into transient state, which may take up
to 4 cycles for it to settle down into steady state again. During this transient state, the ordering of interrupts may
not be predictable, and therefore, a few safety measures need to be taken in software to avoid any
synchronization issues.
IN
Also, it must be noted that the Interrupt Controller configuration registers lie in the APB address range, hence any
R/W access to these registers may take multiple cycles to complete.
IM
In consideration of above mentioned characteristics, users are advised to follow the sequence described below,
whenever modifying any of the Interrupt Controller registers:
1. save the state of MIE and clear MIE to 0
2. read-modify-write one or more Interrupt Controller registers
EL
3. execute FENCE instruction to wait for any pending write operations to complete
4. finally, restore the state of MIE
Due to its critical nature, it is recommended to disable interrupts globally (MIE=0) beforehand, whenever
configuring interrupt controller registers, and then restore MIE right after, as shown in the sequence above.
PR
After execution of the sequence above, the Interrupt Controller will resume operation in steady state.
1.5.3.2 Configuration Procedure
By default, interrupts are disabled globally, since the reset value of MIE bit in mstatus is 0. Software must set
MIE=1 after initialization of the interrupt stack (including setting mtvec to the interrupt vector address) is
done.
During normal execution, if an interrupt n is to be enabled, the below sequence may be followed:
1. save the state of MIE and clear MIE to 0
2. depending upon the type of the interrupt (edge/level), set/unset the nth bit of INT_TYPE_REG
3. set the priority by writing a value to INT_PRIORITY_n_REG in range 1(lowest) to 15 (highest)
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4. set the nth bit of INT_ENABLE_REG
5. execute FENCE instruction
6. restore the state of MIE
When one or more interrupts become pending, the CPU acknowledges (claims) the interrupt with the highest
priority and jumps to the trap vector address corresponding to the interrupt’s ID. Software implementation may
read mcause to infer the type of trap (mcause(31) is 1 for interrupts and 0 for exceptions) and then the ID of the
interrupt (mcause(4-0) gives ID of interrupt or exception). This inference may not be necessary if each entry in the
trap vector are jump instructions to different trap handlers. Ultimately, the trap handler(s) will redirect execution to
the appropriate ISR for this interrupt.
Upon entering into an ISR, software must toggle the nth bit of INT_CLEAR_REG if the interrupt is of edge type, or
RY
clear the source of the interrupt if it is of level type.
Software may also update the value of INT_THRESH_REG and program MIE=1 for allowing higher priority
interrupts to preempt the current ISR (nesting), however, before doing so, all the state CSRs must be saved
(mepc, mstatus, mcause, etc.) since they will get overwritten due to occurrence of such an interrupt. Later, when
exiting the ISR, the values of these CSRs must be restored.
A
Finally, after the execution returns from the ISR back to the trap handler, MRET instruction is used to resume
normal execution.
IN
Later, if the n interrupt is no longer needed and needs to be disabled, the following sequence may be
followed:
1. save the state of MIE and clear MIE to 0
IM
2. check if the interrupt is pending in INT_EIP_REG
3. set/unset the nth bit of INT_ENABLE_REG
4. if the interrupt is of edge type and was found to be pending in step 2 above, nth bit of INT_CLEAR_REG
must be toggled, so that its pending status gets flushed
EL
5. execute FENCE instruction
6. restore the state of MIE
Above is only a suggested scheme of operation. Actual software implementation may vary.
PR
1.5.4 Register Summary
The addresses in this section are relative to Interrupt Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
INT_ENABLE_REG Enables assertion of interrupt to the CPU 0x0104 R/W
INT_TYPE_REG Specify interrupt type as level/edge 0x0108 R/W
INT_CLEAR_REG Write to clear “pulse” type interrupts 0x010C R/W
INT_EIP_REG External/peripheral interrupt pending status to CPU 0x0110 RO
INT_PRIORITY_1_REG Priority setting for interrupt ID=1 0x0118 R/W
INT_PRIORITY_2_REG Priority setting for interrupt ID=2 0x011C R/W
INT_PRIORITY_3_REG Priority setting for interrupt ID=3 0x0120 R/W
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Name Description Address Access
INT_PRIORITY_4_REG Priority setting for interrupt ID=4 0x0124 R/W
INT_PRIORITY_5_REG Priority setting for interrupt ID=5 0x0128 R/W
INT_PRIORITY_6_REG Priority setting for interrupt ID=6 0x012C R/W
INT_PRIORITY_7_REG Priority setting for interrupt ID=7 0x0130 R/W
INT_PRIORITY_8_REG Priority setting for interrupt ID=8 0x0134 R/W
INT_PRIORITY_9_REG Priority setting for interrupt ID=9 0x0138 R/W
INT_PRIORITY_10_REG Priority setting for interrupt ID=10 0x013C R/W
INT_PRIORITY_11_REG Priority setting for interrupt ID=11 0x0140 R/W
INT_PRIORITY_12_REG Priority setting for interrupt ID=12 0x0144 R/W
INT_PRIORITY_13_REG Priority setting for interrupt ID=13 0x0148 R/W
RY
INT_PRIORITY_14_REG Priority setting for interrupt ID=14 0x014C R/W
INT_PRIORITY_15_REG Priority setting for interrupt ID=15 0x0150 R/W
INT_PRIORITY_16_REG Priority setting for interrupt ID=16 0x0154 R/W
INT_PRIORITY_17_REG Priority setting for interrupt ID=17 0x0158 R/W
INT_PRIORITY_18_REG Priority setting for interrupt ID=18 0x015C R/W
A
INT_PRIORITY_19_REG Priority setting for interrupt ID=19 0x0160 R/W
INT_PRIORITY_20_REG Priority setting for interrupt ID=20 0x0164 R/W
INT_PRIORITY_21_REG Priority setting for interrupt ID=21 0x0168 R/W
INT_PRIORITY_22_REG
INT_PRIORITY_23_REG
IN
Priority setting for interrupt ID=22
Priority setting for interrupt ID=23
0x016C
0x0170
R/W
R/W
INT_PRIORITY_24_REG Priority setting for interrupt ID=24 0x0174 R/W
INT_PRIORITY_25_REG Priority setting for interrupt ID=25 0x0178 R/W
IM
INT_PRIORITY_26_REG Priority setting for interrupt ID=26 0x017C R/W
INT_PRIORITY_27_REG Priority setting for interrupt ID=27 0x0180 R/W
INT_PRIORITY_28_REG Priority setting for interrupt ID=28 0x0184 R/W
INT_PRIORITY_29_REG Priority setting for interrupt ID=29 0x0188 R/W
INT_PRIORITY_30_REG Priority setting for interrupt ID=30 0x018C R/W
EL
INT_PRIORITY_31_REG Priority setting for interrupt ID=31 0x0190 R/W
INT_THRESH_REG Priority threshold setting for interrupt assertion to CPU 0x0194 R/W
1.5.5 Register Description
PR
The addresses in this section are relative to Interrupt Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
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Register 1.18. INT_ENABLE_REG (0x0104)
E
BL
)
ed
NA
rv
E
se
T_
(re
IN
31 1 0
0x00000000 0 Reset
INT_ENABLE[n] Setting nth bit enables assertion of nth interrupt to the CPU. (R/W)
• 0: Disabled;
• 1: Enabled;
RY
Register 1.19. INT_TYPE_REG (0x0108)
d)
P
ve
TY
er
T_
s
(re
IN
31 1 0
A
0x00000000 0 Reset
INT_TYPE[n] Setting nth bit enables capturing the rising edge of nth interrupt. (R/W)
• 0: Level type (signal level detection);
IN
• 1: Pulse type (rising edge detection);
IM
Register 1.20. INT_CLEAR_REG (0x010C)
AR
)
ed
LE
rv
C
se
T_
(re
IN
EL
31 1 0
0x00000000 0 Reset
INT_CLEAR[n] Set nth bit to clear pending status of the nth interrupt. (R/W)
This is only useful for “pulse” type interrupts, since “level” type interrupts must be cleared at source.
PR
Note that the set bit must be manually toggled back to 0 afterwards.
• 0: Don’t care;
• 1: Clear pending status;
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Register 1.21. INT_EIP_REG (0x0110)
)
ed
IP
rv
E
se
T_
(re
IN
31 1 0
0x00000000 0 Reset
INT_EIP[n] Read nth bit to get the pending status of nth interrupt to CPU. (RO)
Only enabled and above threshold interrupts are reflected here.
• 0: Not pending
• 1: Pending
RY
Register 1.22. INT_PRIORITY_n_REG (n: 131) (0x0114+4*n)
_n
TY
RI
IO
)
ed
R
A
rv
_P
se
T
(re
IN
31 4 3 0
0x00000000 0x0 Reset
IN
INT_PRIORITY_n Writing a 4-bit value to nth register configures priority of nth interrupt. (R/W)
Note : Interrupts with 0 priority are masked regardless of threshold value.
IM
Register 1.23. INT_THRESH_REG (0x0194)
SH
RE
d)
e
H
rv
_T
se
EL
T
(re
IN
31 4 3 0
0x00000000 0x0 Reset
INT_THRESH Writing a 4-bit value configures the global priority threshold for all interrupts. (R/W)
All interrupts with priority lower than the threshold are masked.
PR
Note : Interrupts with 0 priority are masked regardless of threshold value.
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1.6 Debug
1.6.1 Overview
This section describes how to debug and test software running on CPU core. Debug support is provided through
standard JTAG pins and complies to RISC-V External Debug Support Specification version 0.13.
Figure 1-2 below shows the main components of External Debug Support.
A RY
IN
IM
EL
Figure 12. Debug System Overview
PR
The user interacts with the Debug Host (eg. laptop), which is running a debugger (eg. gdb). The debugger
communicates with a Debug Translator (eg. OpenOCD, which may include a hardware driver) to communicate
with Debug Transport Hardware (eg. Olimex USB-JTAG adapter). The Debug Transport Hardware connects the
Debug Host to the ESP-RV Core’s Debug Transport Module (DTM) through standard JTAG interface. The DTM
provides access to the Debug Module (DM) using the Debug Module Interface (DMI).
The DM allows the debugger to halt the core. Abstract commands provide access to its GPRs (general purpose
registers). The Program Buffer allows the debugger to execute arbitrary code on the core, which allows access to
additional CPU core state. Alternatively, additional abstract commands can provide access to additional CPU
core state. ESP-RV core contains Trigger Module supporting 8 triggers. When trigger conditions are met, cores
will halt spontaneously and inform the debug module that they have halted.
System bus access block allows memory and peripheral register access without using RISC-V core.
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1.6.2 Features
Basic debug functionality supports below features.
• Provides necessary information about the implementation to the debugger.
• Allows the CPU core to be halted and resumed.
• CPU core registers (including CSR’s) can be read/written by debugger.
• CPU can be debugged from the first instruction executed after reset.
• CPU core can be reset through debugger.
• CPU can be halted on software breakpoint (planted breakpoint instruction).
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• Hardware single-stepping.
• Execute arbitrary instructions in the halted CPU by means of the program buffer. 16-word program buffer is
supported.
• System bus access is supported through word aligned address access.
A
• Supports eight Hardware Triggers (can be used as breakpoints/watchpoints) as described in Section 1.7.
1.6.3 Functional Description
IN
As mentioned earlier, Debug Scheme conforms to RISC-V External Debug Support Specification version 0.13.
Please refer the specs for functional operation details.
1.6.4 Register Summary
IM
Below is the list of Debug CSR’s supported by ESP-RV core.
Name Description Address Access
dcsr Debug Control and Status 0x7B0 R/W
dpc Debug PC 0x7B1 R/W
EL
dscratch0 Debug Scratch Register 0 0x7B2 R/W
dscratch1 Debug Scratch Register 1 0x7B3 R/W
.
PR
All the debug module registers are implemented in conformance to RISC-V External Debug Support Specification
version 0.13. Please refer it for more details.
1.6.5 Register Description
Below are the details of Debug CSR’s supported by ESP-RV core
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Register 1.24. dcsr (0x7B0)
tim t
ve
op n
e
m
st cou
d
eb d
st rved
ed
re aku
ug
ve
e
ak
rv
rv
e
eb
op
us
ep
re
re
se
se
se
se
v
xd
eb
pr
ca
st
re
re
re
31 28 27 16 15 14 13 12 11 10 9 8 6 5 3 2 1 0
4 0 0 0 0 0 0 0 0 0 0 0 Reset
xdebugver Debug version. (RO)
• 4: External debug support exists
ebreakm When 1, ebreak instructions in Machine Mode enter Debug Mode. (R/W)
RY
ebreaku When 1, ebreak instructions in User/Application Mode enter Debug Mode. (R/W)
stopcount This bit is not implemented. Debugger will always read this bit as 0. (RO)
stoptime This feature is not implemented. Debugger will always read this bit as 0. (RO)
cause Explains why Debug Mode was entered. When there are multiple reasons to enter Debug
A
Mode in a single cycle, the cause with the highest priority number is the one written.
1. An ebreak instruction was executed. (priority 3)
2. The Trigger Module caused a halt. (priority 4)
3.
4.
haltreq was set. (priority 2)
IN
The CPU core single stepped because step was set. (priority 1)
Other values are reserved for future use. (RO)
IM
step When set and not in Debug Mode, the core will only execute a single instruction and then enter
Debug Mode. Interrupts are enabled* when this bit is set. If the instruction does not complete due
to an exception, the core will immediately enter Debug Mode before executing the trap handler,
with appropriate exception registers set. (R/W)
prv Contains the privilege level the core was operating in when Debug Mode was entered. A debugger
EL
can change this value to change the core’s privilege level when exiting Debug Mode. Only 0x3
(machine mode) and 0x0(user mode) are supported.
PR
*Note: Different from RISC-V Debug specification 0.13
Register 1.25. dpc (0x7B1)
c
dp
31 0
0 Reset
dpc Upon entry to debug mode, dpc is written with the virtual address of the instruction that encoun-
tered the exception. When resuming, the CPU core’s PC is updated to the virtual address stored
in dpc. A debugger may write dpc to change where the CPU resumes. (R/W)
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Register 1.26. dscratch0 (0x7B2)
h0
c
at
cr
ds
31 0
0 Reset
dscratch0 Used by Debug Module internally. (R/W)
Register 1.27. dscratch1 (0x7B3)
RY
1
ch
at
cr
ds
31 0
0 Reset
dscratch1 Used by Debug Module internally. (R/W)
A
IN
IM
EL
PR
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1.7 Hardware Trigger
1.7.1 Features
Hardware Trigger module provides breakpoint and watchpoint capability for debugging. It includes the following
features:
• 8 independent trigger units
• each unit can be configured for matching the address of program counter or load-store accesses
• can preempt execution by causing breakpoint exception
• can halt execution and transfer control to debugger
RY
• support NAPOT (naturally aligned power of two) address encoding
1.7.2 Functional Description
The Hardware Trigger module provides four CSRs, which are listed under register summary section. Among
these, tdata1 and tdata2 are abstract CSRs, which means they are shadow registers for accessing internal
A
registers for each of the eight trigger units, one at a time.
To choose a particular trigger unit write the index (0-7) of that unit into tselect CSR. When tselect is written with a
IN
valid index, the abstract CSRs tdata1 and tdata2 are automatically mapped to reflect internal registers of that
trigger unit. Each trigger unit has two internal registers, namely mcontrol and maddress, which are mapped to
tdata1 and tdata2, respectively.
Writing larger than allowed indexes to tselect will clip the written value to the largest valid index, which can be
IM
read back. This property may be used for enumerating the number of available triggers during initialization or
when using a debugger.
Since software or debugger may need to know the type of the selected trigger to correctly interpret tdata1 and
tdata2, the 4 bits (31-28) of tdata1 encodes the type of the selected trigger. This type field is read-only and always
provides a value of 0x2 for every trigger, which stands for match type trigger, hence, it is inferred that tdata1 and
EL
tdata2 are to be interpreted as mcontrol and maddress. The information regarding other possible values can be
found in the RISC-V Debug Specification v0.13, but this trigger module only supports type 0x2.
Once a trigger unit has been chosen by writing its index to tselect, it will become possible to configure it by setting
the appropriate bits in mcontrol CSR (tdata1) and writing the target address to maddress CSR (tdata2).
PR
Each trigger unit can be configured to either cause breakpoint exception or enter debug mode, by writing to the
action bit of mcontrol. This bit can only be written from debugger, thus by default a trigger, if enabled, will cause
breakpoint exception.
mcontrol for each trigger unit has a hit bit which may be read, after CPU halts or enters exception, to find out if
this was the trigger unit that fired. This bit is set as soon as the corresponding trigger fires, but it has to be
manually cleared before resuming operation. Although, failing to clear it doesn’t affect normal execution in any
way.
Each trigger unit only supports match on address, although this address could either be that of a load/store
access or the virtual address of an instruction. The address and size of a region are specified by writing to
maddress (tdata2) CSR for the selected trigger unit. Larger than 1 byte region sizes are specified through NAPOT
(naturally aligned power of two) encoding (see Table 1-6) and enabled by setting match bit in mcontrol. Note that
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for NAPOT encoded addresses, by definition, the start address is constrained to be aligned to (i.e. an integer
multiple of) the region size.
Table 16. NAPOT encoding for maddress
maddress(31-0) Start Address Size (bytes)
aaa...aaaaaaaaa0 aaa...aaaaaaaaa0 2
aaa...aaaaaaaa01 aaa...aaaaaaaa00 4
aaa...aaaaaaa011 aaa...aaaaaaa000 8
aaa...aaaaaa0111 aaa...aaaaaa0000 16
....
a01...1111111111 a00...0000000000 231
RY
tcontrol CSR is common to all trigger units. It is used for preventing triggers from causing repeated exceptions in
machine-mode while execution is happening inside a trap handler. This also disables breakpoint exceptions
inside ISRs by default, although, it is possible to manually enable this right before entering an ISR, for debugging
purposes. This CSR is not relevant if a trigger is configured to enter debug mode.
A
1.7.3 Trigger Execution Flow IN
When hart is halted and enters debug mode due to the firing of a trigger (action = 1):
• dpc is set to current PC (in decode stage)
• cause field in dcsr is set to 2, which means halt due to trigger
IM
• hit bit is set to 1, corresponding to the trigger(s) which fired
When hart goes into trap due to the firing of a trigger (action = 0) :
• mepc is set to current PC (in decode stage)
• mcause is set to 3, which means breakpoint exception
EL
• mpte is set to the value in mte right before trap
• mte is set to 0
• hit bit is set to 1, corresponding to the trigger(s) which fired
Note : If two different triggers fire at the same time, one with action = 0 and another with action = 1, then hart is
PR
halted and enters debug mode.
1.7.4 Register Summary
Below is a list of Trigger Module CSRs supported by the CPU. These are only accessible from
machine-mode.
Name Description Address Access
tselect Trigger Select Register 0x7A0 R/W
tdata1 Trigger Abstract Data 1 0x7A1 R/W
tdata2 Trigger Abstract Data 2 0x7A2 R/W
tcontrol Global Trigger Control 0x7A5 R/W
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1.7.5 Register Description
Register 1.28. tselect (0x7A0)
d)
ve
t
er
c
ele
s
(re
ts
31 3 2 0
0x00000000 0x0 Reset
tselect Index (0-7) of the selected trigger unit. (R/W)
RY
Register 1.29. tdata1 (0x7A1)
e
od
pe
ta
dm
da
ty
31 28 27 26 0
0x2 0 0x3e00000 Reset
A
type Type of trigger. (RO)
This field is reserved since only match type (0x2) triggers are supported.
IN
dmode This is set to 1 if a trigger is being used by the debugger. (R/W *)
• 0: Both Debug and M-mode can write the tdata1 and tdata2 registers at the selected tselect.
• 1: Only Debug Mode can write the tdata1 and tdata2 registers at the selected tselect. Writes
IM
from other modes are ignored.
* Note : Only writable from debug mode.
data Abstract tdata1 content. (R/W)
This will always be interpreted as fields of mcontrol since only match type (0x2) triggers are sup-
EL
ported.
Register 1.30. tdata2 (0x7A2)
PR
2
a
at
td
31 0
0x00000000 Reset
tdata2 Abstract tdata2 content. (R/W)
This will always be interpreted as maddress since only match type (0x2) triggers are supported.
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Register 1.31. tcontrol (0x7A5)
)
ed
ed
rv
rv
e
se
se
pt
te
(re
(re
m
m
31 8 7 6 1 0
0x000000 0 0x00 0 Reset
mpte Machine mode previous trigger enable bit. (R/W)
• When CPU is taking a machine mode trap, the value of mte is automatically pushed into this.
• When CPU is executing MRET, its value is popped back into mte, so this becomes 0.
mte Machine mode trigger enable bit. (R/W)
RY
• When CPU is taking a machine mode trap, its value is automatically pushed into mpte, so this
becomes 0 and triggers with action=0 are disabled globally.
• When CPU is executing MRET, the value of mpte is automatically popped back into this.
A
IN
IM
EL
PR
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Register 1.32. mcontrol (0x7A1)
)
ed
ed
ed
ed
ed
st ute
e
rv
rv
rv
rv
rv
ch
n
od
se
se
se
se
se
e
io
ec
ad
at
or
dm
t
(re
(re
(re
(re
(re
ac
t
ex
m
lo
hi
u
31 28 27 26 21 20 19 16 15 12 11 10 7 6 5 4 3 2 1 0
0x2 0 0x1f 0 0 0 0 0 0 0 0 0 0 0 Reset
dmode Same as dmode in tdata1.
hit This is found to be 1 if the selected trigger had fired previously. (R/W)
This bit is to be cleared manually.
action Write this for configuring the selected trigger to perform one of the available actions when firing.
RY
(R/W)
Valid options are:
• 0x0: cause breakpoint exception.
• 0x1: enter debug mode (only valid when dmode = 1)
Note : Writing an invalid value will set this to the default value 0x0.
A
match Write this for configuring the selected trigger to perform one of the available matching opera-
tions on a data/instruction address. (R/W) Valid options are:
IN
• 0x0: exact byte match, i.e. address corresponding to one of the bytes in an access must
match the value of maddress exactly.
• 0x1: NAPOT match, i.e. at least one of the bytes of an access must lie in the NAPOT region
specified in maddress.
IM
Note : Writing a larger value will clip it to the largest possible value 0x1.
m Set this for enabling selected trigger to operate in machine mode. (R/W)
u Set this for enabling selected trigger to operate in user mode. (R/W)
EL
execute Set this for configuring the selected trigger to fire right before an instruction with matching
virtual address is executed by the CPU. (R/W)
store Set this for configuring the selected trigger to fire right before a store operation with matching
data address is executed by the CPU. (R/W)
PR
load Set this for configuring the selected trigger to fire right before a load operation with matching
data address is executed by the CPU. (R/W)
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Register 1.33. maddress (0x7A2)
ss
re
d
ad
m
31 0
0x00000000 Reset
maddress Address used by the selected trigger when performing match operation. (R/W)
This is decoded as NAPOT when match=1 in mcontrol.
A RY
IN
IM
EL
PR
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1.8 Memory Protection
1.8.1 Overview
The CPU core includes a physical memory protection unit, which can be used by software to set memory access
privileges (read, write and execute permissions) for required memory regions. However it is not fully compliant to
the Physical Memory Protection (PMP) description specified in RISCV Instruction Set Manual, Volume II:
Privileged Architecture, Version 1.10. Details of existing non-conformance are provided in next section.
For detailed understanding of the RISC-V PMP concept, please refer to RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Version 1.10.
RY
1.8.2 Features
The PMP unit can be used to restrict access to physical memory. It supports 16 regions and a minimum
granularity of 4 bytes. Below are the current non-conformance with PMP description from RISC-V Privilege
specifications:
• Static priority i.e. overlapping regions are not supported
A
• Maximum supported NAPOT range is 1 GB
As per RISC-V Privilege specifications, PMP entries should be statically prioritized and the lowest-numbered PMP
IN
entry that matches any address byte of an access will determine whether that access succeeds or fails. This
means, when any address matches more than one PMP entry i.e. overlapping regions among different PMP
entries, lowest number PMP entry will decide whether such address access will succeed or fail.
However, RISC-V CPU PMP unit in ESP32-C3 does not implement static priority. So, software should make sure
IM
that all enabled PMP entries are programmed with unique regions i.e. without any region overlap among them. If
software still tries to program multiple PMP entries with overlapping region having contradicting permissions, then
access will succeed if it matches at least one of enabled PMP entries. An exception will be generated, if access
matches none of the enabled PMP entries.
EL
1.8.3 Functional Description
Software can program the PMP unit’s configuration and address registers in order to contain faults and support
secure execution. PMP CSR’s can only be programmed in machine-mode. Once enabled, write, read and
execute permission checks are applied to all the accesses in user-mode as per programmed values of enabled
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16 pmpcfgX and pmpaddrX registers (refer Register Summary).
By default, PMP grants permission to all accesses in machine-mode and revokes permission of all access in
user-mode. This implies that it is mandatory to program address range and valid permissions in pmpcfg and
pmpaddr registers (refer Register Summary) for any valid access to pass through in user-mode. However, it is not
required for machine-mode as PMP permits all accesses to go through by deafult. In cases where PMP checks
are also required in machine-mode, software can set the lock bit of required PMP entry to enable permission
checks on it. Once lock bit is set, it can only be cleared through CPU reset.
When any instruction is being fetched from memory region without execute permissions, exception is generated
at processor level and exception cause is set as instruction access fault in mcause CSR. Similarly, any load/store
access without valid read/write permissions, will result in exception generation with mcause updated as load
access and store access fault respectively. In case of load/store access faults, violating address is captured in
mtval CSR.
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1.8.4 Register Summary
Below is a list of PMP CSRs supported by the CPU. These are only accessible from machine-mode.
Name Description Address Access
pmpcfg0 Physical memory protection configuration. 0x3A0 R/W
pmpcfg1 Physical memory protection configuration. 0x3A1 R/W
pmpcfg2 Physical memory protection configuration. 0x3A2 R/W
pmpcfg3 Physical memory protection configuration. 0x3A3 R/W
pmpaddr0 Physical memory protection address register. 0x3B0 R/W
pmpaddr1 Physical memory protection address register. 0x3B1 R/W
pmpaddr2 Physical memory protection address register. 0x3B2 R/W
RY
pmpaddr3 Physical memory protection address register. 0x3B3 R/W
pmpaddr4 Physical memory protection address register. 0x3B4 R/W
pmpaddr5 Physical memory protection address register. 0x3B5 R/W
pmpaddr6 Physical memory protection address register. 0x3B6 R/W
pmpaddr7 Physical memory protection address register. 0x3B7 R/W
A
pmpaddr8 Physical memory protection address register. 0x3B8 R/W
pmpaddr9 Physical memory protection address register. 0x3B9 R/W
pmpaddr10 Physical memory protection address register. 0x3BA R/W
pmpaddr11
pmpaddr12
IN
Physical memory protection address register.
Physical memory protection address register.
0x3BB
0x3BC
R/W
R/W
pmpaddr13 Physical memory protection address register. 0x3BD R/W
pmpaddr14 Physical memory protection address register. 0x3BE R/W
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pmpaddr15 Physical memory protection address register. 0x3BF R/W
1.8.5 Register Description
PMP unit implements all pmpcfg0-3 and pmpaddr0-15 CSRs as defined in RISCV Instruction Set Manual
EL
Volume II: Privileged Architecture, Version 1.10.
PR
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2 GDMA Controller (GDMA)
2.1 Overview
General Direct Memory Access (GDMA) is a feature that allows peripheral-to-memory, memory-to-peripheral, and
memory-to-memory data transfer at a high speed. The CPU is not involved in the GDMA transfer, and therefore it
becomes more efficient with less workload.
The GDMA controller in ESP32-C3 has six independent channels, i.e. three transmit channels and three receive
channels. These six channels are shared by peripherals with GDMA feature, namely SPI2, UHCI0
(UART0/UART1), I2S, AES, SHA, and ADC. Users can assign the six channels to any of these peripherals.
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UART0 and UART1 use UHCI0 together.
The GDMA controller uses fixed-priority and round-robin channel arbitration schemes to manage peripherals’
needs for bandwidth.
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IN
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Figure 21. Modules with GDMA Feature and GDMA Channels
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2.2 Features
The GDMA controller has the following features:
• AHB bus architecture
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• Programmable length of data to be transferred in bytes
• Linked list of descriptors
• INCR burst transfer when accessing internal RAM
• Access to an address space of 384 KB at most in internal RAM
• Three transmit channels and three receive channels
• Software-configurable selection of peripheral requesting its service
• Fixed channel priority and round-robin channel arbitration
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2.3 Architecture
In ESP32-C3, all modules that need high-speed data transfer support GDMA. The GDMA controller and CPU
data bus have access to the same address space in internal RAM. Figure 2-2 shows the basic architecture of the
GDMA engine.
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Figure 22. GDMA Engine Architecture
IN
The GDMA controller has six independent channels, i.e. three transmit channels and three receive channels.
Every channel can be connected to different peripherals. In other words, channels are general-purpose, shared
by peripherals. The GDMA engine reads data from or writes data to internal RAM via the AHB_BUS. For available
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address range of Internal RAM, please see Chapter 3 System and Memory. Software can use the GDMA engine
through linked lists. These linked lists, stored in internal RAM, consist of outlinkn and inlinkn, where n indicates
the channel number (ranging from 0 to 2). The GDMA controller reads an outlinkn (i.e. a linked list of transmit
descriptors) from internal RAM and transmits data in corresponding RAM according to the outlinkn, or reads an
inlinkn (i.e. a linked list of receive descriptors) and stores received data into specific address space in RAM
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according to the inlinkn.
2.4 Functional Description
PR
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2.4.1 Linked List
Linked List
31 30 29 28 27 23 11 0
DWO
DWl
DWO I owner suc_eof reserved! err_eof reserved length size I
DW1 buffer address pointer
DW2
DWO DW2 next descriptor address
DWl
DW2
DWO
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DWl
DW2
Figure 23. Structure of a Linked List
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Figure 2-3 shows the structure of a linked list. An outlink and an inlink have the same structure. A linked list is
formed by one or more descriptors, and each descriptor consists of three words. Linked lists should be in
internal RAM for the GDMA engine to be able to use them. The meaning of each field is as follows:
IN
• Owner (DW0) [31]: Specifies who is allowed to access the buffer that this descriptor points to.
1’b0: CPU can access the buffer;
1’b1: The GDMA controller can access the buffer.
When the GDMA controller stops using the buffer, this bit in a transmit descriptor is automatically cleared by
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hardware, and this bit in a receive descriptor is automatically cleared by hardware only if
GDMA_OUT_AUTO_WRBACK_CHn is set to 1. Software can disable automatic clearing by hardware by
setting GDMA_OUT_LOOP_TEST_CHn or GDMA_IN_LOOP_TEST_CHn bit. When software loads a linked
list, this bit should be set to 1.
Note: GDMA_OUT is the prefix of transmit channel registers, and GDMA_IN is the prefix of receive channel
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registers.
• suc_eof (DW0) [30]: Specifies whether this descriptor is the last descriptor in the list.
1’b0: This descriptor is not the last one;
1’b1: This descriptor is the last one.
PR
Software clears suc_eof bit in receive descriptors. When a packet has been received, this bit in the last
receive descriptor is set by hardware, and this bit in the last transmit descriptor is set by software.
• Reserved (DW0) [29]: Reserved. Value of this bit does not matter.
• err_eof (DW0) [28]: Specifies whether the received data has errors.
This bit is used only when UHCI0 uses GDMA to receive data. When an error is detected in the received
packet, this bit in the receive descriptor is set to 1 by hardware.
• Reserved (DW0) [27:24]: Reserved.
• Length (DW0) [23:12]: Specifies the number of valid bytes in the buffer that this descriptor points to. This
field in a transmit descriptor is written by software and indicates how many bytes can be read from the
buffer; this field in a receive descriptor is written by hardware automatically and indicates how many valid
bytes have been stored into the buffer.
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• Size (DW0) [11:0]: Specifies the size of the buffer that this descriptor points to.
• Buffer address pointer (DW1): Address of the buffer. This field can only point to internal RAM.
• Next descriptor address (DW2): Address of the next descriptor. If the current descriptor is the last one
(suc_eof = 1), this value is 0. This field can only point to internal RAM.
If the length of data received is smaller than the size of the buffer, the GDMA controller will not use available
space of the buffer in the next transaction.
2.4.2 PeripheraltoMemory and MemorytoPeripheral Data Transfer
The GDMA controller can transfer data from memory to peripheral (transmit) and from peripheral to memory
(receive). A transmit channel transfers data in the specified memory location to a peripheral’s transmitter via an
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outlinkn, whereas a receive channel transfers data received by a peripheral to the specified memory location via
an inlinkn.
Every transmit and receive channel can be connected to any peripheral with GDMA feature. Table 2-1 illustrates
how to select the peripheral to be connected via registers. When a channel is connected to a peripheral, the rest
channels can not be connected to that peripheral.
A
Table 21. Selecting Peripherals via Register Configuration
GDMA_IN_PERI_SEL_CHn
GDMA_OUT_PERI_SEL_CHn
IN Peripheral
0 SPI2
1 Reserved
2 UHCI0
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3 I2S
4 Reserved
5 Reserved
6 AES
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7 SHA
8 ADC
2.4.3 MemorytoMemory Data Transfer
PR
The GDMA controller also allows memory-to-memory data transfer. Such data transfer can be enabled by setting
GDMA_MEM_TRANS_EN_CHn, which connects the output of transmit channel n to the input of receive channel
n. Note that a transmit channel is only connected to the receive channel with the same number (n).
2.4.4 Enabling GDMA
Software uses the GDMA controller through linked lists. When the GDMA controller receives data, software loads
an inlink, configures GDMA_INLINK_ADDR_CHn field with address of the first receive descriptor, and sets
GDMA_INLINK_START_CHn bit to enable GDMA. When the GDMA controller transmits data, software loads an
outlink, prepares data to be transmitted, configures GDMA_OUTLINK_ADDR_CHn field with address of the first
transmit descriptor, and sets GDMA_OUTLINK_START_CHn bit to enable GDMA. GDMA_INLINK_START_CHn
bit and GDMA_OUTLINK_START_CHn bit are cleared automatically by hardware.
In some cases, you may want to append more descriptors to a DMA transfer that is already started. Naively, it
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would seem to be possible to do this by clearing the EOF bit of the final descriptor in the existing list and setting
its next descriptor address pointer field (DW2) to the first descriptor of the to-be-added list. However, this
strategy fails if the existing DMA transfer is almost or entirely finished. Instead, the GDMA engine has specialized
logic to make sure a DMA transfer can be continued or restarted: if it is still ongoing, it will make sure to take the
appended descriptors into account; if the transfer has already finished, it will restart with the new descriptors.
This is implemented in the Restart function.
When using the Restart function, software needs to rewrite address of the first descriptor in the new list to DW2
of the last descriptor in the loaded list, and set GDMA_INLINK_RESTART_CHn bit or
GDMA_OUTLINK_RESTART_CHn bit (these two bits are cleared automatically by hardware). As shown in Figure
2-4, by doing so hardware can obtain the address of the first descriptor in the new list when reading the last
descriptor in the loaded list, and then read the new list.
A RY
IN
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Figure 24. Relationship among Linked Lists
2.4.5 Linked List Reading Process
EL
Once configured and enabled by software, the GDMA controller starts to read the linked list from internal RAM.
The GDMA performs checks on descriptors in the linked list. Only if descriptors pass the checks, will the
corresponding GDMA channel transfer data. If the descriptors fail any of the checks, hardware will trigger
descriptor error interrupt (either GDMA_IN_DSCR_ERR_CHn_INT or GDMA_OUT_DSCR_ERR_CHn_INT), and
the channel will get stuck and stop working.
PR
The checks performed on descriptors are:
• Owner bit check when GDMA_IN_CHECK_OWNER_CHn or GDMA_OUT_CHECK_OWNER_CHn is set to
1. If the owner bit is 0, the buffer is accessed by the CPU. In this case, the owner bit fails the check. The
owner bit will not be checked if GDMA_IN_CHECK_OWNER_CHn or GDMA_OUT_CHECK_OWNER_CHn
is 0;
• Buffer address pointer (DW1) check. If the buffer address pointer points to 0x3FC80000 ~ 0x3FCDFFFF
(please refer to Section 2.4.7), it passes the check.
After software detects a descriptor error interrupt, it must reset the corresponding channel, and enable GDMA by
setting GDMA_OUTLINK_START_CHn or GDMA_INLINK_START_CHn bit.
Note: The third word (DW2) in a descriptor can only point to a location in internal RAM, given that the third word
points to the next descriptor to use and that all descriptors must be in internal memory.
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2.4.6 EOF
The GDMA controller uses EOF (end of file) flags to indicate the completion of data transfer.
Before the GDMA controller transmits data, GDMA_OUT_TOTAL_EOF_CHn_INT_ENA bit should be set to enable
GDMA_OUT_TOTAL_EOF_CHn_INT interrupt. If data in the buffer pointed by the last descriptor (with EOF) has
been transmitted, a GDMA_OUT_TOTAL_EOF_CHn_INT interrupt is generated.
Before the GDMA controller receives data, GDMA_IN_SUC_EOF_CHn_INT_ENA bit should be set to enable
GDMA_IN_SUC_EOF_CHn_INT interrupt. If data has been received successfully, a
GDMA_IN_SUC_EOF_CHn_INT interrupt is generated. In addition, when GDMA channel is connected to UHCI0,
the GDMA controller also supports GDMA_IN_ERR_CHn_EOF_INT interrupt. This interrupt is enabled by setting
GDMA_IN_ERR_EOF_CHn_INT_ENA bit, and it indicates that a data packet has been received with errors.
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When detecting a GDMA_OUT_TOTAL_EOF_CHn_INT or a GDMA_IN_SUC_EOF_CHn_INT interrupt, software
can record the value of GDMA_OUT_EOF_DES_ADDR_CHn or GDMA_IN_SUC_EOF_DES_ADDR_CHn field, i.e.
address of the last descriptor. Therefore, software can tell which descriptors have been used and reclaim
them.
Note: In this chapter, EOF of transmit descriptors refers to suc_eof, while EOF of receive descriptors refers to
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both suc_eof and err_eof.
2.4.7 Accessing Internal RAM
IN
Any transmit and receive channels of GDMA can access 0x3FC80000 ~ 0x3FCDFFFF in internal RAM. To
improve data transfer efficiency, GDMA can send data in burst mode, which is disabled by default. This mode is
enabled for receive channels by setting GDMA_IN_DATA_BURST_EN_CHn, and enabled for transmit channels
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by setting GDMA_OUT_DATA_BURST_EN_CHn.
Table 22. Descriptor Field Alignment Requirements
Inlink/Outlink Burst Mode Size Length Buffer Address Pointer
0 — — —
EL
Inlink
1 Word-aligned — Word-aligned
0 — — —
Outlink
1 — — —
Table 2-2 lists the requirements for descriptor field alignment when accessing internal RAM.
PR
When burst mode is disabled, size, length, and buffer address pointer in both transmit and receive descriptors do
not need to be word-aligned. That is to say, GDMA can read data of specified length (1 ~ 4095 bytes) from any
start addresses in the accessible address range, or write received data of the specified length (1 ~ 4095 bytes) to
any contiguous addresses in the accessible address range.
When burst mode is enabled, size, length, and buffer address pointer in transmit descriptors are also not
necessarily word-aligned. However, size and buffer address pointer in receive descriptors except length should
be word-aligned.
2.4.8 Arbitration
To ensure timely response to peripherals running at a high speed with low latency (such as SPI), the GDMA
controller implements a fixed-priority channel arbitration scheme. That is to say, each channel can be assigned a
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priority from 0 ~ 9. The larger the number, the higher the priority, and the more timely the response. When several
channels are assigned the same priority, the GDMA controller adopts a round-robin arbitration scheme.
Please note that the overall throughput of peripherals with GDMA feature cannot exceed the maximum
bandwidth of the GDMA, so that requests from low-priority peripherals can be responded to.
2.4.9 Bandwidth
As an AHB master, the GDMA controller accesses memory via the AHB bus. Without regard to other AHB
masters such as Wi-Fi, the total bandwidth supported by GDMA is calculated as:
All channels in burst mode: 8/5*fhclk MB/s;
All channels not in burst mode: 4/3*fhclk MB/s;
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where fhclk is the frequency of AHB clock fixed at 80 MHz. The total bandwidth according to formulas above is
listed in Table 2-3:
Table 23. Total Bandwidth Supported by GDMA
fpclk All Channels NOT in Burst Mode All Channels in Burst Mode
80 MHz 106.6 MB/s 128 MB/s
A
Please note that since the GDMA controller transfers data via linked list descriptors, the data transfer volume
IN
includes the number of bytes these descriptors have. The transfer efficiency corresponding to one descriptor is
length/(length + 12), where length is the field in the descriptor, and 12 is the number of bytes a descriptor has.
Therefore, applications with multiple linked list descriptors should increase length of each descriptor for higher
transfer efficiency, which can be 99.7% at most.
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When allocating bandwidth to a peripheral, software can estimate the bandwidth occupied by this peripheral
according to:
T*(length + 12)/length
where T stands for the throughput of this peripheral.
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2.5 GDMA Interrupts
• GDMA_OUT_TOTAL_EOF_CHn_INT: Triggered when all data corresponding to a linked list (including
multiple descriptors) has been sent via transmit channel n.
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• GDMA_IN_DSCR_EMPTY_CHn_INT: Triggered when the size of the buffer pointed by receive descriptors is
smaller than the length of data to be received via receive channel n.
• GDMA_OUT_DSCR_ERR_CHn_INT: Triggered when an error is detected in a transmit descriptor on
transmit channel n.
• GDMA_IN_DSCR_ERR_CHn_INT: Triggered when an error is detected in a receive descriptor on receive
channel n.
• GDMA_OUT_EOF_CHn_INT: Triggered when EOF in a transmit descriptor is 1 and data corresponding to
this descriptor has been sent via transmit channel n. If GDMA_OUT_EOF_MODE_CHn is 0, this interrupt
will be triggered when the last byte of data corresponding to this descriptor enters GDMA’s transmit
channel; if GDMA_OUT_EOF_MODE_CHn is 1, this interrupt is triggered when the last byte of data is taken
from GDMA’s transmit channel.
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• GDMA_OUT_DONE_CHn_INT: Triggered when all data corresponding to a transmit descriptor has been
sent via transmit channel n.
• GDMA_IN_ERR_EOF_CHn_INT: Triggered when an error is detected in the data packet received via receive
channel n. This interrupt is used only for UHCI0 peripheral (UART0 or UART1).
• GDMA_IN_SUC_EOF_CHn_INT: Triggered when a data packet has been received via receive channel n.
• GDMA_IN_DONE_CHn_INT: Triggered when all data corresponding to a receive descriptor has been
received via receive channel n.
2.6 Programming Procedures
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2.6.1 Programming Procedures for GDMA’s Transmit Channel
To transmit data, GDMA’s transmit channel should be configured by software as follows:
1. Set GDMA_OUT_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s transmit channel
and FIFO pointer;
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2. Load an outlink, and configure GDMA_OUTLINK_ADDR_CHn with address of the first transmit descriptor;
3. Configure GDMA_PERI_OUT_SEL_CHn with the value corresponding to the peripheral to be connected, as
shown in Table 2-1;
IN
4. Set GDMA_OUTLINK_START_CHn to enable GDMA’s transmit channel for data transfer;
5. Configure and enable the corresponding peripheral (SPI2, UHCI0 (UART0 or UART1), I2S, AES, SHA, and
ADC). See details in individual chapters of these peripherals;
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6. Wait for GDMA_OUT_EOF_CHn_INT interrupt, which indicates the completion of data transfer.
2.6.2 Programming Procedures for GDMA’s Receive Channel
To receive data, GDMA’s receive channel should be configured by software as follows:
EL
1. Set GDMA_IN_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s receive channel and
FIFO pointer;
2. Load an inlink, and configure GDMA_INLINK_ADDR_CHn with address of the first receive descriptor;
3. Configure GDMA_PERI_IN_SEL_CHn with the value corresponding to the peripheral to be connected, as
PR
shown in Table 2-1;
4. Set GDMA_INLINK_START_CHn to enable GDMA receive channel for data transfer;
5. Configure and enable the corresponding peripheral (SPI2, UHCI0 (UART0 or UART1), I2S, AES, SHA, and
ADC). See details in individual chapters of these peripherals;
6. Wait for GDMA_IN_SUC_EOF_CHn_INT interrupt, which indicates that a data packet has been received.
2.6.3 Programming Procedures for MemorytoMemory Transfer
To transfer data from one memory location to another, GDMA should be configured by software as follows:
1. Set GDMA_OUT_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s transmit channel
and FIFO pointer;
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2. Set GDMA_IN_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s receive channel and
FIFO pointer;
3. Load an outlink, and configure GDMA_OUTLINK_ADDR_CHn with address of the first transmit descriptor;
4. Load an inlink, and configure GDMA_INLINK_ADDR_CHn with address of the first receive descriptor;
5. Set GDMA_MEM_TRANS_EN_CHn to enable memory-to-memory transfer;
6. Set GDMA_OUTLINK_START_CHn to enable GDMA’s transmit channel for data transfer;
7. Set GDMA_INLINK_START_CHn to enable GDMA receive channel for data transfer;
8. Wait for GDMA_IN_SUC_EOF_CHn_INT interrupt, which indicates that which indicates that a data
transaction has been completed.
A RY
IN
IM
EL
PR
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2.7 Register Summary
The addresses in this section are relative to GDMA base address provided in Table 3-4 in Chapter 3 System and
Memory.
Name Description Address Access
Interrupt Registers
GDMA_INT_RAW_CH0_REG Raw status interrupt of RX channel 0 0x0000 R/WTC/SS
GDMA_INT_ST_CH0_REG Masked interrupt of RX channel 0 0x0004 RO
GDMA_INT_ENA_CH0_REG Interrupt enable bits of RX channel 0 0x0008 R/W
GDMA_INT_CLR_CH0_REG Interrupt clear bits of RX channel 0 0x000C WT
GDMA_INT_RAW_CH1_REG Raw status interrupt of RX channel 1 0x0010 R/WTC/SS
RY
GDMA_INT_ST_CH1_REG Masked interrupt of RX channel 1 0x0014 RO
GDMA_INT_ENA_CH1_REG Interrupt enable bits of RX channel 1 0x0018 R/W
GDMA_INT_CLR_CH1_REG Interrupt clear bits of RX channel 1 0x001C WT
GDMA_INT_RAW_CH2_REG Raw status interrupt of RX channel 2 0x0020 R/WTC/SS
GDMA_INT_ST_CH2_REG Masked interrupt of RX channel 2 0x0024 RO
A
GDMA_INT_ENA_CH2_REG Interrupt enable bits of RX channel 2 0x0028 R/W
GDMA_INT_CLR_CH2_REG Interrupt clear bits of RX channel 2 0x002C WT
Configuration Register
GDMA_MISC_CONF_REG
Version Registers
IN
MISC register 0x0044 R/W
GDMA_DATE_REG Version control register 0x0048 R/W
Configuration Registers
IM
GDMA_IN_CONF0_CH0_REG Configuration register 0 of RX channel 0 0x0070 R/W
GDMA_IN_CONF1_CH0_REG Configuration register 1 of RX channel 0 0x0074 R/W
GDMA_IN_POP_CH0_REG Pop control register of RX channel 0 0x007C varies
Link descriptor configuration and control
GDMA_IN_LINK_CH0_REG 0x0080 varies
register of RX channel 0
EL
GDMA_OUT_CONF0_CH0_REG Configuration register 0 of TX channel 0 0x00D0 R/W
GDMA_OUT_CONF1_CH0_REG Configuration register 1 of TX channel 0 0x00D4 R/W
GDMA_OUT_PUSH_CH0_REG Push control register of TX channel 0 0x00DC varies
Link descriptor configuration and control
GDMA_OUT_LINK_CH0_REG 0x00E0 varies
register of TX channel 0
PR
GDMA_IN_CONF0_CH1_REG Configuration register 0 of RX channel 1 0x0130 R/W
GDMA_IN_CONF1_CH1_REG Configuration register 1 of RX channel 1 0x0134 R/W
GDMA_IN_POP_CH1_REG Pop control register of RX channel 1 0x013C varies
Link descriptor configuration and control
GDMA_IN_LINK_CH1_REG 0x0140 varies
register of RX channel 1
GDMA_OUT_CONF0_CH1_REG Configuration register 0 of TX channel 1 0x0190 R/W
GDMA_OUT_CONF1_CH1_REG Configuration register 1 of TX channel 1 0x0194 R/W
GDMA_OUT_PUSH_CH1_REG Push control register of TX channel 1 0x019C varies
Link descriptor configuration and control
GDMA_OUT_LINK_CH1_REG 0x01A0 varies
register of TX channel 1
GDMA_IN_CONF0_CH2_REG Configuration register 0 of RX channel 2 0x01F0 R/W
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Name Description Address Access
GDMA_IN_CONF1_CH2_REG Configuration register 1 of RX channel 2 0x01F4 R/W
GDMA_IN_POP_CH2_REG Pop control register of RX channel 2 0x01FC varies
Link descriptor configuration and control
GDMA_IN_LINK_CH2_REG 0x0200 varies
register of RX channel 2
GDMA_OUT_CONF0_CH2_REG Configuration register 0 of TX channel 2 0x0250 R/W
GDMA_OUT_CONF1_CH2_REG Configuration register 1 of TX channel 2 0x0254 R/W
GDMA_OUT_PUSH_CH2_REG Push control register of TX channel 2 0x025C varies
Link descriptor configuration and control
GDMA_OUT_LINK_CH2_REG 0x0260 varies
register of TX channel 2
Status Registers
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GDMA_INFIFO_STATUS_CH0_REG RX FIFO status of RX channel 0 0x0078 RO
GDMA_IN_STATE_CH0_REG Receive status of RX channel 0 0x0084 RO
GDMA_IN_SUC_EOF_DES_ADDR_CH0 Inlink descriptor address when EOF
0x0088 RO
_REG occurs of RX channel 0
GDMA_IN_ERR_EOF_DES_ADDR_CH0 Inlink descriptor address when errors
0x008C RO
A
_REG occur of RX channel 0
Current inlink descriptor address of RX
GDMA_IN_DSCR_CH0_REG 0x0090 RO
channel 0
GDMA_IN_DSCR_BF0_CH0_REG
IN
The last inlink descriptor address of RX
channel 0
0x0094 RO
The second-to-last inlink descriptor
GDMA_IN_DSCR_BF1_CH0_REG 0x0098 RO
address of RX channel 0
IM
GDMA_OUTFIFO_STATUS_CH0_REG TX FIFO status of TX channel 0 0x00D8 RO
GDMA_OUT_STATE_CH0_REG Transmit status of TX channel 0 0x00E4 RO
Outlink descriptor address when EOF
0x00E8 RO
GDMA_OUT_EOF_DES_ADDR_CH0_REG occurs of TX channel 0
GDMA_OUT_EOF_BFR_DES_ADDR_CH0 The last outlink descriptor address when
0x00EC RO
EL
_REG EOF occurs of TX channel 0
Current inlink descriptor address of TX
GDMA_OUT_DSCR_CH0_REG 0x00F0 RO
channel 0
The last inlink descriptor address of TX
GDMA_OUT_DSCR_BF0_CH0_REG 0x00F4 RO
channel 0
PR
The second-to-last inlink descriptor
GDMA_OUT_DSCR_BF1_CH0_REG 0x00F8 RO
address of TX channel 0
GDMA_INFIFO_STATUS_CH1_REG RX FIFO status of RX channel 1 0x0138 RO
GDMA_IN_STATE_CH1_REG Receive status of RX channel 1 0x0144 RO
GDMA_IN_SUC_EOF_DES_ADDR_CH1 Inlink descriptor address when EOF
0x0148 RO
_REG occurs of RX channel 1
GDMA_IN_ERR_EOF_DES_ADDR_CH1 Inlink descriptor address when errors
0x014C RO
_REG occur of RX channel 1
Current inlink descriptor address of RX
GDMA_IN_DSCR_CH1_REG 0x0150 RO
channel 1
The last inlink descriptor address of RX
GDMA_IN_DSCR_BF0_CH1_REG 0x0154 RO
channel 1
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Name Description Address Access
The second-to-last inlink descriptor
GDMA_IN_DSCR_BF1_CH1_REG 0x0158 RO
address of RX channel 1
GDMA_OUTFIFO_STATUS_CH1_REG TX FIFO status of TX channel 1 0x0198 RO
GDMA_OUT_STATE_CH1_REG Transmit status of TX channel 1 0x01A4 RO
Outlink descriptor address when EOF
0x01A8 RO
GDMA_OUT_EOF_DES_ADDR_CH1_REG occurs of TX channel 1
GDMA_OUT_EOF_BFR_DES_ADDR_CH1 The last outlink descriptor address when
0x01AC RO
_REG EOF occurs of TX channel 1
Current inlink descriptor address of TX
GDMA_OUT_DSCR_CH1_REG 0x01B0 RO
channel 1
RY
The last inlink descriptor address of TX
GDMA_OUT_DSCR_BF0_CH1_REG 0x01B4 RO
channel 1
The second-to-last inlink descriptor
GDMA_OUT_DSCR_BF1_CH1_REG 0x01B8 RO
address of TX channel 1
GDMA_INFIFO_STATUS_CH2_REG RX FIFO status of RX channel 2 0x01F8 RO
GDMA_IN_STATE_CH2_REG Receive status of RX channel 2 0x0204 RO
A
GDMA_IN_SUC_EOF_DES_ADDR_CH2 Inlink descriptor address when EOF
0x0208 RO
_REG occurs of RX channel 2
GDMA_IN_ERR_EOF_DES_ADDR_CH2
_REG
IN
Inlink descriptor address when errors
occur of RX channel 2
0x020C RO
Current inlink descriptor address of RX
GDMA_IN_DSCR_CH2_REG 0x0210 RO
channel 2
IM
The last inlink descriptor address of RX
GDMA_IN_DSCR_BF0_CH2_REG 0x0214 RO
channel 2
The second-to-last inlink descriptor
GDMA_IN_DSCR_BF1_CH2_REG 0x0218 RO
address of RX channel 2
GDMA_OUTFIFO_STATUS_CH2_REG TX FIFO status of TX channel 2 0x0258 RO
EL
GDMA_OUT_STATE_CH2_REG Transmit status of TX channel 2 0x0264 RO
Outlink descriptor address when EOF
0x0268 RO
GDMA_OUT_EOF_DES_ADDR_CH2_REG occurs of TX channel 2
GDMA_OUT_EOF_BFR_DES_ADDR_CH2 The last outlink descriptor address when
0x026C RO
_REG EOF occurs of TX channel 2
PR
Current inlink descriptor address of TX
GDMA_OUT_DSCR_CH2_REG 0x0270 RO
channel 2
The last inlink descriptor address of TX
GDMA_OUT_DSCR_BF0_CH2_REG 0x0274 RO
channel 2
The second-to-last inlink descriptor
GDMA_OUT_DSCR_BF1_CH2_REG 0x0278 RO
address of TX channel 2
Priority Registers
GDMA_IN_PRI_CH0_REG Priority register of RX channel 0 0x009C R/W
GDMA_OUT_PRI_CH0_REG Priority register of TX channel 0 0x00FC R/W
GDMA_IN_PRI_CH1_REG Priority register of RX channel 1 0x015C R/W
GDMA_OUT_PRI_CH1_REG Priority register of TX channel 1 0x01BC R/W
GDMA_IN_PRI_CH2_REG Priority register of RX channel 2 0x021C R/W
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Name Description Address Access
GDMA_OUT_PRI_CH2_REG Priority register of TX channel 2 0x027C R/W
Peripheral Select Registers
GDMA_IN_PERI_SEL_CH0_REG Peripheral selection of RX channel 0 0x00A0 R/W
GDMA_OUT_PERI_SEL_CH0_REG Peripheral selection of TX channel 0 0x0100 R/W
GDMA_IN_PERI_SEL_CH1_REG Peripheral selection of RX channel 1 0x0160 R/W
GDMA_OUT_PERI_SEL_CH1_REG Peripheral selection of TX channel 1 0x01C0 R/W
GDMA_IN_PERI_SEL_CH2_REG Peripheral selection of RX channel 2 0x0220 R/W
GDMA_OUT_PERI_SEL_CH2_REG Peripheral selection of TX channel 2 0x0280 R/W
A RY
IN
IM
EL
PR
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2.8 Registers
The addresses in this section are relative to GDMA base address provided in Table 3-4 in Chapter 3 System and
Memory.
Register 2.1. GDMA_INT_RAW_CHn_REG (n: 02) (0x0000+16*n)
G A_ _ER N 0_ 0_ INT AW
G A_ T_ F_ R_ CH INT AW
A_ _S _E CH T_ T_R AW
IN UC OF 0_ RA AW
_ T W
DM O C L 0 _ AW
R
_ R
DM IN R E_ IN IN _R
AW W
_I INT AW
DM IN D C CH 0_ _
DM O E ER _ 0 _
DM IN T F_ 0 N A
G A_ T_ R_ EO INT AW
G A_ _DS CR PT CH AW
_C CH INT W
G A_ T_ R_ ERR CH INT
_R RA
G A_ T_ OV CH 0_I _R
G A_ _DS TA CH INT _R
_D _E _C IN W
NE F_ _ RA
H0 0_ _R
R
_ R
_ H NT
_ _
NT _
DM IN D EM F _
DM O C _ Y 0
O O H0 T_
G A_ FIF UD F_C 0_I
_ V H
_
G A_ FIF O_O F_C
H
_
DM IN IF D
DM O O F
G A_ TF O_U
O
U O
S
O
_
DM O IF
DM IN O
RY
G A_ TF
U
U
U
)
DM O
ed
G A_
rv
DM
se
(re
G
31 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GDMA_IN_DONE_CHn_INT_RAW The raw interrupt bit turns to high level when the last data pointed
A
by one inlink descriptor has been received for Rx channel 0. (R/WTC/SS)
GDMA_IN_SUC_EOF_CHn_INT_RAW The raw interrupt bit turns to high level when the last data
IN
pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt
bit turns to high level when the last data pointed by one inlink descriptor has been received and no
data error is detected for Rx channel 0. (R/WTC/SS)
GDMA_IN_ERR_EOF_CHn_INT_RAW The raw interrupt bit turns to high level when data error is
IM
detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this
raw interrupt is reserved. (R/WTC/SS)
GDMA_OUT_DONE_CHn_INT_RAW The raw interrupt bit turns to high level when the last data
pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. (R/WTC/SS)
EL
GDMA_OUT_EOF_CHn_INT_RAW The raw interrupt bit turns to high level when the last data pointed
by one outlink descriptor has been read from memory for Tx channel 0. (R/WTC/SS)
GDMA_IN_DSCR_ERR_CHn_INT_RAW The raw interrupt bit turns to high level when detecting inlink
PR
descriptor error, including owner error, the second and third word error of inlink descriptor for Rx
channel 0. (R/WTC/SS)
GDMA_OUT_DSCR_ERR_CHn_INT_RAW The raw interrupt bit turns to high level when detecting
outlink descriptor error, including owner error, the second and third word error of outlink descriptor
for Tx channel 0. (R/WTC/SS)
Continued on the next page...
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Register 2.1. GDMA_INT_RAW_CHn_REG (n: 02) (0x0000+16*n)
Continued from the previous page...
GDMA_IN_DSCR_EMPTY_CHn_INT_RAW The raw interrupt bit turns to high level when Rx buffer
pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel
0. (R/WTC/SS)
GDMA_OUT_TOTAL_EOF_CHn_INT_RAW The raw interrupt bit turns to high level when data cor-
responding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx
channel 0. (R/WTC/SS)
RY
GDMA_INFIFO_OVF_CHn_INT_RAW This raw interrupt bit turns to high level when level 1 fifo of Rx
channel 0 is overflow. (R/WTC/SS)
GDMA_INFIFO_UDF_CHn_INT_RAW This raw interrupt bit turns to high level when level 1 fifo of Rx
channel 0 is underflow. (R/WTC/SS)
GDMA_OUTFIFO_OVF_CHn_INT_RAW This raw interrupt bit turns to high level when level 1 fifo of
A
Tx channel 0 is overflow. (R/WTC/SS)
GDMA_OUTFIFO_UDF_CHn_INT_RAW This raw interrupt bit turns to high level when level 1 fifo of
Tx channel 0 is underflow. (R/WTC/SS)
IN
IM
EL
PR
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Register 2.2. GDMA_INT_ST_CHn_REG (n: 02) (0x0004+16*n)
G A_ _ER N 0_ 0_ INT T
G A_ T_ F_ R_ CH INT T
A_ _S _E CH T_ T_S T
S
_ S
DM IN R E_ IN IN _S
DM IN D C CH 0_ _
DM O E ER _ 0 _
IN UC OF 0_ ST T
DM IN T F_ 0 N T
DM O C L 0 _ T
G A_ T_ R_ ERR CH INT
G A_ T_ OV CH 0_I _S
G A_ _DS TA CH INT _S
_S ST
_I INT T
G A_ T_ R_ EO INT T
G A_ _DS CR PT CH T
NE F_ _ ST
H0 0_ _S
S
_ S
U _ _ H T
_ T
_ _
NT _
N
DM IN D EM F _
T
DM O C _ Y 0
_C CH INT
O O H0 T_
G A_ FIF UD F_C 0_I
_D _E _C IN
_ V H
_
G A_ FIF O_O F_C
H
_
DM IN IF D
DM O O F
G A_ TF O_U
O
U O
S
O
DM O IF
DM IN O
G A_ TF
U
U
U
)
DM _O
ed
v
A
er
DM
s
(re
G
G
31 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
GDMA_IN_DONE_CHn_INT_ST The raw interrupt status bit for the GDMA_IN_DONE_CH_INT inter-
rupt. (RO)
GDMA_IN_SUC_EOF_CHn_INT_ST The raw interrupt status bit for the
GDMA_IN_SUC_EOF_CH_INT interrupt. (RO)
GDMA_IN_ERR_EOF_CHn_INT_ST The raw interrupt status bit for the
A
GDMA_IN_ERR_EOF_CH_INT interrupt. (RO)
GDMA_OUT_DONE_CHn_INT_ST The raw interrupt status bit for the GDMA_OUT_DONE_CH_INT
interrupt. (RO)
IN
GDMA_OUT_EOF_CHn_INT_ST The raw interrupt status bit for the GDMA_OUT_EOF_CH_INT in-
terrupt. (RO)
IM
GDMA_IN_DSCR_ERR_CHn_INT_ST The raw interrupt status bit for the
GDMA_IN_DSCR_ERR_CH_INT interrupt. (RO)
GDMA_OUT_DSCR_ERR_CHn_INT_ST The raw interrupt status bit for the
GDMA_OUT_DSCR_ERR_CH_INT interrupt. (RO)
EL
GDMA_IN_DSCR_EMPTY_CHn_INT_ST The raw interrupt status bit for the
GDMA_IN_DSCR_EMPTY_CH_INT interrupt. (RO)
GDMA_OUT_TOTAL_EOF_CHn_INT_ST The raw interrupt status bit for the
GDMA_OUT_TOTAL_EOF_CH_INT interrupt. (RO)
PR
GDMA_INFIFO_OVF_CHn_INT_ST The raw interrupt status bit for the
GDMA_INFIFO_OVF_L1_CH_INT interrupt. (RO)
GDMA_INFIFO_UDF_CHn_INT_ST The raw interrupt status bit for the
GDMA_INFIFO_UDF_L1_CH_INT interrupt. (RO)
GDMA_OUTFIFO_OVF_CHn_INT_ST The raw interrupt status bit for the
GDMA_OUTFIFO_OVF_L1_CH_INT interrupt. (RO)
GDMA_OUTFIFO_UDF_CHn_INT_ST The raw interrupt status bit for the
GDMA_OUTFIFO_UDF_L1_CH_INT interrupt. (RO)
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Register 2.3. GDMA_INT_ENA_CHn_REG (n: 02) (0x0008+16*n)
G A_ _ER N 0_ 0_ INT NA
G A_ T_ F_ R_ CH INT NA
A_ _S _E CH T_ T_E NA
IN UC OF 0_ EN NA
E
_ E
_ T A
E A
DM IN R E_ IN IN _E
DM IN D C CH 0_ _
DM O E ER _ 0 _
NA A
DM IN T F_ 0 N N
DM O C L 0 _ N
_I INT NA
G A_ T_ R_ ERR CH INT
G A_ T_ R_ EO INT NA
G A_ _DS CR PT CH NA
_C CH INT A
_E EN
G A_ T_ OV CH 0_I _E
G A_ _DS TA CH INT _E
NE F_ _ EN
H0 0_ _E
_D _E _C IN A
U _ _ H T
_ E
_ _
NT _
N
DM IN D EM F _
DM O C _ Y 0
O O H0 T_
G A_ FIF UD F_C 0_I
_ V H
_
G A_ FIF O_O F_C
H
_
DM IN IF D
DM O O F
G A_ TF O_U
O
U O
S
O
DM O IF
DM IN O
G A_ TF
U
U
U
)
DM _O
ed
rv
A
DM
se
(re
G
G
31 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
GDMA_IN_DONE_CHn_INT_ENA The interrupt enable bit for the GDMA_IN_DONE_CH_INT inter-
rupt. (R/W)
GDMA_IN_SUC_EOF_CHn_INT_ENA The interrupt enable bit for the GDMA_IN_SUC_EOF_CH_INT
interrupt. (R/W)
GDMA_IN_ERR_EOF_CHn_INT_ENA The interrupt enable bit for the GDMA_IN_ERR_EOF_CH_INT
A
interrupt. (R/W)
GDMA_OUT_DONE_CHn_INT_ENA The interrupt enable bit for the GDMA_OUT_DONE_CH_INT in-
terrupt. (R/W)
IN
GDMA_OUT_EOF_CHn_INT_ENA The interrupt enable bit for the GDMA_OUT_EOF_CH_INT inter-
rupt. (R/W)
IM
GDMA_IN_DSCR_ERR_CHn_INT_ENA The interrupt enable bit for the
GDMA_IN_DSCR_ERR_CH_INT interrupt. (R/W)
GDMA_OUT_DSCR_ERR_CHn_INT_ENA The interrupt enable bit for the
GDMA_OUT_DSCR_ERR_CH_INT interrupt. (R/W)
EL
GDMA_IN_DSCR_EMPTY_CHn_INT_ENA The interrupt enable bit for the
GDMA_IN_DSCR_EMPTY_CH_INT interrupt. (R/W)
GDMA_OUT_TOTAL_EOF_CHn_INT_ENA The interrupt enable bit for the
GDMA_OUT_TOTAL_EOF_CH_INT interrupt. (R/W)
PR
GDMA_INFIFO_OVF_CHn_INT_ENA The interrupt enable bit for the
GDMA_INFIFO_OVF_L1_CH_INT interrupt. (R/W)
GDMA_INFIFO_UDF_CHn_INT_ENA The interrupt enable bit for the
GDMA_INFIFO_UDF_L1_CH_INT interrupt. (R/W)
GDMA_OUTFIFO_OVF_CHn_INT_ENA The interrupt enable bit for the
GDMA_OUTFIFO_OVF_L1_CH_INT interrupt. (R/W)
GDMA_OUTFIFO_UDF_CHn_INT_ENA The interrupt enable bit for the
GDMA_OUTFIFO_UDF_L1_CH_INT interrupt. (R/W)
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Register 2.4. GDMA_INT_CLR_CHn_REG (n: 02) (0x000C+16*n)
G A_ _ER N 0_ 0_ INT LR
G A_ T_ F_ R_ CH INT LR
A_ _S _E CH T_ T_C LR
C
_ C
IN UC OF 0_ CL LR
DM IN T F_ 0 N LR
D M O C L 0 _ LR
DM IN R E_ IN IN _C
DM IN D C CH 0_ _
DM O E ER _ 0 _
LR R
_I INT LR
G A_ T_ R_ ERR CH INT
G A_ T_ R_ EO INT LR
G A_ _DS CR PT CH LR
G A_ T_ OV CH 0_I _C
_C CH INT LR
G A_ _DS TA CH INT _C
_C CL
H0 0_ _C
_D _E _C IN R
C
_ C
_ H NT
NE F_ _ C
_ T
_ _
NT _
DM IN D EM F _
DM O C _ Y 0
O O H0 T_
G A_ FIF UD F_C 0_I
_ V H
_
G A_ FIF O_O F_C
H
_
DM IN IF D
DM O O F
G A_ TF O_U
O
U O
S
O
_
DM O IF
DM IN O
G A_ TF
U
U
U
d)
DM _O
ve
A
er
DM
s
(re
G
G
31 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
GDMA_IN_DONE_CHn_INT_CLR Set this bit to clear the GDMA_IN_DONE_CH_INT interrupt. (WT)
GDMA_IN_SUC_EOF_CHn_INT_CLR Set this bit to clear the GDMA_IN_SUC_EOF_CH_INT inter-
rupt. (WT)
GDMA_IN_ERR_EOF_CHn_INT_CLR Set this bit to clear the GDMA_IN_ERR_EOF_CH_INT inter-
rupt. (WT)
A
GDMA_OUT_DONE_CHn_INT_CLR Set this bit to clear the GDMA_OUT_DONE_CH_INT interrupt.
(WT)
IN
GDMA_OUT_EOF_CHn_INT_CLR Set this bit to clear the GDMA_OUT_EOF_CH_INT interrupt. (WT)
GDMA_IN_DSCR_ERR_CHn_INT_CLR Set this bit to clear the GDMA_IN_DSCR_ERR_CH_INT in-
IM
terrupt. (WT)
GDMA_OUT_DSCR_ERR_CHn_INT_CLR Set this bit to clear the GDMA_OUT_DSCR_ERR_CH_INT
interrupt. (WT)
GDMA_IN_DSCR_EMPTY_CHn_INT_CLR Set this bit to clear the
EL
GDMA_IN_DSCR_EMPTY_CH_INT interrupt. (WT)
GDMA_OUT_TOTAL_EOF_CHn_INT_CLR Set this bit to clear the
GDMA_OUT_TOTAL_EOF_CH_INT interrupt. (WT)
GDMA_INFIFO_OVF_CHn_INT_CLR Set this bit to clear the GDMA_INFIFO_OVF_L1_CH_INT inter-
PR
rupt. (WT)
GDMA_INFIFO_UDF_CHn_INT_CLR Set this bit to clear the GDMA_INFIFO_UDF_L1_CH_INT inter-
rupt. (WT)
GDMA_OUTFIFO_OVF_CHn_INT_CLR Set this bit to clear the GDMA_OUTFIFO_OVF_L1_CH_INT
interrupt. (WT)
GDMA_OUTFIFO_UDF_CHn_INT_CLR Set this bit to clear the GDMA_OUTFIFO_UDF_L1_CH_INT
interrupt. (WT)
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2 GDMA Controller (GDMA)
Register 2.5. GDMA_MISC_CONF_REG (0x0044)
ER
NT
IS
_I
ST
_D
_R
RI
se AR EN
DM d P
BM
G rve B_
(re A_ K_
AH
L
d)
)
DM _C
ve
A_
A
er
DM
s
(re
G
G
31 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GDMA_AHBM_RST_INTER Set this bit, then clear this bit to reset the internal ahb FSM. (R/W)
GDMA_ARB_PRI_DIS Set this bit to disable priority arbitration function. (R/W)
RY
GDMA_CLK_EN reg_clk_en (R/W)
Register 2.6. GDMA_DATE_REG (0x0048)
A
TE
DA
A_
DM
G
31
IN
0x2008250
0
Reset
GDMA_DATE register version. (R/W)
IM
EL
PR
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Register 2.7. GDMA_IN_CONF0_CHn_REG (n: 02) (0x0070+192*n)
_C ST EN H0
H0 H0
ST _TE T_ _C
H0 _C _C
IN O UR T_ 0
A_ _LO _B RS CH
_R P S EN
DM IN C U N_
G A_ DS _B _E
DM IN T NS
G A_ _DA RA
A
R
DM IN _T
A_ EM
)
DM _M
ed
rv
A
DM
se
(re
G
G
G
31 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GDMA_IN_RST_CHn This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. (R/W)
RY
GDMA_IN_LOOP_TEST_CHn This bit is used to fill the owner bit of inlink descriptor by hardware of
inlink descriptor. (R/W)
GDMA_INDSCR_BURST_EN_CHn Set this bit to 1 to enable INCR burst transfer for Rx channel 0
reading link descriptor when accessing internal SRAM. (R/W)
A
GDMA_IN_DATA_BURST_EN_CHn Set this bit to 1 to enable INCR burst transfer for Rx channel 0
receiving data when accessing internal SRAM. (R/W) IN
GDMA_MEM_TRANS_EN_CHn Set this bit 1 to enable automatic transmitting data from memory to
memory via DMA. (R/W)
IM
Register 2.8. GDMA_IN_CONF1_CHn_REG (n: 02) (0x0074+192*n)
0
CH
R_
NE
W
_O
CK
EL
HE
_C
IN
)
)
d
ed
ve
A_
rv
r
DM
se
se
(re
(re
G
31 13 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PR
GDMA_IN_CHECK_OWNER_CHn Set this bit to enable checking the owner attribute of the link de-
scriptor. (R/W)
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2 GDMA Controller (GDMA)
Register 2.9. GDMA_IN_POP_CHn_REG (n: 02) (0x007C+192*n)
H0
0
_C
CH
TA
P_
DA
O
_R
_P
FO
FO
FI
FI
IN
IN
)
ed
A_
A_
rv
DM
DM
se
(re
G
31 13 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800 Reset
GDMA_INFIFO_RDATA_CHn This register stores the data popping from DMA FIFO. (RO)
RY
GDMA_INFIFO_POP_CHn Set this bit to pop data from DMA FIFO. (R/W/SC)
Register 2.10. GDMA_IN_LINK_CHn_REG (n: 02) (0x0080+192*n)
H0
_A P_ H0 0
NK TO _C H
_C
A
LI S T C
0
O 0
A_ LIN ST AR 0
ET
IN K_ AR T_
CH
UT CH
DM IN K S H
_R
G A_ LIN RE _C
R_
_ K
T
DD
DM IN K R
G A_ LIN PA
_A
_
_
DM IN K
NK
G A_ LIN
LI
IN
DM IN
IN
d)
ve
G A_
A_
r
DM
DM
se
(re
31 25 24 23 22 21 20 19 0
0 0 0 0 0 0 0 1 0 0 0 1 0x000 Reset
IM
GDMA_INLINK_ADDR_CHn This register stores the 20 least significant bits of the first inlink descrip-
tor’s address. (R/W)
GDMA_INLINK_AUTO_RET_CHn Set this bit to return to current inlink descriptor’s address, when
there are some errors in current receiving data. (R/W)
EL
GDMA_INLINK_STOP_CHn Set this bit to stop dealing with the inlink descriptors. (R/W/SC)
GDMA_INLINK_START_CHn Set this bit to start dealing with the inlink descriptors. (R/W/SC)
GDMA_INLINK_RESTART_CHn Set this bit to mount a new inlink descriptor. (R/W/SC)
PR
GDMA_INLINK_PARK_CHn 1: the inlink descriptor’s FSM is in idle state; 0: the inlink descriptor’s
FSM is working. (RO)
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Register 2.11. GDMA_OUT_CONF0_CHn_REG (n: 02) (0x00D0+192*n)
O LO _ E_ N_ 0
_R P RB H0 H0
H0 0
A_ UT_ UTO OD _E _CH
H0 _C CH
UT O W C C
DM O A M S N
_C ST K_
G A_ T_ F_ UR _E
ST _TE AC
T
T
DM O E _B S
G A_ T_ CR UR
B
DM O S _
G A_ TD TA
O
U A
DM O D
G A_ T_
U
U
U
)
DM O
ed
G A_
rv
DM
se
(re
G
31 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset
GDMA_OUT_RST_CHn This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. (R/W)
RY
GDMA_OUT_LOOP_TEST_CHn Reserved. (R/W)
GDMA_OUT_AUTO_WRBACK_CHn Set this bit to enable automatic outlink-writeback when all the
data in tx buffer has been transmitted. (R/W)
GDMA_OUT_EOF_MODE_CHn EOF flag generation mode when transmitting data. 1: EOF flag for
A
Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA (R/W)
GDMA_OUTDSCR_BURST_EN_CHn Set this bit to 1 to enable INCR burst transfer for Tx channel
0 reading link descriptor when accessing internal SRAM. (R/W)
IN
GDMA_OUT_DATA_BURST_EN_CHn Set this bit to 1 to enable INCR burst transfer for Tx channel
0 transmitting data when accessing internal SRAM. (R/W)
IM
Register 2.12. GDMA_OUT_CONF1_CHn_REG (n: 02) (0x00D4+192*n)
0
CH
R_
EL
NE
W
_O
CK
HE
_C
UT
)
)
O
ed
ed
A_
rv
rv
DM
se
se
(re
(re
G
PR
31 13 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GDMA_OUT_CHECK_OWNER_CHn Set this bit to enable checking the owner attribute of the link
descriptor. (R/W)
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Register 2.13. GDMA_OUT_PUSH_CHn_REG (n: 02) (0x00DC+192*n)
0
CH
H0
_C
_
TA
SH
DA
U
_W
_P
FO
OF
FI
FI
UT
UT
)
O
ed
A_
A_
rv
DM
DM
se
(re
G
31 10 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
GDMA_OUTFIFO_WDATA_CHn This register stores the data that need to be pushed into DMA FIFO.
RY
(R/W)
GDMA_OUTFIFO_PUSH_CHn Set this bit to push data into DMA FIFO. (R/W/SC)
Register 2.14. GDMA_OUT_LINK_CHn_REG (n: 02) (0x00E0+192*n)
A
TO _C H0
_S RT _C
P_ H0
H0
0
LI _S TA 0
CH
UT K S H
NK TA RT
_C
O IN RE _C
DR
A_ TL K_ RK
IN
D
DM O IN A
G A_ TL K_P
_A
NK
DM O IN
LI
G A_ TL
UT
U
U
U
d)
DM _O
O
e
A_
rv
A
DM
DM
se
(re
G
G
31 24 23 22 21 20 19 0
IM
0 0 0 0 0 0 0 0 1 0 0 0 0x000 Reset
GDMA_OUTLINK_ADDR_CHn This register stores the 20 least significant bits of the first outlink de-
scriptor’s address. (R/W)
EL
GDMA_OUTLINK_STOP_CHn Set this bit to stop dealing with the outlink descriptors. (R/W/SC)
GDMA_OUTLINK_START_CHn Set this bit to start dealing with the outlink descriptors. (R/W/SC)
GDMA_OUTLINK_RESTART_CHn Set this bit to restart a new outlink from the last address.
(R/W/SC)
PR
GDMA_OUTLINK_PARK_CHn 1: the outlink descriptor’s FSM is in idle state; 0: the outlink descrip-
tor’s FSM is working. (RO)
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Register 2.15. GDMA_INFIFO_STATUS_CHn_REG (n: 02) (0x0078+192*n)
UN ER B_C 0
R_ _C 0
1B H0
H0
N_ D 3 H
DE _2B H
AI UN R_ _C
_C
EM IN_ DE 4B
IN EM _ DE 0
A_ _R AIN UN _CH
_R A UN R_
CH 0
L_ CH
0
DM IN M _ Y
0
CH
G A_ _RE AIN GR
UL _
_F PTY
_
DM IN M N
NT
G A_ _RE _HU
FI EM
_C
IN O_
DM IN F
FO
FO
G A_ _BU
A_ IF
FI
F
DM IN
IN
DM IN
d)
d)
ve
ve
G A_
A_
G A_
er
er
DM
DM
DM
s
s
(re
(re
G
G
31 28 27 26 25 24 23 22 8 7 2 1 0
0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Reset
RY
GDMA_INFIFO_FULL_CHn L1 Rx FIFO full signal for Rx channel 0. (RO)
GDMA_INFIFO_EMPTY_CHn L1 Rx FIFO empty signal for Rx channel 0. (RO)
GDMA_INFIFO_CNT_CHn The register stores the byte number of the data in L1 Rx FIFO for Rx
channel 0. (RO)
GDMA_IN_REMAIN_UNDER_1B_CHn Reserved. (RO)
A
GDMA_IN_REMAIN_UNDER_2B_CHn Reserved. (RO) IN
GDMA_IN_REMAIN_UNDER_3B_CHn Reserved. (RO)
GDMA_IN_REMAIN_UNDER_4B_CHn Reserved. (RO)
GDMA_IN_BUF_HUNGRY_CHn Reserved. (RO)
IM
Register 2.16. GDMA_IN_STATE_CHn_REG (n: 02) (0x0084+192*n) 0
H
_C
0
EL
DR
CH
AD
E_
AT
R_
H0
ST
SC
_C
R_
TE
_D
SC
TA
NK
_D
_S
LI
IN
IN
IN
)
ed
A_
A_
A_
rv
DM
DM
DM
se
(re
G
PR
31 23 22 20 19 18 17 0
0 0 0 0 0 0 0 0 0 0 0 0 Reset
GDMA_INLINK_DSCR_ADDR_CHn This register stores the current inlink descriptor’s address. (RO)
GDMA_IN_DSCR_STATE_CHn Reserved. (RO)
GDMA_IN_STATE_CHn Reserved. (RO)
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Register 2.17. GDMA_IN_SUC_EOF_DES_ADDR_CHn_REG (n: 02) (0x0088+192*n)
0
_CH
DR
AD
S_
DE
F_
O
_E
UC
_S
IN
A_
DM
G
31 0
0x000000 Reset
RY
GDMA_IN_SUC_EOF_DES_ADDR_CHn This register stores the address of the inlink descriptor
when the EOF bit in this descriptor is 1. (RO)
Register 2.18. GDMA_IN_ERR_EOF_DES_ADDR_CHn_REG (n: 02) (0x008C+192*n)
A DR
_C
H0
D
_A
IN ES
D
F_
EO
R_
R
_E
IN
A_
DM
G
IM
31 0
0x000000 Reset
GDMA_IN_ERR_EOF_DES_ADDR_CHn This register stores the address of the inlink descriptor
when there are some errors in current receiving data. Only used when peripheral is UHCI0. (RO)
EL
Register 2.19. GDMA_IN_DSCR_CHn_REG (n: 02) (0x0090+192*n)
0
CH
R_
PR
SC
_D
NK
LI
IN
A_
DM
G
31 0
0 Reset
GDMA_INLINK_DSCR_CHn The address of the current inlink descriptor x. (RO)
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Register 2.20. GDMA_IN_DSCR_BF0_CHn_REG (n: 02) (0x0094+192*n)
0
CH
F0_
_B
CR
_ DS
NK
LI
IN
A_
DM
G
31 0
0 Reset
GDMA_INLINK_DSCR_BF0_CHn The address of the last inlink descriptor x-1. (RO)
RY
Register 2.21. GDMA_IN_DSCR_BF1_CHn_REG (n: 02) (0x0098+192*n)
0
CH
1_
F
A
_B
CR
DS
K_
LIN
IN
A_
IN
DM
G
31 0
0 Reset
GDMA_INLINK_DSCR_BF1_CHn The address of the second-to-last inlink descriptor x-2. (RO)
IM
EL
PR
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Register 2.22. GDMA_OUTFIFO_STATUS_CHn_REG (n: 02) (0x00D8+192*n)
UN ER B_C 0
R_ _C 0
1B H0
H0
N_ D 3 H
DE _2B H
AI UN R_ _C
_C
EM IN_ DE 4B
_R A UN R_
CH 0
L_ CH
UT EM _ DE
0
0
CH
UL _
O R AIN N
_F PTY
A_ T_ EM _U
_
NT
N
FI _EM
DM O R I
_C
G A_ T_ MA
FO
UT O
FO
U E
O IF
DM O R
FI
A_ TF
A_ UT_
UT
U
U
)
d)
DM _O
DM O
ed
ve
A_
G A_
rv
er
DM
DM
DM
se
s
(re
(re
G
G
G
G
31 27 26 25 24 23 22 8 7 2 1 0
0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
RY
GDMA_OUTFIFO_FULL_CHn L1 Tx FIFO full signal for Tx channel 0. (RO)
GDMA_OUTFIFO_EMPTY_CHn L1 Tx FIFO empty signal for Tx channel 0. (RO)
GDMA_OUTFIFO_CNT_CHn The register stores the byte number of the data in L1 Tx FIFO for Tx
channel 0. (RO)
A
GDMA_OUT_REMAIN_UNDER_1B_CHn Reserved. (RO)
GDMA_OUT_REMAIN_UNDER_2B_CHn Reserved. (RO) IN
GDMA_OUT_REMAIN_UNDER_3B_CHn Reserved. (RO)
GDMA_OUT_REMAIN_UNDER_4B_CHn Reserved. (RO)
IM
Register 2.23. GDMA_OUT_STATE_CHn_REG (n: 02) (0x00E4+192*n)
H0
_C
H0
DR
_C
AD
E
AT
R_
H0
EL
ST
SC
_C
R_
TE
_D
SC
TA
NK
_D
_S
LI
UT
UT
UT
)
O
ed
A_
A_
A_
rv
DM
DM
DM
se
(re
31 23 22 20 19 18 17 0
PR
0 0 0 0 0 0 0 0 0 0 0 0 Reset
GDMA_OUTLINK_DSCR_ADDR_CHn This register stores the current outlink descriptor’s address.
(RO)
GDMA_OUT_DSCR_STATE_CHn Reserved. (RO)
GDMA_OUT_STATE_CHn Reserved. (RO)
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Register 2.24. GDMA_OUT_EOF_DES_ADDR_CHn_REG (n: 02) (0x00E8+192*n)
0
CH
R_
DD
_A
ES
D
F_
EO
_
UT
O
A_
DM
G
31 0
0x000000 Reset
GDMA_OUT_EOF_DES_ADDR_CHn This register stores the address of the outlink descriptor when
RY
the EOF bit in this descriptor is 1. (RO)
Register 2.25. GDMA_OUT_EOF_BFR_DES_ADDR_CHn_REG (n: 02) (0x00EC+192*n)
A DD
R_
CH
0
_A
ES
IN _D
FR
B
F_
O
_E
UT
O
A_
DM
G
IM
31 0
0x000000 Reset
GDMA_OUT_EOF_BFR_DES_ADDR_CHn This register stores the address of the outlink descriptor
before the last outlink descriptor. (RO)
EL
Register 2.26. GDMA_OUT_DSCR_CHn_REG (n: 02) (0x00F0+192*n)
H0
R_C
PR
SC
_D
NK
LI
UT
O
A_
DM
G
31 0
0 Reset
GDMA_OUTLINK_DSCR_CHn The address of the current outlink descriptor y. (RO)
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Register 2.27. GDMA_OUT_DSCR_BF0_CHn_REG (n: 02) (0x00F4+192*n)
H0
_C
F0
_B
CR
_ DS
NK
LI
UT
O
A_
DM
G
31 0
0 Reset
GDMA_OUTLINK_DSCR_BF0_CHn The address of the last outlink descriptor y-1. (RO)
RY
Register 2.28. GDMA_OUT_DSCR_BF1_CHn_REG (n: 02) (0x00F8+192*n)
H0
_C
F1
A
_B
CR
DS
K_
N
LI
UT
IN A_
O
DM
G
31 0
0 Reset
IM
GDMA_OUTLINK_DSCR_BF1_CHn The address of the second-to-last inlink descriptor x-2. (RO)
Register 2.29. GDMA_IN_PRI_CHn_REG (n: 02) (0x009C+192*n)
EL
0
CH
I_
PR
_
RX
)
ed
A_
rv
DM
se
(re
31 4 3 0
PR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GDMA_RX_PRI_CHn The priority of Rx channel 0. The larger of the value, the higher of the priority.
(R/W)
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Register 2.30. GDMA_OUT_PRI_CHn_REG (n: 02) (0x00FC+192*n)
0
CH
_
RI
_P
TX
)
ed
A_
v
er
DM
s
(re
G
31 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GDMA_TX_PRI_CHn The priority of Tx channel 0. The larger of the value, the higher of the priority.
(R/W)
RY
Register 2.31. GDMA_IN_PERI_SEL_CHn_REG (n: 02) (0x00A0+192*n)
0
CH
L_
SE
N_
_I
A
RI
PE
)
ed
A_
rv
DM
se
(re
G
31 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN
0 0 0 0 0 0 0 0 0 0 0 0x3f Reset
GDMA_PERI_IN_SEL_CHn This register is used to select peripheral for Rx channel 0. 0:SPI2. 1:
reserved. 2: UHCI0. 3: I2S. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC. (R/W)
IM
Register 2.32. GDMA_OUT_PERI_SEL_CHn_REG (n: 02) (0x0100+192*n)
H0
_C
EL
EL
_S
UT
O
I_
ER
)
P
ed
A_
rv
DM
se
(re
31 6 5 0
PR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3f Reset
GDMA_PERI_OUT_SEL_CHn This register is used to select peripheral for Tx channel 0. 0:SPI2. 1:
reserved. 2: UHCI0. 3: I2S. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC. (R/W)
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3 System and Memory
3.1 Overview
The ESP32-C3 is an ultra-low-power and highly-integrated system with a 32-bit RISC-V single-core processor
with a four-stage pipeline that operates at up to 160 MHz. All internal memory, external memory, and peripherals
are located on the CPU buses.
3.2 Features
• Address Space
RY
– 792 KB of internal memory address space accessed from the instruction bus
– 552 KB of internal memory address space accessed from the data bus
– 836 KB of peripheral address space
– 8 MB of external memory virtual address space accessed from the instruction bus
A
– 8 MB of external memory virtual address space accessed from the data bus
– 384 KB of internal DMA address space
• Internal Memory
IN
– 384 KB of Internal ROM
– 400 KB of Internal SRAM
IM
– 8 KB of RTC Memory
• External Memory
– Supports up to 16 MB external flash
• Peripheral Space
EL
– 35 modules/peripherals in total
• GDMA
– 7 GDMA-supported modules/peripherals
PR
Figure 3-1 illustrates the system structure and address mapping.
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A RY
IN
IM
Figure 31. System Structure and Address Mapping
EL
Note:
• The address space with gray background is not available to users.
PR
• The range of addresses available in the address space may be larger than the actual available memory of a particular
type.
3.3 Functional Description
3.3.1 Address Mapping
Addresses below 0x4000_0000 are accessed using the data bus. Addresses in the range of 0x4000_0000 ~
0x4FFF_FFFF are accessed using the instruction bus. Addresses over and including 0x5000_0000 are shared by
the data bus and the instruction bus.
Both data bus and instruction bus are little-endian. The CPU can access data via the data bus using single-byte,
double-byte, 4-byte alignment. The CPU can also access data via the instruction bus, but only in 4-byte aligned
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manner.
The CPU can:
• directly access the internal memory via both data bus and instruction bus;
• access the external memory which is mapped into the virtual address space via cache;
• directly access modules/peripherals via data bus.
Table 3-1 lists the address ranges on the data bus and instruction bus and their corresponding target
memory.
Some internal and external memory can be accessed via both data bus and instruction bus. In such cases, the
CPU can access the same memory using multiple addresses.
RY
Table 31. Address Mapping
Boundary Address
Bus Type Size Target
Low Address High Address
0x0000_0000 0x3BFF_FFFF Reserved
A
Data bus 0x3C00_0000 0x3C7F_FFFF 8 MB External memory
0x3C80_0000 0x3FC7_FFFF Reserved
Data bus 0x3FC8_0000 0x3FCD_FFFF 384 KB Internal memory
Data bus
0x3FCE_0000
0x3FF0_0000
IN 0x3FEF_FFFF
0x3FF1_FFFF 128 KB
Reserved
Internal memory
0x3FF2_0000 0x3FFF_FFFF Reserved
Instruction bus 0x4000_0000 0x4005_FFFF 384 KB Internal memory
IM
0x4006_0000 0x4037_BFFF Reserved
Instruction bus 0x4037_C000 0x403D_FFFF 400 KB Internal memory
0x403E_0000 0x41FF_FFFF Reserved
Instruction bus 0x4200_0000 0x427F_FFFF 8 MB External memory
0x4280_0000 0x4FFF_FFFF Reserved
EL
Data/Instruction bus 0x5000_0000 0x5000_1FFF 8 KB Internal memory
0x5000_2000 0x5FFF_FFFF Reserved
Data/Instruction bus 0x6000_0000 0x600D_0FFF 836 KB Peripherals
0x600D_1000 0xFFFF_FFFF Reserved
PR
3.3.2 Internal Memory
The ESP32-C3 consists of the following three types of internal memory:
• Internal ROM (384 KB): The Internal ROM of the ESP32-C3 is a Mask ROM, meaning it is strictly read-only
and cannot be reprogrammed. Internal ROM contains the ROM code (software instructions and some
software read-only data) of some low level system software.
• Internal SRAM (400 KB): The Internal Static RAM (SRAM) is a volatile memory that can be quickly accessed
by the CPU (generally within a single CPU clock cycle).
– A part of the SRAM can be configured to operate as a cache for external memory access.
– Some parts of the SRAM can only be accessed via the CPU’s instruction bus.
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– Some parts of the SRAM can be accessed via both the CPU’s instruction bus and the CPU’s data bus.
• RTC Memory (8 KB): The RTC (Real Time Clock) memory implemented as Static RAM (SRAM) thus is
volatile. However, RTC memory has the added feature of being persistent in deep sleep (i.e., the RTC
memory retains its values throughout deep sleep).
– RTC FAST Memory (8 KB): RTC FAST memory can only be accessed by the CPU and can be
generally used to store instructions and data that needs to persist across a deep sleep.
Based on the three different types of internal memory described above, the internal memory of the ESP32-C3 is
split into three segments: Internal ROM (384 KB), Internal SRAM (400 KB), RTC FAST Memory (8 KB).
However, within each segment, there may be different bus access restrictions (e.g., some parts of the segment
may only be accessible by the CPU’s Data bus). Therefore, each some segments are also further divided into
RY
parts. Table 3-2 describes each part of internal memory and their address ranges on the data bus and/or
instruction bus.
Table 32. Internal Memory Address Mapping
Boundary Address
Bus Type Size (KB) Target
A
Low Address High Address
0x3FF0_0000 0x3FF1_FFFF 128 Internal ROM 1
Data bus
0x3FC8_0000 0x3FCD_FFFF 384 Internal SRAM 1
0x4000_0000
0x4004_0000
IN 0x4003_FFFF
0x4005_FFFF
256
128
Internal ROM 0
Internal ROM 1
Instruction bus
0x4037_C000 0x4037_FFFF 16 Internal SRAM 0
0x4038_0000 0x403D_FFFF 384 Internal SRAM 1
IM
Data/Instruction bus 0x5000_0000 0x5000_1FFF 8 RTC FAST Memory
Note:
All of the internal memories are managed by Permission Control module. An internal memory can only be accessed
EL
when it is allowed by Permission Control, then the internal memory can be available to the CPU. For more information
about Permission Control, please refer to Chapter 2 Permission Control (PMS) [to be added later].
1. Internal ROM 0
Internal ROM 0 is a 256 KB, read-only memory space, addressed by the CPU only through the instruction bus via
PR
0x4000_0000 ~ 0x4003_FFFF, as shown in Table 3-2.
2. Internal ROM 1
Internal ROM 1 is a 128 KB, read-only memory space, addressed by the CPU through the instruction bus via
0x4004_0000 ~ 0x4005_FFFF or through the data bus via 0x3FF0_0000 ~ 0x3FF1_FFFF in the same order, as
shown in Table 3-2.
This means, for example, address 04004_0000 and 0x3FF0_0000 correspond to the same word, 0x4004_0004
and 0x3FF0_0004 correspond to the same word, 0x4004_0008 and 0x3FF0_0008 correspond to the same
word, etc (the same ordering applies for Internal SRAM 1).
3. Internal SRAM 0
Internal SRAM 0 is a 16 KB, read-and-write memory space, addressed by the CPU through the instruction bus
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via the range described in Table 3-2.
This memory managed by Permission Control, can be configured as instruction cache to store cache instructions
or read-only data of the external memory. In this case, the memory cannot be accessed by the CPU. For more
information about Permission Control, please refer to Chapter 2 Permission Control (PMS) [to be added
later].
4. Internal SRAM 1
Internal SRAM 1 is a 384 KB, read-and-write memory space, addressed by the CPU through the data bus or
instruction bus, in the same order, via the ranges described in Table 3-2.
5. RTC FAST Memory
RY
RTC FAST Memory is a 8 KB, read-and-write SRAM, addressed by the CPU through the data/instruction bus via
the shared address 0x5000_0000 ~ 0x5000_1FFF, as described in Table 3-2.
3.3.3 External Memory
ESP32-C3 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple external flash.
A
It supports hardware manual encryption and automatic decryption based on XTS_AES to protect user programs
and data in the external flash.
3.3.3.1 External Memory Address Mapping
IN
The CPU accesses the external memory via the cache. According to the MMU (Memory Management Unit)
settings, the cache maps the CPU’s address to the external memory’s physical address. Due to this address
mapping, the ESP32-C3 can address up to 16 MB external flash.
IM
Using the cache, ESP32-C3 is able to support the following address space mappings. Note that the instruction
bus address space (8MB) and the data bus address space (8 MB) is always shared.
• Up to 8 MB instruction bus address space can be mapped into the external flash. The mapped address
space is organized as individual 64-KB blocks.
EL
• Up to 8 MB data bus (read-only) address space can be mapped into the external flash. The mapped
address space is organized as individual 64-KB blocks.
Table 3-3 lists the mapping between the cache and the corresponding address ranges on the data bus and
instruction bus.
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Table 33. External Memory Address Mapping
Boundary Address
Bus Type Size (MB) Target
Low Address High Address
Data bus (read-only) 0x3C00_0000 0x3C7F_FFFF 8 MB Uniform Cache
Instruction bus 0x4200_0000 0x427F_FFFF 8 MB Uniform Cache
Note:
Only if the CPU obtains permission for accessing the external memory, can it be responded for memory access.
For more detailed information about permission control, please refer to Chapter 2 Permission Control (PMS) [to be
added later].
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3.3.3.2 Cache
As shown in Figure 3-2, ESP32-C3 has a read-only uniform cache which is eight-way set-associative, its size is
16 KB and its block size is 32 bytes. When cache is active, some internal memory space will be occupied by
cache (see Internal SRAM 0 in Section 3.3.2).
The uniform cache is accessible by the instruction bus and the data bus at the same time, but can only respond
to one of them at a time. When a cache miss occurs, the cache controller will initiate a request to the external
memory.
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IN
Figure 32. Cache Structure
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3.3.3.3 Cache Operations
ESP32-C3 cache support the following operations:
1. Invalidate: This operation is used to clear valid data in the cache. After this operation is completed, the
data will only be stored in the external memory. The CPU needs to access the external memory in order to
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read this data. There are two types of invalidate-operation: automatic invalidation (Auto-Invalidate) and
manual invalidation (Manual-Invalidate). Manual-Invalidate is performed only on data in the specified area in
the cache, while Auto-Invalidate is performed on all data in the cache.
2. Preload: This operation is used to load instructions and data into the cache in advance. The minimum unit
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of preload-operation is one block. There are two types of preload-operation: manual preload
(Manual-Preload) and automatic preload (Auto-Preload). Manual-Preload means that the hardware
prefetches a piece of continuous data according to the virtual address specified by the software.
Auto-Preload means the hardware prefetches a piece of continuous data according to the current address
where the cache hits or misses (depending on configuration).
3. Lock/Unlock: The lock operation is used to prevent the data in the cache from being easily replaced.
There are two types of lock: prelock and manual lock. When prelock is enabled, the cache locks the data
in the specified area when filling the missing data to cache memory, while the data outside the specified
area will not be locked. When manual lock is enabled, the cache checks the data that is already in the
cache memory and only locks the data in the specified area, and leaves the data outside the specified area
unlocked. When there are missing data, the cache will replace the data in the unlocked way first, so the
data in the locked way is always stored in the cache and will not be replaced. But when all ways within the
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cache are locked, the cache will replace data, as if it was not locked. Unlocking is the reverse of locking,
except that it only can be done manually.
Please note that the Manual-Invalidate operations will only work on the unlocked data. If you expect to
perform such operation on the locked data, please unlock them first.
3.3.4 GDMA Address Space
The GDMA (General Direct Memory Access) peripheral in ESP32-C3 can provide DMA (Direct Memory Access)
services including:
• Data transfers between different locations of internal memory;
• Data transfers between modules/peripherals and internal memory.
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GDMA uses the same addresses as the data bus to read and write Internal SRAM 1. Specifically, GDMA uses
address range 0x3FC8_0000 ~ 0x3FCD_FFFF to access Internal SRAM 1. Note that GDMA cannot access the
internal memory occupied by the cache.
There are 7 peripherals/modules that can work together with GDMA.
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As shown in Figure 3-3, these 7 vertical lines in turn correspond to these 7 peripherals/modules with GDMA
function, the horizontal line represents a certain channel of GDMA (can be any channel), and the intersection of
the vertical line and the horizontal line indicates that a peripheral/module has the ability to access the
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corresponding channel of GDMA. If there are multiple intersections on the same line, it means that these
peripherals/modules cannot enable the GDMA function at the same time.
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Figure 33. Peripherals/modules that can work with GDMA
These peripherals/modules can access any memory available to GDMA. For more information, please refer to
Chapter 2 GDMA Controller (GDMA).
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Note:
When accessing a memory via GDMA, a corresponding access permission is needed, otherwise this access may
fail. For more information about permission control, please refer to Chapter 2 Permission Control (PMS) [to be added
later].
3.3.5 Modules/Peripherals
The CPU can access modules/peripherals via 0x6000_0000 ~ 0x600D_0FFF shared by the data/instruction
bus.
3.3.5.1 Module/Peripheral Address Mapping
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Table 3-4 lists all the modules/peripherals and their respective address ranges. Note that the address space of
specific modules/peripherals is defined by ”Boundary Address” (including both Low Address and High
Address).
Table 34. Module/Peripheral Address Mapping
A
Boundary Address
Target Size (KB) Notes
Low Address High Address
UART Controller 0
Reserved
IN
0x6000_0000
0x6000_1000
0x6000_0FFF
0x6000_1FFF
4
SPI Controller 1 0x6000_2000 0x6000_2FFF 4
SPI Controller 0 0x6000_3000 0x6000_3FFF 4
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GPIO 0x6000_4000 0x6000_4FFF 4
Reserved 0x6000_5000 0x6000_6FFF
TIMER 0x6000_7000 0x6000_7FFF 4
Low-Power Management 0x6000_8000 0x6000_8FFF 4
IO MUX 0x6000_9000 0x6000_9FFF 4
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Reserved 0x6000_A000 0x6000_FFFF
UART Controller 1 0x6001_0000 0x6001_0FFF 4
Reserved 0x6001_1000 0x6001_2FFF
I2C Controller 0x6001_3000 0x6001_3FFF 4
UHCI0 0x6001_4000 0x6001_4FFF 4
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Reserved 0x6001_5000 0x6001_5FFF
Remote Control Peripheral 0x6001_6000 0x6001_6FFF 4
Reserved 0x6001_7000 0x6001_8FFF
LED PWM Controller 0x6001_9000 0x6001_9FFF 4
eFuse Controller 0x6001_A000 0x6001_AFFF 4
Reserved 0x6001_B000 0x6001_EFFF
Timer Group 0 0x6001_F000 0x6001_FFFF 4
Timer Group 1 0x6002_0000 0x6002_0FFF 4
Reserved 0x6002_1000 0x6002_2FFF
System Timer 0x6002_3000 0x6002_3FFF 4
SPI Controller 2 0x6002_4000 0x6002_4FFF 4
Cont’d on next page
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Table 34 – cont’d from previous page
Boundary Address
Target Size (KB) Notes
Low Address High Address
Reserved 0x6002_5000 0x6002_5FFF
APB Controller 0x6002_6000 0x6002_6FFF 4
Reserved 0x6002_7000 0x6002_AFFF
Two-wire Automotive Interface 0x6002_B000 0x6002_BFFF 4
Reserved 0x6002_C000 0x6002_CFFF
I2S Controller 0x6002_D000 0x6002_DFFF 4
Reserved 0x6002_E000 0x6003_9FFF
AES Accelerator 0x6003_A000 0x6003_AFFF 4
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SHA Accelerator 0x6003_B000 0x6003_BFFF 4
RSA Accelerator 0x6003_C000 0x6003_CFFF 4
Digital Signature 0x6003_D000 0x6003_DFFF 4
HMAC Accelerator 0x6003_E000 0x6003_EFFF 4
GDMA Controller 0x6003_F000 0x6003_FFFF 4
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ADC Controller 0x6004_0000 0x6004_0FFF 4
Reserved 0x6004_1000 0x6002_FFFF
USB Serial/JTAG Controller 0x6004_3000 0x6004_3FFF 4
Reserved
System Registers
IN
0x6004_4000
0x600C_0000
0x600B_FFFF
0x600C_0FFF 4
Sensitive Register 0x600C_1000 0x600C_1FFF 4
Interrupt Matrix 0x600C_2000 0x600C_2FFF 4
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Reserved 0x600C_3000 0x600C_3FFF
Configure Cache 0x600C_4000 0x600C_BFFF 32
External Memory Encryption and 0x600C_C000 0x600C_CFFF 4
Decryption
Reserved 0x600C_D000 0x600C_DFFF
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Assist Debug 0x600C_E000 0x600C_EFFF 4
Reserved 0x600C_F000 0x600C_FFFF
World Controller 0x600D_0000 0x600D_0FFF 4
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4 eFuse Controller (EFUSE)
4.1 Overview
ESP32-C3 contains a 4096-bit eFuse controller to store parameters. Once an eFuse bit is programmed to 1, it
can never be reverted to 0. The eFuse controller programs individual bits of parameters in eFuse according to
software configurations. Some of these parameters can be read by software using the eFuse controller, while
some can be directly used by hardware modules.
4.2 Features
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• 4096-bit One-time programmable storage
• Programmable write-protection
• Programmable read-protection against software
• Various hardware encoding schemes against data corruption
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4.3 Functional Description IN
4.3.1 Structure
eFuse data is organized in 11 blocks (BLOCK0 ~ BLOCK10).
BLOCK0, which holds most parameters, has 9 bits that can only be used by hardware and are invisible to
software, and 60 further bits are reserved for future use.
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Table 4-1 lists all the parameters in BLOCK0 and their offsets, bit widths, as well as information on whether they
can be used by hardware, which bits are write-protected, and corresponding descriptions.
The EFUSE_WR_DIS parameter is used to disable the writing of other parameters, while EFUSE_RD_DIS is
used to disable software from reading BLOCK4 ~ BLOCK10. For more information on these two parameters,
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please see Section 4.3.1.1 and Section 4.3.1.2.
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Table 41. Parameters in eFuse BLOCK0
Write-Protect
Bit Hardware
Parameters Bits in Description
PR
Width Use
EFUSE_WR_DIS
EFUSE_WR_DIS 32 Y N/A Disable writing of individual eFuses.
EFUSE_RD_DIS 7 Y 0 Disable software from reading eFuse blocks BLOCK4 ~ 10.
EFUSE_DIS_ICACHE 1 Y 2 Disable ICache.
EFUSE_DIS_USB_JTAG 1 Y 2 Disable usb-to-jtag function.
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EFUSE_DIS_DOWNLOAD_ICACHE 1 Y 2 Disable ICache in Download mode.
EFUSE_DIS_USB_SERIAL_JTAG 1 Y 2 Disable usb_serial_jtag peripheral.
EFUSE_DIS_FORCE_DOWNLOAD 1 Y 2 Disable chip from force-entering Download mode.
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EFUSE_DIS_TWAI 1 Y 2 Disable TWAI Controller.
EFUSE_JTAG_SEL_ENABLE 1 Y 2 Set 1 to use jtag directly.
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Disable JTAG by programming 1 to odd number of bits. JTAG can
EFUSE_SOFT_DIS_JTAG 3 Y 31
be re-enabled via HMAC peripheral.
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EFUSE_DIS_PAD_JTAG 1 Y 2 Hardware Disable JTAG permanently.
EFUSE_DIS_DOWNLOAD_ MANUAL_ENCRYPT 1 Y 2 Disable flash encryption in Download boot mode.
EFUSE_USB_EXCHG_PINS 1 Y 30 Exchange USB D+/D- pins.
IN
Set this parameter to 1 to override the function of the VDD SPI pin
EFUSE_VDD_SPI_AS_GPIO 1 N 30
and use it as a normal GPIO pin instead.
EFUSE_WDT_DELAY_SEL 2 Y 3 Select RTC WDT timeout threshold.
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Enable SPI boot encryption and decryption. This feature is enabled
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EFUSE_SPI_BOOT_CRYPT_CNT 3 Y 4 when odd number of bits are set in this parameter, disabled other-
wise.
EFUSE_SECURE_BOOT_KEY_ REVOKE0 1 N 5 Revoke the first secure boot key when enabled.
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EFUSE_SECURE_BOOT_KEY_ REVOKE1 1 N 6 Revoke the second secure boot key when enabled.
EFUSE_SECURE_BOOT_KEY_ REVOKE2 1 N 7 Revoke the third secure boot key when enabled.
EFUSE_KEY_PURPOSE_0 4 Y 8 Key0 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_1 4 Y 9 Key1 purpose, see Table 4-2.
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4 eFuse Controller (EFUSE)
Write-Protect
Bit Hardware
Parameters Bits in Description
Width Use
EFUSE_WR_DIS
PR
EFUSE_KEY_PURPOSE_2 4 Y 10 Key2 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_3 4 Y 11 Key3 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_4 4 Y 12 Key4 purpose, see Table 4-2.
EFUSE_KEY_PURPOSE_5 4 Y 13 Key5 purpose, see Table 4-2.
EFUSE_SECURE_BOOT_EN 1 N 15 Enable secure boot.
EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE 1 N 16 Enable aggressive Secure boot key revocation mode.
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Configure flash startup delay after SoC being powered up (the unit
EFUSE_FLASH_TPUW 4 N 18
is ms/2). When the value is 15, delay will be 7.5 ms.
EFUSE_DIS_DOWNLOAD_MODE 1 N 18 Disable all download boot modes.
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EFUSE_USB_PRINT_CHANNEL 1 N 18 Set this parameter to 1, the usb print function will be disabled.
Disable the USB OTG download feature in UART download boot
EFUSE_DIS_USB_DOWNLOAD_MODE 1 N 18
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mode.
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EFUSE_ENABLE_SECURITY_DOWNLOAD 1 N 18 Enable UART secure download mode (read/write flash only).
Set UART boot message output mode. 2’b00: Force print; 2’b01:
EFUSE_UART_PRINT_CONTROL 2 N 18 Low-level print, controlled by GPIO 8; 2’b10: High-level print, con-
trolled by GPIO 8; 2’b11: Print force disabled.
IN
Force ROM code to send an SPI flash resume command during SPI
EFUSE_FORCE_SEND_RESUME 1 N 18
boot.
EFUSE_SECURE_VERSION 16 N 18 Secure version (used by ESP-IDF anti-rollback feature).
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1: use BLOCK0 to check error record registers; 0: disable such
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EFUSE_ERR_RST_ENABLE 1 N 19
check.
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4 eFuse Controller (EFUSE)
Table 4-2 lists all key purpose and their values. Setting the eFuse parameter EFUSE_KEY_PURPOSE_n declares
the purpose of KEYn (n: 0 ~ 5).
Table 42. Secure Key Purpose Values
Key Purpose Values Purposes
0 For users (software-only)
1 Reserved
2 XTS_AES_256_KEY_1 (flash/SRAM encryption and decryption)
3 XTS_AES_256_KEY_2 (flash/SRAM encryption and decryption)
4 XTS_AES_128_KEY (flash/SRAM encryption and decryption)
5 HMAC Downstream mode (both JTAG and DS)
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6 JTAG in HMAC Downstream mode
7 Digital Signature peripheral in HMAC Downstream mode
8 HMAC Upstream mode
9 SECURE_BOOT_DIGEST0 (secure boot key digest)
10 SECURE_BOOT_DIGEST1 (secure boot key digest)
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11 SECURE_BOOT_DIGEST2 (secure boot key digest)
Table 4-3 provides the details of parameters in BLOCK1 ~ BLOCK10.
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Table 43. Parameters in BLOCK1 to BLOCK10
Software
Write-Protect
Hardware Read-Protect
BLOCK Parameters Bit Width Bits in Description
IM
Use Bits in
EFUSE_WR_DIS
EFUSE_RD_DIS
BLOCK1 EFUSE_MAC 48 N 20 N/A MAC address
EFUSE_SPI_PAD_ [0:5] N 20 N/A CLK
CONFIGURE [6:11] N 20 N/A Q (D1)
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[12:17] N 20 N/A D (D0)
[18:23] N 20 N/A CS
[24:29] N 20 N/A HD (D3)
[30:35] N 20 N/A WP (D2)
[36:41] N 20 N/A DQS
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[42:47] N 20 N/A D4
[48:53] N 20 N/A D5
[54:59] N 20 N/A D6
[60:65] N 20 N/A D7
EFUSE_SYS_DATA_PART0 78 N 20 N/A System data
BLOCK2 EFUSE_SYS_DATA_PART1 256 N 21 N/A System data
BLOCK3 EFUSE_USR_DATA 256 N 22 N/A User data
BLOCK4 EFUSE_KEY0_DATA 256 Y 23 0 KEY0 or user data
BLOCK5 EFUSE_KEY1_DATA 256 Y 24 1 KEY1 or user data
BLOCK6 EFUSE_KEY2_DATA 256 Y 25 2 KEY2 or user data
BLOCK7 EFUSE_KEY3_DATA 256 Y 26 3 KEY3 or user data
BLOCK8 EFUSE_KEY4_DATA 256 Y 27 4 KEY4 or user data
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Software
Write-Protect
Hardware Read-Protect
BLOCK Parameters Bit Width Bits in Description
Use Bits in
EFUSE_WR_DIS
EFUSE_RD_DIS
BLOCK9 EFUSE_KEY5_DATA 256 Y 28 5 KEY5 or user data
BLOCK10 EFUSE_SYS_DATA_PART2 256 N 29 6 System data
Among these blocks, BLOCK4 ~ 9 stores KEY0 ~ 5, respectively. Up to six 256-bit keys can be written into
eFuse. Whenever a key is written, its purpose value should also be written (see table 4-2). For example, when a
key for the JTAG function in HMAC Downstream mode is written to KEY3 (i.e., BLOCK7), its key purpose value 6
should also be written to EFUSE_KEY_PURPOSE_3.
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BLOCK1 ~ BLOCK10 use the RS coding scheme, so there are some restrictions on writing to these parameters.
For more detailed information, please refer to Section 4.3.1.3 and Section 4.3.2.
4.3.1.1 EFUSE_WR_DIS
Parameter EFUSE_WR_DIS determines whether individual eFuse parameters are write-protected. After
A
EFUSE_WR_DIS has been programmed, execute an eFuse read operation so the new values would take
effect.
Column “Write-Protect Bits in EFUSE_WR_DIS” in Table 4-1 and Table 4-3 list the specific bits in
EFUSE_WR_DIS that disable writing.
IN
When the write-protect bit of a parameter is set to 0, it means that this parameter is not write-protected and can
be programmed, unless it has been programmed before.
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When the write-protect bit of a parameter is set to 1, it means that this parameter is write-protected and none of
its bits can be modified, with non-programmed bits always remaining 0 while programmed bits always remain
1.
4.3.1.2 EFUSE_RD_DIS
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Only parameters in BLCOK4 ~ BLOCK10 may be read-protected against software reads, as shown in column
“Software Read-Protect Bits in EFUSE_RD_DIS” of Table 4-3. After EFUSE_RD_DIS has been programmed,
execute an eFuse read operation so the new values would take effect.
If a bit in EFUSE_RD_DIS is 0, it means that its parameters are not read-protected against software; if a bit in
PR
EFUSE_RD_DIS is 1, it means that its parameters are read-protected against software.
Other parameters that are not in BLOCK4 ~ BLOCK10 can always be read by software.
However, even if BLOCK4 ~ BLOCK10 are set to be read-protected, they can still be read by hardware modules,
if the EFUSE_KEY_PURPOSE_n bit is set accordingly.
4.3.1.3 Data Storage
Internally, eFuses use hardware encoding schemes to protect data from corruption, which are invisible for
users.
All BLOCK0 parameters except for EFUSE_WR_DIS are stored with four backups, meaning each bit is stored
four times. This backup scheme is not visible to software.
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BLOCK1 ~ BLOCK10 use RS (44, 32) coding scheme that supports up to 6 bytes of automatic error correction.
The primitive polynomial of RS (44, 32) is p(x) = x8 + x4 + x3 + x2 + 1.
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Figure 41. Shift Register Circuit (first 32 output)
IN
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Figure 42. Shift Register Circuit (last 12 output)
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The shift register circuit shown in Figure 4-1 and 4-2 processes 32 data bytes using RS (44, 32). This coding
scheme encodes 32 bytes of data into 44 bytes:
• Bytes [0:31] are the data bytes itself
• Bytes [32:43] are the encoded parity bytes stored in 8-bit flip-flops DFF1, DFF2, ..., DFF12 (gf_mul_n,
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where n is an integer, is the result of multiplying a byte of data ...)
After that, the hardware burns into eFuse the 44-byte codeword consisting of the data bytes followed by the
parity bytes.
When the eFuse block is read back, the eFuse controller automatically decodes the codeword and applies error
correction if needed.
Because the RS check codes are generated on the entire 256-bit eFuse block, each block can only be written
once.
4.3.2 Software Programming of Parameters
The eFuse controller can only program eFuse parameters in one block at a time. BLOCK0 ~ BLOCK10 share the
same address range to store the parameters to be programmed. Configure parameter EFUSE_BLK_NUM to
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4 eFuse Controller (EFUSE)
indicate which block should be programmed.
Programming BLOCK0
When EFUSE_BLK_NUM is set to 0, BLOCK0 will be programmed. Register EFUSE_PGM_DATA0_REG stores
EFUSE_WR_DIS. Registers EFUSE_PGM_DATA1_REG ~ EFUSE_PGM_DATA5_REG store the information of
parameters to be programmed. Note that 7 bits can only be used by hardware and must always be set to 0. The
specific bits are:
• EFUSE_PGM_DATA1_REG[24:21]
• EFUSE_PGM_DATA1_REG[31:27]
Data in registers EFUSE_PGM_DATA6_REG ~ EFUSE_PGM_DATA7_REG and
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EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG are ignored when programming
BLOCK0.
Programming BLOCK1
When EFUSE_BLK_NUM is set to 1, registers EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA5_REG store the
BLOCK1 parameters to be programmed. Registers EFUSE_PGM_CHECK_VALUE0_REG ~
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EFUSE_PGM_DATA2_REG store the corresponding RS check codes. Data in registers
EFUSE_PGM_DATA6_REG ~ EFUSE_PGM_DATA7_REG are ignored when programming BLOCK1, and the RS
check codes will be calculated with these bits all treated as 0.
Programming BLOCK2 ~ 10
IN
When EFUSE_BLK_NUM is set to 2 ~ 10, registers
EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA7_REG store the parameters to be programmed to this block.
IM
Registers EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG store the corresponding
RS check codes.
Programming process
The process of programming parameters is as follows:
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1. Configure the value of parameter EFUSE_BLK_NUM to determine the block to be programmed.
2. Write parameters to be programmed to registers EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA7_REG
and EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG.
3. Make sure the eFuse programming voltage VDDQ is configured correctly as described in Section 4.3.4.
PR
4. Configure the field EFUSE_OP_CODE of register EFUSE_CONF_REG to 0x5A5A.
5. Configure the field EFUSE_PGM_CMD of register EFUSE_CMD_REG to 1.
6. Poll register EFUSE_CMD_REG until software reads 0x0, or wait for a PGM_DONE interrupt. For more
information on how to identify a PGM/READ_DONE interrupt, please see the end of Section 4.3.3.
7. Clear the parameters in EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA7_REG and
EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG.
8. Trigger an eFuse read operation (see Section 4.3.3) to update eFuse registers with the new values.
9. Check error record registers. If the values read in error record registers are not 0, the programming process
should be performed again following above steps 1 ~ 7. Please check the following error record registers
for different eFuse blocks:
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• BLOCK0: EFUSE_RD_REPEAT_ERR0_REG ~ EFUSE_RD_REPEAT_ERR4_REG
• BLOCK1: EFUSE_RD_RS_ERR0_REG[2:0], EFUSE_RD_RS_ERR0_REG[7]
• BLOCK2: EFUSE_RD_RS_ERR0_REG[6:4], EFUSE_RD_RS_ERR0_REG[11]
• BLOCK3: EFUSE_RD_RS_ERR0_REG[10:8], EFUSE_RD_RS_ERR0_REG[15]
• BLOCK4: EFUSE_RD_RS_ERR0_REG[14:12], EFUSE_RD_RS_ERR0_REG[19]
• BLOCK5: EFUSE_RD_RS_ERR0_REG[18:16], EFUSE_RD_RS_ERR0_REG[23]
• BLOCK6: EFUSE_RD_RS_ERR0_REG[22:20], EFUSE_RD_RS_ERR0_REG[27]
• BLOCK7: EFUSE_RD_RS_ERR0_REG[26:24], EFUSE_RD_RS_ERR0_REG[31]
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• BLOCK8: EFUSE_RD_RS_ERR0_REG[30:28], EFUSE_RD_RS_ERR1_REG[3]
• BLOCK9: EFUSE_RD_RS_ERR1_REG[2:0], EFUSE_RD_RS_ERR1_REG[2:0][7]
• BLOCK10: EFUSE_RD_RS_ERR1_REG[2:0][6:4]
Limitations
A
In BLOCK0, each bit can be programmed separately. However, we recommend to minimize programming cycles
and program all the bits of a parameter in one programming action. In addition, after all parameters controlled by
a certain bit of EFUSE_WR_DIS are programmed, that bit should be immediately programmed. The
IN
programming of parameters controlled by a certain bit of EFUSE_WR_DIS, and the programming of the bit itself
can even be completed at the same time. Repeated programming of already programmed bits is strictly
forbidden, otherwise, programming errors will occur.
BLOCK1 cannot be programmed by users as it has been programmed at manufacturing.
IM
BLOCK2 ~ 10 can only be programmed once. Repeated programming is not allowed.
4.3.3 Software Reading of Parameters
Software cannot read eFuse bits directly. The eFuse Controller hardware reads all eFuse bits and stores the
EL
results to their corresponding registers in its memory space. Then, software can read eFuse bits by reading the
registers that start with EFUSE_RD_. Details are provided in Table 4-4.
Table 44. Registers Information
BLOCK Read Registers Registers When Programming This Block
PR
0 EFUSE_RD_WR_DIS_REG EFUSE_PGM_DATA0_REG
0 EFUSE_RD_REPEAT_DATA0 ~ 4_REG EFUSE_PGM_DATA1 ~ 5_REG
1 EFUSE_RD_MAC_SPI_SYS_0 ~ 5_REG EFUSE_PGM_DATA0 ~ 5_REG
2 EFUSE_RD_SYS_DATA_PART1_0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG
3 EFUSE_RD_USR_DATA0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG
4-9 EFUSE_RD_KEYn_DATA0 ~ 7_REG (n: 0 ~ 5) EFUSE_PGM_DATA0 ~ 7_REG
10 EFUSE_RD_SYS_DATA_PART2_0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG
Updating eFuse read registers
The eFuse Controller reads internal eFuses to update corresponding registers. This read operation happens on
system reset and can also be triggered manually by software as needed (e.g., if new eFuse values have been
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4 eFuse Controller (EFUSE)
programmed). The process of triggering a read operation by software is as follows:
1. Configure the field EFUSE_OP_CODE in register EFUSE_CONF_REG to 0x5AA5.
2. Configure the field EFUSE_READ_CMD in register EFUSE_CMD_REG to 1.
3. Poll register EFUSE_CMD_REG until software reads 0x0, or wait for a READ_DONE interrupt. Information
on how to identify a PGM/READ_DONE interrupt is provided below in this section.
4. Software reads the values of each parameter from memory.
The eFuse read registers will hold all values until the next read operation.
Error detection
RY
Error record registers allow software to detect if there are any inconsistencies in the stored backup eFuse
parameters.
Registers EFUSE_RD_REPEAT_ERR0 ~ 3_REG indicate if there are any errors of programmed parameters
(except for EFUSE_WR_DIS) in BLOCK0 (value 1 indicates an error is detected, and the bit becomes invalid;
value 0 indicates no error).
A
Registers EFUSE_RD_RS_ERR0 ~ 1_REG store the number of corrected bytes as well as the result of RS
decoding during eFuse reading BLOCK1 ~ BLOCK10.
The values of above registers will be updated every time after the eFuse read registers have been updated.
Identifying program/read operation
IN
The methods to identify the completion of a program/read operation are described below. Please note that bit 1
corresponds to a program operation, and bit 0 corresponds to a read operation.
IM
• Method one:
1. Poll bit 1/0 in register EFUSE_INT_RAW_REG until it becomes 1, which represents the completion of a
program/read operation.
• Method two:
EL
1. Set bit 1/0 in register EFUSE_INT_ENA_REG to 1 to enable the eFuse Controller to post a
PGM/READ_DONE interrupt.
2. Configure the Interrupt Matrix to enable the CPU to respond to eFuse interrupt signals, see Chapter 8
Interrupt Matrix (INTMTRX).
PR
3. Wait for the PGM/READ_DONE interrupt.
4. Set bit 1/0 in register EFUSE_INT_CLR_REG to 1 to clear the PGM/READ_DONE interrupt.
Note
When eFuse controller updating its registers, it will use EFUSE_PGM_DATAn_REG (n=0�1�..,7) again to store
data. So please do not write important data into these registers before this updating process initiated.
During the chip boot process, eFuse controller will update eFuse data into registers which can be accessed by
software automatically. You can get programmed eFuse data by reading corresponding registers. Thus, it is no
need to update eFuse read registers in such case.
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4.3.4 eFuse VDDQ Timing
The eFuse Controller operates with 20 MHz of clock frequency, and its programming voltage VDDQ should be
configured as follows:
• EFUSE_DAC_NUM (the rising period of VDDQ): The default value of VDDQ is 2.5 V and the voltage
increases by 0.01 V in each clock cycle. Thus, the default value of this parameter is 255;
• EFUSE_DAC_CLK_DIV (the clock divisor of VDDQ): The clock period to program VDDQ should be larger
than 1 µs;
• EFUSE_PWR_ON_NUM (the power-up time for VDDQ): The programming voltage should be stabilized after
this time, which means the value of this parameter should be configured to exceed the result of
RY
EFUSE_DAC_CLK_DIV times EFUSE_DAC_NUM;
• EFUSE_PWR_OFF_NUM (the power-out time for VDDQ): The value of this parameter should be larger than
10 µs.
Table 45. Configuration of Default VDDQ Timing Parameters
A
EFUSE_DAC_NUM EFUSE_DAC_CLK_DIV EFUSE_PWR_ON_NUM EFUSE_PWR_OFF_NUM
0xFF 0x28 0x3000 0x190
4.3.5 The Use of Parameters by Hardware Modules
IN
Some hardware modules are directly connected to the eFuse peripheral in order to use the parameters listed in
Table 4-1 and Table 4-3, specifically those marked with “Y” in columns “Hardware Use”. Software cannot
intervene in this process.
IM
4.3.6 Interrupts
• PGM_DONE interrupt: Triggered when eFuse programming has finished. To enable this interrupt, set the
EFUSE_PGM_DONE_INT_ENA field of register EFUSE_INT_ENA_REG to 1;
EL
• READ_DONE interrupt: Triggered when eFuse reading has finished. To enable this interrupt, set the
EFUSE_READ_DONE_INT_ENA field of register EFUSE_INT_ENA_REG to 1.
PR
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4.4 Register Summary
The addresses in this section are relative to eFuse Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
PGM Data Register
EFUSE_PGM_DATA0_REG Register 0 that stores data to be programmed 0x0000 R/W
EFUSE_PGM_DATA1_REG Register 1 that stores data to be programmed 0x0004 R/W
EFUSE_PGM_DATA2_REG Register 2 that stores data to be programmed 0x0008 R/W
EFUSE_PGM_DATA3_REG Register 3 that stores data to be programmed 0x000C R/W
EFUSE_PGM_DATA4_REG Register 4 that stores data to be programmed 0x0010 R/W
RY
EFUSE_PGM_DATA5_REG Register 5 that stores data to be programmed 0x0014 R/W
EFUSE_PGM_DATA6_REG Register 6 that stores data to be programmed 0x0018 R/W
EFUSE_PGM_DATA7_REG Register 7 that stores data to be programmed 0x001C R/W
EFUSE_PGM_CHECK_VALUE0_REG Register 0 that stores the RS code to be pro- 0x0020 R/W
grammed
A
EFUSE_PGM_CHECK_VALUE1_REG Register 1 that stores the RS code to be pro- 0x0024 R/W
grammed
EFUSE_PGM_CHECK_VALUE2_REG Register 2 that stores the RS code to be pro- 0x0028 R/W
Read Data Register
grammed
IN
EFUSE_RD_WR_DIS_REG BLOCK0 data register 0 0x002C RO
EFUSE_RD_REPEAT_DATA0_REG BLOCK0 data register 1 0x0030 RO
IM
EFUSE_RD_REPEAT_DATA1_REG BLOCK0 data register 2 0x0034 RO
EFUSE_RD_REPEAT_DATA2_REG BLOCK0 data register 3 0x0038 RO
EFUSE_RD_REPEAT_DATA3_REG BLOCK0 data register 4 0x003C RO
EFUSE_RD_REPEAT_DATA4_REG BLOCK0 data register 5 0x0040 RO
EFUSE_RD_MAC_SPI_SYS_0_REG BLOCK1 data register 0 0x0044 RO
EL
EFUSE_RD_MAC_SPI_SYS_1_REG BLOCK1 data register 1 0x0048 RO
EFUSE_RD_MAC_SPI_SYS_2_REG BLOCK1 data register 2 0x004C RO
EFUSE_RD_MAC_SPI_SYS_3_REG BLOCK1 data register 3 0x0050 RO
EFUSE_RD_MAC_SPI_SYS_4_REG BLOCK1 data register 4 0x0054 RO
EFUSE_RD_MAC_SPI_SYS_5_REG BLOCK1 data register 5 0x0058 RO
PR
EFUSE_RD_SYS_PART1_DATA0_REG Register 0 of BLOCK2 (system) 0x005C RO
EFUSE_RD_SYS_PART1_DATA1_REG Register 1 of BLOCK2 (system) 0x0060 RO
EFUSE_RD_SYS_PART1_DATA2_REG Register 2 of BLOCK2 (system) 0x0064 RO
EFUSE_RD_SYS_PART1_DATA3_REG Register 3 of BLOCK2 (system) 0x0068 RO
EFUSE_RD_SYS_PART1_DATA4_REG Register 4 of BLOCK2 (system) 0x006C RO
EFUSE_RD_SYS_PART1_DATA5_REG Register 5 of BLOCK2 (system) 0x0070 RO
EFUSE_RD_SYS_PART1_DATA6_REG Register 6 of BLOCK2 (system) 0x0074 RO
EFUSE_RD_SYS_PART1_DATA7_REG Register 7 of BLOCK2 (system) 0x0078 RO
EFUSE_RD_USR_DATA0_REG Register 0 of BLOCK3 (user) 0x007C RO
EFUSE_RD_USR_DATA1_REG Register 1 of BLOCK3 (user) 0x0080 RO
EFUSE_RD_USR_DATA2_REG Register 2 of BLOCK3 (user) 0x0084 RO
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Name Description Address Access
EFUSE_RD_USR_DATA3_REG Register 3 of BLOCK3 (user) 0x0088 RO
EFUSE_RD_USR_DATA4_REG Register 4 of BLOCK3 (user) 0x008C RO
EFUSE_RD_USR_DATA5_REG Register 5 of BLOCK3 (user) 0x0090 RO
EFUSE_RD_USR_DATA6_REG Register 6 of BLOCK3 (user) 0x0094 RO
EFUSE_RD_USR_DATA7_REG Register 7 of BLOCK3 (user) 0x0098 RO
EFUSE_RD_KEY0_DATA0_REG Register 0 of BLOCK4 (KEY0) 0x009C RO
EFUSE_RD_KEY0_DATA1_REG Register 1 of BLOCK4 (KEY0) 0x00A0 RO
EFUSE_RD_KEY0_DATA2_REG Register 2 of BLOCK4 (KEY0) 0x00A4 RO
EFUSE_RD_KEY0_DATA3_REG Register 3 of BLOCK4 (KEY0) 0x00A8 RO
EFUSE_RD_KEY0_DATA4_REG Register 4 of BLOCK4 (KEY0) 0x00AC RO
RY
EFUSE_RD_KEY0_DATA5_REG Register 5 of BLOCK4 (KEY0) 0x00B0 RO
EFUSE_RD_KEY0_DATA6_REG Register 6 of BLOCK4 (KEY0) 0x00B4 RO
EFUSE_RD_KEY0_DATA7_REG Register 7 of BLOCK4 (KEY0) 0x00B8 RO
EFUSE_RD_KEY1_DATA0_REG Register 0 of BLOCK5 (KEY1) 0x00BC RO
EFUSE_RD_KEY1_DATA1_REG Register 1 of BLOCK5 (KEY1) 0x00C0 RO
A
EFUSE_RD_KEY1_DATA2_REG Register 2 of BLOCK5 (KEY1) 0x00C4 RO
EFUSE_RD_KEY1_DATA3_REG Register 3 of BLOCK5 (KEY1) 0x00C8 RO
EFUSE_RD_KEY1_DATA4_REG Register 4 of BLOCK5 (KEY1) 0x00CC RO
EFUSE_RD_KEY1_DATA5_REG
EFUSE_RD_KEY1_DATA6_REG
IN
Register 5 of BLOCK5 (KEY1)
Register 6 of BLOCK5 (KEY1)
0x00D0
0x00D4
RO
RO
EFUSE_RD_KEY1_DATA7_REG Register 7 of BLOCK5 (KEY1) 0x00D8 RO
EFUSE_RD_KEY2_DATA0_REG Register 0 of BLOCK6 (KEY2) 0x00DC RO
IM
EFUSE_RD_KEY2_DATA1_REG Register 1 of BLOCK6 (KEY2) 0x00E0 RO
EFUSE_RD_KEY2_DATA2_REG Register 2 of BLOCK6 (KEY2) 0x00E4 RO
EFUSE_RD_KEY2_DATA3_REG Register 3 of BLOCK6 (KEY2) 0x00E8 RO
EFUSE_RD_KEY2_DATA4_REG Register 4 of BLOCK6 (KEY2) 0x00EC RO
EFUSE_RD_KEY2_DATA5_REG Register 5 of BLOCK6 (KEY2) 0x00F0 RO
EL
EFUSE_RD_KEY2_DATA6_REG Register 6 of BLOCK6 (KEY2) 0x00F4 RO
EFUSE_RD_KEY2_DATA7_REG Register 7 of BLOCK6 (KEY2) 0x00F8 RO
EFUSE_RD_KEY3_DATA0_REG Register 0 of BLOCK7 (KEY3) 0x00FC RO
EFUSE_RD_KEY3_DATA1_REG Register 1 of BLOCK7 (KEY3) 0x0100 RO
EFUSE_RD_KEY3_DATA2_REG Register 2 of BLOCK7 (KEY3) 0x0104 RO
PR
EFUSE_RD_KEY3_DATA3_REG Register 3 of BLOCK7 (KEY3) 0x0108 RO
EFUSE_RD_KEY3_DATA4_REG Register 4 of BLOCK7 (KEY3) 0x010C RO
EFUSE_RD_KEY3_DATA5_REG Register 5 of BLOCK7 (KEY3) 0x0110 RO
EFUSE_RD_KEY3_DATA6_REG Register 6 of BLOCK7 (KEY3) 0x0114 RO
EFUSE_RD_KEY3_DATA7_REG Register 7 of BLOCK7 (KEY3) 0x0118 RO
EFUSE_RD_KEY4_DATA0_REG Register 0 of BLOCK8 (KEY4) 0x011C RO
EFUSE_RD_KEY4_DATA1_REG Register 1 of BLOCK8 (KEY4) 0x0120 RO
EFUSE_RD_KEY4_DATA2_REG Register 2 of BLOCK8 (KEY4) 0x0124 RO
EFUSE_RD_KEY4_DATA3_REG Register 3 of BLOCK8 (KEY4) 0x0128 RO
EFUSE_RD_KEY4_DATA4_REG Register 4 of BLOCK8 (KEY4) 0x012C RO
EFUSE_RD_KEY4_DATA5_REG Register 5 of BLOCK8 (KEY4) 0x0130 RO
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Name Description Address Access
EFUSE_RD_KEY4_DATA6_REG Register 6 of BLOCK8 (KEY4) 0x0134 RO
EFUSE_RD_KEY4_DATA7_REG Register 7 of BLOCK8 (KEY4) 0x0138 RO
EFUSE_RD_KEY5_DATA0_REG Register 0 of BLOCK9 (KEY5) 0x013C RO
EFUSE_RD_KEY5_DATA1_REG Register 1 of BLOCK9 (KEY5) 0x0140 RO
EFUSE_RD_KEY5_DATA2_REG Register 2 of BLOCK9 (KEY5) 0x0144 RO
EFUSE_RD_KEY5_DATA3_REG Register 3 of BLOCK9 (KEY5) 0x0148 RO
EFUSE_RD_KEY5_DATA4_REG Register 4 of BLOCK9 (KEY5) 0x014C RO
EFUSE_RD_KEY5_DATA5_REG Register 5 of BLOCK9 (KEY5) 0x0150 RO
EFUSE_RD_KEY5_DATA6_REG Register 6 of BLOCK9 (KEY5) 0x0154 RO
EFUSE_RD_KEY5_DATA7_REG Register 7 of BLOCK9 (KEY5) 0x0158 RO
RY
EFUSE_RD_SYS_PART2_DATA0_REG Register 0 of BLOCK10 (system) 0x015C RO
EFUSE_RD_SYS_PART2_DATA1_REG Register 1 of BLOCK10 (system) 0x0160 RO
EFUSE_RD_SYS_PART2_DATA2_REG Register 2 of BLOCK10 (system) 0x0164 RO
EFUSE_RD_SYS_PART2_DATA3_REG Register 3 of BLOCK10 (system) 0x0168 RO
EFUSE_RD_SYS_PART2_DATA4_REG Register 4 of BLOCK10 (system) 0x016C RO
A
EFUSE_RD_SYS_PART2_DATA5_REG Register 5 of BLOCK10 (system) 0x0170 RO
EFUSE_RD_SYS_PART2_DATA6_REG Register 6 of BLOCK10 (system) 0x0174 RO
EFUSE_RD_SYS_PART2_DATA7_REG Register 7 of BLOCK10 (system) 0x0178 RO
Report Register
EFUSE_RD_REPEAT_ERR0_REG
IN
Programming error record register 0 of BLOCK0 0x017C RO
EFUSE_RD_REPEAT_ERR1_REG Programming error record register 1 of BLOCK0 0x0180 RO
EFUSE_RD_REPEAT_ERR2_REG Programming error record register 2 of BLOCK0 0x0184 RO
IM
EFUSE_RD_REPEAT_ERR3_REG Programming error record register 3 of BLOCK0 0x0188 RO
EFUSE_RD_REPEAT_ERR4_REG Programming error record register 4 of BLOCK0 0x0190 RO
EFUSE_RD_RS_ERR0_REG Programming error record register 0 of BLOCK1- 0x01C0 RO
10
EFUSE_RD_RS_ERR1_REG Programming error record register 1 of BLOCK1- 0x01C4 RO
EL
10
Configuration Register
EFUSE_CLK_REG eFuse clock configuration register 0x01C8 R/W
EFUSE_CONF_REG eFuse operation mode configuration register 0x01CC R/W
EFUSE_CMD_REG eFuse command register 0x01D4 varies
PR
EFUSE_DAC_CONF_REG Controls the eFuse programming voltage 0x01E8 R/W
EFUSE_RD_TIM_CONF_REG Configures read timing parameters 0x01EC R/W
EFUSE_WR_TIM_CONF1_REG Configuration register 1 of eFuse programming 0x01F0 R/W
timing parameters
EFUSE_WR_TIM_CONF2_REG Configuration register 2 of eFuse programming 0x01F4 R/W
timing parameters
Status Register
EFUSE_STATUS_REG eFuse status register 0x01D0 RO
Interrupt Register
EFUSE_INT_RAW_REG eFuse raw interrupt register 0x01D8 R/WC/SS
EFUSE_INT_ST_REG eFuse interrupt status register 0x01DC RO
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Name Description Address Access
EFUSE_INT_ENA_REG eFuse interrupt enable register 0x01E0 R/W
EFUSE_INT_CLR_REG eFuse interrupt clear register 0x01E4 WO
Version Register
EFUSE_DATE_REG Version control register 0x01FC R/W
A RY
IN
IM
EL
PR
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4.5 Registers
The addresses in this section are relative to eFuse Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 4.1. EFUSE_PGM_DATA0_REG (0x0000)
0
A_
AT
_D
M
PG
E_
US
EF
31 0
RY
0x000000 Reset
EFUSE_PGM_DATA_0 The content of the 0th 32-bit data to be programmed. (R/W)
Register 4.2. EFUSE_PGM_DATA1_REG (0x0004)
A
1
A_
AT
_D
IN E_
PG
M
US
EF
31 0
0x000000 Reset
IM
EFUSE_PGM_DATA_1 The content of the 1st 32-bit data to be programmed. (R/W)
Register 4.3. EFUSE_PGM_DATA2_REG (0x0008)
EL
2
A_
AT
_D
M
PG
E_
US
EF
PR
31 0
0x000000 Reset
EFUSE_PGM_DATA_2 The content of the 2nd 32-bit data to be programmed. (R/W)
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Register 4.4. EFUSE_PGM_DATA3_REG (0x000C)
3
A_
AT
_D
M
PG
E_
US
EF
31 0
0x000000 Reset
EFUSE_PGM_DATA_3 The content of the 3rd 32-bit data to be programmed. (R/W)
RY
Register 4.5. EFUSE_PGM_DATA4_REG (0x0010)
4
A_
AT
_D
M
PG
E_
US
A
EF
31 0
0x000000
IN Reset
EFUSE_PGM_DATA_4 The content of the 4th 32-bit data to be programmed. (R/W)
Register 4.6. EFUSE_PGM_DATA5_REG (0x0014)
IM
5
A_
AT
_D
M
PG
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_PGM_DATA_5 The content of the 5th 32-bit data to be programmed. (R/W)
PR
Register 4.7. EFUSE_PGM_DATA6_REG (0x0018)
6
A_
AT
_D
M
PG
E_
US
EF
31 0
0x000000 Reset
EFUSE_PGM_DATA_6 The content of the 6th 32-bit data to be programmed. (R/W)
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Register 4.8. EFUSE_PGM_DATA7_REG (0x001C)
7
A_
AT
_D
M
PG
E_
US
EF
31 0
0x000000 Reset
EFUSE_PGM_DATA_7 The content of the 7th 32-bit data to be programmed. (R/W)
RY
Register 4.9. EFUSE_PGM_CHECK_VALUE0_REG (0x0020)
_0
TA
DA
S_
_R
M
PG
E_
A
US
EF
31 0
0x000000 Reset
IN
EFUSE_PGM_RS_DATA_0 The content of the 0th 32-bit RS code to be programmed. (R/W)
IM
Register 4.10. EFUSE_PGM_CHECK_VALUE1_REG (0x0024)
_1
TA
DA
S_
_R
M
G
EL
_P
SE
U
EF
31 0
0x000000 Reset
EFUSE_PGM_RS_DATA_1 The content of the 1st 32-bit RS code to be programmed. (R/W)
PR
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Register 4.11. EFUSE_PGM_CHECK_VALUE2_REG (0x0028)
2
A_
AT
_D
S
_R
M
PG
E_
US
EF
31 0
0x000000 Reset
EFUSE_PGM_RS_DATA_2 The content of the 2nd 32-bit RS code to be programmed. (R/W)
RY
Register 4.12. EFUSE_RD_WR_DIS_REG (0x002C)
S
DI
R_
W
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_WR_DIS Disable programming of individual eFuses. (RO)
IM
EL
PR
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Register 4.13. EFUSE_RD_REPEAT_DATA0_REG (0x0030)
T
YP
CR
EN
L_
HE
UA
E_ S_I B_ OA JTA D
US DI US L L_ OA
DI CA JTA D_ G
AC
AN
T
EF SE_ IS_ WN RIA NL
O
S_ C G IC
AG _M
E
G PIO
O
EF SE_ IS_ B_ DO 6
S
BL
U D DO SE W
U D US E_ D
IN
_B
JT D
AG
EF E_ _ C E
EF E_ T4 AI NA
D_ OA
CH _G
_P
M
US DI O ER
JT
RA
US RP W E
EX S
PA NL
RT HE
_
B_ I_A
EF SE_ IS_ ES
EF E_ S_ EL
IS
C_
S_ W
R
US SP
_D
U D _R
US DI _S
DI O
IS
E_ S_D
_D
E_ D_
FT
EF E_ AG
S
SO
RD
US VD
US JT
US DI
d)
)
ed
EF SE_
EF E_
E_
EF E_
E_
ve
rv
US
US
US
US
er
se
U
s
EF
EF
EF
EF
EF
(re
(re
31 27 26 25 24 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0 0 0 0x0 Reset
RY
EFUSE_RD_DIS Set this bit to disable reading from BlOCK4-10. (RO)
EFUSE_DIS_RTC_RAM_BOOT Reserved (used for four backups method). (RO)
EFUSE_DIS_ICACHE Set this bit to disable Icache. (RO)
A
EFUSE_DIS_USB_JTAG Set this bit to disable function of usb switch to jtag in module of
usb_serial_jtag. (RO) IN
EFUSE_DIS_DOWNLOAD_ICACHE Set this bit to disable Icache in download mode
(boot_mode[3:0] is 0, 1, 2, 4, 5, 6, 7). (RO)
EFUSE_DIS_USB_SERIAL_JTAG Set this bit to disable usb_serial_jtag module. (RO)
EFUSE_DIS_FORCE_DOWNLOAD Set this bit to disable the function that forces chip into download
IM
mode. (RO)
EFUSE_RPT4_RESERVED6 Reserved (used for four backups method). (RO)
EFUSE_DIS_TWAI Set this bit to disable twai function. (RO)
EL
EFUSE_JTAG_SEL_ENABLE Set this bit to use JTAG directly. (RO)
EFUSE_SOFT_DIS_JTAG Set these bits to disable JTAG in the soft way (odd number 1 means disable
). JTAG can be enabled in HMAC module. (RO)
EFUSE_DIS_PAD_JTAG Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
PR
(RO)
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT Set this bit to disable flash encryption when in
download boot mode (except in SPI boot mode ). (RO)
EFUSE_USB_EXCHG_PINS Set this bit to exchange USB D+ and D- pins. (RO)
EFUSE_VDD_SPI_AS_GPIO Set this bit to vdd spi pin function as gpio. (RO)
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Register 4.14. EFUSE_RD_REPEAT_DATA1_REG (0x0034)
Y_ VO E2
VO E1
0
KE
KE RE K
RE K
T_ _ O
O EY V
O _K RE
T
CN
_B OT EY_
T_
2
RE BO _K
_1
_0
ED
EL
YP
CU E_ OT
SE
SE
_S
RV
CR
SE R O
O
AY
SE
T_
E_ CU _B
P
RP
EL
UR
E
O
E
PU
_R
O
_D
US SE R
_P
B
EF SE_ ECU
T4
Y_
DT
I_
EY
RP
SP
KE
W
K
U S
E_
E_
EF E_
E_
E_
E_
US
US
US
US
US
US
EF
EF
EF
EF
EF
EF
31 28 27 24 23 22 21 20 18 17 16 15 0
0x0 0x0 0 0 0 0x0 0x0 0x00 Reset
RY
EFUSE_RPT4_RESERVED2 Reserved (used for four backups method). (RO)
EFUSE_WDT_DELAY_SEL Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 00:
40000. 01: 80000. 10: 160000. 11: 320000. (RO)
EFUSE_SPI_BOOT_CRYPT_CNT Set this bit to enable SPI boot encrypt/decrypt. Odd number of
1: enable. even number of 1: disable. (RO)
A
EFUSE_SECURE_BOOT_KEY_REVOKE0 Set this bit to enable revoking first secure boot key. (RO)
IN
EFUSE_SECURE_BOOT_KEY_REVOKE1 Set this bit to enable revoking second secure boot key.
(RO)
EFUSE_SECURE_BOOT_KEY_REVOKE2 Set this bit to enable revoking third secure boot key. (RO)
IM
EFUSE_KEY_PURPOSE_0 Purpose of Key0. (RO)
EFUSE_KEY_PURPOSE_1 Purpose of Key1. (RO)
EL
PR
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Register 4.15. EFUSE_RD_REPEAT_DATA2_REG (0x0038)
KE
VO
RE
E_
IV
SS
EN RE
T_ G
O G
D0
D3
O _A
_5
_4
_3
_2
VE
VE
_B OT
SE
SE
SE
SE
W
ER
ER
RE BO
O
PU
RP
RP
RP
RP
ES
ES
CU E_
_T
PU
PU
PU
PU
R
_R
SE R
SH
4_
E_ CU
T4
Y_
Y_
Y_
Y_
PT
A
RP
KE
KE
KE
KE
US SE
FL
R
E_
E_
EF E_
E_
E_
E_
E_
E_
US
US
US
US
US
US
US
US
EF
EF
EF
EF
EF
EF
EF
EF
31 28 27 22 21 20 19 16 15 12 11 8 7 4 3 0
RY
0x0 0x0 0 0 0x0 0x0 0x0 0x0 0x0 Reset
EFUSE_KEY_PURPOSE_2 Purpose of Key2. (RO)
EFUSE_KEY_PURPOSE_3 Purpose of Key3. (RO)
EFUSE_KEY_PURPOSE_4 Purpose of Key4. (RO)
A
EFUSE_KEY_PURPOSE_5 Purpose of Key5. (RO)
EFUSE_RPT4_RESERVED3 Reserved (used for four backups method). (RO)
EFUSE_SECURE_BOOT_EN Set this bit to enable secure boot. (RO)
IN
EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE Set this bit to enable revoking aggressive secure
boot. (RO)
IM
EFUSE_RPT4_RESERVED0 Reserved (used for four backups method). (RO)
EFUSE_FLASH_TPUW Configures flash waiting time after power-up, in unit of ms. If the value is
less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the
configurable value. (RO)
EL
PR
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4 eFuse Controller (EFUSE)
Register 4.16. EFUSE_RD_REPEAT_DATA3_REG (0x003C)
O D
M OA
DE
DI _R T_ D7 D_ L
E_ T4 IN VE OA WN
DE
L
E
US RP PR ER L O
RO
NL ED EL
UM
O
EF E_ B_ ES WN Y_
W V N
NT
_M
ES
N
ER LE
N
D1
O 8
US US _R DO IT
ED
O
DO SE A
O
AD
_R
EF E_ T4 _ UR
ES AB
VE
S_ E CH
SI
_C
RV
ND
ER
US RP S EC
_R EN
R
EF SE_ AB INT
SE
_V
SE
EF SE_ IS_ E_S
T4 T_
U EN PR
E
B
RE
E_
RP RS
_R
U D L
_
U
RC
CU
RT
E_ R_
T4
UA
RP
O
US ER
SE
_F
EF SE_
E_
E_
EF E_
E
E
US
US
US
US
US
U
EF
EF
EF
EF
EF
EF
31 30 29 14 13 12 8 7 6 5 4 3 2 1 0
0 0 0x00 0 0 0x0 0 0 0 0 0 0 Reset
RY
EFUSE_DIS_DOWNLOAD_MODE Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2,
4, 5, 6, 7). (RO)
EFUSE_RPT4_RESERVED8 Reserved (used for four backups method). (RO)
EFUSE_USB_PRINT_CHANNEL Set this bit to disable usb printing. (RO)
A
EFUSE_RPT4_RESERVED7 Reserved (used for four backups method). (RO)
EFUSE_DIS_USB_DOWNLOAD_MODE Set this bit to disable download through USB. (RO)
IN
EFUSE_ENABLE_SECURITY_DOWNLOAD Set this bit to enable security download mode. (RO)
EFUSE_UART_PRINT_CONTROL Set the type of UART print control. 00: Forces to print. 01: Con-
trolled by GPIO8, print at low level. 10: Controlled by GPIO8, print at high level. 11: Forces to
IM
disable print. (RO)
EFUSE_RPT4_RESERVED5 Reserved (used for four backups method). (RO)
EFUSE_FORCE_SEND_RESUME Set this bit to force ROM code to send a resume command during
SPI boot. (RO)
EL
EFUSE_SECURE_VERSION Secure version used by ESP-IDF anti-rollback feature. (RO)
EFUSE_RPT4_RESERVED1 Reserved (used for four backups method). (RO)
EFUSE_ERR_RST_ENABLE The bit be set means enable the check for error registers of block0.
(RO)
PR
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4 eFuse Controller (EFUSE)
Register 4.17. EFUSE_RD_REPEAT_DATA4_REG (0x0040)
D4
VE
ER
ES
_R
T4
RP
)
ed
E_
rv
US
se
EF
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000 Reset
EFUSE_RPT4_RESERVED4 Reserved (used for four backups method). (RO)
RY
Register 4.18. EFUSE_RD_MAC_SPI_SYS_0_REG (0x0044)
_0
AC
M
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_MAC_0 Stores the low 32 bits of MAC address. (RO)
Register 4.19. EFUSE_RD_MAC_SPI_SYS_1_REG (0x0048)
IM O
NF
_0
_C
D
_1
PA
AC
I_
SP
M
E_
E_
EL US
US
EF
EF
31 16 15 0
0x00 0x00 Reset
EFUSE_MAC_1 Stores the high 16 bits of MAC address. (RO)
PR
EFUSE_SPI_PAD_CONF_0 Stores the zeroth part of SPI_PAD_CONF. (RO)
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4 eFuse Controller (EFUSE)
Register 4.20. EFUSE_RD_MAC_SPI_SYS_2_REG (0x004C)
_1
NF
O
_C
AD
_P
PI
E _S
US
EF
31 0
0x000000 Reset
EFUSE_SPI_PAD_CONF_1 Stores the first part of SPI_PAD_CONF. (RO)
RY
Register 4.21. EFUSE_RD_MAC_SPI_SYS_3_REG (0x0050)
_0
T0
_2
R
NF
PA
O
A_
_C
AT
D
PA
_D
A I_
YS
SP
S
E_
E_
US
US
EF
EF
31 18 17 0
0x00
IN 0x000 Reset
EFUSE_SPI_PAD_CONF_2 Stores the second part of SPI_PAD_CONF. (RO)
EFUSE_SYS_DATA_PART0_0 Stores the fist 14 bits of the zeroth part of system data. (RO)
IM
Register 4.22. EFUSE_RD_MAC_SPI_SYS_4_REG (0x0054)
EL
_1
R T0
PA
A_
AT
_D
YS
_S
SE
U
EF
PR
31 0
0x000000 Reset
EFUSE_SYS_DATA_PART0_1 Stores the fist 32 bits of the zeroth part of system data. (RO)
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4 eFuse Controller (EFUSE)
Register 4.23. EFUSE_RD_MAC_SPI_SYS_5_REG (0x0058)
_2
T0
AR
_P
TA
DA
S_
SY
E_
US
EF
31 0
0x000000 Reset
EFUSE_SYS_DATA_PART0_2 Stores the second 32 bits of the zeroth part of system data. (RO)
RY
Register 4.24. EFUSE_RD_SYS_PART1_DATA0_REG (0x005C)
_0
RT1
PA
A_
AT
A
D
S_
SY
E_
US
EF
31
IN
0x000000
0
Reset
EFUSE_SYS_DATA_PART1_0 Stores the zeroth 32 bits of the first part of system data. (RO)
IM
Register 4.25. EFUSE_RD_SYS_PART1_DATA1_REG (0x0060)
_1
RT1
EL
PA
_
TA
DA
S_
SY
E_
US
EF
31 0
PR
0x000000 Reset
EFUSE_SYS_DATA_PART1_1 Stores the first 32 bits of the first part of system data. (RO)
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4 eFuse Controller (EFUSE)
Register 4.26. EFUSE_RD_SYS_PART1_DATA2_REG (0x0064)
_2
T1
AR
_P
TA
DA
S_
SY
E_
US
EF
31 0
0x000000 Reset
EFUSE_SYS_DATA_PART1_2 Stores the second 32 bits of the first part of system data. (RO)
RY
Register 4.27. EFUSE_RD_SYS_PART1_DATA3_REG (0x0068)
_3
RT1
PA
A_
AT
A
D
S_
SY
E_
US
EF
31
IN
0x000000
0
Reset
EFUSE_SYS_DATA_PART1_3 Stores the third 32 bits of the first part of system data. (RO)
IM
Register 4.28. EFUSE_RD_SYS_PART1_DATA4_REG (0x006C)
_4
RT1
EL
PA
_
TA
DA
S_
SY
E_
US
EF
31 0
PR
0x000000 Reset
EFUSE_SYS_DATA_PART1_4 Stores the fourth 32 bits of the first part of system data. (RO)
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4 eFuse Controller (EFUSE)
Register 4.29. EFUSE_RD_SYS_PART1_DATA5_REG (0x0070)
_5
T1
AR
_P
TA
DA
S_
SY
E_
US
EF
31 0
0x000000 Reset
EFUSE_SYS_DATA_PART1_5 Stores the fifth 32 bits of the first part of system data. (RO)
RY
Register 4.30. EFUSE_RD_SYS_PART1_DATA6_REG (0x0074)
_6
RT1
PA
A_
AT
A
D
S_
SY
E_
US
EF
31
IN
0x000000
0
Reset
EFUSE_SYS_DATA_PART1_6 Stores the sixth 32 bits of the first part of system data. (RO)
IM
Register 4.31. EFUSE_RD_SYS_PART1_DATA7_REG (0x0078)
_7
RT1
EL
PA
_
TA
DA
S_
SY
E_
US
EF
31 0
PR
0x000000 Reset
EFUSE_SYS_DATA_PART1_7 Stores the seventh 32 bits of the first part of system data. (RO)
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4 eFuse Controller (EFUSE)
Register 4.32. EFUSE_RD_USR_DATA0_REG (0x007C)
0
TA
DA
R_
US
E_
US
EF
31 0
0x000000 Reset
EFUSE_USR_DATA0 Stores the zeroth 32 bits of BLOCK3 (user). (RO)
RY
Register 4.33. EFUSE_RD_USR_DATA1_REG (0x0080)
1
TA
DA
R_
US
E_
US
EF
A
31 0
0x000000 Reset
IN
EFUSE_USR_DATA1 Stores the first 32 bits of BLOCK3 (user). (RO)
Register 4.34. EFUSE_RD_USR_DATA2_REG (0x0084)
IM
2
TA
DA
R_
US
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_USR_DATA2 Stores the second 32 bits of BLOCK3 (user). (RO)
PR
Register 4.35. EFUSE_RD_USR_DATA3_REG (0x0088)
3
TA
DA
R_
US
E_
US
EF
31 0
0x000000 Reset
EFUSE_USR_DATA3 Stores the third 32 bits of BLOCK3 (user). (RO)
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4 eFuse Controller (EFUSE)
Register 4.36. EFUSE_RD_USR_DATA4_REG (0x008C)
4
TA
DA
R_
US
E_
US
EF
31 0
0x000000 Reset
EFUSE_USR_DATA4 Stores the fourth 32 bits of BLOCK3 (user). (RO)
RY
Register 4.37. EFUSE_RD_USR_DATA5_REG (0x0090)
5
TA
DA
R_
US
E_
US
EF
A
31 0
0x000000 Reset
IN
EFUSE_USR_DATA5 Stores the fifth 32 bits of BLOCK3 (user). (RO)
Register 4.38. EFUSE_RD_USR_DATA6_REG (0x0094)
IM
6
TA
DA
R_
US
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_USR_DATA6 Stores the sixth 32 bits of BLOCK3 (user). (RO)
PR
Register 4.39. EFUSE_RD_USR_DATA7_REG (0x0098)
7
TA
DA
R_
US
E_
US
EF
31 0
0x000000 Reset
EFUSE_USR_DATA7 Stores the seventh 32 bits of BLOCK3 (user). (RO)
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4 eFuse Controller (EFUSE)
Register 4.40. EFUSE_RD_KEY0_DATA0_REG (0x009C)
A0
AT
_D
Y0
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY0_DATA0 Stores the zeroth 32 bits of KEY0. (RO)
RY
Register 4.41. EFUSE_RD_KEY0_DATA1_REG (0x00A0)
A1
AT
_D
Y0
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY0_DATA1 Stores the first 32 bits of KEY0. (RO)
Register 4.42. EFUSE_RD_KEY0_DATA2_REG (0x00A4)
IM
A2
AT
_D
Y0
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY0_DATA2 Stores the second 32 bits of KEY0. (RO)
PR
Register 4.43. EFUSE_RD_KEY0_DATA3_REG (0x00A8)
A3
AT
_D
Y0
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY0_DATA3 Stores the third 32 bits of KEY0. (RO)
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4 eFuse Controller (EFUSE)
Register 4.44. EFUSE_RD_KEY0_DATA4_REG (0x00AC)
A4
AT
_D
Y0
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY0_DATA4 Stores the fourth 32 bits of KEY0. (RO)
RY
Register 4.45. EFUSE_RD_KEY0_DATA5_REG (0x00B0)
A5
AT
_D
Y0
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY0_DATA5 Stores the fifth 32 bits of KEY0. (RO)
Register 4.46. EFUSE_RD_KEY0_DATA6_REG (0x00B4)
IM
A6
AT
_D
Y0
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY0_DATA6 Stores the sixth 32 bits of KEY0. (RO)
PR
Register 4.47. EFUSE_RD_KEY0_DATA7_REG (0x00B8)
A7
AT
_D
Y0
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY0_DATA7 Stores the seventh 32 bits of KEY0. (RO)
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4 eFuse Controller (EFUSE)
Register 4.48. EFUSE_RD_KEY1_DATA0_REG (0x00BC)
A0
AT
_D
Y1
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY1_DATA0 Stores the zeroth 32 bits of KEY1. (RO)
RY
Register 4.49. EFUSE_RD_KEY1_DATA1_REG (0x00C0)
A1
AT
_D
Y1
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY1_DATA1 Stores the first 32 bits of KEY1. (RO)
Register 4.50. EFUSE_RD_KEY1_DATA2_REG (0x00C4)
IM
A2
AT
_D
Y1
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY1_DATA2 Stores the second 32 bits of KEY1. (RO)
PR
Register 4.51. EFUSE_RD_KEY1_DATA3_REG (0x00C8)
A3
AT
_D
Y1
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY1_DATA3 Stores the third 32 bits of KEY1. (RO)
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4 eFuse Controller (EFUSE)
Register 4.52. EFUSE_RD_KEY1_DATA4_REG (0x00CC)
A4
AT
_D
Y1
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY1_DATA4 Stores the fourth 32 bits of KEY1. (RO)
RY
Register 4.53. EFUSE_RD_KEY1_DATA5_REG (0x00D0)
A5
AT
_D
Y1
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY1_DATA5 Stores the fifth 32 bits of KEY1. (RO)
Register 4.54. EFUSE_RD_KEY1_DATA6_REG (0x00D4)
IM
A6
AT
_D
Y1
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY1_DATA6 Stores the sixth 32 bits of KEY1. (RO)
PR
Register 4.55. EFUSE_RD_KEY1_DATA7_REG (0x00D8)
A7
AT
_D
Y1
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY1_DATA7 Stores the seventh 32 bits of KEY1. (RO)
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4 eFuse Controller (EFUSE)
Register 4.56. EFUSE_RD_KEY2_DATA0_REG (0x00DC)
A0
AT
_D
Y2
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY2_DATA0 Stores the zeroth 32 bits of KEY2. (RO)
RY
Register 4.57. EFUSE_RD_KEY2_DATA1_REG (0x00E0)
A1
AT
_D
Y2
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY2_DATA1 Stores the first 32 bits of KEY2. (RO)
Register 4.58. EFUSE_RD_KEY2_DATA2_REG (0x00E4)
IM
A2
AT
_D
Y2
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY2_DATA2 Stores the second 32 bits of KEY2. (RO)
PR
Register 4.59. EFUSE_RD_KEY2_DATA3_REG (0x00E8)
A3
AT
_D
Y2
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY2_DATA3 Stores the third 32 bits of KEY2. (RO)
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4 eFuse Controller (EFUSE)
Register 4.60. EFUSE_RD_KEY2_DATA4_REG (0x00EC)
A4
AT
_D
Y2
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY2_DATA4 Stores the fourth 32 bits of KEY2. (RO)
RY
Register 4.61. EFUSE_RD_KEY2_DATA5_REG (0x00F0)
A5
AT
_D
Y2
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY2_DATA5 Stores the fifth 32 bits of KEY2. (RO)
Register 4.62. EFUSE_RD_KEY2_DATA6_REG (0x00F4)
IM
A6
AT
_D
Y2
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY2_DATA6 Stores the sixth 32 bits of KEY2. (RO)
PR
Register 4.63. EFUSE_RD_KEY2_DATA7_REG (0x00F8)
A7
AT
_D
Y2
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY2_DATA7 Stores the seventh 32 bits of KEY2. (RO)
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4 eFuse Controller (EFUSE)
Register 4.64. EFUSE_RD_KEY3_DATA0_REG (0x00FC)
A0
AT
_D
Y3
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY3_DATA0 Stores the zeroth 32 bits of KEY3. (RO)
RY
Register 4.65. EFUSE_RD_KEY3_DATA1_REG (0x0100)
A1
AT
_D
Y3
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY3_DATA1 Stores the first 32 bits of KEY3. (RO)
Register 4.66. EFUSE_RD_KEY3_DATA2_REG (0x0104)
IM
A2
AT
_D
Y3
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY3_DATA2 Stores the second 32 bits of KEY3. (RO)
PR
Register 4.67. EFUSE_RD_KEY3_DATA3_REG (0x0108)
A3
AT
_D
Y3
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY3_DATA3 Stores the third 32 bits of KEY3. (RO)
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4 eFuse Controller (EFUSE)
Register 4.68. EFUSE_RD_KEY3_DATA4_REG (0x010C)
A4
AT
_D
Y3
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY3_DATA4 Stores the fourth 32 bits of KEY3. (RO)
RY
Register 4.69. EFUSE_RD_KEY3_DATA5_REG (0x0110)
A5
AT
_D
Y3
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY3_DATA5 Stores the fifth 32 bits of KEY3. (RO)
Register 4.70. EFUSE_RD_KEY3_DATA6_REG (0x0114)
IM
A6
AT
_D
Y3
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY3_DATA6 Stores the sixth 32 bits of KEY3. (RO)
PR
Register 4.71. EFUSE_RD_KEY3_DATA7_REG (0x0118)
A7
AT
_D
Y3
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY3_DATA7 Stores the seventh 32 bits of KEY3. (RO)
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4 eFuse Controller (EFUSE)
Register 4.72. EFUSE_RD_KEY4_DATA0_REG (0x011C)
A0
AT
_D
Y4
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY4_DATA0 Stores the zeroth 32 bits of KEY4. (RO)
RY
Register 4.73. EFUSE_RD_KEY4_DATA1_REG (0x0120)
A1
AT
_D
Y4
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY4_DATA1 Stores the first 32 bits of KEY4. (RO)
Register 4.74. EFUSE_RD_KEY4_DATA2_REG (0x0124)
IM
A2
AT
_D
Y4
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY4_DATA2 Stores the second 32 bits of KEY4. (RO)
PR
Register 4.75. EFUSE_RD_KEY4_DATA3_REG (0x0128)
A3
AT
_D
Y4
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY4_DATA3 Stores the third 32 bits of KEY4. (RO)
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4 eFuse Controller (EFUSE)
Register 4.76. EFUSE_RD_KEY4_DATA4_REG (0x012C)
A4
AT
_D
Y4
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY4_DATA4 Stores the fourth 32 bits of KEY4. (RO)
RY
Register 4.77. EFUSE_RD_KEY4_DATA5_REG (0x0130)
A5
AT
_D
Y4
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY4_DATA5 Stores the fifth 32 bits of KEY4. (RO)
Register 4.78. EFUSE_RD_KEY4_DATA6_REG (0x0134)
IM
A6
AT
_D
Y4
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY4_DATA6 Stores the sixth 32 bits of KEY4. (RO)
PR
Register 4.79. EFUSE_RD_KEY4_DATA7_REG (0x0138)
A7
AT
_D
Y4
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY4_DATA7 Stores the seventh 32 bits of KEY4. (RO)
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4 eFuse Controller (EFUSE)
Register 4.80. EFUSE_RD_KEY5_DATA0_REG (0x013C)
A0
AT
_D
Y5
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY5_DATA0 Stores the zeroth 32 bits of KEY5. (RO)
RY
Register 4.81. EFUSE_RD_KEY5_DATA1_REG (0x0140)
A1
AT
_D
Y5
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY5_DATA1 Stores the first 32 bits of KEY5. (RO)
Register 4.82. EFUSE_RD_KEY5_DATA2_REG (0x0144)
IM
A2
AT
_D
Y5
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY5_DATA2 Stores the second 32 bits of KEY5. (RO)
PR
Register 4.83. EFUSE_RD_KEY5_DATA3_REG (0x0148)
A3
AT
_D
Y5
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY5_DATA3 Stores the third 32 bits of KEY5. (RO)
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Register 4.84. EFUSE_RD_KEY5_DATA4_REG (0x014C)
A4
AT
_D
Y5
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY5_DATA4 Stores the fourth 32 bits of KEY5. (RO)
RY
Register 4.85. EFUSE_RD_KEY5_DATA5_REG (0x0150)
A5
AT
_D
Y5
KE
E_
US
EF
A
31 0
0x000000
IN Reset
EFUSE_KEY5_DATA5 Stores the fifth 32 bits of KEY5. (RO)
Register 4.86. EFUSE_RD_KEY5_DATA6_REG (0x0154)
IM
A6
AT
_D
Y5
KE
E_
US
EF
EL
31 0
0x000000 Reset
EFUSE_KEY5_DATA6 Stores the sixth 32 bits of KEY5. (RO)
PR
Register 4.87. EFUSE_RD_KEY5_DATA7_REG (0x0158)
A7
AT
_D
Y5
KE
E_
US
EF
31 0
0x000000 Reset
EFUSE_KEY5_DATA7 Stores the seventh 32 bits of KEY5. (RO)
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4 eFuse Controller (EFUSE)
Register 4.88. EFUSE_RD_SYS_PART2_DATA0_REG (0x015C)
_0
T2
AR
_P
TA
DA
S_
SY
E_
US
EF
31 0
0x000000 Reset
EFUSE_SYS_DATA_PART2_0 Stores the 0th 32 bits of the 2nd part of system data. (RO)
RY
Register 4.89. EFUSE_RD_SYS_PART2_DATA1_REG (0x0160)
_1
RT2
PA
A_
AT
A
D
S_
SY
E_
US
EF
31
IN
0x000000
0
Reset
EFUSE_SYS_DATA_PART2_1 Stores the 1st 32 bits of the 2nd part of system data. (RO)
IM
Register 4.90. EFUSE_RD_SYS_PART2_DATA2_REG (0x0164)
_2
RT2
EL
PA
_
TA
DA
S_
SY
E_
US
EF
31 0
PR
0x000000 Reset
EFUSE_SYS_DATA_PART2_2 Stores the 2nd 32 bits of the 2nd part of system data. (RO)
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Register 4.91. EFUSE_RD_SYS_PART2_DATA3_REG (0x0168)
_3
T2
AR
_P
TA
DA
S_
SY
E_
US
EF
31 0
0x000000 Reset
EFUSE_SYS_DATA_PART2_3 Stores the 3rd 32 bits of the 2nd part of system data. (RO)
RY
Register 4.92. EFUSE_RD_SYS_PART2_DATA4_REG (0x016C)
_4
RT2
PA
A_
AT
A
D
S_
SY
E_
US
EF
31
IN
0x000000
0
Reset
EFUSE_SYS_DATA_PART2_4 Stores the 4th 32 bits of the 2nd part of system data. (RO)
IM
Register 4.93. EFUSE_RD_SYS_PART2_DATA5_REG (0x0170)
_5
RT2
EL
PA
_
TA
DA
S_
SY
E_
US
EF
31 0
PR
0x000000 Reset
EFUSE_SYS_DATA_PART2_5 Stores the 5th 32 bits of the 2nd part of system data. (RO)
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Register 4.94. EFUSE_RD_SYS_PART2_DATA6_REG (0x0174)
_6
T2
AR
_P
TA
DA
S_
SY
E_
US
EF
31 0
0x000000 Reset
EFUSE_SYS_DATA_PART2_6 Stores the 6th 32 bits of the 2nd part of system data. (RO)
RY
Register 4.95. EFUSE_RD_SYS_PART2_DATA7_REG (0x0178)
_7
T2
R
PA
A_
AT
A
D
S_
SY
E_
US
EF
31
IN
0x000000
0
Reset
EFUSE_SYS_DATA_PART2_7 Stores the 7th 32 bits of the 2nd part of system data. (RO)
IM
EL
PR
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4 eFuse Controller (EFUSE)
Register 4.96. EFUSE_RD_REPEAT_ERR0_REG (0x017C)
RR
_E
PT
RY
NC
RR
S_ C G IC _E R
_E
DI CA JTA D_ G ER
RT HE _E AC RR
_E
R
AL
E_ S_I B_ OA JTA D_
C_ _E RR HE
ER
R
RR U
S_ R
U D DO SE W RR
R
US DI US L L_ OA
ER
_E AN
T_
IN ER
ER
RR
EF E_ _ _ O _E
EF SE_ IS_ WN RIA NL
EF E_ S_ ES R E_
O
_P _
AG _M
G PIO
O
US DI US E_ D6
_E
US DI _R ER BL
RA RR
_B
JT D
AG
EF SE_ IS_ RC VE
EF E_ T4 I_ A
D_ OA
CH _G
M
D
N
U D FO ER
JT
RR
US RP TW _E
EX S
PA NL
B_ I_A
EF E_ S_ EL
IS
_E
S_ W
B
US SP
_D
US DI _S
DI O
IS
E_ S_D
_D
E_ D_
FT
EF E_ G A
S
SO
RD
US VD
US JT
US DI
d)
)
ed
EF SE_
EF E_
E_
EF E_
E_
ve
rv
US
US
US
US
er
se
U
s
EF
EF
EF
EF
EF
(re
(re
31 27 26 25 24 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 0
RY
0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0 0 0 0x0 Reset
EFUSE_RD_DIS_ERR If any bit in RD_DIS is 1, then it indicates a programming error. (RO)
EFUSE_DIS_RTC_RAM_BOOT_ERR Reserved. (RO)
EFUSE_DIS_ICACHE_ERR If any bit in DIS_ICACHE is 1, then it indicates a programming error. (RO)
A
EFUSE_DIS_USB_JTAG_ERR If any bit in DIS_USB_JTAG is 1, then it indicates a programming error.
(RO)
IN
EFUSE_DIS_DOWNLOAD_ICACHE_ERR If any bit in DIS_DOWNLOAD_ICACHE is 1, then it indi-
cates a programming error. (RO)
IM
EFUSE_DIS_USB_SERIAL_JTAG_ERR If any bit in DIS_USB_SERIAL_JTAG is 1, then it indicates a
programming error. (RO)
EFUSE_DIS_FORCE_DOWNLOAD_ERR If any bit in DIS_FORCE_DOWNLOAD is 1, then it indicates
a programming error. (RO)
EL
EFUSE_RPT4_RESERVED6_ERR Reserved. (RO)
EFUSE_DIS_TWAI_ERR If any bit in DIS_TWAI is 1, then it indicates a programming error. (RO)
EFUSE_JTAG_SEL_ENABLE_ERR If any bit in JTAG_SEL_ENABLE is 1, then it indicates a program-
ming error. (RO)
PR
EFUSE_SOFT_DIS_JTAG_ERR If any bit in SOFT_DIS_JTAG is 1, then it indicates a programming
error. (RO)
EFUSE_DIS_PAD_JTAG_ERR If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.
(RO)
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR If any bit in
DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. (RO)
EFUSE_USB_EXCHG_PINS_ERR If any bit in USB_EXCHG_PINS is 1, then it indicates a program-
ming error. (RO)
EFUSE_VDD_SPI_AS_GPIO_ERR If any bit in VDD_SPI_AS_GPIO is 1, then it indicates a program-
ming error. (RO)
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4 eFuse Controller (EFUSE)
Register 4.97. EFUSE_RD_REPEAT_ERR1_REG (0x0180)
VO E1_ R
0_ R
R
RE K ER
KE ER
ER
Y_ VO E2_
RR
KE RE K
T_ _ O
E
O EY V
T_
O _K RE
R
RR
RR
RR
CN
ER
_B OT EY_
_E
_E
2_
_E
T_
RE BO _K
_1
_0
ED
EL
YP
CU E_ OT
SE
SE
_S
RV
CR
SE R O
PO
PO
AY
SE
T_
E_ CU _B
EL
UR
UR
E
O
E
_R
O
_D
US SE R
_P
_P
B
EF E_ CU
T4
DT
I_
EY
EY
RP
SP
US SE
W
_K
_K
EF E_
E_
E_
E_
E
SE
US
US
US
US
US
U
EF
EF
EF
EF
EF
EF
31 28 27 24 23 22 21 20 18 17 16 15 0
0x0 0x0 0 0 0 0x0 0x0 0x00 Reset
RY
EFUSE_RPT4_RESERVED2_ERR Reserved. (RO)
EFUSE_WDT_DELAY_SEL_ERR If any bit in WDT_DELAY_SEL is 1, then it indicates a programming
error. (RO)
EFUSE_SPI_BOOT_CRYPT_CNT_ERR If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a
A
programming error. (RO)
EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR If any bit in SECURE_BOOT_KEY_REVOKE0 is 1,
then it indicates a programming error. (RO)
IN
EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR If any bit in SECURE_BOOT_KEY_REVOKE1 is 1,
then it indicates a programming error. (RO)
IM
EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR If any bit in SECURE_BOOT_KEY_REVOKE2 is 1,
then it indicates a programming error. (RO)
EFUSE_KEY_PURPOSE_0_ERR If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming
error. (RO)
EL
EFUSE_KEY_PURPOSE_1_ERR If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming
error. (RO)
PR
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4 eFuse Controller (EFUSE)
Register 4.98. EFUSE_RD_REPEAT_ERR2_REG (0x0184)
RR
_E
KE
O
EV
_R
RR IVE
_E SS
EN RE
RR
RR
RR
RR
RR
ER
T_ G
_E
_E
_E
_E
_E
_
O G
RR
D0
D3
O _A
_5
_4
_3
_2
_E
VE
VE
_B OT
SE
SE
SE
SE
W
ER
ER
RE BO
O
PU
RP
RP
RP
RP
ES
ES
CU _
_T
PU
PU
PU
PU
R
_R
SE R
SH
4_
E_ CU
T4
Y_
Y_
Y_
Y_
PT
LA
RP
KE
KE
KE
KE
US SE
_R
_F
EF E_
E_
E_
E_
E_
E_
E
E
US
US
US
US
US
US
US
US
EF
EF
EF
EF
EF
EF
EF
EF
RY
31 28 27 22 21 20 19 16 15 12 11 8 7 4 3 0
0x0 0x0 0 0 0x0 0x0 0x0 0x0 0x0 Reset
EFUSE_KEY_PURPOSE_2_ERR If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming
error. (RO)
EFUSE_KEY_PURPOSE_3_ERR If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming
A
error. (RO)
EFUSE_KEY_PURPOSE_4_ERR If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming
error. (RO)
IN
EFUSE_KEY_PURPOSE_5_ERR If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming
error. (RO)
IM
EFUSE_RPT4_RESERVED3_ERR Reserved. (RO)
EFUSE_SECURE_BOOT_EN_ERR If any bit in SECURE_BOOT_EN is 1, then it indicates a program-
ming error. (RO)
EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR If any bit in SE-
EL
CURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. (RO)
EFUSE_RPT4_RESERVED0_ERR Reserved. (RO)
EFUSE_FLASH_TPUW_ERR If any bit in FLASH_TPUW is 1, then it indicates a programming error.
PR
(RO)
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Register 4.99. EFUSE_RD_REPEAT_ERR3_REG (0x0188)
ER R
W RV NN R E_ _ER
R
DO SE A ER OD D
S_ E CH _ M OA
RR
US RP PR ER L O R
R
DI _R T_ D7 D_ L
_M RR R
ER
ER
E_ T4 IN VE OA WN
_E
AD E R
L_
O 8_ _E
E_
DE
RR
D1 RR
RR
RO
NL ED EL
UM
ER
O
E
VE _E
_E
EF E_ B_ ES WN Y_
NT
N_
5_
ES
ER LE
US US _R DO IT
ED
IO
CO
_R
EF E_ T4 B_ UR
ES AB
RS
RV
ND
T_
US RP US EC
_R EN
VE
SE
N
SE
EF SE_ IS_ E_S
T4 T_
RI
E_
E
E_
RP RS
EF SE_ T_P
_R
UR
U D L
RC
EF E_ AB
E_ R_
T4
R
EC
EF _UA
RP
US EN
O
US ER
_S
_F
EF SE_
E_
E
E
US
US
US
US
U
U
EF
EF
EF
EF
EF
31 30 29 14 13 12 8 7 6 5 4 3 2 1 0
RY
0 0 0x00 0 0 0x0 0 0 0 0 0 0 Reset
EFUSE_DIS_DOWNLOAD_MODE_ERR If any bit in DIS_DOWNLOAD_MODE is 1, then it indicates
a programming error. (RO)
EFUSE_RPT4_RESERVED8_ERR Reserved. (RO)
EFUSE_USB_PRINT_CHANNEL_ERR If any bit in USB_PRINT_CHANNEL is 1, then it indicates a
A
programming error. (RO)
EFUSE_RPT4_RESERVED7_ERR Reserved. (RO)
IN
EFUSE_DIS_USB_DOWNLOAD_MODE_ERR If any bit in DIS_USB_DOWNLOAD_MODE is 1, then
it indicates a programming error. (RO)
EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR If any bit in ENABLE_SECURITY_DOWNLOAD is
IM
1, then it indicates a programming error. (RO)
EFUSE_UART_PRINT_CONTROL_ERR If any bit in UART_PRINT_CONTROL is 1, then it indicates
a programming error. (RO)
EFUSE_RPT4_RESERVED5_ERR Reserved. (RO)
EL
EFUSE_FORCE_SEND_RESUME_ERR If any bit in FORCE_SEND_RESUME is 1, then it indicates
a programming error. (RO)
EFUSE_SECURE_VERSION_ERR If any bit in SECURE_VERSION is 1, then it indicates a program-
ming error. (RO)
PR
EFUSE_RPT4_RESERVED1_ERR Reserved. (RO)
EFUSE_ERR_RST_ENABLE_ERR If any bit in ERR_RST_ENABLE is 1, then it indicates a program-
ming error. (RO)
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4 eFuse Controller (EFUSE)
Register 4.100. EFUSE_RD_REPEAT_ERR4_REG (0x0190)
RR
_E
D4
VE
ER
ES
_R
T4
RP
d)
E_
ve
US
er
s
EF
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000 Reset
EFUSE_RPT4_RESERVED4_ERR Reserved. (RO)
A RY
IN
IM
EL
PR
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4 eFuse Controller (EFUSE)
Register 4.101. EFUSE_RD_RS_ERR0_REG (0x01C0)
UM
UM
_N
_N
RR
L
UM
AI
IL
UM
UM
UM
RR
L
_E
_F
FA
U
NU
AI
_N
_N
_N
_N
_N
8M
M
_E
_F
1_
T1
R_
_8
TA
TA
RR
RR
RR
RR
RT
L
IL
I_
AI
AI
AI
R
ER
PI
FA
SP
DA
DA
PA
PA
_E
_E
_E
_F
_F
_F
_S
2_
0_
1_
_
R_
R_
Y3
Y4
Y2
Y3
Y1
Y0
S_
S_
AC
AC
EY
EY
EY
US
US
KE
KE
KE
KE
KE
KE
SY
SY
M
M
)
_K
_K
_K
ed
E_
E_
E_
E_
E_
E_
E_
E_
E_
E_
E_
E_
E
rv
US
US
US
US
US
US
US
US
US
US
US
US
US
US
US
se
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
EF
(re
31 30 28 27 26 24 23 22 20 19 18 16 15 14 12 11 10 8 7 6 4 3 2 0
0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 Reset
EFUSE_MAC_SPI_8M_ERR_NUM The value of this signal means the number of error bytes. (RO)
RY
EFUSE_SYS_PART1_NUM The value of this signal means the number of error bytes. (RO)
EFUSE_MAC_SPI_8M_FAIL 0: Means no failure and that the data of MAC_SPI_8M is reliable 1:
Means that programming data of MAC_SPI_8M failed and the number of error bytes is over 6.
(RO)
A
EFUSE_USR_DATA_ERR_NUM The value of this signal means the number of error bytes. (RO)
EFUSE_SYS_PART1_FAIL 0: Means no failure and that the data of system part1 is reliable 1: Means
that programming data of system part1 failed and the number of error bytes is over 6. (RO)
IN
EFUSE_KEY0_ERR_NUM The value of this signal means the number of error bytes. (RO)
EFUSE_USR_DATA_FAIL 0: Means no failure and that the user data is reliable 1: Means that pro-
gramming user data failed and the number of error bytes is over 6. (RO)
IM
EFUSE_KEY1_ERR_NUM The value of this signal means the number of error bytes. (RO)
EFUSE_KEY0_FAIL 0: Means no failure and that the data of key0 is reliable 1: Means that program-
ming key0 failed and the number of error bytes is over 6. (RO)
EL
EFUSE_KEY2_ERR_NUM The value of this signal means the number of error bytes. (RO)
EFUSE_KEY1_FAIL 0: Means no failure and that the data of key1 is reliable 1: Means that program-
ming key1 failed and the number of error bytes is over 6. (RO)
EFUSE_KEY3_ERR_NUM The value of this signal means the number of error bytes. (RO)
PR
EFUSE_KEY2_FAIL 0: Means no failure and that the data of key2 is reliable 1: Means that program-
ming key2 failed and the number of error bytes is over 6. (RO)
EFUSE_KEY4_ERR_NUM The value of this signal means the number of error bytes. (RO)
EFUSE_KEY3_FAIL 0: Means no failure and that the data of key3 is reliable 1: Means that program-
ming key3 failed and the number of error bytes is over 6. (RO)
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4 eFuse Controller (EFUSE)
Register 4.102. EFUSE_RD_RS_ERR1_REG (0x01C4)
UM
_N
RR
UM
_E
_N
T2
RR
L
IL
AI
FA
PA
_E
_F
4_
Y5
Y5
S_
EY
KE
KE
d)
_K
_S
E_
E_
ve
SE
E
US
US
US
er
U
s
EF
EF
EF
EF
(re
31 8 7 6 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0x0 Reset
EFUSE_KEY5_ERR_NUM The value of this signal means the number of error bytes. (RO)
RY
EFUSE_KEY4_FAIL 0: Means no failure and that the data of KEY4 is reliable 1: Means that program-
ming KEY4 data failed and the number of error bytes is over 6. (RO)
EFUSE_SYS_PART2_ERR_NUM The value of this signal means the number of error bytes. (RO)
EFUSE_KEY5_FAIL 0: Means no failure and that the data of KEY5 is reliable 1: Means that program-
A
ming KEY5 data failed and the number of error bytes is over 6. (RO)
IN
Register 4.103. EFUSE_CLK_REG (0x01C8)
_F E_O PU
PD
O N
EM C _
E_
M OR CE
RC
E_ _F OR
US LK _F
IM
EF _C M
E_ EM ME
EN
US M E_
EF SE_ US
K_
CL
U EF
d)
d)
E_
EF E_
ve
e
rv
US
US
r
se
se
EF
EF
(re
(re
31 17 16 15 3 2 1 0
EL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
EFUSE_EFUSE_MEM_FORCE_PD Set this bit to force eFuse SRAM into power-saving mode. (R/W)
EFUSE_MEM_CLK_FORCE_ON Set this bit and force to activate clock signal of eFuse SRAM. (R/W)
PR
EFUSE_EFUSE_MEM_FORCE_PU Set this bit to force eFuse SRAM into working mode. (R/W)
EFUSE_CLK_EN Set this bit and force to enable clock signal of eFuse memory. (R/W)
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4 eFuse Controller (EFUSE)
Register 4.104. EFUSE_CONF_REG (0x01CC)
DE
CO
P_
O
d)
E_
ve
US
r
se
EF
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00 Reset
EFUSE_OP_CODE 0x5A5A: Operate programming command 0x5AA5: Operate read command.
(R/W)
RY
Register 4.105. EFUSE_CMD_REG (0x01D4)
D
AD MD
M
M
_C
NU
RE _C
K_
E_ M
US PG
BL
d)
E_
EF E_
e
rv
US
US
se
A EF
EF
(re
31 6 5 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 Reset
EFUSE_READ_CMD Set this bit to send read command. (R/WS/SC)
IN
EFUSE_PGM_CMD Set this bit to send programming command. (R/WS/SC)
EFUSE_BLK_NUM The serial number of the block to be programmed. Value 0-10 corresponds to
IM
block number 0-10, respectively. (R/W)
Register 4.106. EFUSE_DAC_CONF_REG (0x01E8)
EL
EL
D _S
V
PA
DI
K_
K_
M
NU
CL
CL
R
CL
C_
C_
C_
E_
DA
DA
DA
_O
d)
E_
E_
E_
ve
SE
US
US
US
r
se
U
PR
EF
EF
EF
EF
(re
31 18 17 16 9 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255 0 28 Reset
EFUSE_DAC_CLK_DIV Controls the division factor of the rising clock of the programming voltage.
(R/W)
EFUSE_DAC_CLK_PAD_SEL Don’t care. (R/W)
EFUSE_DAC_NUM Controls the rising period of the programming voltage. (R/W)
EFUSE_OE_CLR Reduces the power supply of the programming voltage. (R/W)
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Register 4.107. EFUSE_RD_TIM_CONF_REG (0x01EC)
M
NU
T_
NI
_I
AD
RE
)
ed
E_
rv
US
se
EF
(re
31 24 23 0
0x12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_READ_INIT_NUM Configures the initial read time of eFuse. (R/W)
RY
Register 4.108. EFUSE_WR_TIM_CONF1_REG (0x01F0)
M
NU
N_
O
R_
PW
)
)
ed
ed
A
E_
rv
rv
US
se
se
EF
(re
(re
31 24 23 8 7 0
0 0 0 0 0 0 0 0 0x2880 0 0 0 0 0 0 0 0 Reset
EFUSE_PWR_ON_NUM Configures the power up time for VDDQ. (R/W)
IN
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Register 4.109. EFUSE_WR_TIM_CONF2_REG (0x01F4)
UM
_N
FF
O
R_
PW
EL ed
)
E_
rv
US
se
EF
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x190 Reset
EFUSE_PWR_OFF_NUM Configures the power outage time for VDDQ. (R/W)
PR
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4 eFuse Controller (EFUSE)
Register 4.110. EFUSE_STATUS_REG (0x01D0)
NT
_C
RR
_E
AT
E
PE
AT
RE
ST
)
)
ed
ed
E_
E_
rv
rv
US
US
se
se
EF
EF
(re
(re
31 18 17 10 9 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0x0 Reset
EFUSE_STATE Indicates the state of the eFuse state machine. (RO)
EFUSE_REPEAT_ERR_CNT Indicates the number of error bits during programming BLOCK0. (RO)
RY
Register 4.111. EFUSE_INT_RAW_REG (0x01D8)
AW
NT W
_I RA
_R
A
NE _
O INT
_D E_
AD ON
RE _D
E_ M
US PG
IN
d)
EF SE_
e
rv
se
U
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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EFUSE_READ_DONE_INT_RAW The raw bit signal for read_done interrupt. (R/WC/SS)
EFUSE_PGM_DONE_INT_RAW The raw bit signal for pgm_done interrupt. (R/WC/SS)
EL
Register 4.112. EFUSE_INT_ST_REG (0x01DC)
T
_I ST
_S
NE _
NT
O INT
_D E_
AD ON
RE _D
E_ M
PR
US PG
d)
EF SE_
ve
r
se
U
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_READ_DONE_INT_ST The status signal for read_done interrupt. (RO)
EFUSE_PGM_DONE_INT_ST The status signal for pgm_done interrupt. (RO)
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Register 4.113. EFUSE_INT_ENA_REG (0x01E0)
NA
NT A
_I EN
_E
NE _
O INT
_D E_
AD ON
RE _D
E_ M
US PG
)
ed
EF SE_
v
er
U
s
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_READ_DONE_INT_ENA The enable signal for read_done interrupt. (R/W)
RY
EFUSE_PGM_DONE_INT_ENA The enable signal for pgm_done interrupt. (R/W)
Register 4.114. EFUSE_INT_CLR_REG (0x01E4)
A
LR
NT R
_I CL
_C
NE _
O INT
_D E_
AD ON
RE _D
IN
E_ M
US PG
d)
EF SE_
e
rv
se
U
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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EFUSE_READ_DONE_INT_CLR The clear signal for read_done interrupt. (WO)
EFUSE_PGM_DONE_INT_CLR The clear signal for pgm_done interrupt. (WO)
EL
Register 4.115. EFUSE_DATE_REG (0x01FC)
TE
DA
)
ed
E_
rv
US
se
EF
(re
PR
31 28 27 0
0 0 0 0 0x2006300 Reset
EFUSE_DATE Stores eFuse version. (R/W)
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
5 IO MUX and GPIO Matrix (GPIO, IO MUX)
5.1 Overview
The ESP32-C3 chip features 22 physical GPIO pins. Each pin can be used as a general-purpose I/O, or be
connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be
from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide
highly configurable I/O.
Note that the GPIO pins are numbered from 0 ~ 21.
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5.2 Features
GPIO Matrix Features
• A full-switching matrix between the peripheral input/output signals and the pins.
• 42 peripheral input signals can be sourced from the input of any GPIO pins.
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• The output of any GPIO pins can be from any of the 78 peripheral output signals.
• Supports signal synchronization for peripheral inputs based on APB clock bus.
IN
• Provides input signal filter.
• Supports sigma delta modulated output.
• Supports GPIO simple input and output.
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IO MUX Features
• Provides one configuration register IO_MUX_GPIOn_REG for each GPIO pin. The pin can be configured to
– perform GPIO function routed by GPIO matrix;
– or perform direct connection bypassing GPIO matrix.
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• Supports some high-speed digital signals (SPI, JTAG, UART) bypassing GPIO matrix for better
high-frequency digital performance. In this case, IO MUX is used to connect these pins directly to
peripherals.
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5.3 Architectural Overview
This section provides an overview to the architecture of IO MUX and GPIO matrix with the following figures:
• Figure 5-1 shows the general work flow of IO MUX and GPIO matix.
• Figure 5-2 shows in details how IO MUX and GPIO matrix route signals from pins to peripherals, and from
peripherals to pins.
• Figure 5-3 shows the interface logic for a GPIO pin.
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Figure 51. Diagram of IO MUX and GPIO Matrix
A
IN
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Figure 52. Architecture of IO MUX and GPIO Matirx
1. Only part of peripheral input signals (marked “yes” in column “Direct input through IO MUX” in Table 5-1)
can bypass GPIO matrix. The other input signals can only be routed to peripherals via GPIO matrix.
2. There are only 22 inputs from GPIO SYNC to GPIO matrix, since ESP32-C3 provides 22 GPIO pins in total.
3. The pins supplied by VDD3P3_CPU or by VDD3P3_RTC are controlled by the signals: IE, OE, WPU, and
WPD.
4. Only part of peripheral outputs (marked “yes” in column “Direct output through IO MUX” in Table 5-1) can
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be routed to pins bypassing GPIO matrix. See Table 5-1.
5. There are only 22 outputs (GPIO pin X: 0 ~ 21) from GPIO matrix to IO MUX.
Figure 5-3 shows the internal structure of a pad, which is an electrical interface between the chip logic and the
GPIO pin. The structure is applicable to all 22 GPIO pins and can be controlled using IE, OE, WPU, and WPD
signals.
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IN
Figure 53. Internal Structure of a Pad
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Note:
• IE: input enable
• OE: output enable
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• WPU: internal weak pull-up
• WPD: internal weak pull-down
• Bonding pad: a terminal point of the chip logic used to make a physical connection from the chip die to GPIO pin
in the chip package.
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5.4 Peripheral Input via GPIO Matrix
5.4.1 Overview
To receive a peripheral input signal via GPIO matrix, the matrix is configured to source the peripheral input signal
from one of the 22 GPIOs (0 ~ 21), see Table 5-1. Meanwhile, register corresponding to the peripheral signal
should be set to receive input signal via GPIO matrix.
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5.4.2 Signal Synchronization
When signals are directed from pins using GPIO matrix, the signals will be synchronized to the APB bus clock by
GPIO SYNC hardware, then go to GPIO matrix. This synchronization applies to all GPIO matrix signals but does
not apply when using the IO MUX, see Figure 5-2.
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Figure 54. GPIO Input Synchronized on APB Clock Rising Edge or on Falling Edge
IN
Figure 5-4 shows the functionality of GPIO SYNC. In the figure, negative sync and positive sync mean GPIO input
is synchronized on APB clock falling edge and on APB clock rising edge, respectively.
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5.4.3 Functional Description
To read GPIO pin X1 into peripheral signal Y, follow the steps below:
1. Configure register GPIO_FUNCy_IN_SEL_CFG_REG corresponding to peripheral signal Y in GPIO matrix:
• Set GPIO_SIGy_IN_SEL to enable peripheral signal input via GPIO matrix.
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• Set GPIO_FUNCy_IN_SEL to the desired GPIO pin, i.e. X here.
Note that some peripheral signals have no valid GPIO_SIGy_IN_SEL bit, namely, these peripherals can only
receive input signals via GPIO matrix.
2. Optionally enable the filter for pin input signals by setting the register IO_MUX_GPIOn_FILTER_EN. Only the
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signals with a valid width of more than two clock cycles can be sampled, see Figure 5-5.
Figure 55. Filter Timing of GPIO Input Signals
3. Synchronize GPIO input. To do so, please set GPIO_PINx_REG corresponding to GPIO pin X as follows:
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• Set GPIO_PINx_SYNC1_BYPASS to enable input signal synchronized on rising edge or on falling edge
in the first clock, see Figure 5-4.
• Set GPIO_PINx_SYNC2_BYPASS to enable input signal synchronized on rising edge or on falling edge
in the second clock, see Figure 5-4.
4. Configure IO MUX register to enable pin input. For this end, please set IO_MUX_GPIOx_REG
corresponding to GPIO pin X as follows:
• Set IO_MUX_GPIOx_FUN_IE to enable input2 .
• Set or clear IO_MUX_GPIOx_FUN_WPU and IO_MUX_GPIOx_FUN_WPD, as desired, to enable or
disable pull-up and pull-down resistors.
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For example, to connect I2S MCLK input signal3 (I2S_MCLK_in, signal index 12) to GPIO7, please follow the
steps below. Note that GPIO7 is also named as MTDO pin.
1. Set GPIO_SIG12_IN_SEL in register GPIO_FUNC12_IN_SEL_CFG_REG to enable peripheral signal input
via GPIO matrix.
2. Set GPIO_FUNC12_IN_SEL in register GPIO_FUNC12_IN_SEL_CFG_REG to 7.
A
3. Set IO_MUX_GPIO7_FUN_IE in register IO_MUX_GPIO7_REG to enable pin input.
Note:
IN
1. One input pin can be connected to multiple peripheral input signals.
2. The input signal can be inverted by configuring GPIO_FUNCy_IN_INV_SEL.
3. It is possible to have a peripheral read a constantly low or constantly high input value without connecting this input
IM
to a pin. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a GPIO number:
• When GPIO_FUNCy_IN_SEL is set to 0x1F, input signal is always 0.
• When GPIO_FUNCy_IN_SEL is set to 0x1E, input signal is always 1.
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5.4.4 Simple GPIO Input
GPIO_IN_REG holds the input values of each GPIO pin. The input value of any GPIO pin can be read at any time
without configuring GPIO matrix for a particular peripheral signal. However, it is necessary to enable the input via
IO MUX by setting IO_MUX_GPIOx_FUN_IE bit in register IO_MUX_GPIOx_REG corresponding to pin X, as
PR
mentioned in Section 5.4.2.
5.5 Peripheral Output via GPIO Matrix
5.5.1 Overview
To output a signal from a peripheral via GPIO matrix, the matrix is configured to route peripheral output signals
(only signals with a name assigned in the column ”Output signal” in Table 5-1) to one of the 22 GPIOs (0 ~ 21).
See Table 5-1.
The output signal is routed from the peripheral into GPIO matrix and then into IO MUX. IO MUX must be
configured to set the chosen pin to GPIO function. This enables the output GPIO signal to be connected to the
pin.
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Note:
There is a range of peripheral output signals (97 ~ 100) which are not connected to any peripheral, but to the input signals
(97 ~ 100 in Table 5-1) directly. These can be used to input a signal from one GPIO pin and output directly to another
GPIO pin.
5.5.2 Functional Description
Some of the 78 output signals (signals with a name assigned in the column ”Output signal” in Table 5-1) can be
set to go through GPIO matrix into IO MUX and then to a pin. Figure 5-2 illustrates the configuration.
To output peripheral signal Y to a particular GPIO pin X1 , follow these steps:
1. Configure register GPIO_FUNCx_OUT_SEL_CFG_REG and GPIO_ENABLE_REG[x] corresponding to GPIO
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pin X in GPIO matrix. Recommended operation: use corresponding W1TS (write 1 to set) and W1TC (write
1 to clear) registers to set or clear GPIO_ENABLE_REG.
• Set the GPIO_FUNCx_OUT_SEL field in register GPIO_FUNCx_OUT_SEL_CFG_REG to the index of
the desired peripheral output signal Y.
• If the signal should always be enabled as an output, set the GPIO_FUNCx_OEN_SEL bit in register
A
GPIO_FUNCx_OUT_SEL_CFG_REG and the bit in register GPIO_ENABLE_W1TS_REG,
corresponding to GPIO pin X. To have the output enable signal decided by internal logic (for example,
the SPIQ_oe in column “Output enable signal when GPIO_FUNCn_OEN_SEL = 0” in Table 5-1), clear
GPIO_FUNCx
_OEN_SEL bit instead.
IN
• Set the corresponding bit in register GPIO_ENABLE_W1TC_REG to disable the output from the GPIO
pin.
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2. For an open drain output, set the GPIO_PINx_PAD_DRIVER bit in register GPIO_PINx_REG corresponding
to GPIO pin X.
3. Configure IO MUX register to enable output via GPIO matrix. Set the IO_MUX_GPIOx_REG corresponding
to GPIO pin X as follows:
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• Set the field IO_MUX_GPIOx_MCU_SEL to desired IO MUX function corresponding to GPIO pinX. This
is Function 1 (GPIO function), numeric value 1, for all pins.
• Set the IO_MUX_GPIOx_FUN_DRV field to the desired value for output strength (0 ~ 3). The higher the
driver strength, the more current can be sourced/sunk from the pin.
PR
– 0: ~5 mA
– 1: ~10 mA
– 2: ~20 mA (default value)
– 3: ~40 mA
• If using open drain mode, set/clear the IO_MUX_GPIOx_FUN_WPU and IO_MUX_GPIOx_FUN_WPD
bits to enable/disable the internal pull-up/pull-down resistors.
Note:
1. The output signal from a single peripheral can be sent to multiple pins simultaneously.
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2. The output signal can be inverted by setting GPIO_FUNCx_OUT_INV_SEL bit.
5.5.3 Simple GPIO Output
GPIO matrix can also be used for simple GPIO output. This can be done as below:
• Set GPIO matrix GPIO_FUNCn_OUT_SEL with a special peripheral index 128 (0x80);
• Set the corresponding bit in GPIO_OUT_REG register to the desired GPIO output value.
Note:
• GPIO_OUT_REG[0] ~ GPIO_OUT_REG[21] correspond to GPIO0 ~ GPIO21, and GPIO_OUT_REG[25:22] are in-
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valid.
• Recommended operation: use corresponding W1TS and W1TC registers, such as GPIO_OUT_W1TS/GPIO_OUT
_W1TC to set or clear the registers GPIO_OUT_REG.
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5.5.4 Sigma Delta Modulated Output (SDM)
5.5.4.1 Functional Description IN
Four out of the 125 peripheral outputs (output index: 55 ~ 58 in Table 5-1) support 1-bit second-order sigma
delta modulation. By default output is enabled for these four channels. This modulator can also output PDM
(pulse density modulation) signal with configurable duty cycle. The transfer function of this second-order SDM
modulator is:
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H(z) = X(z)z−1 + E(z)(1-z−1 )2
E(z) is quantization error and X(z) is the input.
Sigma Delta modulator supports scaling down of APB_CLK by divider 1 ~ 256:
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• Set GPIOSD_FUNCTION_CLK_EN to enable the modulator clock.
• Configure register GPIOSD_SDn_PRESCALE (n is 0 ~ 3 for four channels).
After scaling, the clock cycle is equal to one pulse output cycle from the modulator.
PR
GPIOSD_SDn_IN is a signed number with a range of [-128, 127] and is used to control the duty cycle 1 of PDM
output signal.
• GPIOSD_SDn_IN = -128, the duty cycle of the output signal is 0%.
• GPIOSD_SDn_IN = 0, the duty cycle of the output signal is near 50%.
• GPIOSD_SDn_IN = 127, the duty cycle of the output signal is close to 100%.
The formula for calculating PDM signal duty cycle is shown as below:
GP IOSD_SDn_IN + 128
Duty_Cycle =
256
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Note:
For PDM signals, duty cycle refers to the percentage of high level cycles to the whole statistical period (several pulse
cycles, for example 256 pulse cycles).
5.5.4.2 SDM Configuration
The configuration of SDM is shown below:
• Route one of SDM outputs to a pin via GPIO matrix, see Section 5.5.2.
• Enable the modulator clock by setting the register GPIOSD_FUNCTION_CLK_EN.
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• Configure the divider value by setting the register GPIOSD_SDn_PRESCALE.
• Configure the duty cycle of SDM output signal by setting the register GPIOSD_SDn_IN.
5.6 Direct Input and Output via IO MUX
A
5.6.1 Overview
Some high-speed signals (SPI and JTAG) can bypass GPIO matrix for better high-frequency digital performance.
In this case, IO MUX is used to connect these pins directly to peripherals.
IN
This option is less flexible than routing signals via GPIO matrix, as the IO MUX register for each GPIO pin can only
select from a limited number of functions, but high-frequency digital performance can be improved.
5.6.2 Functional Description
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Two registers must be configured in order to bypass GPIO matrix for peripheral input signals:
1. IO_MUX_GPIOn_MCU_SEL for the GPIO pin must be set to the required pin function. For the list of pin
functions, please refer to Section 5.11.
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2. Clear GPIO_SIGn_IN_SEL to route the input directly to the peripheral.
To bypass GPIO matrix for peripheral output signals, IO_MUX_GPIOn_MCU_SEL for the GPIO pin must be set to
the required pin function. For the list of pin functions, please refer to Section 5.11.
Note:
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Not all signals can be directly connected to peripheral via IO MUX. Some input/output signals can only be connected to
peripheral via GPIO matrix.
5.7 Analog Functions of GPIO Pins
Some GPIO pins in ESP32-C3 provide analog functions. When the pin is used for analog purpose, make sure
that pull-up and pull-down resistors are disabled by following configuration:
• Set IO_MUX_GPIOn_MCU_SEL to 1, and clear IO_MUX_GPIOn_FUN_IE, IO_MUX_GPIOn_FUN_WPU, IO_
MUX_GPIOn_FUN_WPD.
• Write 1 to GPIO_ENABLE_W1TC[n], to clear output enable.
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See Table 5-4 for analog functions of ESP32-C3 pins.
5.8 Pin Hold Feature
Each GPIO pin (including the RTC pins: GPIO0 ~ GPIO5) has an individual hold function controlled by a RTC
register. When the pin is set to hold, the state is latched at that moment and will not change no matter how the
internal signals change or how the IO MUX/GPIO configuration is modified. Users can use the hold function for
the pins to retain the pin state through a core reset and system reset triggered by watchdog time-out or
Deep-sleep events.
Note:
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• For digital pins (GPIO6 ~21), to maintain pin input/output status in Deep-sleep mode, users can set RTC_CNTL_DIG
_PAD_HOLDn in register RTC_CNTL_DIG_PAD_HOLD_REG to 1 before powering down. To disable the hold func-
tion after the chip is woken up, users can set RTC_CNTL_DIG_PAD_HOLDn to 0.
• For RTC pins (GPIO0 ~5), the input and output values are controlled by the corresponding bits of register RTC_CNTL
_RTC_PAD_HOLD_REG, and users can set it to 1 to hold the value or set it to 0 to unhold the value.
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5.9 Power Supplies and Management of GPIO Pins
5.9.1 Power Supplies of GPIO Pins
IN
For more information on the power supply for GPIO pins, please refer to Pin Definition in ESP32-C3 Datasheet. All
the pins can be used to wake up the chip from Light-sleep mode, but only the pins (GPIO0 ~ GPIO5) in
VDD3P3_RTC domain can be used to wake up the chip from Deep-sleep mode.
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5.9.2 Power Supply Management
Each ESP32-C3 pin is connected to one of the two different power domains.
• VDD3P3_RTC: the input power supply for both RTC and CPU
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• VDD3P3_CPU: the input power supply for CPU
5.10 Peripheral Signal List
Table 5-1 shows the peripheral input/output signals via GPIO matrix.
PR
Please pay attention to the configuration of the bit GPIO_FUNCn_OEN_SEL:
• GPIO_FUNCn_OEN_SEL = 1: the output enable is controlled by the corresponding bit n of
GPIO_ENABLE_REG:
– GPIO_ENABLE_REG = 0: output is disabled;
– GPIO_ENABLE_REG = 1: output is enabled;
• GPIO_FUNCn_OEN_SEL = 0: use the output enable signal from peripheral, for example SPIQ_oe in the
column “Output enable signal when GPIO_FUNCn_OEN_SEL = 0” of Table 5-1. Note that the signals such
as SPIQ_oe can be 1 (1’d1) or 0 (1’d0), depending on the configuration of corresponding peripherals. If it’s
1’d1 in the “Output enable signal when GPIO_FUNCn_OEN_SEL = 0”, it indicates that once the register
GPIO_FUNCn_OEN_SEL is cleared, the output signal is always enabled by default.
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Note:
Signals are numbered consecutively, but not all signals are valid.
• Only the signals with a name assigned in the column ”Input signal” in Table 5-1 are valid input signals.
• Only the signals with a name assigned in the column ”Output signal” in Table 5-1 are valid output signals.
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Table 51. Peripheral Signals via GPIO Matrix
Direct Direct
Signal Default Output enable signal when
Input Signal Input via Output Signal Output via
PR
No. value GPIO_FUNCn_OEN_SEL = 0
IO MUX IO MUX
0 SPIQ_in 0 yes SPIQ_out SPIQ_oe yes
1 SPID_in 0 yes SPID_out SPID_oe yes
2 SPIHD_in 0 yes SPIHD_out SPIHD_oe yes
3 SPIWP_in 0 yes SPIWP_out SPIWP_oe yes
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4 - - - SPICLK_out_mux SPICLK_oe yes
5 - - - SPICS0_out SPICS0_oe yes
6 U0RXD_in 0 yes U0TXD_out 1’d1 yes
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7 U0CTS_in 0 yes U0RTS_out 1’d1 no
8 U0DSR_in 0 no U0DTR_out 1’d1 no
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9 U1RXD_in 0 yes U1TXD_out 1’d1 no
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10 U1CTS_in 0 yes U1RTS_out 1’d1 no
11 U1DSR_in 0 no U1DTR_out 1’d1 no
12 I2S_MCLK_in 0 no I2S_MCLK_out 1’d1 no
13 I2SO_BCK_in 0 no I2SO_BCK_out 1’d1 no
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14 I2SO_WS_in 0 no I2SO_WS_out 1’d1 no
15 I2SI_SD_in 0 no I2SO_SD_out 1’d1 no
16 I2SI_BCK_in 0 no I2SI_BCK_out 1’d1 no
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17 I2SI_WS_in 0 no I2SI_WS_out 1’d1 no
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18 gpio_bt_priority 0 no gpio_wlan_prio 1’d1 no
19 gpio_bt_active 0 no gpio_wlan_active 1’d1 no
20 - - - - 1’d1 no
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21 - - - - 1’d1 no
22 - - - - 1’d1 no
23 - - - - 1’d1 no
24 - - - - 1’d1 no
Espressif Systems
5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Direct Direct
Signal Default Output enable signal when
Input Signal Input via Output Signal Output via
No. value GPIO_FUNCn_OEN_SEL = 0
IO MUX IO MUX
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25 - - - - 1’d1 no
26 - - - - 1’d1 no
27 - - - - 1’d1 no
28 cpu_gpio_in0 0 no cpu_gpio_out0 cpu_gpio_out_oen0 no
29 cpu_gpio_in1 0 no cpu_gpio_out1 cpu_gpio_out_oen1 no
30 cpu_gpio_in2 0 no cpu_gpio_out2 cpu_gpio_out_oen2 no
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31 cpu_gpio_in3 0 no cpu_gpio_out3 cpu_gpio_out_oen3 no
32 cpu_gpio_in4 0 no cpu_gpio_out4 cpu_gpio_out_oen4 no
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33 cpu_gpio_in5 0 no cpu_gpio_out5 cpu_gpio_out_oen5 no
34 cpu_gpio_in6 0 no cpu_gpio_out6 cpu_gpio_out_oen6 no
35 cpu_gpio_in7 0 no cpu_gpio_out7 cpu_gpio_out_oen7 no
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36 - - - usb_jtag_tck 1’d1 no
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37 - - - usb_jtag_tms 1’d1 no
38 - - - usb_jtag_tdi 1’d1 no
39 - - - usb_jtag_tdo 1’d1 no
IN
40 - - - - 1’d1 no
41 - - - - 1’d1 no
42 - - - - 1’d1 no
ESP32-C3 TRM (Pre-release v0.4)
43 - - - - 1’d1 no
44 - - - - 1’d1 no
A
45 ext_adc_start 0 no ledc_ls_sig_out0 1’d1 no
46 - - - ledc_ls_sig_out1 1’d1 no
RY
47 - - - ledc_ls_sig_out2 1’d1 no
48 - - - ledc_ls_sig_out3 1’d1 no
49 - - - ledc_ls_sig_out4 1’d1 no
50 - - - ledc_ls_sig_out5 1’d1 no
51 rmt_sig_in0 0 no rmt_sig_out0 1’d1 no
Espressif Systems
5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Direct Direct
Signal Default Output enable signal when
Input Signal Input via Output Signal Output via
No. value GPIO_FUNCn_OEN_SEL = 0
IO MUX IO MUX
PR
52 rmt_sig_in1 0 no rmt_sig_out1 1’d1 no
53 I2CEXT0_SCL_in 1 no I2CEXT0_SCL_out I2CEXT0_SCL_oe no
54 I2CEXT0_SDA_in 1 no I2CEXT0_SDA_out I2CEXT0_SDA_oe no
55 - - - gpio_sd0_out 1’d1 no
56 - - - gpio_sd1_out 1’d1 no
57 - - - gpio_sd2_out 1’d1 no
EL
58 - - - gpio_sd3_out 1’d1 no
59 - - - I2SO_SD1_out 1’d1 no
Submit Documentation Feedback
60 - - - - 1’d1 no
61 - - - - 1’d1 no
62 - - - - 1’d1 no
IM
63 FSPICLK_in 0 yes FSPICLK_out_mux FSPICLK_oe yes
153
64 FSPIQ_in 0 yes FSPIQ_out FSPIQ_oe yes
65 FSPID_in 0 yes FSPID_out FSPID_oe yes
66 FSPIHD_in 0 yes FSPIHD_out FSPIHD_oe yes
IN
67 FSPIWP_in 0 yes FSPIWP_out FSPIWP_oe yes
68 FSPICS0_in 0 yes FSPICS0_out FSPICS0_oe yes
69 - - - FSPICS1_out FSPICS1_oe no
ESP32-C3 TRM (Pre-release v0.4)
70 - - - FSPICS2_out FSPICS2_oe no
71 - - - FSPICS3_out FSPICS3_oe no
A
72 - - - FSPICS4_out FSPICS4_oe no
73 - - - FSPICS5_out FSPICS5_oe no
RY
74 twai_rx 1 no twai_tx 1’d1 no
75 - - - twai_bus_off_on 1’d1 no
76 - - - twai_clkout 1’d1 no
77 - - - - 1’d1 no
78 - - - - 1’d1 no
Espressif Systems
5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Direct Direct
Signal Default Output enable signal when
Input Signal Input via Output Signal Output via
No. value GPIO_FUNCn_OEN_SEL = 0
IO MUX IO MUX
PR
79 - - - - 1’d1 no
80 - - - - 1’d1 no
81 - - - - 1’d1 no
82 - - - - 1’d1 no
83 - - - - 1’d1 no
84 - - - - 1’d1 no
EL
85 - - - - 1’d1 no
86 - - - - 1’d1 no
Submit Documentation Feedback
87 - - - - 1’d1 no
88 - - - - 1’d1 no
89 - - - ant_sel0 1’d1 no
IM
90 - - - ant_sel1 1’d1 no
154
91 - - - ant_sel2 1’d1 no
92 - - - ant_sel3 1’d1 no
93 - - - ant_sel4 1’d1 no
IN
94 - - - ant_sel5 1’d1 no
95 - - - ant_sel6 1’d1 no
96 - - - ant_sel7 1’d1 no
ESP32-C3 TRM (Pre-release v0.4)
97 sig_in_func_97 0 no sig_in_func97 1’d1 no
98 sig_in_func_98 0 no sig_in_func98 1’d1 no
A
99 sig_in_func_99 0 no sig_in_func99 1’d1 no
100 sig_in_func_100 0 no sig_in_func100 1’d1 no
RY
101 - - - - 1’d1 no
102 - - - - 1’d1 no
103 - - - - 1’d1 no
104 - - - - 1’d1 no
105 - - - - 1’d1 no
Espressif Systems
5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Direct Direct
Signal Default Output enable signal when
Input Signal Input via Output Signal Output via
No. value GPIO_FUNCn_OEN_SEL = 0
IO MUX IO MUX
PR
106 - - - - 1’d1 no
107 - - - - 1’d1 no
108 - - - - 1’d1 no
109 - - - - 1’d1 no
110 - - - - 1’d1 no
111 - - - - 1’d1 no
EL
112 - - - - 1’d1 no
113 - - - - 1’d1 no
Submit Documentation Feedback
114 - - - - 1’d1 no
115 - - - - 1’d1 no
116 - - - - 1’d1 no
IM
117 - - - - 1’d1 no
155
118 - - - - 1’d1 no
119 - - - - 1’d1 no
120 - - - - 1’d1 no
IN
121 - - - - 1’d1 no
122 - - - - 1’d1 no
123 - - - CLK_OUT_out1 1’d1 no
ESP32-C3 TRM (Pre-release v0.4)
124 - - - CLK_OUT_out2 1’d1 no
125 - - - CLK_OUT_out3 1’d1 no
A
126 - - - SPICS1_out 1’d1 no
127 - - - usb_jtag_trst 1’d1 no
RY
5 IO MUX and GPIO Matrix (GPIO, IO MUX)
5.11 IO MUX Functions List
Table 5-2 shows the IO MUX functions of each pin.
Table 52. IO MUX Pin Functions
GPIO Pin Name Function 0 Function 1 Function 2 Function 3 DRV Reset Notes
0 XTAL_32K_P GPIO0 GPIO0 - - 2 0 R
1 XTAL_32K_N GPIO1 GPIO1 - - 2 0 R
2 GPIO2 GPIO2 GPIO2 FSPIQ - 2 1 R
3 GPIO3 GPIO3 GPIO3 - - 2 1 R
4 MTMS MTMS GPIO4 FSPIHD - 2 1 R
RY
5 MTDI MTDI GPIO5 FSPIWP - 2 1 R
6 MTCK MTCK GPIO6 FSPICLK - 2 1* G
7 MTDO MTDO GPIO7 FSPID - 2 1 G
8 GPIO8 GPIO8 GPIO8 - - 2 1 -
9 GPIO9 GPIO9 GPIO9 - - 2 3 -
A
10 GPIO10 GPIO10 GPIO10 FSPICS0 - 2 1 G
11 VDD_SPI GPIO11 GPIO11 - - 2 0 -
12 SPIHD SPIHD GPIO12 - - 2 3 -
13
14
SPIWP
SPICS0
SPIWP
SPICS0
GPIO13
GPIO14
IN -
-
-
-
2
2
3
3
-
-
15 SPICLK SPICLK GPIO15 - - 2 3 -
16 SPID SPID GPIO16 - - 2 3 -
IM
17 SPIQ SPIQ GPIO17 - - 2 3 -
18 GPIO18 GPIO18 GPIO18 - - 3 0 USB,
G
19 GPIO19 GPIO19 GPIO19 - - 3 0* USB
20 U0RXD U0RXD GPIO20 - - 2 1 G
EL
21 U0TXD U0TXD GPIO21 - - 2 1 -
Drive Strength
“DRV” column shows the drive strength of each pin after reset:
PR
• 0 - Drive current = ~5 mA
• 1 - Drive current = ~10 mA
• 2 - Drive current = ~20 mA
• 3 - Drive current = ~40 mA
Reset Configurations
“Reset” column shows the default configuration of each pin after reset:
• 0 - IE = 0 (input disabled)
• 1 - IE = 1 (input enabled)
• 2 - IE = 1, WPD = 1 (input enabled, pull-down resistor enabled)
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
• 3 - IE = 1, WPU = 1 (input enabled, pull-up resistor enabled)
• 0* - IE = 0, WPU = 0. The USB pull-up value of GPIO19 is 1 by default, therefore, the pin’s pull-up resistor
is enabled. For more information, see the note below.
• 1* - If eFuse bit EFUSE_DIS_PAD_JTAG = 1, the pin MTCK is left floating after reset, i.e. IE = 1. If eFuse bit
EFUSE_DIS_PAD_JTAG = 0, the pin MTCK is connected to internal pull-up resistor, i.e. IE = 1, WPU = 1.
Note:
• R - Pins in VDD3P3_RTC domain, and part of them have analog functions, see Table 5-4.
• USB - GPIO18 and GPIO19 are USB pins. The pull-up value of the two pins are controlled by the pins’
pull-up value together with USB pull-up value. If any one of the pull-up value is 1, the pin’s pull-up resistor
RY
will be enabled. The pull-up resistors of USB pins are controlled by USB_SERIAL_JTAG_DP_PULLUP.
• G - These pins have glitches during power-up. See details in Table 5-3.
Table 53. PowerUp Glitches on Pins
Typical Time Period
Pin Glitch
A
(ns)
MTCK Low-level glitch 5
MTDO Low-level glitch 5
GPIO10
U0RXD
IN
Low-level glitch
Low-level glitch
5
5
GPIO18 Pull-up glitch 50000
IM
5.12 Analog Functions List
Table 5-4 shows the IO MUX pins with analog functions.
Table 54. Analog Functions of IO MUX Pins
EL
GPIO Num Pin Name Analog Function 0 Analog Function 1
0 XTAL_32K_P XTAL_32K_P ADC1_CH0
1 XTAL_32K_N XTAL_32K_N ADC1_CH1
2 GPIO2 - ADC1_CH2
PR
3 GPIO3 - ADC1_CH3
4 MTMS - ADC1_CH4
5.13 Register Summary
5.13.1 GPIO Matrix Register Summary
The addresses in this section are relative to the GPIO base address provided in Table 3-4 in Chapter 3 System
and Memory.
Name Description Address Access
Configuration Registers
GPIO_BT_SELECT_REG GPIO bit select register 0x0000 R/W
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Name Description Address Access
GPIO_OUT_REG GPIO output register 0x0004 R/W/SS
GPIO_OUT_W1TS_REG GPIO output set register 0x0008 WT
GPIO_OUT_W1TC_REG GPIO output clear register 0x000C WT
GPIO_ENABLE_REG GPIO output enable register 0x0020 R/W/SS
GPIO_ENABLE_W1TS_REG GPIO output enable set register 0x0024 WT
GPIO_ENABLE_W1TC_REG GPIO output enable clear register 0x0028 WT
GPIO_STRAP_REG pin strapping register 0x0038 RO
GPIO_IN_REG GPIO input register 0x003C RO
GPIO_STATUS_REG GPIO interrupt status register 0x0044 R/W/SS
GPIO_STATUS_W1TS_REG GPIO interrupt status set register 0x0048 WT
RY
GPIO_STATUS_W1TC_REG GPIO interrupt status clear register 0x004C WT
GPIO_PCPU_INT_REG GPIO PRO_CPU interrupt status register 0x005C RO
GPIO_PCPU_NMI_INT_REG GPIO PRO_CPU (non-maskable) interrupt status 0x0060 RO
register
GPIO_STATUS_NEXT_REG GPIO interrupt source register 0x014C RO
A
Pin Configuration Registers
GPIO_PIN0_REG GPIO pin0 configuration register 0x0074 R/W
GPIO_PIN1_REG GPIO pin1 configuration register 0x0078 R/W
GPIO_PIN2_REG
GPIO_PIN3_REG
IN
GPIO pin2 configuration register
GPIO pin3 configuration register
0x007C
0x0080
R/W
R/W
GPIO_PIN4_REG GPIO pin4 configuration register 0x0084 R/W
GPIO_PIN5_REG GPIO pin5 configuration register 0x0088 R/W
IM
GPIO_PIN6_REG GPIO pin6 configuration register 0x008C R/W
GPIO_PIN7_REG GPIO pin7 configuration register 0x0090 R/W
GPIO_PIN8_REG GPIO pin8 configuration register 0x0094 R/W
GPIO_PIN9_REG GPIO pin9 configuration register 0x0098 R/W
GPIO_PIN10_REG GPIO pin10 configuration register 0x009C R/W
EL
GPIO_PIN11_REG GPIO pin11 configuration register 0x00A0 R/W
GPIO_PIN12_REG GPIO pin12 configuration register 0x00A4 R/W
GPIO_PIN13_REG GPIO pin13 configuration register 0x00A8 R/W
GPIO_PIN14_REG GPIO pin14 configuration register 0x00AC R/W
GPIO_PIN15_REG GPIO pin15 configuration register 0x00B0 R/W
PR
GPIO_PIN16_REG GPIO pin16 configuration register 0x00B4 R/W
GPIO_PIN17_REG GPIO pin17 configuration register 0x00B8 R/W
GPIO_PIN18_REG GPIO pin18 configuration register 0x00BC R/W
GPIO_PIN19_REG GPIO pin19 configuration register 0x00C0 R/W
GPIO_PIN20_REG GPIO pin20 configuration register 0x00C4 R/W
GPIO_PIN21_REG GPIO pin21 configuration register 0x00C8 R/W
Input Function Configuration Registers
GPIO_FUNC0_IN_SEL_CFG_REG Configuration register for input signal 0 0x0154 R/W
GPIO_FUNC1_IN_SEL_CFG_REG Configuration register for input signal 1 0x0158 R/W
... ... ... ...
GPIO_FUNC126_IN_SEL_CFG_REG Configuration register for input signal 126 0x034C R/W
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Name Description Address Access
GPIO_FUNC127_IN_SEL_CFG_REG Configuration register for input signal 127 0x0350 R/W
Output Function Configuration Registers
GPIO_FUNC0_OUT_SEL_CFG_REG Configuration register for GPIO0 output 0x0554 R/W
GPIO_FUNC1_OUT_SEL_CFG_REG Configuration register for GPIO1 output 0x0558 R/W
GPIO_FUNC2_OUT_SEL_CFG_REG Configuration register for GPIO2 output 0x055C R/W
GPIO_FUNC3_OUT_SEL_CFG_REG Configuration register for GPIO3 output 0x0560 R/W
GPIO_FUNC4_OUT_SEL_CFG_REG Configuration register for GPIO4 output 0x0564 R/W
GPIO_FUNC5_OUT_SEL_CFG_REG Configuration register for GPIO5 output 0x0568 R/W
GPIO_FUNC6_OUT_SEL_CFG_REG Configuration register for GPIO6 output 0x056C R/W
GPIO_FUNC7_OUT_SEL_CFG_REG Configuration register for GPIO7 output 0x0570 R/W
RY
GPIO_FUNC8_OUT_SEL_CFG_REG Configuration register for GPIO8 output 0x0574 R/W
GPIO_FUNC9_OUT_SEL_CFG_REG Configuration register for GPIO9 output 0x0578 R/W
GPIO_FUNC10_OUT_SEL_CFG_REG Configuration register for GPIO10 output 0x057C R/W
GPIO_FUNC11_OUT_SEL_CFG_REG Configuration register for GPIO11 output 0x0580 R/W
GPIO_FUNC12_OUT_SEL_CFG_REG Configuration register for GPIO12 output 0x0584 R/W
A
GPIO_FUNC13_OUT_SEL_CFG_REG Configuration register for GPIO13 output 0x0588 R/W
GPIO_FUNC14_OUT_SEL_CFG_REG Configuration register for GPIO14 output 0x058C R/W
GPIO_FUNC15_OUT_SEL_CFG_REG Configuration register for GPIO15 output 0x0590 R/W
GPIO_FUNC16_OUT_SEL_CFG_REG
GPIO_FUNC17_OUT_SEL_CFG_REG
IN
Configuration register for GPIO16 output
Configuration register for GPIO17 output
0x0594
0x0598
R/W
R/W
GPIO_FUNC18_OUT_SEL_CFG_REG Configuration register for GPIO18 output 0x059C R/W
GPIO_FUNC19_OUT_SEL_CFG_REG Configuration register for GPIO19 output 0x05A0 R/W
IM
GPIO_FUNC20_OUT_SEL_CFG_REG Configuration register for GPIO20 output 0x05A4 R/W
GPIO_FUNC21_OUT_SEL_CFG_REG Configuration register for GPIO21 output 0x05A8 R/W
Version Register
GPIO_DATE_REG GPIO version register 0x06FC R/W
Clock Gate Register
EL
GPIO_CLOCK_GATE_REG GPIO clock gate register 0x062C R/W
5.13.2 IO MUX Register Summary
The addresses in this section are relative to the IO MUX base address provided in Table 3-4 in Chapter 3 System
PR
and Memory.
Name Description Address Access
Configuration Registers
IO_MUX_PIN_CTRL_REG Clock output configuration Register 0x0000 R/W
IO_MUX_GPIO0_REG IO MUX configuration register for pin 0x0004 R/W
XTAL_32K_P
IO_MUX_GPIO1_REG IO MUX configuration register for pin 0x0008 R/W
XTAL_32K_N
IO_MUX_GPIO2_REG IO MUX configuration register for pin GPIO2 0x000C R/W
IO_MUX_GPIO3_REG IO MUX configuration register for pin GPIO3 0x0010 R/W
IO_MUX_GPIO4_REG IO MUX configuration register for pin MTMS 0x0014 R/W
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Name Description Address Access
IO_MUX_GPIO5_REG IO MUX configuration register for pin MTDI 0x0018 R/W
IO_MUX_GPIO6_REG IO MUX configuration register for pin MTCK 0x001C R/W
IO_MUX_GPIO7_REG IO MUX configuration register for pin MTDO 0x0020 R/W
IO_MUX_GPIO8_REG IO MUX configuration register for pin GPIO8 0x0024 R/W
IO_MUX_GPIO9_REG IO MUX configuration register for pin GPIO9 0x0028 R/W
IO_MUX_GPIO10_REG IO MUX configuration register for pin GPIO10 0x002C R/W
IO_MUX_GPIO11_REG IO MUX configuration register for pin VDD_SPI 0x0030 R/W
IO_MUX_GPIO12_REG IO MUX configuration register for pin SPIHD 0x0034 R/W
IO_MUX_GPIO13_REG IO MUX configuration register for pin SPIWP 0x0038 R/W
IO_MUX_GPIO14_REG IO MUX configuration register for pin SPICS0 0x003C R/W
RY
IO_MUX_GPIO15_REG IO MUX configuration register for pin SPICLK 0x0040 R/W
IO_MUX_GPIO16_REG IO MUX configuration register for pin SPID 0x0044 R/W
IO_MUX_GPIO17_REG IO MUX configuration register for pin SPIQ 0x0048 R/W
IO_MUX_GPIO18_REG IO MUX configuration register for pin GPIO18 0x004C R/W
IO_MUX_GPIO19_REG IO MUX configuration register for pin GPIO19 0x0050 R/W
A
IO_MUX_GPIO20_REG IO MUX configuration register for pin U0RXD 0x0054 R/W
IO_MUX_GPIO21_REG IO MUX configuration register for pin U0TXD 0x0058 R/W
Version Register
IO_MUX_DATE_REG
IN
IO MUX Version Control Register 0x00FC R/W
5.13.3 SDM Register Summary
IM
The addresses in this section are relative to (GPIO base address provided in Table 3-4 in Chapter 3 System and
Memory + 0x0F00).
Name Description Address Access
Configuration registers
EL
GPIOSD_SIGMADELTA0_REG Duty Cycle Configuration Register of SDM0 0x0000 R/W
GPIOSD_SIGMADELTA1_REG Duty Cycle Configuration Register of SDM1 0x0004 R/W
GPIOSD_SIGMADELTA2_REG Duty Cycle Configuration Register of SDM2 0x0008 R/W
GPIOSD_SIGMADELTA3_REG Duty Cycle Configuration Register of SDM3 0x000C R/W
GPIOSD_SIGMADELTA_CG_REG Clock Gating Configuration Register 0x0020 R/W
PR
GPIOSD_SIGMADELTA_MISC_REG MISC Register 0x0024 R/W
Version register
GPIOSD_SIGMADELTA_VERSION_REG Version Control Register 0x0028 R/W
5.14 Registers
5.14.1 GPIO Matrix Registers
The addresses in this section are relative to the GPIO base address provided in Table 3-4 in Chapter 3 System
and Memory.
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Register 5.1. GPIO_BT_SELECT_REG (0x0000)
L
SE
T_
_B
O
PI
G
31 0
0x000000 Reset
GPIO_BT_SEL Reserved (R/W)
Register 5.2. GPIO_OUT_REG (0x0004)
RY
G
RI
O
A_
AT
_D
UT
)
ed
_O
rv
O
se
PI
(re
A
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_OUT_DATA_ORIG GPIO0 ~ 21 output value in simple GPIO output mode. The values of bit0 ~
IN
bit21 correspond to the output value of GPIO0 ~ GPIO21 respectively, and bit22 ~ bit25 are invalid.
(R/W/SS)
IM
Register 5.3. GPIO_OUT_W1TS_REG (0x0008)
S
1T
_W
UT
)
ed
_O
rv
EL
O
se
PI
(re
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_OUT_W1TS GPIO0 ~ 21 output set register. Bit0 ~ bit21 are corresponding to GPIO0
~ 21, and bit22 ~ bit25 are invalid. If the value 1 is written to a bit here, the correspond-
PR
ing bit in GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set
GPIO_OUT_REG. (WT)
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Register 5.4. GPIO_OUT_W1TC_REG (0x000C)
C
1T
W_
UT
)
ed
_O
v
er
O
s
PI
(re
G
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_OUT_W1TC GPIO0 ~ 21 output clear register. Bit0 ~ bit21 are corresponding to GPIO0
~ 21, and bit22 ~ bit25 are invalid. If the value 1 is written to a bit here, the correspond-
ing bit in GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear
RY
GPIO_OUT_REG. (WT)
Register 5.5. GPIO_ENABLE_REG (0x0020)
TA
DA
A E_
BL
NA
d)
_E
e
rv
O
se
PI
(re
31
0 0 0 0 0
26
0
25
IN 0x00000
0
Reset
GPIO_ENABLE_DATA GPIO output enable register for GPIO0 ~ 21. Bit0 ~ bit21 are corresponding
to GPIO0 ~ 21, and bit22 ~ bit25 are invalid. (R/W/SS)
IM
Register 5.6. GPIO_ENABLE_W1TS_REG (0x0024)
EL
S
1T
W
E_
BL
NA
d)
_E
rve
O
se
PI
(re
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
PR
GPIO_ENABLE_W1TS GPIO0 ~ 21 output enable set register. Bit0 ~ bit21 are corresponding to
GPIO0 ~ 21, and bit22 ~ bit25 are invalid. If the value 1 is written to a bit here, the corresponding
bit in GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set
GPIO_ENABLE_REG. (WT)
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Register 5.7. GPIO_ENABLE_W1TC_REG (0x0028)
C
1T
_W
E
BL
NA
d)
_E
ve
er
O
s
PI
(re
G
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_ENABLE_W1TC GPIO0 ~ 21 output enable clear register. Bit0 ~ bit21 are corresponding to
GPIO0 ~ 21, and bit22 ~ bit25 are invalid. If the value 1 is written to a bit here, the corresponding
bit in GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear
RY
GPIO_ENABLE_REG. (WT)
Register 5.8. GPIO_STRAP_REG (0x0038)
A AP
TR
PI
NG
d)
_S
e
rv
O
se
PI
(re
G
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN
16
0
15
0x00
0
Reset
GPIO_STRAPPING GPIO strapping values. (RO)
IM
• bit 0: GPIO2
• bit 2: GPIO8
• bit 3: GPIO9
EL
Register 5.9. GPIO_IN_REG (0x003C)
XT
NE
_
TA
PR
DA
N_
d)
ve
_I
r
O
se
PI
(re
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_IN_DATA_NEXT GPIO0 ~ 21 input value. Bit0 ~ bit21 are corresponding to GPIO0 ~ 21, and
bit22 ~ bit25 are invalid. Each bit represents a pin input value, 1 for high level and 0 for low level.
(RO)
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Register 5.10. GPIO_STATUS_REG (0x0044)
T
UP
RR
TE
IN
S_
TU
TA
)
ed
_S
rv
O
se
PI
(re
G
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_STATUS_INTERRUPT GPIO0 ~ 21 interrupt status register. Bit0 ~ bit21 are corresponding to
GPIO0 ~ 21, and bit22 ~ bit25 are invalid. (R/W/SS)
RY
Register 5.11. GPIO_STATUS_W1TS_REG (0x0048)
S
1T
W
S_
A
TU
TA
d)
_S
e
rv
O
se
PI
(re
31 26 25
0 0 0 0 0 0
IN 0x00000
0
Reset
GPIO_STATUS_W1TS GPIO0 ~ 21 interrupt status set register. Bit0 ~ bit21 are corresponding to
GPIO0 ~ 21, and bit22 ~ bit25 are invalid. If the value 1 is written to a bit here, the corresponding
IM
bit in GPIO_STATUS_INTERRUPT will be set to 1. Recommended operation: use this register to
set GPIO_STATUS_INTERRUPT. (WT)
EL
Register 5.12. GPIO_STATUS_W1TC_REG (0x004C)
C
1T
_W
T US
TA
d)
_S
e
rv
O
se
PI
(re
G
PR
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_STATUS_W1TC GPIO0 ~ 21 interrupt status clear register. Bit0 ~ bit21 are corresponding to
GPIO0 ~ 21, and bit22 ~ bit25 are invalid. If the value 1 is written to a bit here, the corresponding
bit in GPIO_STATUS_INTERRUPT will be cleared. Recommended operation: use this register to
clear GPIO_STATUS_INTERRUPT. (WT)
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5 IO MUX and GPIO Matrix (GPIO, IO MUX)
Register 5.13. GPIO_PCPU_INT_REG (0x005C)
T
IN
U_
CP
RO
)
ed
_P
rv
O
se
PI
(re
G
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_PROCPU_INT GPIO0 ~ 21 PRO_CPU interrupt status. Bit0 ~ bit21 are corresponding to
GPIO0 ~ 21, and bit22 ~ bit25 are invalid. This interrupt status is corresponding to the bit in
GPIO_STATUS_REG when assert (high) enable signal (bit13 of GPIO_PINn_REG). (RO)
RY
Register 5.14. GPIO_PCPU_NMI_INT_REG (0x0060)
T
IN
I_
NM
A U_
CP
O
d)
R
_P
e
rv
O
se
PI
(re
31
0 0 0 0 0
26
0
25
IN 0x00000
0
Reset
GPIO_PROCPU_NMI_INT GPIO0 ~ 21 PRO_CPU non-maskable interrupt status. Bit0 ~ bit21 are
corresponding to GPIO0 ~ 21, and bit22 ~ bit25 are invalid. This interrupt status is corresponding
IM
to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG). (RO)
EL
PR
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Register 5.15. GPIO_PINn_REG (n: 021) (0x0074+4*n)
LE
SS
AB
_D PAS
PA
EN
NC ER
_P PAD BY
BY
P_
SY RIV
PE
NA
PI Nn_ C1_
2_
IG
EU
TY
NF
_E
AK
T_
_P SYN
NT
IN
W
_C
I
n_
n_
n_
PI Nn_
n_
n
IN
IN
IN
IN
IN
d)
)
ed
I
_P
_P
_P
_P
_P
ve
rv
er
O
se
s
PI
PI
PI
PI
PI
(re
(re
G
G
31 18 17 13 12 11 10 9 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0 0x0 0 0 0x0 0 0x0 Reset
GPIO_PINn_SYNC2_BYPASS For the second stage synchronization, GPIO input data can be syn-
RY
chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge;
2 and 3: synchronized on rising edge. (R/W)
GPIO_PINn_PAD_DRIVER pin drive selection. 0: normal output; 1: open drain output. (R/W)
GPIO_PINn_SYNC1_BYPASS For the first stage synchronization, GPIO input data can be synchro-
nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2
A
and 3: synchronized on rising edge. (R/W)
GPIO_PINn_INT_TYPE Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2:
IN
falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)
GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable bit, only wakes up the CPU from Light-sleep.
(R/W)
GPIO_PINn_CONFIG reserved (R/W)
IM
GPIO_PINn_INT_ENA Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable
interrupt enabled. (R/W)
EL
Register 5.16. GPIO_STATUS_NEXT_REG (0x014C)
XT
NE
T_
P
RU
ER
PR
NT
_I
T US
TA
)
ed
_S
rv
O
se
PI
(re
31 26 25 0
0 0 0 0 0 0 0x00000 Reset
GPIO_STATUS_INTERRUPT_NEXT Interrupt source signal of GPIO0 ~ 21, could be rising edge in-
terrupt, falling edge interrupt, level sensitive interrupt and any edge interrupt. Bit0 ~ bit21 are
corresponding to GPIO0 ~ 21, and bit22 ~ bit25 are invalid. (RO)
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Register 5.17. GPIO_FUNCn_IN_SEL_CFG_REG (n: 0127) (0x0154+4*n)
L
SE
V_
L
SE
IN
_I L
Cn SE
N_
N_
UN N_
_I
Cn
_F _I
O n
UN
PI SIG
)
ed
_F
rv
_
O
O
se
PI
PI
(re
G
G
G
31 7 6 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
GPIO_FUNCn_IN_SEL Selection control for peripheral input signal n, selects a pin from the 22 GPIO
matrix pins to connect this input signal. Or selects 0x1e for a constantly high input or 0x1f for a
RY
constantly low input. (R/W)
GPIO_FUNCn_IN_INV_SEL Invert the input value. 1: invert enabled; 0: invert disabled. (R/W)
GPIO_SIGn_IN_SEL Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals di-
rectly to peripheral configured in IO MUX. (R/W)
A
Register 5.18. GPIO_FUNCn_OUT_SEL_CFG_REG (n: 021) (0x0554+4*n)
IN
UT EL EL
EL
_O _S _S
_S
EL
Cn EN INV
NV
_S
_I
UN _O _
_F Cn EN
UT
O N O
_O
PI U _
G _F Cn
Cn
O N
UN
)
PI U
d
IM ve
G _F
_F
er
O
s
PI
PI
(re
G
31 11 10 9 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80 Reset
GPIO_FUNCn_OUT_SEL Selection control for GPIO output n. If a value Y (0<=Y<128) is written to
EL
this field, the peripheral output signal Y will be connected to GPIO output n. If a value 128 is written
to this field, bit n of GPIO_OUT_REG and GPIO_ENABLE_REG will be selected as the output value
and output enable. (R/W)
GPIO_FUNCn_OUT_INV_SEL 0: Do not invert the output value; 1: Invert the output value. (R/W)
PR
GPIO_FUNCn_OEN_SEL 0: Use output enable signal from peripheral; 1: Force the output enable
signal to be sourced from bit n of GPIO_ENABLE_REG. (R/W)
GPIO_FUNCn_OEN_INV_SEL 0: Do not invert the output enable signal; 1: Invert the output enable
signal. (R/W)
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Register 5.19. GPIO_CLOCK_GATE_REG (0x062C)
N
_E
LK
d)
_C
ve
r
O
se
PI
(re
G
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
GPIO_CLK_EN Clock gating enable bit. If set to 1, the clock is free running. (R/W)
Register 5.20. GPIO_DATE_REG (0x06FC)
RY
G
E
E _R
AT
)
ed
_D
rv
O
se
PI
(re
G
31 28 27 0
A
0 0 0 0 0x2006130 Reset
GPIO_DATE_REG Version control register (R/W) IN
5.14.2 IO MUX Registers
The addresses in this section are relative to the IO MUX base address provided in Table 3-4 in Chapter 3 System
IM
and Memory.
Register 5.21. IO_MUX_PIN_CTRL_REG (0x0000)
3
1
UT
UT
UT
_O
_O
_O
EL
LK
LK
LK
_C
_C
_C
d)
UX
UX
UX
e
rv
_M
_M
_M
se
(re
IO
IO
IO
31 12 11 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7 0xf 0xf Reset
PR
IO_MUX_CLK_OUTx If you want to output clock for I2S to CLK_OUT_outx, set IO_MUX_CLK_OUTx
to 0x0. CLK_OUT_outx can be found in Table 5-1. (R/W)
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Register 5.22. IO_MUX_GPIOn_REG (n: 021) (0x0004+4*n)
PI _S _W U
n_ _ D
N
N_ PU
PD
EL
RV
_G On CU P
O LP P
_E
CU L
E
UX PI _M _W
IO UX PI _M _IE
M SE
_O
_S
FU W
W
PI _F _IE
_D
ER
n_ _
U
_M _G On CU
_M _G On CU
UN
(re X_G IOn UN
O UN
LT
C
_M
IO UX PI _M
FI
_M _G n_F
U P F
n_
_
n
_M _G O n
_M _G O n
O
O
PI
PI
IO UX PI
IO UX PI
_M GP
G
_G
_M _G
d)
)
_
ed
UX
UX
UX
IO UX
IO UX
ve
rv
er
_M
_M
_M
_M
se
s
(re
IO
IO
IO
IO
IO
31 16 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x2 1 1 0 0 0 0 0 0 0 0 Reset
IO_MUX_GPIOn_MCU_OE Output enable of the pin in sleep mode. 1: output enabled; 0: output
disabled. (R/W)
RY
IO_MUX_GPIOn_SLP_SEL Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.
(R/W)
IO_MUX_GPIOn_MCU_WPD Pull-down enable of the pin in sleep mode. 1: internal pull-down en-
abled; 0: internal pull-down disabled. (R/W)
A
IO_MUX_GPIOn_MCU_WPU Pull-up enable of the pin during sleep mode. 1: internal pull-up en-
abled; 0: internal pull-up disabled. (R/W) IN
IO_MUX_GPIOn_MCU_IE Input enable of the pin during sleep mode. 1: input enabled; 0: input
disabled. (R/W)
IO_MUX_GPIOn_FUN_WPD Pull-down enable of the pin. 1: internal pull-down enabled; 0: internal
pull-down disabled. (R/W)
IM
IO_MUX_GPIOn_FUN_WPU Pull-up enable of the pin. 1: internal pull-up enabled; 0: internal pull-up
disabled. (R/W)
IO_MUX_GPIOn_FUN_IE Input enable of the pin. 1: input enabled; 0: input disabled. (R/W)
EL
IO_MUX_GPIOn_FUN_DRV Select the drive strength of the pin. 0: ~5 mA; 1: ~ 10 mA; 2: ~ 20 mA;
3: ~40mA. (R/W)
IO_MUX_GPIOn_MCU_SEL Select IO MUX function for this signal. 0: Select Function 0; 1: Select
Function 1; etc. (R/W)
IO_MUX_GPIOn_FILTER_EN Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
PR
(R/W)
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Register 5.23. IO_MUX_DATE_REG (0x00FC)
EG
_R
E
AT
_D
)
ed
UX
rv
_M
se
(re
IO
31 28 27 0
0 0 0 0 0x2006050 Reset
IO_MUX_DATE_REG Version control register (R/W)
RY
5.14.3 SDM Output Registers
The addresses in this section are relative to (GPIO base address provided in Table 3-4 in Chapter 3 System and
Memory + 0x0F00).
Register 5.24. GPIOSD_SIGMADELTAn_REG (n: 03) (0x0000+4*n)
A R ES
CA
LE
IN
_P
n_
IN Dn
D
_S
_S
)
ed
SD
SD
rv
O
se
PI
PI
(re
G
31 16 15 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xff 0x0 Reset
IM
GPIOSD_SDn_IN This field is used to configure the duty cycle of sigma delta modulation output.
(R/W)
GPIOSD_SDn_PRESCALE This field is used to set a divider value to divide APB clock. (R/W)
EL
Register 5.25. GPIOSD_SIGMADELTA_CG_REG (0x0020)
N
_E
LK
_C
PR
d)
SD
e
rv
O
se
PI
(re
G
31 30 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIOSD_CLK_EN Clock enable bit of configuration registers for sigma delta modulation. (R/W)
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Register 5.26. GPIOSD_SIGMADELTA_MISC_REG (0x0024)
EN
K_
CL
N_
CT P
IO
UN A
_F _SW
SD PI
O S
)
PI D_
ed
S
rv
O
se
PI
(re
G
G
31 30 29 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIOSD_FUNCTION_CLK_EN Clock enable bit of sigma delta modulation. (R/W)
RY
GPIOSD_SPI_SWAP Reserved. (R/W)
Register 5.27. GPIOSD_SIGMADELTA_VERSION_REG (0x0028)
A
AT
_D
)
ed
SD
rv
O
se
PI
(re
31 28 27 0
0 0 0 0
IN 0x2006230 Reset
GPIOSD_DATE Version Control Register. (R/W)
IM
EL
PR
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6 Reset and Clock
6.1 Reset
6.1.1 Overview
ESP32-C3 provides four types of reset that occur at different levels, namely CPU Reset, Core Reset, System
Reset, and Chip Reset. All reset types mentioned above (except Chip Reset) maintain the data stored in internal
memory. Figure 6-1 shows the scope of affected subsystems by each type of reset.
6.1.2 Architectural Overview
A RY
IN
IM
EL
Figure 61. Reset Types
6.1.3 Features
PR
• Support four reset levels:
– CPU Reset: Only resets CPU core. Once such reset is triggered, the instructions from the CPU reset
vector will be executed.
– Core Reset: Resets the whole digital system except RTC, including CPU, peripherals, Wi-Fi,
Bluetooth® LE, and digital GPIOs.
– System Reset: Resets the whole digital system, including RTC.
– Chip Reset: Resets the whole chip.
• Support software reset and hardware reset:
– Software Reset: the CPU can trigger a software reset by configuring the corresponding registers.
– Hardware Reset: Hardware reset is directly triggered by the circuit.
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Note:
If CPU is reset, SENSITIVE registers will be reset, too.
6.1.4 Functional Description
CPU will be reset immediately when any of the reset above occurs. Users can get reset source codes by reading
register RTC_CNTL_RESET_CAUSE_PROCPU after the reset is released.
Table 6-1 lists possible reset sources and the types of reset they trigger.
Table 61. Reset Sources
Code Source Reset Type Comments
RY
1
0x01 Chip reset Chip Reset -
Chip Reset or
0x0F Brown-out system reset Triggered by brown-out detector2
System Reset
0x10 RWDT system reset System Reset See Chapter 11 Watchdog Timers (WDT)
0x12 Super Watchdog reset System Reset See Chapter 11 Watchdog Timers (WDT)
0x13 CLK GLITCH reset System Reset See Chapter 20 Clock Glitch Detection
A
0x03 Software system reset Core Reset Triggered by configuring RTC_CNTL_SW_SYS_RST
See Chapter 4 Low-Power Management (RTC_CNTL) [to be
0x05 Deep-sleep reset Core Reset
0x07 MWDT0 core reset Core Reset
IN
added later]
See Chapter 11 Watchdog Timers (WDT)
0x08 MWDT1 core reset Core Reset See Chapter 11 Watchdog Timers (WDT)
0x09 RWDT core reset Core Reset See Chapter 11 Watchdog Timers (WDT)
IM
0x14 eFuse reset Core Reset Triggered by eFuse CRC error
Triggered when external USB host sends a specific command
0x15 USB (UART) reset Core Reset to the Serial interface of USB-Serial-JTAG. See 24 USB Se-
rial/JTAG Controller (USB_SERIAL_JTAG)
Triggered when external USB host sends a specific command
EL
0x16 USB (JTAG) reset Core Reset to the JTAG interface of USB-Serial-JTAG. See 24 USB Se-
rial/JTAG Controller (USB_SERIAL_JTAG)
0x17 Power glitch reset Core Reset Triggered by power glitch
0x0B MWDT0 CPU reset CPU Reset See Chapter 11 Watchdog Timers (WDT)
0x0C Software CPU reset CPU Reset Triggered by configuring RTC_CNTL_SW_PROCPU_RST
PR
0x0D RWDT CPU reset CPU Reset See Chapter 11 Watchdog Timers (WDT)
0x11 MWDT1 CPU reset CPU Reset See Chapter 11 Watchdog Timers (WDT)
1
Chip Reset can be triggered by the following two sources:
• Triggered by chip power-on.
• Triggered by brown-out detector.
2
Once brown-out status is detected, the detector will trigger System Reset or Chip Reset, depending on register
configuration. See Chapter 4 Low-Power Management (RTC_CNTL) [to be added later].
6.2 Clock
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6.2.1 Overview
ESP32-C3 clocks are mainly sourced from oscillator (OSC), RC, and PLL circuit, and then processed by the
dividers or selectors, which allows most functional modules to select their working clock according to their power
consumption and performance requirements. Figure 6-2 shows the system clock structure.
6.2.2 Architectural Overview
A RY
IN
IM
EL
Figure 62. System Clock
PR
6.2.3 Features
ESP32-C3 clocks can be classified in two types depending on their frequencies:
• High speed clocks for devices working at a higher frequency, such as CPU and digital peripherals
– PLL_CLK (320 MHz or 480 MHz): internal PLL clock
– XTAL_CLK (40 MHz): external crystal clock
• Slow speed clocks for low-power devices, such as RTC module and low-power peripherals
– XTAL32K_CLK (32 kHz): external crystal clock
– FOSC_CLK (17.5 MHz by default): internal fast RC oscillator with adjustable frequency
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– FOSC_DIV_CLK: internal fast RC oscillator derived from FOSC_CLK divided by 256
– RTC_CLK (136 kHz by default): internal low RC oscillator with adjustable frequency
6.2.4 Functional Description
6.2.4.1 CPU Clock
As Figure 6-2 shows, CPU_CLK is the master clock for CPU and it can be as high as 160 MHz when CPU works
in high performance mode. Alternatively, CPU can run at lower frequencies, such as at 2 MHz, to lower power
consumption. Users can set PLL_CLK, FOSC_CLK or XTAL_CLK as CPU_CLK clock source by configuring
register SYSTEM_SOC_CLK_SEL, see Table 6-2 and Table 6-3. By default, the CPU clock is sourced from
RY
XTAL_CLK with a divider of 2, i.e. the CPU clock is 20 MHz.
Table 62. CPU_CLK Clock Source
SYSTEM_SOC_CLK_SEL Value CPU Clock Source
0 XTAL_CLK
1 PLL_CLK
A
2 FOSC_CLK
IN
Table 63. CPU Clock Frequency
CPU Clock Source SEL_0* SEL_1* SEL_2* CPU Clock Frequency
CPU_CLK = XTAL_CLK/(SYSTEM_PRE_DIV_CNT + 1)
XTAL_CLK 0 - -
SYSTEM_PRE_DIV_CNT ranges from 0 ~ 1023. Default is 1
IM
CPU_CLK = PLL_CLK/6
PLL_CLK (480 MHz) 1 1 0
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK/3
PLL_CLK (480 MHz) 1 1 1
CPU_CLK frequency is 160 MHz
EL
CPU_CLK = PLL_CLK/4
PLL_CLK (320 MHz) 1 0 0
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK/2
PLL_CLK (320 MHz) 1 0 1
CPU_CLK frequency is 160 MHz
CPU_CLK = FOSC_CLK/(SYSTEM_PRE_DIV_CNT + 1)
FOSC_CLK 2 - -
PR
SYSTEM_PRE_DIV_CNT ranges from 0 ~ 1023. Default is 1
*
The value of register SYSTEM_SOC_CLK_SEL.
*
The value of register SYSTEM_PLL_FREQ_SEL.
*
The value of register SYSTEM_CPUPERIOD_SEL.
6.2.4.2 Peripheral Clock
Peripheral clocks include APB_CLK, CRYPTO_CLK, PLL_160M_CLK, LEDC_SCLK, XTAL_CLK, and
FOSC_CLK. Table 6-4 shows which clock can be used by each peripheral.
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Table 64. Peripheral Clocks
Peripheral XTAL_CLK APB_CLK PLL_160M_CLK (RTC) FAST_CLK FOSC_CLK CRYPTO_CLK LEDC_SCLK
PR
TIMG Y Y
I2S Y Y
UHCI Y
UART Y Y Y
RMT Y Y Y
I2C Y Y
EL
SPI Y Y
eFuse Controller Y
SARADC Y
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Temperature Y Y
Sensor
IM
USB Y
176
CRYPTO Y
TWAI Controller Y
LEDC Y Y Y Y Y
SYS_TIMER Y Y
IN
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6 Reset and Clock
APB_CLK
The frequency of APB_CLK is determined by the clock source of CPU_CLK as shown in Table 6-5.
Table 65. APB_CLK Clock Frequency
CPU_CLK Source APB_CLK Frequency
PLL_CLK 80 MHz
XTAL_CLK CPU_CLK
FOSC_CLK CPU_CLK
CRYPTO_CLK
RY
The frequency of CRYPTO_CLK is determined by the CPU_CLK source, as shown in Table 6-6.
Table 66. CRYPTO_CLK Frequency
CPU_CLK Source CRYPTO_CLK Frequency
PLL_CLK 160 MHz
A
XTAL_CLK CPU_CLK
FOSC_CLK IN CPU_CLK
PLL_160M_CLK
PLL_160M_CLK is divided from PLL_CLK according to current PLL frequency.
LEDC_SCLK
IM
LEDC module uses FOSC_CLK as clock source when APB_CLK is disabled. In other words, when the system is
in low-power mode, most peripherals will be halted (as APB_CLK is turned off), but LEDC can still work normally
via FOSC_CLK.
EL
6.2.4.3 WiFi and Bluetooth® LE Clock
Wi-Fi and Bluetooth LE can only work when CPU_CLK uses PLL_CLK as its clock source. Suspending PLL_CLK
requires that Wi-Fi and Bluetooth LE have entered low-power mode first.
LOW_POWER_CLK uses XTAL32K_CLK, XTAL_CLK, FOSC_CLK or SLOW_CLK (the low clock selected by
PR
RTC) as its clock source for Wi-Fi and Bluetooth LE in low-power mode.
6.2.4.4 RTC Clock
The clock sources for SLOW_CLK and FAST_CLK are low-frequency clocks. RTC module can operate when
most other clocks are stopped. SLOW_CLK derived from RTC_CLK, XTAL32K_CLK or FOSC_DIV_CLK is used
to clock Power Management module. FAST_CLK is used to clock On-chip Sensor module. It can be sourced
from a divided XTAL_CLK or from a divided FOSC_CLK.
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7 Chip Boot Control
7.1 Overview
ESP32-C3 has three strapping pins:
• GPIO2
• GPIO8
• GPIO9
These strapping pins are used to control the following functions during chip power-on or hardware reset:
RY
• control chip boot mode
• enable or disable ROM code printing to UART
During system reset triggered by power-on, brown-out or by analog super watchdog (see Chapter 6 Reset and
Clock), hardware captures samples and stores the voltage level of strapping pins as strapping bit of “0” or “1” in
latches, and holds these bits until the chip is powered down or shut down. Software can read the latch status
A
(strapping value) from the register GPIO_STRAPPING.
By default, GPIO9 is connected to the chip’s internal pull-up resistor. If GPIO9 is not connected or connected to
IN
an external high-impedance circuit, the internal weak pull-up determines the default input level of this strapping
pin (see Table 7-1).
Table 71. Default Configuration of Strapping Pins
IM
Strapping Pin Defualt Configuration
GPIO2 N/A
GPIO8 N/A
GPIO9 Pull-up
EL
To change the strapping bit values, users can apply external pull-down/pull-up resistors, or use host MCU GPIOs
to control the voltage level of these pins when powering on ESP32-C3. After the reset is released, the strapping
pins work as normal-function pins.
Note:
PR
The following section provides description of the chip functions and the pattern of the strapping pins values to invoke
each function. Only documented patterns should be used. If some pattern is not documented, it may trigger unexpected
behavior.
7.2 Boot Mode Control
GPIO2, GPIO8, and GPIO9 control the boot mode after the reset is released.
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Table 72. Boot Mode Control
Boot Mode GPIO2 GPIO8 GPIO9
SPI Boot 1 x 1
Download Boot 1 1 0
Table 7-2 shows the strapping pin values of GPIO2, GPIO8 and GPIO9, and the associated boot modes. “x”
means that this value is ignored.
In SPI Boot mode, the CPU boots the system by reading the program stored in SPI flash. SPI Boot mode can be
further classified as follows:
RY
• Normal Flash Boot: supports Security Boot and programs run in RAM.
• Direct Boot: does not support Security Boot and programs run directly in flash. To enable this mode, make
sure that the first two words of the bin file downloading to flash (address: 0x42000000) are 0xaebd041d.
In Download Boot mode, users can download code to flash using UART0 or USB interface. It is also possible to
load a program into SRAM and execute it in this mode.
A
The following eFuses control boot mode behaviors:
• EFUSE_DIS_FORCE_DOWNLOAD
IN
If this eFuse is 0 (default), software can force switch the chip from SPI Boot mode to Download Boot mode
by setting register RTC_CNTL_FORCE_DOWNLOAD_BOOT and triggering a CPU reset. If this eFuse is 1,
RTC_CNTL_FORCE_DOWNLOAD_BOOT is disabled.
• EFUSE_DIS_DOWNLOAD_MODE
IM
If this eFuse is 1, Download Boot mode is disabled.
• EFUSE_ENABLE_SECURITY_DOWNLOAD
If this eFuse is 1, Download Boot mode only allows reading, writing, and erasing plaintext flash and does
EL
not support any SRAM or register operations. Ignore this eFuse if Download Boot mode is disabled.
USB Serial/JTAG Controller can also force the chip into Download Boot mode from SPI Boot mode, as well as
force the chip into SPI Boot mode from Download Boot mode. For detailed information, please refer to Chapter
24 USB Serial/JTAG Controller (USB_SERIAL_JTAG).
PR
7.3 ROM Code Printing Control
GPIO8 controls ROM code printing of information during the early boot process. This GPIO is used together with
EFUSE_UART_PRINT_CONTROL.
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7 Chip Boot Control
Table 73. ROM Code Printing Control
eFuse1 GPIO8 ROM Code Printing
ROM code is always printed to UART during boot.
0 x
The value of GPIO8 is ignored.
0 Print is enabled during boot.
1
1 Print is disabled during boot.
0 Print is disabled during boot.
2
1 Print is enabled during boot.
Print is always disabled during boot. The value of GPIO8 is
3 x
ignored.
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1
eFuse: EFUSE_UART_PRINT_CONTROL
ROM code will print to pin U0TXD (default) or to USB Serial/JTAG Controller during power-on, depending on the
eFuse bit EFUSE_USB_PRINT_CHANNEL (0: USB; 1: UART). Note that if this eFuse bit is set to 0, i.e., USB is
selected, but USB Serial/JTAG Controller is disabled, then ROM code will not print.
A
IN
IM
EL
PR
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8 Interrupt Matrix (INTMTRX)
8 Interrupt Matrix (INTMTRX)
8.1 Overview
The interrupt matrix embedded in ESP32-C3 independently routes peripheral interrupt sources to the
ESP-RISC-V CPU’s peripheral interrupts, to timely inform CPU to process the coming interrupts.
The ESP32-C3 has 62 peripheral interrupt sources. To map them to 31 CPU interrupts, this interrupt matrix is
needed.
Note:
This chapter focuses on how to map peripheral interrupt sources to CPU interrupts. For more details about interrupt
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configuration, vector, and ISA suggested operations, please refer to Chapter 1 ESP-RISC-V CPU.
8.2 Features
• Accept 62 peripheral interrupt sources as input
A
• Generate 31 CPU peripheral interrupts to CPU as output
• Query current interrupt status of peripheral interrupt sources
IN
• Configure priority, type, threshold, and enable signal of CPU interrupts
Figure 8-1 shows the structure of the interrupt matrix.
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EL
PR
Figure 81. Interrupt Matrix Structure
8.3 Functional Description
8.3.1 Peripheral Interrupt Sources
The ESP32-C3 has 62 peripheral interrupt sources in total. Table 8-1 lists all these sources and their
configuration/status registers.
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8 Interrupt Matrix (INTMTRX)
• Column “No.”: Peripheral interrupt source number, can be 0 ~ 61.
• Column “Source”: Name of the peripheral interrupt source.
• Column “Configuration Register”: Registers used for routing the peripheral interrupt sources to CPU
peripheral interrupts
• Column “Status Register”: Registers used for indicating the interrupt status of peripheral interrupt sources.
– Column “Status Register - Bit”: Bit position in status register, indicating the interrupt status.
– Column “Status Register - Name”: Name of status registers.
A RY
IN
IM
EL
PR
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8 Interrupt Matrix (INTMTRX)
Table 81. CPU Peripheral Interrupt Configuration/Status Registers and Peripheral Interrupt Sources
Status Register
No. Source Configuration Register
Bit Name
PR
0 reserved reserved 0
1 reserved reserved 1
2 PWR_INTR INTERRUPT_CORE0_PWR_INTR_MAP_REG 2
3 reserved reserved 3
4 reserved reserved 4
5 reserved reserved 5
6 reserved reserved 6
EL
7 reserved reserved 7
8 reserved reserved 8
9 reserved reserved 9
10 reserved reserved 10
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11 I2C_MST_INT INTERRUPT_CORE0_I2C_MST_INT_MAP_REG 11
12 SLC0_INTR INTERRUPT_CORE0_SLC0_INTR_MAP_REG 12
13 SLC1_INTR INTERRUPT_CORE0_SLC1_INTR_MAP_REG 13
IM
14 APB_CTRL_INTR INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG 14
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15 UHCI0_INTR INTERRUPT_CORE0_UHCI0_INTR_MAP_REG 15
INTERRUPT_CORE0_INTR_STATUS_0_REG
16 GPIO_INTERRUPT_PRO INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG 16
17 GPIO_INTERRUPT_PRO_NMI INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG 17
18 SPI_INTR_1 INTERRUPT_CORE0_SPI_INTR_1_MAP_REG 18
19 SPI_INTR_2 INTERRUPT_CORE0_SPI_INTR_2_MAP_REG 19
IN
20 I2S1_INT INTERRUPT_CORE0_I2S1_INT_MAP_REG 20
21 UART_INTR INTERRUPT_CORE0_UART_INTR_MAP_REG 21
22 UART1_INTR INTERRUPT_CORE0_UART1_INTR_MAP_REG 22
23 LEDC_INT INTERRUPT_CORE0_LEDC_INT_MAP_REG 23
ESP32-C3 TRM (Pre-release v0.4)
24 EFUSE_INT INTERRUPT_CORE0_EFUSE_INT_MAP_REG 24
A
25 CAN_INT INTERRUPT_CORE0_CAN_INT_MAP_REG 25
26 USB_INTR INTERRUPT_CORE0_USB_INTR_MAP_REG 26
27 RTC_CORE_INTR INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG 27
28 RMT_INTR INTERRUPT_CORE0_RMT_INTR_MAP_REG 28
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29 I2C_EXT0_INTR INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG 29
30 TIMER_INT1 INTERRUPT_CORE0_TIMER_INT1_MAP_REG 30
31 TIMER_INT2 INTERRUPT_CORE0_TIMER_INT2_MAP_REG 31
Espressif Systems
8 Interrupt Matrix (INTMTRX)
Status Register
No. Source Configuration Register
Bit Name
32 TG_T0_INT INTERRUPT_CORE0_TG_T0_INT_MAP_REG 0
33 TG_WDT_INT INTERRUPT_CORE0_TG_WDT_INT_MAP_REG 1
PR
34 TG1_T0_INT INTERRUPT_CORE0_TG1_T0_INT_MAP_REG 2
35 TG1_WDT_INT INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG 3
36 CACHE_IA_INT INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG 4
37 SYSTIMER_TARGET0_INT INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG 5
38 SYSTIMER_TARGET1_INT INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG 6
39 SYSTIMER_TARGET2_INT INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG 7
40 SPI_MEM_REJECT_INTR INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG 8
EL
41 ICACHE_PRELOAD_INT INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG 9
42 ICACHE_SYNC_INT INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG 10
43 APB_ADC_INT INTERRUPT_CORE0_APB_ADC_INT_MAP_REG 11
44 DMA_CH0_INT INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG 12
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45 DMA_CH1_INT INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG 13
46 DMA_CH2_INT INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG 14
INTERRUPT_CORE0_INTR_STATUS_1_REG
47 RSA_INTR INTERRUPT_CORE0_RSA_INTR_MAP_REG 15
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48 AES_INTR INTERRUPT_CORE0_AES_INTR_MAP_REG 16
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49 SHA_INTR INTERRUPT_CORE0_SHA_INTR_MAP_REG 17
50 CPU_INTR_FROM_CPU_0 INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG 18
51 CPU_INTR_FROM_CPU_1 INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG 19
52 CPU_INTR_FROM_CPU_2 INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG 20
53 CPU_INTR_FROM_CPU_3 INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG 21
IN
54 ASSIST_DEBUG_INTR INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG 22
55 DMA_APB_PMS_MONITOR_VIOLATE_INTR INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG 23
56 CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG 24
ESP32-C3 TRM (Pre-release v0.4)
57 CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG 25
58 CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG 26
A
59 CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG 27
60 BACKUP_PMS_VIOLATE_INT INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG 28
61 CACHE_CORE0_ACS_INT INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG 29
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8 Interrupt Matrix (INTMTRX)
8.3.2 CPU Interrupts
The ESP32-C3 implements its interrupt mechanism using an interrupt controller instead of RISC-V Privileged ISA
specification. The ESP-RISC-V CPU has 31 interrupts, numbered from 1 ~ 31. Each CPU interrupt has the
following properties.
• Priority levels from 1 (lowest) to 15 (highest).
• Configurable as level-triggered or edge-triggered.
• Lower-priority interrupts mask-able by setting interrupt threshold.
Note:
For detailed information about how to configure CPU interrupts, see Chapter 1 ESP-RISC-V CPU.
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8.3.3 Allocate Peripheral Interrupt Source to CPU Interrupt
In this section, the following terms are used to describe the operation of the interrupt matrix.
A
• Source_X: stands for a peripheral interrupt source, wherein X means the number of this interrupt source in
Table 8-1.
• INTERRUPT_CORE0_SOURCE_X_MAP_REG: stands for a configuration register for the peripheral
interrupt source (Source_X).
IN
• Num_P: the index of CPU interrupts, can be 1 ~ 31.
• Interrupt_P: stands for the CPU interrupt numbered as Num_P.
IM
8.3.3.1 Allocate one peripheral interrupt source (Source_X) to CPU
Setting the corresponding configuration register INTERRUPT_CORE0_SOURCE_X_MAP_REG of Source_X to
Num_P allocates this interrupt source to Interrupt_P.
EL
8.3.3.2 Allocate multiple peripheral interrupt sources (Source_Xn) to CPU
Setting the corresponding configuration register INTERRUPT_CORE0_SOURCE_Xn_MAP_REG of each interrupt
source to the same Num_P allocates multiple sources to the same Interrupt_P. Any of these sources can trigger
CPU Interrupt_P. When an interrupt signal is generated, CPU should check the interrupt status registers to figure
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out which peripheral generated the interrupt. For more information, see Chapter 1 ESP-RISC-V CPU.
8.3.3.3 Disable CPU peripheral interrupt source (Source_X)
Clearing the configuration register INTERRUPT_CORE0_SOURCE_X_MAP_REG disables the corresponding
interrupt source.
8.3.4 Query Current Interrupt Status of Peripheral Interrupt Source
Users can query current interrupt status of a peripheral interrupt source by reading the bit value in
INTERRUPT_CORE0
_INTR_STATUS_n_REG (read only). For the mapping between INTERRUPT_CORE0_INTR_STATUS_n_REG and
peripheral interrupt sources, please refer to Table 8-1.
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8 Interrupt Matrix (INTMTRX)
8.4 Register Summary
The addresses in this section are relative to the interrupt matrix base address provided in Table 3-4 in Chapter 3 System and Memory.
PR
Name Description Address Access
Interrupt Source Mapping Registers
INTERRUPT_CORE0_PWR_INTR_MAP_REG PWR_INTR mapping register 0x0008 R/W
INTERRUPT_CORE0_I2C_MST_INT_MAP_REG I2C_MST_INT mapping register 0x002C R/W
INTERRUPT_CORE0_SLC0_INTR_MAP_REG SLC0_INTR mapping register 0x0030 R/W
EL
INTERRUPT_CORE0_SLC1_INTR_MAP_REG SLC1_INTR mapping register 0x0034 R/W
INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG APB_CTRL_INTR mapping register 0x0038 R/W
INTERRUPT_CORE0_UHCI0_INTR_MAP_REG UHCI0_INTR mapping register 0x003C R/W
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INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG GPIO_INTERRUPT_PRO mapping register 0x0040 R/W
INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG GPIO_INTERRUPT_PRO_NMI mapping register 0x0044 R/W
IM
INTERRUPT_CORE0_SPI_INTR_1_MAP_REG SPI_INTR_1 mapping register 0x0048 R/W
INTERRUPT_CORE0_SPI_INTR_2_MAP_REG SPI_INTR_2 mapping register 0x004C R/W
186
INTERRUPT_CORE0_I2S1_INT_MAP_REG I2S1_INT mapping register 0x0050 R/W
INTERRUPT_CORE0_UART_INTR_MAP_REG UART_INTR mapping register 0x0054 R/W
INTERRUPT_CORE0_UART1_INTR_MAP_REG UART1_INTR mapping register 0x0058 R/W
IN
INTERRUPT_CORE0_LEDC_INT_MAP_REG LEDC_INT mapping register 0x005C R/W
INTERRUPT_CORE0_EFUSE_INT_MAP_REG EFUSE_INT mapping register 0x0060 R/W
INTERRUPT_CORE0_CAN_INT_MAP_REG CAN_INT mapping register 0x0064 R/W
ESP32-C3 TRM (Pre-release v0.4)
INTERRUPT_CORE0_USB_INTR_MAP_REG USB_INTR mapping register 0x0068 R/W
A
INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG RTC_CORE_INTR mapping register 0x006C R/W
INTERRUPT_CORE0_RMT_INTR_MAP_REG RMT_INTR mapping register 0x0070 R/W
INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG I2C_EXT0 intr mapping register 0x0074 R/W
RY
INTERRUPT_CORE0_TIMER_INT1_MAP_REG TIMER_INT1 mapping register 0x0078 R/W
INTERRUPT_CORE0_TIMER_INT2_MAP_REG TIMER_INT2 mapping register 0x007C R/W
INTERRUPT_CORE0_TG_T0_INT_MAP_REG TG_T0_INT mapping register 0x0080 R/W
INTERRUPT_CORE0_TG_WDT_INT_MAP_REG TG_WDT_INT mapping register 0x0084 R/W
INTERRUPT_CORE0_TG1_T0_INT_MAP_REG TG1_T0_INT mapping register 0x0088 R/W
Espressif Systems
8 Interrupt Matrix (INTMTRX)
Name Description Address Access
INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG TG1_WDT_INT mapping register 0x008C R/W
INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG CACHE_IA_INT mapping register 0x0090 R/W
PR
INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG SYSTIMER_TARGET0_INT mapping register 0x0094 R/W
INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG SYSTIMER_TARGET1_INT mapping register 0x0098 R/W
INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG SYSTIMER_TARGET2_INT mapping register 0x009C R/W
INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG SPI_MEM_REJECT_INTR mapping register 0x00A0 R/W
INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG ICACHE_PRELOAD_INT mapping register 0x00A4 R/W
INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG ICACHE_SYNC_INT mapping register 0x00A8 R/W
EL
INTERRUPT_CORE0_APB_ADC_INT_MAP_REG APB_ADC_INT mapping register 0x00AC R/W
INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG DMA_CH0_INT mapping register 0x00B0 R/W
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INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG DMA_CH1_INT mapping register 0x00B4 R/W
INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG DMA_CH2_INT mapping register 0x00B8 R/W
INTERRUPT_CORE0_RSA_INT_MAP_REG RSA_INT mapping register 0x00BC R/W
IM
INTERRUPT_CORE0_AES_INT_MAP_REG AES_INT mapping register 0x00C0 R/W
187
INTERRUPT_CORE0_SHA_INT_MAP_REG SHA_INT mapping register 0x00C4 R/W
INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG CPU_INTR_FROM_CPU_0 mapping register 0x00C8 R/W
INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG CPU_INTR_FROM_CPU_1 mapping register 0x00CC R/W
IN
INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG CPU_INTR_FROM_CPU_2 mapping register 0x00D0 R/W
INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG CPU_INTR_FROM_CPU_3 intr mapping register 0x00D4 R/W
INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG ASSIST_DEBUG_INTR mapping register 0x00D8 R/W
ESP32-C3 TRM (Pre-release v0.4)
INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_
DMA_APBPERI_PMS_MONITOR_VIOLATE mapping register 0x00DC R/W
A
INTR_MAP_REG
INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE
IRAM0_PMS_MONITOR_VIOLATE mapping register 0x00E0 R/W
_INTR_MAP_REG
RY
INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLAT
DRAM0_PMS_MONITOR_VIOLATE mapping register 0x00E4 R/W
E_INTR_MAP_REG
INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_
PIF_PMS_MONITOR_VIOLATE mapping register 0x00E8 R/W
INTR_MAP_REG
Espressif Systems
8 Interrupt Matrix (INTMTRX)
Name Description Address Access
INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_
PIF_PMS_MONITOR_VIOLATE_SIZE mapping register 0x00EC R/W
SIZE_INTR_MAP_REG
PR
INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG BACKUP_PMS_VIOLATE mapping register 0x00F0 R/W
INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG CACHE_CORE0_ACS mapping register 0x00F4 R/W
Interrupt Source Status Registers
INTERRUPT_CORE0_INTR_STATUS_0_REG Status register for interrupt sources 0 ~ 31 0x00F8 RO
INTERRUPT_CORE0_INTR_STATUS_1_REG Status register for interrupt sources 32 ~ 61 0x00FC RO
Clock Register
EL
INTERRUPT_CORE0_CLOCK_GATE_REG Clock register 0x0100 R/W
CPU Interrupt Registers
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INTERRUPT_CORE0_CPU_INT_ENABLE_REG Enable register for CPU interrupts 0x0104 R/W
INTERRUPT_CORE0_CPU_INT_TYPE_REG Type configuration register for CPU interrupts 0x0108 R/W
INTERRUPT_CORE0_CPU_INT_CLEAR_REG CPU interrupt clear register 0x010C R/W
IM
INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG Pending status register for CPU interrupts 0x0110 RO
188
INTERRUPT_CORE0_CPU_INT_PRI_1_REG Priority configuration register for CPU interrupt 1 0x0118 R/W
INTERRUPT_CORE0_CPU_INT_PRI_2_REG Priority configuration register for CPU interrupt 2 0x011C R/W
INTERRUPT_CORE0_CPU_INT_PRI_3_REG Priority configuration register for CPU interrupt 3 0x0120 R/W
IN
INTERRUPT_CORE0_CPU_INT_PRI_4_REG Priority configuration register for CPU interrupt 4 0x0124 R/W
INTERRUPT_CORE0_CPU_INT_PRI_5_REG Priority configuration register for CPU interrupt 5 0x0128 R/W
INTERRUPT_CORE0_CPU_INT_PRI_6_REG Priority configuration register for CPU interrupt 6 0x012C R/W
ESP32-C3 TRM (Pre-release v0.4)
INTERRUPT_CORE0_CPU_INT_PRI_7_REG Priority configuration register for CPU interrupt 7 0x0130 R/W
A
INTERRUPT_CORE0_CPU_INT_PRI_8_REG Priority configuration register for CPU interrupt 8 0x0134 R/W
INTERRUPT_CORE0_CPU_INT_PRI_9_REG Priority configuration register for CPU interrupt 9 0x0138 R/W
INTERRUPT_CORE0_CPU_INT_PRI_10_REG Priority configuration register for CPU interrupt 10 0x013C R/W
RY
INTERRUPT_CORE0_CPU_INT_PRI_11_REG Priority configuration register for CPU interrupt 11 0x0140 R/W
INTERRUPT_CORE0_CPU_INT_PRI_12_REG Priority configuration register for CPU interrupt 12 0x0144 R/W
INTERRUPT_CORE0_CPU_INT_PRI_13_REG Priority configuration register for CPU interrupt 13 0x0148 R/W
INTERRUPT_CORE0_CPU_INT_PRI_14_REG Priority configuration register for CPU interrupt 14 0x014C R/W
INTERRUPT_CORE0_CPU_INT_PRI_15_REG Priority configuration register for CPU interrupt 15 0x0150 R/W
Espressif Systems
8 Interrupt Matrix (INTMTRX)
Name Description Address Access
INTERRUPT_CORE0_CPU_INT_PRI_16_REG Priority configuration register for CPU interrupt 16 0x0154 R/W
INTERRUPT_CORE0_CPU_INT_PRI_17_REG Priority configuration register for CPU interrupt 17 0x0158 R/W
PR
INTERRUPT_CORE0_CPU_INT_PRI_18_REG Priority configuration register for CPU interrupt 18 0x015C R/W
INTERRUPT_CORE0_CPU_INT_PRI_19_REG Priority configuration register for CPU interrupt 19 0x0160 R/W
INTERRUPT_CORE0_CPU_INT_PRI_20_REG Priority configuration register for CPU interrupt 20 0x0164 R/W
INTERRUPT_CORE0_CPU_INT_PRI_21_REG Priority configuration register for CPU interrupt 21 0x0168 R/W
INTERRUPT_CORE0_CPU_INT_PRI_22_REG Priority configuration register for CPU interrupt 22 0x016C R/W
INTERRUPT_CORE0_CPU_INT_PRI_23_REG Priority configuration register for CPU interrupt 23 0x0170 R/W
EL
INTERRUPT_CORE0_CPU_INT_PRI_24_REG Priority configuration register for CPU interrupt 24 0x0174 R/W
INTERRUPT_CORE0_CPU_INT_PRI_25_REG Priority configuration register for CPU interrupt 25 0x0178 R/W
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INTERRUPT_CORE0_CPU_INT_PRI_26_REG Priority configuration register for CPU interrupt 26 0x017C R/W
INTERRUPT_CORE0_CPU_INT_PRI_27_REG Priority configuration register for CPU interrupt 27 0x0180 R/W
INTERRUPT_CORE0_CPU_INT_PRI_28_REG Priority configuration register for CPU interrupt 28 0x0184 R/W
IM
INTERRUPT_CORE0_CPU_INT_PRI_29_REG Priority configuration register for CPU interrupt 29 0x0188 R/W
189
INTERRUPT_CORE0_CPU_INT_PRI_30_REG Priority configuration register for CPU interrupt 30 0x018C R/W
INTERRUPT_CORE0_CPU_INT_PRI_31_REG Priority configuration register for CPU interrupt 31 0x0190 R/W
INTERRUPT_CORE0_CPU_INT_THRESH_REG Threshold configuration register for CPU interrupts 0x0194 R/W
IN
Version Register
INTERRUPT_CORE0_INTERRUPT_DATE_REG Version control register 0x07FC R/W
ESP32-C3 TRM (Pre-release v0.4)
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8 Interrupt Matrix (INTMTRX)
8.5 Registers
The addresses in this section are relative to the interrupt matrix base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 8.1. INTERRUPT_CORE0_PWR_INTR_MAP_REG (0x0008)
Register 8.2. INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (0x002C)
Register 8.3. INTERRUPT_CORE0_SLC0_INTR_MAP_REG (0x0030)
Register 8.4. INTERRUPT_CORE0_SLC1_INTR_MAP_REG (0x0034)
Register 8.5. INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (0x0038)
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Register 8.6. INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (0x003C)
Register 8.7. INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (0x0040)
Register 8.8. INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (0x0044)
Register 8.9. INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (0x0048)
Register 8.10. INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (0x004C)
A
Register 8.11. INTERRUPT_CORE0_I2S1_INT_MAP_REG (0x0050)
Register 8.12. INTERRUPT_CORE0_UART_INTR_MAP_REG (0x0054)
IN
Register 8.13. INTERRUPT_CORE0_UART1_INTR_MAP_REG (0x0058)
Register 8.14. INTERRUPT_CORE0_LEDC_INT_MAP_REG (0x005C)
Register 8.15. INTERRUPT_CORE0_EFUSE_INT_MAP_REG (0x0060)
IM
Register 8.16. INTERRUPT_CORE0_CAN_INT_MAP_REG (0x0064)
Register 8.17. INTERRUPT_CORE0_USB_INTR_MAP_REG (0x0068)
Register 8.18. INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (0x006C)
Register 8.19. INTERRUPT_CORE0_RMT_INTR_MAP_REG (0x0070)
EL
Register 8.20. INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (0x0074)
Register 8.21. INTERRUPT_CORE0_TIMER_INT1_MAP_REG (0x0078)
Register 8.22. INTERRUPT_CORE0_TIMER_INT2_MAP_REG (0x007C)
Register 8.23. INTERRUPT_CORE0_TG_T0_INT_MAP_REG (0x0080)
PR
Register 8.24. INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (0x0084)
Register 8.25. INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (0x0088)
Register 8.26. INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (0x008C)
Register 8.27. INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (0x0090)
Register 8.28. INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (0x0094)
Register 8.29. INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (0x0098)
Register 8.30. INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (0x009C)
Register 8.31. INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (0x00A0)
Register 8.32. INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (0x00A4)
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8 Interrupt Matrix (INTMTRX)
Register 8.33. INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (0x00A8)
Register 8.34. INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (0x00AC)
Register 8.35. INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (0x00B0)
Register 8.36. INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (0x00B4)
Register 8.37. INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (0x00B8)
Register 8.38. INTERRUPT_CORE0_RSA_INT_MAP_REG (0x00BC)
Register 8.39. INTERRUPT_CORE0_AES_INT_MAP_REG (0x00C0)
Register 8.40. INTERRUPT_CORE0_SHA_INT_MAP_REG (0x00C4)
Register 8.41. INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (0x00C8)
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Register 8.42. INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (0x00CC)
Register 8.43. INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (0x00D0)
Register 8.44. INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (0x00D4)
Register 8.45. INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (0x00D8)
A
Register 8.46. INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (0x00DC)
Register 8.47. INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (0x00E0)
IN
Register 8.48. INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (0x00E4)
Register 8.49. INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (0x00E8)
Register 8.50. INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (0x00EC)
IM
Register 8.51. INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (0x00F0)
Register 8.52. INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (0x00F4)
AP
_M
_X
EL
CE
UR
SO
0_
RE
CO
T_
UP
d )
ve
RR
r
se
TE
(re
IN
PR
31 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
INTERRUPT_CORE0_SOURCE_X_MAP Map the interrupt source (SOURCE_X) into one CPU inter-
rupts. For the information of SOURCE_X, see Table 8-1. (R/W)
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Register 8.53. INTERRUPT_CORE0_INTR_STATUS_0_REG (0x00F8)
0
S_
TU
TA
_S
TR
IN
0_
RE
O
_C
PT
R RU
TE
IN
31 0
0x000000 Reset
RY
INTERRUPT_CORE0_INTR_STATUS_0 This register stores the status of the first 32 interrupt
sources: 0 ~ 31. If the bit is 1 here, it means the corresponding source triggered an interrupt.
(RO)
Register 8.54. INTERRUPT_CORE0_INTR_STATUS_1_REG (0x00FC)
A TU
1
S_
TA
IN R RU
PT
O
_C
0_
RE
IN
_S
TR
TE
IM IN
31 0
0x000000 Reset
INTERRUPT_CORE0_INTR_STATUS_1 This register stores the status of the first 32 interrupt
sources: 32 ~ 61. If the bit is 1 here, it means the corresponding source triggered an interrupt.(RO)
EL
Register 8.55. INTERRUPT_CORE0_CLOCK_GATE_REG (0x0100)
N
PR
_E
LK
C
0_
RE
CO
T_
UP
)
ed
RR
rv
se
TE
(re
IN
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
INTERRUPT_CORE0_CLK_EN Set 1 to force interrupt register clock-gate on. (R/W)
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Register 8.56. INTERRUPT_CORE0_CPU_INT_ENABLE_REG (0x0104)
LE
AB
_ EN
NT
I
U_
CP
0_
RE
CO
T_
UP
RR
TE
IN
31 0
0 Reset
RY
INTERRUPT_CORE0_CPU_INT_ENABLE Writing 1 to the bit here enables its corresponding CPU
interrupt. For more information about how to use this register, see Chapter 1 ESP-RISC-V CPU.
(R/W)
A
Register 8.57. INTERRUPT_CORE0_CPU_INT_TYPE_REG (0x0108)
E
YP
_T
IN RU
R
_C
PT
O
RE
0_
CP
U_
IN
T
IM IN
TE
31 0
0 Reset
INTERRUPT_CORE0_CPU_INT_TYPE Configure CPU interrupt type. 0: level-triggered; 1: edge-
EL
triggered. For more information about how to use this register, see Chapter 1 ESP-RISC-V CPU.
(R/W)
PR
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Register 8.58. INTERRUPT_CORE0_CPU_INT_CLEAR_REG (0x010C)
E AR
CL
T_
IN
U_
CP
0_
RE
O
_C
PT
RU
R
TE
IN
31 0
0 Reset
RY
INTERRUPT_CORE0_CPU_INT_CLEAR Writing 1 to the bit here clears its corresponding CPU in-
terrupt. For more information about how to use this register, see Chapter 1 ESP-RISC-V CPU.
(R/W)
A
Register 8.59. INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (0x0110)
S
TU
TA
_S
IN _C
PT
O
RE
0_
CP
U_
IN
_E
T
IP
IM IN
TE
RU
R
31 0
0 Reset
EL
INTERRUPT_CORE0_CPU_INT_EIP_STATUS Store the pending status of CPU interrupts. For more
information about how to use this register, see Chapter 1 ESP-RISC-V CPU. (RO)
PR
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Register 8.60. INTERRUPT_CORE0_CPU_INT_PRI_n_REG (n: 1 31)(0x0118 + 0x4*n)
AP
M
_
_n
RI
P
U_
CP
0_
RE
O
_C
T
UP
)
ed
RR
rv
se
TE
(re
IN
31 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
INTERRUPT_CORE0_CPU_PRI_n_MAP Set the priority for CPU interrupt n. The priority here can
be 1 (lowest) ~ 15 (highest). For more information about how to use this register, see Chapter 1
ESP-RISC-V CPU. (R/W)
A
Register 8.61. INTERRUPT_CORE0_CPU_INT_THRESH_REG (0x0194)
SH
RE
H
IN
T _T
IN
U_
CP
0_
RE
O
_C
PT
d)
RU
IM e
rv
ER
se
T
(re
IN
31 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
INTERRUPT_CORE0_CPU_INT_THRESH Set threshold for interrupt assertion to CPU. Only when
EL
the interrupt priority is equal to or higher than this threshold, CPU will respond to this interrupt. For
more information about how to use this register, see Chapter 1 ESP-RISC-V CPU. (R/W)
Register 8.62. INTERRUPT_CORE0_INTERRUPT_DATE_REG (0x07FC)
PR
E
AT
_D
PT
RU
ER
NT
0_I
RE
CO
T_
UP
)
ed
RR
rv
se
TE
(re
IN
31 28 27 0
0 0 0 0 0x2007210 Reset
INTERRUPT_CORE0_INTERRUPT_DATE Version control register. (R/W)
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9 System Timer (SYSTIMER)
9.1 Overview
ESP32-C3 provides a 52-bit timer, which can be used to generate tick interrupts for operating system, or be
used as a general timer to generate periodic interrupts or one-time interrupts. With the help of RTC timer, system
timer can keep updated during Light-sleep or Deep-sleep.
The timer consists of two counters UNIT0 and UNIT1. The counter values can be monitored by three
comparators COMP0, COMP1 and COMP2. See the timer block diagram on Figure 9-1.
A RY
IN
IM
Figure 91. System Timer Structure
9.2 Features
EL
• Consist of two 52-bit counters and three 52-bit comparators
• Software accessing registers is clocked by APB_CLK
• Use CNT_CLK for counting, with an average frequency of 16 MHz in two counting cycles
• Use 40 MHz XTAL_CLK as the clock source of CNT_CLK
PR
• Support for 52-bit alarm values (t) and 26-bit alarm periods (δt)
• Provide two modes to generate alarms:
– Target mode: only a one-time alarm is generated based on the alarm value (t)
– Period mode: periodic alarms are generated based on the alarm period (δt)
• Three comparators can generate three independent interrupts based on configured alarm value (t) or alarm
period (δt)
• Load back sleep time recorded by RTC timer via software after Deep-sleep or Light-sleep
• Can be configured to stall or continue running when CPU stalls or enters on-chip-debugging mode
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9.3 Clock Source Selection
The counters and comparators are driven using XTAL_CLK. After scaled by a fractional divider, a fXT AL_CLK /3
clock is generated in one count cycle and a fXT AL_CLK /2 clock in another count cycle. The average clock
frequency is fXT AL_CLK /2.5, which is 16 MHz, i.e. the CNT_CLK in Figure 9-2. The timer counting is
incremented by 1/16 µs on each CNT_CLK cycle.
Software operation such as configuring registers is clocked by APB_CLK. For more information about APB_CLK,
see Chapter 6 Reset and Clock.
The following two bits of system registers are also used to control the system timer:
• SYSTEM_SYSTIMER_CLK_EN in register SYSTEM_PERIP_CLK_EN0_REG: enable APB_CLK signal to
RY
system timer.
• SYSTEM_SYSTIMER_RST in register SYSTEM_PERIP_RST_EN0_REG: reset system timer.
Note that if the timer is reset, its registers will be restored to their default values. For more information, please
refer to Table Peripheral Clock Gating and Reset in Chapter 13 System Registers (SYSREG).
A
9.4 Functional Description
IN
IM
EL
Figure 92. System Timer Alarm Generation
Figure 9-2 shows the procedure to generate alarm in system timer. In this process, one timer counter and one
timer comparator are used. An alarm interrupt will be generated accordingly based on the comparison result in
PR
comparator.
9.4.1 Counter
The system timer has two 52-bit timer counters, shown as UNITn (n = 0 or 1). Their counting clock source is a 16
MHz clock, i.e. CNT_CLK. Whether UNITn works or not is controlled by two bits in register
SYSTIMER_CONF_REG:
• SYSTIMER_TIMER_UNITn_WORK_EN: set this bit to enable the counter UNITn in system timer.
• SYSTIMER_TIMER_UNITn_CORE0_STALL_EN: if this bit is set, the counter UNITn stops when CPU is
stalled. The counter continues its counting after the CPU resumes.
The configuration of the two bits to control the counter UNITn is shown below, assuming that CPU is
stalled.
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Table 91. UNITn Configuration Bits
SYSTIMER_TIMER_ SYSTIMER_TIMER_ Counter
UNITn_WORK_EN UNITn_CORE0_STALL_EN UNITn
*
0 x Not at work
Stop counting, but will continue its
1 1
counting after the CPU resumes.
1 0 Keep counting
*
x: Don’t-care.
When the counter UNITn is at work, the count value is incremented on each counting cycle. When the counter
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UNITn is stopped, the count value stops increasing and keeps unchanged.
The lower 32 and higher 20 bits of initial count value are loaded from the registers
SYSTIMER_TIMER_UNITn_LOAD
_LO and SYSTIMER_TIMER_UNITn_LOAD_HI. Writing 1 to the bit SYSTIMER_TIMER_UNITn_LOAD will trigger a
reload event, and the current count value will be changed immediately. If UNITn is at work, the counter will
A
continue to count up from the new reloaded value.
Writing 1 to SYSTIMER_TIMER_UNITn_UPDATE will trigger an update event. The lower 32 and higher 20 bits of
current count value will be locked into the registers SYSTIMER_TIMER_UNITn_VALUE_LO and
SYSTIMER_TIMER_
IN
UNITn_VALUE_HI, and then SYSTIMER_TIMER_UNITn_VALUE_VALID is asserted. Before the next update event,
the values of SYSTIMER_TIMER_UNITn_VALUE_LO and SYSTIMER_TIMER_UNITn_VALUE_HI remain
unchanged.
IM
9.4.2 Comparator and Alarm
The system timer has three 52-bit comparators, shown as COMPx (x = 0, 1, or 2). The comparators can
generate independent interrupts based on different alarm values (t) or alarm periods (δt).
EL
Configure SYSTIMER_TARGETx_PERIOD_MODE to choose from the two alarm modes for each COMPx:
• 1: select period mode
• 0: select target mode
In period mode, the alarm period (δt) is provided by the register SYSTIMER_TARGETx_PERIOD. Assuming that
PR
current count value is t1, when it reaches (t1 + δt), an alarm interrupt will be generated. Another alarm interrupt
also will be generated when the counter value reaches (t1 + 2*δt). By such way, periodic alarms are
generated.
In target mode, the lower 32 bits and higher 20 bits of the alarm value (t) are provided by
SYSTIMER_TIMER_TARGET
x_LO and SYSTIMER_TIMER_TARGETx_HI. Assuming that current count value is t2 (t2 <= t), an alarm interrupt
will be generated when the count value reaches the alarm value (t). Unlike in period mode, only one alarm
interrupt is generated in target mode.
SYSTIMER_TARGETx_TIMER_UNIT_SEL is used to choose the count value from which timer counter to be
compared for alarm:
• 1: use the count value from UNIT1
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• 0: use the count value from UNIT0
Finally, set SYSTIMER_TARGETx_WORK_EN and COMPx starts to compare the count value with the alarm value
(t) in target mode or with the alarm period (t1 + n*δt) in period mode.
An alarm is generated when the count value equals to the alarm value (t) in target mode or to the start value +
n*alarm period δt (n = 1,2,3...) in period mode. But if the alarm value (t) set in registers is less than current count
value, i.e. the target has already passed, or current count value is larger than the target value (t) within a range (0
~ 251 -1), an alarm interrupt also is generated immediately. The relationship between current count value tc , the
alarm value tt and alarm trigger point is shown below.
Table 92. Trigger Point
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Relationship Between tc and tt Trigger Point
tc - tt <= 0 tc = tt , an alarm is triggered.
51
0 <= tc - tt < 2 -1 An alarm is triggered immediately.
tc overflows after counting to its maximum value
51
tc - tt >= 2 -1 52’hfffffffffffff, and then starts counting up from 0.
When its value reaches tt , an alarm is triggered.
A
9.4.3 Synchronization Operation
IN
The clock (APB_CLK) used in software operation is not the same one as the timer counters and comparators
working on CNT_CLK. Synchronization is needed for some configuration registers. A complete synchronization
action takes two steps:
IM
1. Software writes suitable values to configuration fields, see the first column in Table 9-3.
2. Software writes 1 to corresponding bits to start synchronization, see the second column in Table 9-3.
Table 93. Synchronization Operation
EL
Configuration Fields Synchronization Enable Bit
SYSTIMER_TIMER_UNITn_LOAD_LO
SYSTIMER_TIMER_UNITn_LOAD
SYSTIMER_TIMER_UNITn_LOAD_HI
SYSTIMER_TARGETx_PERIOD
SYSTIMER_TIMER_TARGETx_HI SYSTIMER_TIMER_COMPx_LOAD
PR
SYSTIMER_TIMER_TARGETx_LO
9.4.4 Interrupt
Each comparator has one level-type alarm interrupt, named as SYSTIMER_TARGETx_INT. Interrupts signal is
asserted high when the comparator starts to alarm. Until the interrupt is cleared by software, it remains high. To
enable interrupts, set the bit SYSTIMER_TARGETx_INT_ENA.
9.5 Programming Procedure
9.5.1 Read Current Count Value
1. Set SYSTIMER_TIMER_UNITn_UPDATE to update the current count value into SYSTIMER_TIMER_UNITn_
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VALUE_HI and SYSTIMER_TIMER_UNITn_VALUE_LO.
2. Poll the reading of SYSTIMER_TIMER_UNITn_VALUE_VALID, till it’s 1, which means user now can read the
count value from SYSTIMER_TIMER_UNITn_VALUE_HI and SYSTIMER_TIMER_UNITn_VALUE_LO.
3. Read the lower 32 bits and higher 20 bits from SYSTIMER_TIMER_UNITn_VALUE_LO and
SYSTIMER_TIMER_UNITn_VALUE_HI.
9.5.2 Configure OneTime Alarm in Target Mode
1. Set SYSTIMER_TARGETx_TIMER_UNIT_SEL to select the counter (UNIT0 or UNIT1) used for COMPx.
2. Read current count value, see Section 9.5.1. This value will be used to calculate the alarm value (t) in Step
4.
RY
3. Clear SYSTIMER_TARGETx_PERIOD_MODE to enable target mode.
4. Set an alarm value (t), and fill its lower 32 bits to SYSTIMER_TIMER_TARGETx_LO, and the higher 20 bits
to SYSTIMER_TIMER_TARGETx_HI.
5. Set SYSTIMER_TIMER_COMPx_LOAD to synchronize the alarm value (t) to COMPx, i.e. load the alarm
A
value (t) to the COMPx.
6. Set SYSTIMER_TARGETx_WORK_EN to enable the selected COMPx. COMPx starts comparing the count
value with the alarm value (t).
IN
7. Set SYSTIMER_TARGETx_INT_ENA to enable timer interrupt. When Unitn counts to the alarm value (t), a
SYSTIMER_TARGETx_INT interrupt is triggered.
IM
9.5.3 Configure Periodic Alarms in Period Mode
1. Set SYSTIMER_TARGETx_TIMER_UNIT_SEL to select the counter (UNIT0 or UNIT1) used for COMPx.
2. Set an alarm period (δt), and fill it to SYSTIMER_TARGETx_PERIOD.
3. Set SYSTIMER_TIMER_COMPx_LOAD to synchronize the alarm period (δt) to COMPx, i.e. load the alarm
EL
period (δt) to COMPx.
4. Set SYSTIMER_TARGETx_PERIOD_MODE to configure COMPx into period mode.
5. Set SYSTIMER_TARGETx_WORK_EN to enable the selected COMPx. COMPx starts comparing the count
value with the sum of start value + n*δt (n = 1, 2, 3...).
PR
6. Set SYSTIMER_TARGETx_INT_ENA to enable timer interrupt. A SYSTIMER_TARGETx_INT interrupt is
triggered when Unitn counts to start value + n*δt (n = 1, 2, 3...) set in step 2.
9.5.4 Update After Deepsleep and Lightsleep
1. Configure RTC timer before the chip goes to Deep-sleep or Light-sleep, to record the exact sleep time. For
more information, see Chapter 4 Low-Power Management (RTC_CNTL) [to be added later].
2. Read the sleep time from RTC timer when the chip is woken up from Deep-sleep or Light-sleep.
3. Read current count value of system timer, see Section 9.5.1.
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4. Convert the time value recorded by RTC timer from the clock cycles based on RTC_SLOW_CLK to that
based on 16 MHz CNT_CLK. For example, if the frequency of RTC_SLOW_CLK is 32 KHz, the recorded
RTC timer value should be converted by multiplying by 500.
5. Add the converted RTC value to current count value of system timer:
• Fill the new value into SYSTIMER_TIMER_UNITn_LOAD_LO (low 32 bits) and
SYSTIMER_TIMER_UNITn_LOAD_HI (high 20 bits).
• Set SYSTIMER_TIMER_UNITn_LOAD to load new timer value into system timer. By such way, the
system timer is updated.
9.6 Register Summary
RY
The addresses in this section are relative to system timer base address provided in Table 3-4 in Chapter 3 System
and Memory.
Name Description Address Access
Clock Control Register
A
SYSTIMER_CONF_REG Configure system timer clock 0x0000 R/W
UNIT0 Control and Configuration Registers
SYSTIMER_UNIT0_OP_REG Read UNIT0 value to registers 0x0004 varies
SYSTIMER_UNIT0_LOAD_HI_REG
SYSTIMER_UNIT0_LOAD_LO_REG
IN
High 20 bits to be loaded to UNIT0
Low 32 bits to be loaded to UNIT0
0x000C
0x0010
R/W
R/W
SYSTIMER_UNIT0_VALUE_HI_REG UNIT0 value, high 20 bits 0x0040 RO
SYSTIMER_UNIT0_VALUE_LO_REG UNIT0 value, low 32 bits 0x0044 RO
IM
SYSTIMER_UNIT0_LOAD_REG UNIT0 synchronization register 0x005C WT
UNIT1 Control and Configuration Registers
SYSTIMER_UNIT1_OP_REG Read UNIT1 value to registers 0x0008 varies
SYSTIMER_UNIT1_LOAD_HI_REG High 20 bits to be loaded to UNIT1 0x0014 R/W
SYSTIMER_UNIT1_LOAD_LO_REG Low 32 bits to be loaded to UNIT1 0x0018 R/W
EL
SYSTIMER_UNIT1_VALUE_HI_REG UNIT1 value, high 20 bits 0x0048 RO
SYSTIMER_UNIT1_VALUE_LO_REG UNIT1 value, low 32 bits 0x004C RO
SYSTIMER_UNIT1_LOAD_REG UNIT1 synchronization register 0x0060 WT
Comparator0 Control and Configuration Registers
SYSTIMER_TARGET0_HI_REG Alarm value to be loaded to COMP0, high 20 0x001C R/W
PR
bits
SYSTIMER_TARGET0_LO_REG Alarm value to be loaded to COMP0, low 32 0x0020 R/W
bits
SYSTIMER_TARGET0_CONF_REG Configure COMP0 alarm mode 0x0034 R/W
SYSTIMER_COMP0_LOAD_REG COMP0 synchronization register 0x0050 WT
Comparator1 Control and Configuration Registers
SYSTIMER_TARGET1_HI_REG Alarm value to be loaded to COMP1, high 20 0x0024 R/W
bits
SYSTIMER_TARGET1_LO_REG Alarm value to be loaded to COMP1, low 32 0x0028 R/W
bits
SYSTIMER_TARGET1_CONF_REG Configure COMP1 alarm mode 0x0038 R/W
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Name Description Address Access
SYSTIMER_COMP1_LOAD_REG COMP1 synchronization register 0x0054 WT
Comparator2 Control and Configuration Registers
SYSTIMER_TARGET2_HI_REG Alarm value to be loaded to COMP2, high 20 0x002C R/W
bits
SYSTIMER_TARGET2_LO_REG Alarm value to be loaded to COMP2, low 32 0x0030 R/W
bits
SYSTIMER_TARGET2_CONF_REG Configure COMP2 alarm mode 0x003C R/W
SYSTIMER_COMP2_LOAD_REG COMP2 synchronization register 0x0058 WT
Interrupt Registers
SYSTIMER_INT_ENA_REG Interrupt enable register of system timer 0x0064 R/W
RY
SYSTIMER_INT_RAW_REG Interrupt raw register of system timer 0x0068 R/WTC/SS
SYSTIMER_INT_CLR_REG Interrupt clear register of system timer 0x006C WT
SYSTIMER_INT_ST_REG Interrupt status register of system timer 0x0070 RO
Version Register
SYSTIMER_DATE_REG Version control register 0x00FC R/W
A
IN
IM
EL
PR
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9.7 Registers
The addresses in this section are relative to system timer base address provided in Table 3-4 in Chapter 3 System
and Memory.
Register 9.1. SYSTIMER_CONF_REG (0x0000)
EN
EN
L_
L_
AL
AL
ST
T
_C RK N
RE N
S
T0 O E
O _E
0_
0_
NI _W K_
2_ R EN
RK N
N
RE
_U IT1 OR
O E
_E
ET O _
W K_
CO
G _W RK
ER N W
S d) IM _U 0_
1_
AR T O
_T GE _W
SY rve _T ER NIT
T
NI
ER AR T0
1
se ER IM _U
_U
ST ER IM N
IM _T GE
SY TIM _T _E
(re IM _T ER
ER
RY
S ER LK
ST ER R
ST d) IM
A
SY IM _C
SY rve _T
SY IM _T
ST ER
se ER
ST ER
)
ed
SY TIM
(re TIM
SY IM
rv
se
S
SY
(re
31 30 29 28 27 26 25 24 23 22 21 0
0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
A
SYSTIMER_TARGET2_WORK_EN COMP2 work enable bit. (R/W)
SYSTIMER_TARGET1_WORK_EN COMP1 work enable bit. (R/W) IN
SYSTIMER_TARGET0_WORK_EN COMP0 work enable bit. (R/W)
SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN UNIT1 is stalled when CPU stalled. (R/W)
SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN UNIT0 is stalled when CPU stalled. (R/W)
IM
SYSTIMER_TIMER_UNIT1_WORK_EN UNIT1 work enable bit. (R/W)
SYSTIMER_TIMER_UNIT0_WORK_EN UNIT0 work enable bit. (R/W)
SYSTIMER_CLK_EN Register clock gating. 1: Register clock is always enabled for read and write
operations. 0: Only enable needed clock for register read or write operations. (R/W)
EL
PR
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Register 9.2. SYSTIMER_UNIT0_OP_REG (0x0004)
D
A LI
_V
AL E
_V AT
UE
T0 PD
NI _U
_U IT0
ER N
IM _U
_T ER
ER IM
IM _T
ST ER
S d)
d)
SY TIM
SY rve
ve
r
se
se
(re
(re
31 30 29 28 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
SYSTIMER_TIMER_UNIT0_VALUE_VALID Timer value is synchronized and valid. (R/SS/WTC)
SYSTIMER_TIMER_UNIT0_UPDATE Update timer UNIT0, i.e. read the UNIT0 count value to SYS-
TIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO. (WT)
A
Register 9.3. SYSTIMER_UNIT0_LOAD_HI_REG (0x000C)
I
_H
IN
AD
O
_L
T0
NI
_U
ER
IM
_T
ER
d)
IM
ve
IM
r
ST
se
SY
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_UNIT0_LOAD_HI The value to be loaded to UNIT0, high 20 bits. (R/W)
EL
Register 9.4. SYSTIMER_UNIT0_LOAD_LO_REG (0x0010)
O
_L
PR
AD
LO
0_
N IT
_U
ER
IM
_T
ER
IM
ST
SY
31 0
0 Reset
SYSTIMER_TIMER_UNIT0_LOAD_LO The value to be loaded to UNIT0, low 32 bits. (R/W)
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Register 9.5. SYSTIMER_UNIT0_VALUE_HI_REG (0x0040)
I
_H
LUE
VA
T0_
NI
_U
ER
IM
_T
ER
d)
IM
ve
er
ST
s
SY
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_UNIT0_VALUE_HI UNIT0 read value, high 20 bits. (RO)
RY
Register 9.6. SYSTIMER_UNIT0_VALUE_LO_REG (0x0044)
O
_L
A UE
AL
_V
T0
NI
_U
ER
IN IM
ER
_T
IM
ST
SY
31 0
0 Reset
IM
SYSTIMER_TIMER_UNIT0_VALUE_LO UNIT0 read value, low 32 bits. (RO)
EL
Register 9.7. SYSTIMER_UNIT0_LOAD_REG (0x005C)
AD
LO
0_
T
NI
_U
ER
IM
_T
PR
ER
)
ed
M
rv
I
ST
se
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_UNIT0_LOAD UNIT0 synchronization enable signal. Set this bit to reload the val-
ues of SYSTIMER_TIMER_UNIT0_LOAD_HI and SYSTIMER_TIMER_UNIT0_LOAD_LO to UNIT0.
(WT)
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9 System Timer (SYSTIMER)
Register 9.8. SYSTIMER_UNIT1_OP_REG (0x0008)
D
A LI
_V
AL E
_V AT
UE
T1 PD
NI _U
_U IT1
ER N
IM _U
_T ER
ER IM
IM _T
ST ER
S d)
d)
SY TIM
SY rve
ve
r
se
se
(re
(re
31 30 29 28 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
SYSTIMER_TIMER_UNIT1_VALUE_VALID UNIT1 value is synchronized and valid. (R/SS/WTC)
SYSTIMER_TIMER_UNIT1_UPDATE Update timer UNIT1, i.e. read the UNIT1 count value to SYS-
TIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO. (WT)
A
Register 9.9. SYSTIMER_UNIT1_LOAD_HI_REG (0x0014)
I
_H
IN
AD
O
_L
T1
NI
_U
ER
IM
_T
ER
d)
IM
ve
IM
r
ST
se
SY
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_UNIT1_LOAD_HI The value to be loaded to UNIT1, high 20 bits. (R/W)
EL
Register 9.10. SYSTIMER_UNIT1_LOAD_LO_REG (0x0018)
O
_L
PR
AD
LO
1_
N IT
_U
ER
IM
_T
ER
IM
ST
SY
31 0
0 Reset
SYSTIMER_TIMER_UNIT1_LOAD_LO The value to be loaded to UNIT1, low 32 bits. (R/W)
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9 System Timer (SYSTIMER)
Register 9.11. SYSTIMER_UNIT1_VALUE_HI_REG (0x0048)
I
_H
LUE
VA
T1_
NI
_U
ER
IM
_T
ER
d)
IM
ve
er
ST
s
SY
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_UNIT1_VALUE_HI UNIT1 read value, high 20 bits. (RO)
RY
Register 9.12. SYSTIMER_UNIT1_VALUE_LO_REG (0x004C)
O
_L
A UE
AL
_V
T1
NI
_U
ER
IN IM
ER
_T
IM
ST
SY
31 0
0 Reset
IM
SYSTIMER_TIMER_UNIT1_VALUE_LO UNIT1 read value, low 32 bits. (RO)
EL
Register 9.13. SYSTIMER_UNIT1_LOAD_REG (0x0060)
AD
LO
1_
T
NI
_U
ER
IM
_T
PR
ER
)
ed
M
rv
I
ST
se
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_UNIT1_LOAD UNIT1 synchronization enable signal. Set this bit to reload the val-
ues of SYSTIMER_TIMER_UNIT1_LOAD_HI and SYSTIMER_TIMER_UNIT1_LOAD_LO to UNIT1.
(WT)
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9 System Timer (SYSTIMER)
Register 9.14. SYSTIMER_TARGET0_HI_REG (0x001C)
HI
0_
ET
G
AR
_T
ER
IM
_T
ER
)
ed
IM
rv
ST
se
SY
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_TARGET0_HI The alarm value to be loaded to COMP0, high 20 bits. (R/W)
RY
Register 9.15. SYSTIMER_TARGET0_LO_REG (0x0020)
LO
0_
ET
G
A
AR
_T
ER
IM
_T
ER
IM
IN
ST
SY
31 0
0 Reset
SYSTIMER_TIMER_TARGET0_LO The alarm value to be loaded to COMP0, low 32 bits. (R/W)
IM
Register 9.16. SYSTIMER_TARGET0_CONF_REG (0x0034)
EL O L
M SE
D_ _
O IT
RI UN
DE
D
PE R_
O
0_ E
RI
ET IM
PE
G 0_T
0_
AR T
ET
_T GE
G
ER AR
AR
IM _T
_T
ST ER
ER
PR SY TIM
ed
)
IM
rv
ST
se
S
SY
SY
(re
31 30 29 26 25 0
0 0 0 0 0 0 0x00000 Reset
SYSTIMER_TARGET0_PERIOD COMP0 alarm period. (R/W)
SYSTIMER_TARGET0_PERIOD_MODE Set COMP0 to period mode. (R/W)
SYSTIMER_TARGET0_TIMER_UNIT_SEL Select which unit to compare for COMP0. (R/W)
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9 System Timer (SYSTIMER)
Register 9.17. SYSTIMER_COMP0_LOAD_REG (0x0050)
AD
O
_L
P0
M
O
_C
ER
IM
_T
ER
d)
IM
ver
ST
se
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_COMP0_LOAD COMP0 synchronization enable signal. Set this bit to reload the
RY
alarm value/period to COMP0. (WT)
Register 9.18. SYSTIMER_TARGET1_HI_REG (0x0024)
A M
ER
_T
AR
G
ET
1_
HI
IN
I
_T
ER
d)
IM
ve
er
ST
s
SY
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IM
SYSTIMER_TIMER_TARGET1_HI The alarm value to be loaded to COMP1, high 20 bits. (R/W)
Register 9.19. SYSTIMER_TARGET1_LO_REG (0x0028)
EL
LO
1_
ET
G
AR
_T
ER
IM
_T
PR
ER
IM
ST
SY
31 0
0 Reset
SYSTIMER_TIMER_TARGET1_LO The alarm value to be loaded to COMP1, low 32 bits. (R/W)
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9 System Timer (SYSTIMER)
Register 9.20. SYSTIMER_TARGET1_CONF_REG (0x0038)
O L
M SE
DE
D_ _
O IT
RI UN
D
PE R_
O
1_ E
RI
ET IM
PE
G 1_T
1_
AR T
ET
_T GE
G
ER AR
AR
IM _T
_T
ST ER
ER
)
ed
SY TIM
IM
rv
ST
se
S
SY
SY
(re
31 30 29 26 25 0
0 0 0 0 0 0 0x00000 Reset
RY
SYSTIMER_TARGET1_PERIOD COMP1 alarm period. (R/W)
SYSTIMER_TARGET1_PERIOD_MODE Set COMP1 to period mode. (R/W)
SYSTIMER_TARGET1_TIMER_UNIT_SEL Select which unit to compare for COMP1. (R/W)
A
Register 9.21. SYSTIMER_COMP1_LOAD_REG (0x0054)
IN
AD
O
_L
P1
M
O
_C
ER
IM
_T
ER
d)
IM
IM
r ve
ST
se
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_COMP1_LOAD COMP1 synchronization enable signal. Set this bit to reload the
EL
alarm value/period to COMP1. (WT)
Register 9.22. SYSTIMER_TARGET2_HI_REG (0x002C)
PR
HI
2_
ET
G
AR
_T
ER
IM
_T
ER
)
ed
M
rv
TI
se
S
SY
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_TARGET2_HI The alarm value to be loaded to COMP2, high 20 bits. (R/W)
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9 System Timer (SYSTIMER)
Register 9.23. SYSTIMER_TARGET2_LO_REG (0x0030)
LO
2_
ET
G
AR
_T
ER
IM
_T
ER
IM
ST
SY
31 0
0 Reset
SYSTIMER_TIMER_TARGET2_LO The alarm value to be loaded to COMP2, low 32 bits. (R/W)
RY
Register 9.24. SYSTIMER_TARGET2_CONF_REG (0x003C)
O L
M SE
DE
D_ _
O IT
RI UN
A D
PE R_
O
2_ E
RI
ET IM
PE
G 2_T
2_
AR T
ET
_T GE
G
ER AR
AR
IN
IM _T
_T
ST ER
ER
)
ed
SY TIM
IM
rv
ST
se
S
SY
SY
(re
31 30 29 26 25 0
0 0 0 0 0 0 0x00000 Reset
IM
SYSTIMER_TARGET2_PERIOD COMP2 alarm period. (R/W)
SYSTIMER_TARGET2_PERIOD_MODE Set COMP2 to period mode. (R/W)
SYSTIMER_TARGET2_TIMER_UNIT_SEL Select which unit to compare for COMP2. (R/W)
EL
Register 9.25. SYSTIMER_COMP2_LOAD_REG (0x0058)
AD
O
PR
_L
P2
M
O
_C
ER
IM
_T
ER
d)
M
e
rv
I
ST
se
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_COMP2_LOAD COMP2 synchronization enable signal. Set this bit to reload the
alarm value/period to COMP2. (WT)
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9 System Timer (SYSTIMER)
Register 9.26. SYSTIMER_INT_ENA_REG (0x0064)
ET NT A
T_ A
A
G 1_I _EN
IN N
EN
0_ _E
AR T T
_T GE _IN
ER AR T2
IM _T GE
ST ER AR
SY TIM _T
S ER
)
ed
SY TIM
v
er
S
s
SY
(re
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TARGET0_INT_ENA SYSTIMER_TARGET0_INT enable bit. (R/W)
RY
SYSTIMER_TARGET1_INT_ENA SYSTIMER_TARGET1_INT enable bit. (R/W)
SYSTIMER_TARGET2_INT_ENA SYSTIMER_TARGET2_INT enable bit. (R/W)
Register 9.27. SYSTIMER_INT_RAW_REG (0x0068)
A
ET NT AW
T_ W
W
IN A
RA
G 1_I _R
0_ _R
AR T T
_T GE _IN
IN
ER AR T2
IM _T GE
ST ER AR
SY TIM _T
S ER
)
ed
SY IM
rv
ST
se
SY
(re
IM
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TARGET0_INT_RAW SYSTIMER_TARGET0_INT raw bit. (R/WTC/SS)
SYSTIMER_TARGET1_INT_RAW SYSTIMER_TARGET1_INT raw bit. (R/WTC/SS)
EL
SYSTIMER_TARGET2_INT_RAW SYSTIMER_TARGET2_INT raw bit. (R/WTC/SS)
PR
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9 System Timer (SYSTIMER)
Register 9.28. SYSTIMER_INT_CLR_REG (0x006C)
ET NT LR
T_ R
R
IN L
CL
G 1_I _C
0_ _C
AR T T
_T GE _IN
ER AR T2
IM _T GE
ST ER AR
SY TIM _T
S ER
)
ed
SY TIM
rv
se
S
SY
(re
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TARGET0_INT_CLR SYSTIMER_TARGET0_INT clear bit. (WT)
RY
SYSTIMER_TARGET1_INT_CLR SYSTIMER_TARGET1_INT clear bit. (WT)
SYSTIMER_TARGET2_INT_CLR SYSTIMER_TARGET2_INT clear bit. (WT)
Register 9.29. SYSTIMER_INT_ST_REG (0x0070)
A
G 1_I _ST
IN T
ST
0_ _S
T_
AR T T
ET NT
_T GE _IN
IN
ER AR T2
IM _T GE
ST ER AR
SY TIM _T
S ER
)
ed
SY IM
rv
ST
se
SY
(re
31 3 2 1 0
IM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TARGET0_INT_ST SYSTIMER_TARGET0_INT status bit. (RO)
SYSTIMER_TARGET1_INT_ST SYSTIMER_TARGET1_INT status bit. (RO)
EL
SYSTIMER_TARGET2_INT_ST SYSTIMER_TARGET2_INT status bit. (RO)
Register 9.30. SYSTIMER_DATE_REG (0x00FC)
PR
E
AT
_D
ER
I M
ST
SY
31 0
0x2006171 Reset
SYSTIMER_DATE Version control register. (R/W)
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10 Timer Group (TIMG)
10 Timer Group (TIMG)
10.1 Overview
General purpose timers can be used to precisely time an interval, trigger an interrupt after a particular interval
(periodically and aperiodically), or act as a hardware clock. As shown in Figure 10-1, the ESP32-C3 chip contains
two timer groups, namely timer group 0 and timer group 1. Each timer group consists of one general purpose
timer referred to as T0 and one Main System Watchdog Timer. All general purpose timers are based on 16-bit
prescalers and 54-bit auto-reload-capable up-down counters.
A RY
IN
Figure 101. Timer Units within Groups
Note that while the Main System Watchdog Timer registers are described in this chapter, their functional
description is included in the Chapter 11 Watchdog Timers (WDT). Therefore, the term ‘timers’ within this chapter
IM
refers to the general purpose timers.
The timers’ features are summarized as follows:
• A 16-bit clock prescaler, from 2 to 65536
• A 54-bit time-base counter programmable to incrementing or decrementing
EL
• Able to read real-time value of the time-base counter
• Halting and resuming the time-base counter
• Programmable alarm generation
PR
• Timer value reload (Auto-reload at alarm or software-controlled instant reload)
• Level interrupt generation
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10 Timer Group (TIMG)
10.2 Functional Description
RY
Figure 102. Timer Group Architecture
Figure10-2 is a diagram of timer T0 in a timer group. T0 contains a clock selector, a 16-bit integer divider as a
prescaler, a timer-based counter and a comparator for alarm generation.
A
10.2.1 16bit Prescaler and Clock Selection
The timer can select between the APB clock (APB_CLK) or external clock (XTAL_CLK) as its clock source by
setting the TIMG_T0_USE_XTAL field of the TIMG_T0CONFIG_REG register. The selected clock is switched on
IN
by setting TIMG_TIMER_CLK_IS_ACTIVE field of the TIMG_REGCLK_REG register to 1 and switched off by
setting it to 0. The clock is then divided by a 16-bit prescaler to generate the time-base counter clock (TB_CLK)
used by the time-base counter. When the TIMG_T0_DIVIDER field is configured as 2 ~ 65536, the divisor of the
prescaler would be 2 ~ 65536. Note that programming value 0 to TIMG_T0_DIVIDER will result in the divisor
IM
being 65536. When the TIMG_T0_DIVIDER is set to 1, the actual divisor is 2 so the timer counter value
represents the half of real time.
To modify the 16-bit prescaler, please first configure the TIMG_T0_DIVIDER field, and then set
TIMG_T0_DIVIDER_RST to 1. Meanwhile, the timer must be disabled (i.e. TIMG_T0_EN should be cleared).
EL
Otherwise, the result can be unpredictable.
10.2.2 54bit Timebase Counter
The 54-bit time-base counters are based on TB_CLK and can be configured to increment or decrement via the
TIMG_T0_INCREASE field. The time-base counter can be enabled or disabled by setting or clearing the
PR
TIMG_T0_EN field, respectively. When enabled, the time-base counter increments or decrements on each cycle
of TB_CLK. When disabled, the time-base counter is essentially frozen. Note that the TIMG_T0_INCREASE field
can be changed while TIMG_T0_EN is set and this will cause the time-base counter to change direction
instantly.
To read the 54-bit value of the time-base counter, the timer value must be latched to two registers before being
read by the CPU (due to the CPU being 32-bit). By writing any value to the TIMG_T0UPDATE_REG, the current
value of the 54-bit timer is instantly latched into the TIMG_T0LO_REG and TIMG_T0HI_REG registers containing
the lower 32-bits and higher 22-bits, respectively. TIMG_T0LO_REG and TIMG_T0HI_REG registers will remain
unchanged for the CPU to read in its own time until TIMG_T0UPDATE_REG is written to again.
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10 Timer Group (TIMG)
10.2.3 Alarm Generation
A timer can be configured to trigger an alarm when the timer’s current value matches the alarm value. An alarm
will cause an interrupt to occur and (optionally) an automatic reload of the timer’s current value (see Section
10.2.4).
The 54-bit alarm value is configured using TIMG_T0ALARMLO_REG and TIMG_T0ALARMHI_REG, which
represent the lower 32-bits and higher 22-bits of the alarm value, respectively. However, the configured alarm
value is ineffective until the alarm is enabled by setting the TIMG_T0_ALARM_EN field. To avoid alarm being
enabled ‘too late’ (i.e. the timer value has already passed the alarm value when the alarm is enabled), the
hardware will trigger the alarm immediately if the current timer value is higher than the alarm value (within a
defined range) when the up-down counter increments, or lower than the alarm value (within a defined range)
RY
when the up-down counter decrements. Table 10-1 and Table 10-2 show the relationship between the current
value of the timer, the alarm value, and when an alarm is triggered.The current time value and the alarm value are
defined as follows:
• TIMG_VALUE = {TIMG_T0HI_REG, TIMG_T0LO_REG}
• ALARM_VALUE = {TIMG_T0ALARMHI_REG, TIMG_T0ALARMLO_REG}
A
Table 101. Alarm Generation When UpDown Counter Increments
Scenario Range Alarm
1 ALARM_VALUE − TIMG_VALUE > 2
IN53
Triggered
Triggered when the up-down counter counts
2 0 < ALARM_VALUE − TIMG_VALUE ≤ 253
TIMG_VALUE up to ALARM_VALUE
3 0 ≤ TIMG_VALUE − ALARM_VALUE < 2 53
Triggered
IM
Triggered when the up-down counter restarts
counting up from 0 after reaching the timer’s
4 TIMG_VALUE − ALARM_VALUE ≥ 253
maximum value and counts TIMG_VALUE up
to ALARM_VALUE
EL
Table 102. Alarm Generation When UpDown Counter Decrements
Scenario Range Alarm
5 TIMG_VALUE − ALARM_VALUE > 2 53
Triggered
PR
Triggered when the up-down counter counts
6 0 < TIMG_VALUE − ALARM_VALUE ≤ 253
TIMG_VALUE down to ALARM_VALUE
7 0 ≤ ALARM_VALUE − TIMG_VALUE < 2 53
Triggered
Triggered when the up-down counter restarts
counting down from the timer’s maximum value
8 ALARM_VALUE − TIMG_VALUE ≥ 253
after reaching the minimum value and counts
TIMG_VALUE down to ALARM_VALUE
When an alarm occurs, the TIMG_T0_ALARM_EN field is automatically cleared and no alarm will occur again until
the TIMG_T0_ALARM_EN is set next time.
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10 Timer Group (TIMG)
10.2.4 Timer Reload
A timer is reloaded when a timer’s current value is overwritten with a reload value stored in the
TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI fields that correspond to the lower 32-bits and higher 22-bits of
the timer’s new value, respectively. However, writing a reload value to TIMG_T0_LOAD_LO and
TIMG_T0_LOAD_HI will not cause the timer’s current value to change. Instead, the reload value is ignored by the
timer until a reload event occurs. A reload event can be triggered either by a software instant reload or an
auto-reload at alarm.
A software instant reload is triggered by the CPU writing any value to TIMG_T0LOAD_REG, which causes the
timer’s current value to be instantly reloaded. If TIMG_T0_EN is set, the timer will continue incrementing or
decrementing from the new value. If TIMG_T0_EN is cleared, the timer will remain frozen at the new value until
RY
counting is re-enabled.
An auto-reload at alarm will cause a timer reload when an alarm occurs, thus allowing the timer to continue
incrementing or decrementing from the reload value. This is generally useful for resetting the timer’s value when
using periodic alarms. To enable auto-reload at alarm, the TIMG_T0_AUTORELOAD field should be set. If not
enabled, the timer’s value will continue to increment or decrement past the alarm value after an alarm.
A
10.2.5 SLOW_CLK Frequency Calculation
Via XTAL_CLK, a timer could calculate the frequency of clock sources for SLOW_CLK (i.e. RTC_CLK,
RTC20M_D256_CLK, and XTAL32K_CLK) as follows:
IN
1. Start periodic or one-shot frequency calculation;
2. Once receiving the signal to start calculation, the counter of XTAL_CLK and the counter of SLOW_CLK
IM
begin to work at the same time. When the counter of SLOW_CLK counts to C0, the two counters stop
counting simultaneously;
3. Assume the value of XTAL_CLK’s counter is C1, and the frequency of SLOW_CLK would be calculated as:
C0×f _XT AL_CLK
f _rtc = C1
EL
10.2.6 Interrupts
Each timer has its own interrupt line that can be routed to the CPU, and thus each timer group has a total of two
interrupt lines. Timers generate level interrupts that must be explicitly cleared by the CPU on each
triggering.
PR
Interrupts are triggered after an alarm (or stage timeout for watchdog timers) occurs. Level interrupts will be held
high after an alarm (or stage timeout) occurs, and will remain so until manually cleared. To enable a timer’s
interrupt, the TIMG_T0_INT_ENA bit should be set.
The interrupts of each timer group are governed by a set of registers. Each timer within the group has a
corresponding bit in each of these registers:
• TIMG_T0_INT_RAW : An alarm event sets it to 1. The bit will remain set until the timer’s corresponding bit in
TIMG_T0_INT_CLR is written.
• TIMG_WDT_INT_RAW : A stage time out will set the timer’s bit to 1. The bit will remain set until the timer’s
corresponding bit in TIMG_WDT_INT_CLR is written.
• TIMG_T0_INT_ST : Reflects the status of each timer’s interrupt and is generated by masking the bits of
TIMG_T0_INT_RAW with TIMG_T0_INT_ENA.
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10 Timer Group (TIMG)
• TIMG_WDT_INT_ST : Reflects the status of each watchdog timer’s interrupt and is generated by masking
the bits of TIMG_WDT_INT_RAW with TIMG_WDT_INT_ENA.
• TIMG_T0_INT_ENA : Used to enable or mask the interrupt status bits of timers within the group.
• TIMG_WDT_INT_ENA : Used to enable or mask the interrupt status bits of watchdog timer within the group.
• TIMG_T0_INT_CLR : Used to clear a timer’s interrupt by setting its corresponding bit to 1. The timer’s
corresponding bit in TIMG_T0_INT_RAW and TIMG_T0_INT_ST will be cleared as a result. Note that a
timer’s interrupt must be cleared before the next interrupt occurs.
• TIMG_WDT_INT_CLR : Used to clear a timer’s interrupt by setting its corresponding bit to 1. The watchdog
timer’s corresponding bit in TIMG_WDT_INT_RAW and TIMG_WDT_INT_ST will be cleared as a result.
Note that a watchdog timer’s interrupt must be cleared before the next interrupt occurs.
RY
10.3 Configuration and Usage
10.3.1 Timer as a Simple Clock
1. Configure the time-base counter
A
• Select clock source by setting or clearing TIMG_T0_USE_XTAL field.
• Configure the 16-bit prescaler by setting TIMG_T0_DIVIDER.
IN
• Configure the timer direction by setting or clearing TIMG_T0_INCREASE.
• Set the timer’s starting value by writing the starting value to TIMG_T0_LOAD_LO and
TIMG_T0_LOAD_HI, then reloading it into the timer by writing any value to TIMG_T0LOAD_REG.
IM
2. Start the timer by setting TIMG_T0_EN.
3. Get the timer’s current value.
• Write any value to TIMG_T0UPDATE_REG to latch the timer’s current value.
EL
• Read the latched timer value from TIMG_T0LO_REG and TIMG_T0HI_REG.
10.3.2 Timer as Oneshot Alarm
1. Configure the time-base counter following step 1 of Section 10.3.1.
2. Configure the alarm.
PR
• Configure the alarm value by setting TIMG_T0ALARMLO_REG and TIMG_T0ALARMHI_REG.
• Enable interrupt by setting TIMG_T0_INT_ENA.
3. Disable auto reload by clearing TIMG_T0_AUTORELOAD.
4. Start the alarm by setting TIMG_T0_ALARM_EN.
5. Handle the alarm interrupt.
• Clear the interrupt by setting the timer’s corresponding bit in TIMG_T0_INT_CLR.
• Disable the timer by clearing TIMG_T0_EN.
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10.3.3 Timer as Periodic Alarm
1. Configure the time-base counter following step 1 in Section 10.3.1.
2. Configure the alarm following step 2 in Section 10.3.2.
3. Enable auto reload by setting TIMG_T0_AUTORELOAD and configure the reload value via
TIMG_T0_LOAD_LO and TIMG_T0_LOAD_HI.
4. Start the alarm by setting TIMG_T0_ALARM_EN.
5. Handle the alarm interrupt (repeat on each alarm iteration).
• Clear the interrupt by setting the timer’s corresponding bit in TIMG_T0_INT_CLR.
RY
• If the next alarm requires a new alarm value and reload value (i.e. different alarm interval per iteration),
then TIMG_T0ALARMLO_REG, TIMG_T0ALARMHI_REG, TIMG_T0_LOAD_LO, and
TIMG_T0_LOAD_HI should be reconfigured as needed. Otherwise, the aforementioned registers
should remain unchanged.
• Re-enable the alarm by setting TIMG_T0_ALARM_EN.
A
6. Stop the timer (on final alarm iteration).
• Clear the interrupt by setting the timer’s corresponding bit in TIMG_T0_INT_CLR.
IN
• Disable the timer by clearing TIMG_T0_EN.
10.3.4 SLOW_CLK Frequency Calculation
1. One-shot frequency calculation
IM
• Select the clock whose frequency is to be calculated (clock source of SLOW_CLK) via
TIMG_RTC_CALI_CLK_SEL, and configure the time of calculation via TIMG_RTC_CALI_MAX.
• Select one-shot frequency calculation by clearing TIMG_RTC_CALI_START_CYCLING, and enable
the two counters via TIMG_RTC_CALI_START.
EL
• Once TIMG_RTC_CALI_RDY becomes 1, read TIMG_RTC_CALI_VALUE to get the value of
XTAL_CLK’s counter, and calculate the frequency of SLOW_CLK.
2. Periodic frequency calculation
• Select the clock whose frequency is to be calculated (clock source of SLOW_CLK) via
PR
TIMG_RTC_CALI_CLK_SEL, and configure the time of calculation via TIMG_RTC_CALI_MAX.
• Select periodic frequency calculation by enabling TIMG_RTC_CALI_START_CYCLING.
• When TIMG_RTC_CALI_CYCLING_DATA_VLD is 1, TIMG_RTC_CALI_VALUE is valid.
3. Timeout
If the counter of SLOW_CLK cannot finish counting in TIMG_RTC_CALI_TIMEOUT_RST_CNT cycles,
TIMG_RTC_CALI_TIMEOUT will be set to indicate a timeout.
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10.4 Register Summary
The addresses in this section are relative to Timer Group base addresses (one for Timer Group 0 and another
one for Timer Group 1) provided in Table 3-4 in Chapter 3 System and Memory.
Name Description Address Access
T0 control and configuration registers
TIMG_T0CONFIG_REG Timer 0 configuration register 0x0000 varies
TIMG_T0LO_REG Timer 0 current value, low 32 bits 0x0004 RO
TIMG_T0HI_REG Timer 0 current value, high 22 bits 0x0008 RO
TIMG_T0UPDATE_REG Write to copy current timer value to 0x000C R/W/SC
TIMGn_T0_(LO/HI)_REG
RY
TIMG_T0ALARMLO_REG Timer 0 alarm value, low 32 bits 0x0010 R/W
TIMG_T0ALARMHI_REG Timer 0 alarm value, high bits 0x0014 R/W
TIMG_T0LOADLO_REG Timer 0 reload value, low 32 bits 0x0018 R/W
TIMG_T0LOADHI_REG Timer 0 reload value, high 22 bits 0x001C R/W
TIMG_T0LOAD_REG Write to reload timer from 0x0020 WT
A
TIMG_T0_(LOADLOLOADHI)_REG
WDT control and configuration registers
TIMG_WDTCONFIG0_REG Watchdog timer configuration register 0x0048 varies
TIMG_WDTCONFIG1_REG
TIMG_WDTCONFIG2_REG
IN
Watchdog timer prescaler register
Watchdog timer stage 0 timeout value
0x004C
0x0050
varies
R/W
TIMG_WDTCONFIG3_REG Watchdog timer stage 1 timeout value 0x0054 R/W
TIMG_WDTCONFIG4_REG Watchdog timer stage 2 timeout value 0x0058 R/W
IM
TIMG_WDTCONFIG5_REG Watchdog timer stage 3 timeout value 0x005C R/W
TIMG_WDTFEED_REG Write to feed the watchdog timer 0x0060 WT
TIMG_WDTWPROTECT_REG Watchdog write protect register 0x0064 R/W
RTC frequency calculation control and configuration registers
TIMG_RTCCALICFG_REG RTC frequency calculation configuration reg- 0x0068 varies
EL
ister 0
TIMG_RTCCALICFG1_REG RTC frequency calculation configuration reg- 0x006C RO
ister 1
TIMG_RTCCALICFG2_REG RTC frequency calculation configuration reg- 0x0080 varies
ister 2
PR
Interrupt registers
TIMG_INT_ENA_TIMERS_REG Interrupt enable bits 0x0070 R/W
TIMG_INT_RAW_TIMERS_REG Raw interrupt status 0x0074 R/SS/WTC
TIMG_INT_ST_TIMERS_REG Masked interrupt status 0x0078 RO
TIMG_INT_CLR_TIMERS_REG Interrupt clear bits 0x007C WT
Version register
TIMG_NTIMERS_DATE_REG Timer version control register 0x00F8 R/W
Clock configuration registers
TIMG_REGCLK_REG Timer group clock gate register 0x00FC R/W
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10.5 Registers
The addresses in this section are relative to Timer Group base address provided in Table 3-4 in Chapter 3 System
and Memory.
Register 10.1. TIMG_T0CONFIG_REG (0x0000)
AD
ST
LO
E_ _EN
_R
TO SE
AL
RE
ER
XT
AU EA
US M
E
0_ AR
ID
M d ID
0_ R
_T C
IV
TI rve DIV
TI _T N
_T L
G _IN
G _A
G _E
0_
se 0_
G )
)
ed
M 0
M 0
M 0
TI _T
_T
(re _T
TI _T
rv
G
se
M
(re
TI
TI
TI
31 30 29 28 13 12 11 10 9 8 0
RY
0 1 1 0x01 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_T0_USE_XTAL 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as
the source clock of timer group. (R/W)
TIMG_T0_ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an alarm
A
occurs. (R/W/SC)
TIMG_T0_DIVIDER_RST When set, Timer 0 ’s clock divider counter will be reset. (WT)
IN
TIMG_T0_DIVIDER Timer 0 clock (T0_clk) prescaler value. (R/W)
TIMG_T0_AUTORELOAD When set, Timer 0 auto-reload at alarm is enabled. (R/W)
TIMG_T0_INCREASE When set, the Timer 0 time-base counter will increment every clock tick. When
IM
cleared, the Timer 0 time-base counter will decrement. (R/W)
TIMG_T0_EN When set, the Timer 0 time-base counter is enabled. (R/W)
EL
Register 10.2. TIMG_T0LO_REG (0x0004)
LO
0_
_T
G
M
TI
31 0
PR
0x000000 Reset
TIMG_T0_LO After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter of
Timer 0 can be read here. (RO)
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Register 10.3. TIMG_T0HI_REG (0x0008)
HI
0_
d)
ve
_T
r
G
se
M
(re
TI
31 22 21 0
0 0 0 0 0 0 0 0 0 0 0x0000 Reset
TIMG_T0_HI After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter of
Timer 0 can be read here. (RO)
RY
Register 10.4. TIMG_T0UPDATE_REG (0x000C)
TE
DA
UP
0_
)
ed
_T
rv
G
se
M
(re
TI
31 30 0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_T0_UPDATE After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
(R/W/SC)
IN
Register 10.5. TIMG_T0ALARMLO_REG (0x0010)
IM
O
_L
RM
LA
0 _A
_T
G
M
TI
EL
31 0
0x000000 Reset
TIMG_T0_ALARM_LO Timer 0 alarm trigger time-base counter value, low 32 bits. (R/W)
PR
Register 10.6. TIMG_T0ALARMHI_REG (0x0014)
I
_H
RM
LA
A
0_
e d)
_T
rv
G
se
M
(re
TI
31 22 21 0
0 0 0 0 0 0 0 0 0 0 0x0000 Reset
TIMG_T0_ALARM_HI Timer 0 alarm trigger time-base counter value, high 22 bits. (R/W)
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Register 10.7. TIMG_T0LOADLO_REG (0x0018)
O
_L
AD
LO
0_
_T
G
M
TI
31 0
0x000000 Reset
TIMG_T0_LOAD_LO Low 32 bits of the value that a reload will load onto Timer 0 time-base counter.
(R/W)
RY
Register 10.8. TIMG_T0LOADHI_REG (0x001C)
I
_H
AD
LO
0_
d)
ve
_T
r
A
se
M
(re
TI
31 22 21 0
0 0 0 0 0 0 0 0 0 0 0x0000 Reset
IN
TIMG_T0_LOAD_HI High 22 bits of the value that a reload will load onto Timer 0 time-base counter.
(R/W)
IM
Register 10.9. TIMG_T0LOAD_REG (0x0020)
AD
LO
0_
_T
G
EL
M
TI
31 0
0x000000 Reset
TIMG_T0_LOAD Write any value to trigger a Timer 0 time-base counter reload. (WT)
PR
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Register 10.10. TIMG_WDTCONFIG0_REG (0x0048)
RE ET EN
TH
TH
SE _EN
EN
U_ ES D_
EN
NG
T_
CP _R MO
EN
L E_
LE
_L
TA AT
PP U _
T_
T
ET
_X PD
_A C O
SE
DT O O
S
SE _U
RE
B
RE
P
_W _ SH
_U NF
_
0
_
PU
TG
TI _W STG
YS
G DT LA
DT O
_W EN
R
ST
ST
_C
_S
P
TI _W _F
_
T_
_W _
_
DT
DT
DT
DT
G DT
DT
DT
G DT
D
d)
_W
_W
_W
_W
_W
_W
TI _W
ve
r
G
se
M
M
M
M
M
M
(re
TI
TI
TI
TI
TI
TI
TI
TI
TI
31 30 29 28 27 26 25 24 23 22 21 20 18 17 15 14 13 12 11 0
0 0 0 0 0 0 0 0x1 0x1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_WDT_APPCPU_RESET_EN WDT reset CPU enable. (R/W)
RY
TIMG_WDT_PROCPU_RESET_EN WDT reset CPU enable. (R/W)
TIMG_WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. (R/W)
TIMG_WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns, 2:
300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W)
A
TIMG_WDT_CPU_RESET_LENGTH CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300
ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W)
TIMG_WDT_USE_XTAL Chooses WDT clock. 0: APB_CLK; 1:XTAL_CLK. (R/W)
IN
TIMG_WDT_CONF_UPDATE_EN Updates the WDT configuration registers. (WT)
TIMG_WDT_STG3 Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W)
IM
TIMG_WDT_STG2 Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W)
TIMG_WDT_STG1 Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W)
TIMG_WDT_STG0 Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. (R/W)
EL
TIMG_WDT_EN When set, MWDT is enabled. (R/W)
Register 10.11. TIMG_WDTCONFIG1_REG (0x004C)
PR
E
AL
T
SC
RS
RE
T_
_P
CN
LK
IV
_C
_D
DT
DT
d)
_W
_W
e
rv
G
G
se
M
M
(re
TI
TI
31 16 15 1 0
0x01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_WDT_DIVCNT_RST When set, WDT ’s clock divider counter will be reset. (WT)
TIMG_WDT_CLK_PRESCALE MWDT clock prescaler value. MWDT clock period = 12.5 ns *
TIMG_WDT_CLK_PRESCALE. (R/W)
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Register 10.12. TIMG_WDTCONFIG2_REG (0x0050)
LD
HO
0_
TG
_S
DT
_W
G
M
TI
31 0
26000000 Reset
TIMG_WDT_STG0_HOLD Stage 0 timeout value, in MWDT clock cycles. (R/W)
RY
Register 10.13. TIMG_WDTCONFIG3_REG (0x0054)
LD
HO
1_
TG
_S
DT
A
_W
G
M
TI
31 0
IN
0x7ffffff
TIMG_WDT_STG1_HOLD Stage 1 timeout value, in MWDT clock cycles. (R/W)
Reset
IM
Register 10.14. TIMG_WDTCONFIG4_REG (0x0058)
LD
HO
2_
G
T
_S
EL
DT
_W
G
M
TI
31 0
0x0fffff Reset
TIMG_WDT_STG2_HOLD Stage 2 timeout value, in MWDT clock cycles. (R/W)
PR
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Register 10.15. TIMG_WDTCONFIG5_REG (0x005C)
LD
HO
3_
GT
_S
DT
_W
G
M
TI
31 0
0x0fffff Reset
TIMG_WDT_STG3_HOLD Stage 3 timeout value, in MWDT clock cycles. (R/W)
RY
Register 10.16. TIMG_WDTFEED_REG (0x0060)
D
EE
_F
DT
_W
G
M
A
TI
31 0
0x000000
IN Reset
TIMG_WDT_FEED Write any value to feed the MWDT. (WO) (WT)
Register 10.17. TIMG_WDTWPROTECT_REG (0x0064)
IM
Y
KE
_W
DT
_W
G
M
TI
EL
31 0
0x50d83aa1 Reset
TIMG_WDT_WKEY If the register contains a different value than its reset value, write protection is
enabled. (R/W)
PR
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Register 10.18. TIMG_RTCCALICFG_REG (0x0068)
G
IN
CL
CY
ST EL
T_
AL K_S
T
AR
AR
AX
Y
_C RD
L
ST
_M
C
I_
TC LI_
TC LI_
I_
LI
AL
CA
A
_C
_C
_C
_
TC
TC
TC
)
ed
_R
_R
_R
_R
_R
rv
G
se
M
(re
TI
TI
TI
TI
TI
31 30 16 15 14 13 12 11 0
0 0x01 0 0x1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_RTC_CALI_START_CYCLING Enables periodic frequency calculation. (R/W)
RY
TIMG_RTC_CALI_CLK_SEL 0: RTC_CLK; 1: RTC20M_D256_CLK; 2: XTAL32K_CLK. (R/W)
TIMG_RTC_CALI_RDY Marks the completion of frequency calculation. (RO)
TIMG_RTC_CALI_MAX Configures the time of frequency calculation. (R/W)
A
TIMG_RTC_CALI_START Enables one-shot frequency calculation. (R/W)
IN
Register 10.19. TIMG_RTCCALICFG1_REG (0x006C)
D
VL
A_
AT
_D
IM
G
IN
E
CL
LU
CY
VA
_
I_
LI
AL
CA
_C
C_
TC
)
T
ed
_R
_R
rv
G
G
se
M
M
(re
TI
TI
EL
31 7 6 1 0
0x00000 0 0 0 0 0 0 0 Reset
TIMG_RTC_CALI_CYCLING_DATA_VLD Marks the completion of periodic frequency calculation.
(RO)
PR
TIMG_RTC_CALI_VALUE Frequency calculation result. (RO)
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Register 10.20. TIMG_RTCCALICFG2_REG (0x0080)
NT
S
_C
E
HR
ST
_R
_T
UT
UT
UT
EO
EO
EO
M
M
TI
TI
TI
I_
I_
I_
AL
AL
AL
_C
_C
_C
TC
TC
TC
)
ed
_R
_R
_R
rv
G
G
se
M
M
(re
TI
TI
TI
31 7 6 3 2 1 0
0x1ffffff 3 0 0 0 Reset
RY
TIMG_RTC_CALI_TIMEOUT Indicates frequency calculation timeout. (RO)
TIMG_RTC_CALI_TIMEOUT_RST_CNT Cycles to reset frequency calculation timeout. (R/W)
TIMG_RTC_CALI_TIMEOUT_THRES Threshold value for the frequency calculation timer. If the
timer’s value exceeds this threshold, a timeout is triggered. (R/W)
A
Register 10.21. TIMG_INT_ENA_TIMERS_REG (0x0070)
IN
EN A
T_ N
A
IN _E
0_ INT
_T _
G DT
d)
TI _W
e
rv
G
se
M
M
(re
TI
IM
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_T0_INT_ENA The interrupt enable bit for the TIMG_T0_INT interrupt. (R/W)
TIMG_WDT_INT_ENA The interrupt enable bit for the TIMG_WDT_INT interrupt. (R/W)
EL
Register 10.22. TIMG_INT_RAW_TIMERS_REG (0x0074)
RA W
PR
T_ A
W
IN _R
0_ INT
_T _
G DT
d)
TI _W
e
rv
G
se
M
M
(re
TI
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_T0_INT_RAW The raw interrupt status bit for the TIMG_T0_INT interrupt. (R/SS/WTC)
TIMG_WDT_INT_RAW The raw interrupt status bit for the TIMG_WDT_INT interrupt. (R/SS/WTC)
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Register 10.23. TIMG_INT_ST_TIMERS_REG (0x0078)
T_ T
IN _S
ST
0_ INT
_T _
G DT
)
ed
TI _W
v
er
G
M
M
s
(re
TI
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_T0_INT_ST The masked interrupt status bit for the TIMG_T0_INT interrupt. (RO)
TIMG_WDT_INT_ST The masked interrupt status bit for the TIMG_WDT_INT interrupt. (RO)
RY
Register 10.24. TIMG_INT_CLR_TIMERS_REG (0x007C)
CL R
T_ L
R
IN _C
0_ INT
_T _
G DT
A
)
ed
TI _W
rv
G
se
M
M
(re
TI
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN
0
TIMG_T0_INT_CLR Set this bit to clear the TIMG_T0_INT interrupt. (WT)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_WDT_INT_CLR Set this bit to clear the TIMG_WDT_INT interrupt. (WT)
IM
Register 10.25. TIMG_NTIMERS_DATE_REG (0x00F8)
TE
DA
EL
S_
G
M
TI
)
ed
_N
rv
G
se
M
(re
TI
31 28 27 0
0 0 0 0 0x2006191 Reset
PR
TIMG_NTIMGS_DATE Timer version control register (R/W)
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Register 10.26. TIMG_REGCLK_REG (0x00FC)
TI E
AC TIV
VE
S_ C
_I _A
LK IS
_C LK_
DT _C
M IM N
TI _T E
_W R
G K_
G E
d)
M L
TI _C
ve
er
G
M
s
(re
TI
31 30 29 28 0
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_WDT_CLK_IS_ACTIVE enable WDT’s clock (R/W)
RY
TIMG_TIMER_CLK_IS_ACTIVE enable Timer 0’s clock (R/W)
TIMG_CLK_EN Register clock gate signal. 0: The clock used by software to read and write registers
is on only when there is software operation. 1: The clock used by software to read and write
registers is always on. (R/W)
A
IN
IM
EL
PR
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11 Watchdog Timers (WDT)
11 Watchdog Timers (WDT)
11.1 Overview
Watchdog timers are hardware timers used to detect and recover from malfunctions. They must be periodically
fed (reset) to prevent a timeout. A system/software that is behaving unexpectedly (e.g. is stuck in a software loop
or in overdue events) will fail to feed the watchdog thus trigger a watchdog timeout. Therefore, watchdog timers
are useful for detecting and handling erroneous system/software behavior.
As shown in Figure 11-1, ESP32-C3 contains three digital watchdog timers: one in each of the two timer groups
in Chapter 10 Timer Group (TIMG)(called Main System Watchdog Timers, or MWDT) and one in the RTC Module
RY
(called the RTC Watchdog Timer, or RWDT). Each digital watchdog timer allows for four separately configurable
stages and each stage can be programmed to take one action upon expiry, unless the watchdog is fed or
disabled. MWDT supports three timeout actions: interrupt, CPU reset, and core reset, while RWDT supports four
timeout actions: interrupt, CPU reset, core reset, and system reset (see details in Section 11.2.2.2 Stages and
Timeout Actions). A timeout value can be set for each stage individually.
During the flash boot process, RWDT and the first MWDT in timergroup 0 are enabled automatically in order to
A
detect and recover from booting errors.
ESP32-C3 also has one analog watchdog timer: Super watchdog (SWD). It is an ultra-low-power circuit in
IN
analog domain that helps to prevent the system from operating in a sub-optimal state and resets the system if
required.
IM
EL
PR
Figure 111. Watchdog Timers Overview
Note that while this chapter provides the functional descriptions of the watchdog timer’s, their register
descriptions are provided in Chapter 10 Timer Group (TIMG) and Chapter 4 Low-Power Management (RTC_CNTL)
[to be added later].
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11.2 Digital Watchdog Timers
11.2.1 Features
Watchdog timers have the following features:
• Four stages, each with a programmable timeout value. Each stage can be configured and
enabled/disabled separately
• Three timeout actions (interrupt, CPU reset, or core reset) for MWDT and four timeout actions (interrupt,
CPU reset, core reset, or system reset) for RWDT upon expiry of each stage
• 32-bit expiry counter
RY
• Write protection, to prevent RWDT and MWDT configuration from being altered inadvertently
• Flash boot protection
If the boot process from an SPI flash does not complete within a predetermined period of time, the
watchdog will reboot the entire main system.
A
11.2.2 Functional Description
IN
IM
EL
PR
Figure 112. Watchdog Timers in ESP32C3
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Figure 11-2 shows the three watchdog timers in ESP32-C3 digital systems.
11.2.2.1 Clock Source and 32Bit Counter
At the core of each watchdog timer is a 32-bit counter.
MWDTs can select between the APB clock (APB_CLK) or external clock (XTAL_CLK) as its clock source by
setting the TIMG_WDT_USE_XTAL field of the TIMG_WDTCONFIG0_REG register. The selected clock is
switched on by setting TIMG_WDT_CLK_IS_ACTIVE field of the TIMG_REGCLK_REG register to 1 and switched
off by setting it to 0. Then the selected clock is divided by a 16-bit configurable prescaler. The 16-bit prescaler
for MWDTs is configured via the TIMG_WDT_CLK_PRESCALE field of TIMG_WDTCONFIG1_REG.When
TIMG_WDT_DIVCNT_RST field is set, the prescaler is reset and it can be re-configured at once.
RY
In contrast, the clock source of RWDT is derived directly from an RTC slow clock (the RTC slow clock source
shown in Chapter 6 Reset and Clock).
MWDTs and RWDT are enabled by setting the TIMG_WDT_EN and RTC_CNTL_WDT_EN fields respectively.
When enabled, the 32-bit counters of each watchdog will increment on each source clock cycle until the timeout
value of the current stage is reached (i.e. expiry of the current stage). When this occurs, the current counter value
A
is reset to zero and the next stage will become active. If a watchdog timer is fed by software, the timer will return
to stage 0 and reset its counter value to zero. Software can feed a watchdog timer by writing any value to
TIMG_WDTFEED_REG for MDWTs and RTC_CNTL_RTC_WDT_FEED for RWDT.
11.2.2.2 Stages and Timeout Actions
IN
Timer stages allow for a timer to have a series of different timeout values and corresponding expiry action. When
IM
one stage expires, the expiry action is triggered, the counter value is reset to zero, and the next stage becomes
active. MWDTs/ RWDT provide four stages (called stages 0 to 3). The watchdog timers will progress through
each stage in a loop (i.e. from stage 0 to 3, then back to stage 0).
Timeout values of each stage for MWDTs are configured in TIMG_WDTCONFIGi_REG (where i ranges from 2 to
5), whilst timeout values for RWDT are configured using RTC_CNTL_WDT_STGj_HOLD field (where j ranges from
EL
0 to 3).
Please note that the timeout value of stage 0 for RWDT (Thold0 ) is determined by the combination of the
EFUSE_WDT_DELAY_SEL field of eFuse register EFUSE_RD_REPEAT_DATA1_REG and
RTC_CNTL_WDT_STG0_HOLD. The relationship is as follows:
PR
Thold0 = RT C_CN T L_W DT _ST G0_HOLD << (EF U SE_W DT _DELAY _SEL + 1)
where << is a left-shift operator.
Upon the expiry of each stage, one of the following expiry actions will be executed:
• Trigger an interrupt
When the stage expires, an interrupt is triggered.
• CPU reset – Reset a CPU core
When the stage expires, the CPU core will be reset.
• Core reset – Reset the main system
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When the stage expires, the main system (which includes MWDTs, CPU, and all peripherals) will be reset.
The power management unit and RTC peripheral will not be reset.
• System reset – Reset the main system, power management unit and RTC peripheral
When the stage expires the main system, power management unit and RTC peripheral (see details in
Chapter 4 Low-Power Management (RTC_CNTL) [to be added later]) will all be reset. This action is only
available in RWDT.
• Disabled
This stage will have no effects on the system.
For MWDTs, the expiry action of all stages is configured in TIMG_WDTCONFIG0_REG. Likewise for RWDT, the
expiry action is configured in RTC_CNTL_WDTCONFIG0_REG.
RY
11.2.2.3 Write Protection
Watchdog timers are critical to detecting and handling erroneous system/software behavior, thus should not be
disabled easily (e.g. due to a misplaced register write). Therefore, MWDTs and RWDT incorporate a write
protection mechanism that prevent the watchdogs from being disabled or tampered with due to an accidental
A
write. The write protection mechanism is implemented using a write-key field for each timer (TIMG_WDT_WKEY
for MWDT, RTC_CNTL_WDT_WKEY for RWDT). The value 0x50D83AA1 must be written to the watchdog timer’s
write-key field before any other register of the same watchdog timer can be changed. Any attempts to write to a
IN
watchdog timer’s registers (other than the write-key field itself) whilst the write-key field’s value is not
0x50D83AA1 will be ignored. The recommended procedure for accessing a watchdog timer is as follows:
1. Disable the write protection by writing the value 0x50D83AA1 to the timer’s write-key field.
IM
2. Make the required modification of the watchdog such as feeding or changing its configuration.
3. Re-enable write protection by writing any value other than 0x50D83AA1 to the timer’s write-key field.
11.2.2.4 Flash Boot Protection
EL
During flash booting process, MWDT in timer group 0 (see Figure 10-1 Timer Units within Groups), as well as
RWDT, are automatically enabled. Stage 0 for the enabled MWDT is automatically configured to reset the system
upon expiry. Likewise, stage 0 for RWDT is configured to reset the main system and RTC when it expires. After
booting, TIMG_WDT_FLASHBOOT_MOD_EN and RTC_CNTL_WDT_FLASHBOOT_MOD_EN should be cleared
to stop the flash boot protection procedure for both MWDT and RWDT respectively. After this, MWDT and RWDT
PR
can be configured by software.
11.3 Super Watchdog
Super watchdog (SWD) is an ultra-low-power circuit in analog domain that helps to prevent the system from
operating in a sub-optimal state and resets the system if required. SWD contains a watchdog circuit that needs
to be fed for at least once during its timeout period, which is slightly less than one second. About 100 ms before
watchdog timeout, it will also send out a WD_INTR signal as a request to remind the system to feed the
watchdog.
If the system doesn’t respond to SWD feed request and watchdog finally times out, SWD will generate a system
level signal SWD_RSTB to reset whole digital circuits on the chip.
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11.3.1 Features
SWD has the following features:
• Ultra-low power
• Interrupt to indicate that the SWD timeout period is close to expiring
• Various dedicated methods for software to feed SWD, which enables SWD to monitor the working state of
the whole operating system
11.3.2 Super Watchdog Controller
11.3.2.1 Structure
A RY
IN
IM
Figure 113. Super Watchdog Controller Structure
EL
11.3.2.2 Workflow
In normal state:
• SWD controller receives feed request from SWD.
PR
• SWD controller can send an interrupt to main CPU or ULP-RISC-V.
• Main CPU can decide whether to feed SWD directly by setting RTC_CNTL_SWD_FEED, or send an
interrupt to ULP-RISC-V and ask ULP-RISC-V to feed SWD by setting RTC_CNTL_SWD_FEED.
• When trying to feed SWD, CPU or ULP-RISC-V needs to disable SWD controller’s write protection by
writing 0x8F1D312A to RTC_CNTL_SWD_WKEY. This prevents SWD from being fed by mistake when the
system is operating in sub-optimal state.
• If setting RTC_CNTL_SWD_AUTO_FEED_EN to 1, SWD controller can also feed SWD itself without any
interaction with CPU or ULP-RISC-V.
After reset:
• Check RTC_CNTL_RESET_CAUSE_PROCPU[5:0] for the cause of CPU reset.
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If RTC_CNTL_RESET_CAUSE_PROCPU[5:0] == 0x12, it indicates that the cause is SWD reset.
• Set RTC_CNTL_SWD_RST_FLAG_CLR to clear the SWD reset flag.
11.4 Interrupts
For watchdog timer interrupts, please refer to Section 10.2.6 Interrupts in Chapter 10 Timer Group (TIMG).
11.5 Registers
MWDT registers are part of the timer submodule and are described in Section 10.4 Register Summary in Chapter
10 Timer Group (TIMG). RWDT and SWD registers are part of the RTC submodule and are described in Section 6
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Register Summary in Chapter 4 Low-Power Management (RTC_CNTL) [to be added later].
A
IN
IM
EL
PR
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12 XTAL32K Watchdog Timers (XTWDT)
12.1 Overview
The XTAL32K watchdog timer on ESP32-C3 is used to monitor the status of external crystal XTAL32K_CLK. This
watchdog timer can detect the oscillation failure of XTAL32K_CLK, change the clock source of RTC, etc. When
XTAL32K_CLK works as the clock source of RTC SLOW_CLK (for clock description, see Chapter 6 Reset and
Clock) and stops vibrating, the XTAL32K watchdog timer first switches to BACKUP32K_CLK derived from
RTC_CLK and generates an interrupt (if the chip is in Light-sleep and Deep-sleep mode, the CPU will be woken
up), and then switches back to XTAL32K_CLK after it is restarted by software.
A RY
IN
IM
Figure 121. XTAL32K Watchdog Timer
EL
12.2 Features
12.2.1 Interrupt and WakeUp
When the XTAL32K watchdog timer detects the oscillation failure of XTAL32K_CLK, an oscillation failure interrupt
RTC_XTAL32K_DEAD_INT (for interrupt description, please refer to Chapter 4 Low-Power Management
PR
(RTC_CNTL) [to be added later]) is generated. At this point, the CPU will be woken up if in Light-sleep and
Deep-sleep mode.
12.2.2 BACKUP32K_CLK
Once the XTAL32K watchdog timer detects the oscillation failure of XTAL32K_CLK, it replaces XTAL32K_CLK
with BACKUP32K_CLK (with a frequency of 32 kHz or so) derived from RTC_CLK as RTC’s SLOW_CLK, so as
to ensure proper functioning of the system.
12.3 Functional Description
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12.3.1 Workflow
1. The XTAL32K watchdog timer starts counting when RTC_CNTL_XTAL32K_WDT_EN is enabled. The
counter based on RTC_CLK keeps counting until it detects the positive edge of XTAL_32K and is then
cleared. When the counter reaches RTC_CNTL_XTAL32K_WDT_TIMEOUT, it generates an interrupt or a
wake-up signal and is then reset.
2. If RTC_CNTL_XTAL32K_AUTO_BACKUP is set and step 1 is finished, the XTAL32K watchdog timer will
automatically enable BACKUP32K_CLK as the alternative clock source of RTC SLOW_CLK, to ensure the
system’s proper functioning and the accuracy of timers running on RTC SLOW_CLK (e.g. RTC_TIMER).
For information about clock frequency configuration, please refer to Section 12.3.2.
3. Software restarts XTAL32K_CLK by turning its XPD (meaning no power-down) signal off and on again via
RY
the RTC_CNTL_XPD_XTAL_32K bit. Then, the XTAL32K watchdog timer switches back to XTAL32K_CLK
as the clock source of RTC SLOW_CLK by clearing RTC_CNTL_XTAL32K_WDT_EN
(BACKUP32K_CLK_EN is also automatically cleared). If the chip is in Light-sleep and Deep-sleep mode,
the XTAL32K watchdog timer will wake up the CPU to finish the above steps.
12.3.2 BACKUP32K_CLK Working Principle
A
Chips have different RTC_CLK frequencies due to production process variations. To ensure the accuracy of
RTC_TIMER and other timers running on SLOW_CLK when BACKUP32K_CLK is at work, the divisor of
IN
BACKUP32K_CLK should be configured according to the actual frequency of RTC_CLK (see details in Chapter 4
Low-Power Management (RTC_CNTL) [to be added later]) via the RTC_CNTL_XTAL32K_CLK_FACTOR_REG
register. Each byte in this register corresponds to a divisor component (x0 ~x7 ). BACKUP32K_CLK is divided by
a fraction where the denominator is always 4, as calculated below.
IM
f _back_clk/4 = f _rtc_clk/S
S = x0 + x1 + ... + x7
EL
f_back_clk is the desired frequency of BACKUP32K_CLK, i.e. 32.768 kHz; f_rtc_clk is the actual frequency of
RTC_CLK; x0 ~x7 correspond to the pulse width in high and low state of four BACKUP32K_CLK clock signals
(unit: RTC_CLK clock cycle).
12.3.3 Configuring the Divisor Component of BACKUP32K_CLK
PR
Based on principles described in Section 12.3.2, configure the divisor component as follows:
• Calculate the sum of divisor components S according to the frequency of RTC_CLK and the desired
frequency of BACKUP32K_CLK;
• Calculate the integer part of divisor N = f _rtc_clk/f _back_clk;
• Calculate the integer part of divisor component M = N /2. The integer part of divisor N are separated into
two parts because a divisor component corresponds to a pulse width in high or low state;
• Calculate the number of divisor components that equal M (xn = M) and the number of divisor components
that equal M + 1 (xn = M + 1) according to the value of M and S. (M + 1) is the fractional part of divisor
component.
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For example, if the frequency of RTC_CLK is 163 kHz, then f _rtc_clk = 163000, f _back_clk = 32768, S = 20,
M = 2, and {x0 , x1 , x2 , x3 , x4 , x5 , x6 , x7 } = {2, 3, 2, 3, 2, 3, 2, 3}. As a result, the frequency of BACKUP32K_CLK
is 32.6 kHz.
A RY
IN
IM
EL
PR
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13 System Registers (SYSREG)
13.1 Overview
The ESP32-C3 integrates a large number of peripherals, and enables the control of individual peripherals to
achieve optimal characteristics in performance-vs-power-consumption scenarios. Specifically, ESP32-C3 has
various system configuration registers that can be used for the chip’s clock management (clock gating), power
management, and the configuration of peripherals and core-system modules. This chapter lists all these system
registers and their functions.
13.2 Features
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ESP32-C3 system registers can be used to control the following peripheral blocks and core modules:
• System and memory
• Clock
• Software Interrupt
A
• Low-power management
• Peripheral clock gating and reset
IN
13.3 Function Description
13.3.1 System and Memory Registers
IM
13.3.1.1 Internal Memory
The following registers can be used to control ESP32-C3’s internal memory:
• In register APB_CTRL_CLKGATE_FORCE_ON_REG:
EL
– Setting different bits of the APB_CTRL_ROM_CLKGATE_FORCE_ON field forces on the clock gates
of different blocks of Internal ROM 0 and Internal ROM 1.
– Setting different bits of the APB_CTRL_SRAM_CLKGATE_FORCE_ON field forces on the clock gates
of different blocks of Internal SRAM.
PR
– This means when the respective bits of this register are set to 1, the clock gate of the corresponding
ROM or SRAM blocks will always be on. Otherwise, the clock gate will turn on automatically when the
corresponding ROM or SRAM blocks are accessed and turn off automatically when the corresponding
ROM or SRAM blocks are not accessed. Therefore, it’s recommended to configure these bits to 0 to
lower power consumption.
• In register APB_CTRL_MEM_POWER_DOWN_REG:
– Setting different bits of the APB_CTRL_ROM_POWER_DOWN field sends different blocks of Internal
ROM 0 and Internal ROM 1 into retention state.
– Setting different bits of the APB_CTRL_SRAM_POWER_DOWN field sends different blocks of Internal
SRAM into retention state.
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– The “Retention” state is a low-power state of a memory block. In this state, the memory block still
holds all the data stored but cannot be accessed, thus reducing the power consumption. Therefore,
you can send a certain block of memory into the retention state to reduce power consumption if you
know you are not going to use such memory block for some time.
• In register APB_CTRL_MEM_POWER_UP_REG:
– By default, all memory enters low-power state when the chip enters the Light-sleep mode.
– Setting different bits of the APB_CTRL_ROM_POWER_UP field forces different blocks of Internal ROM
0 and Internal ROM 1 to work as normal (do not enter the retention state) when the chip enters
Light-sleep.
– Setting different bits of the APB_CTRL_SRAM_POWER_UP field forces different blocks of Internal
RY
SRAM to work as normal (do not enter the retention state) when the chip enters Light-sleep.
For detailed information about the controlling bits of different blocks, please see Table 13-1 below.
Table 131. Memory Controlling Bit
Memory Lowest Address1 Highest Address1 Lowest Address2 Highest Address2 Controlling Bit
A
ROM 0 0x4000_0000 0x4003_FFFF - - Bit0
ROM 1 0x4004_0000 0x4005_FFFF IN 0x3FF0_0000 0x3FF1_FFFF Bit1
SRAM Block 0 0x4037_C000 0x4037_FFFF - - Bit0
SRAM Block 1 0x4038_0000 0x4039_FFFF 0x3FC8_0000 0x3FC9_FFFF Bit1
SRAM Block 2 0x403A_0000 0x403B_FFFF 0x3FCA_0000 0x3FCB_FFFF Bit2
SRAM Block 3 0x403C_0000 0x403D_FFFF 0x3FCC_0000 0x3FCD_FFFF Bit3
IM
For more information, please refer to Chapter 3 System and Memory.
13.3.1.2 External Memory
EL
SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG configures encryption and decryption
options of the external memory. For details, please refer to Chapter 5 External Memory Encryption and Decryption
(XTS_AES) [to be added later].
13.3.1.3 RSA Memory
PR
SYSTEM_RSA_PD_CTRL_REG controls the SRAM memory in the RSA accelerator.
• Setting the SYSTEM_RSA_MEM_PD bit to send the RSA memory into retention state. This bit has the
lowest priority, meaning it can be masked by the SYSTEM_RSA_MEM_FORCE_PU field. This bit is invalid
when the Digital Signature (DS) occupies the RSA.
• Setting the SYSTEM_RSA_MEM_FORCE_PU bit to force the RSA memory to work as normal when the
chip enters light sleep. This bit has the second highest priority, meaning it overrides the
SYSTEM_RSA_MEM_PD field.
• Setting the SYSTEM_RSA_MEM_FORCE_PD bit to send the RSA memory into retention state. This bit has
the highest priority, meaning it sends the RSA memory into retention state regardless of the
SYSTEM_RSA_MEM_FORCE_PU field.
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13.3.2 Clock Registers
The following registers are used to set clock sources and frequency. For more information, please refer to
Chapter 6 Reset and Clock.
• SYSTEM_CPU_PER_CONF_REG
• SYSTEM_SYSCLK_CONF_REG
• SYSTEM_BT_LPCK_DIV_FRAC_REG
13.3.3 Interrupt Signal Registers
The following registers are used for generating the interrupt signals, which then can be routed to the CPU
RY
peripheral interrupts via the interrupt matrix. To be more specific, writing 1 to any of the following registers
generates an interrupt signal. Therefore, these registers can be used by software to control interrupts. For more
information, please refer to Chapter 8 Interrupt Matrix (INTMTRX).
• SYSTEM_CPU_INTR_FROM_CPU_0_REG
• SYSTEM_CPU_INTR_FROM_CPU_1_REG
A
• SYSTEM_CPU_INTR_FROM_CPU_2_REG
• SYSTEM_CPU_INTR_FROM_CPU_3_REG
13.3.4 Lowpower Management Registers
IN
The following registers are used for low-power management. For more information, please refer to Chapter 4
Low-Power Management (RTC_CNTL) [to be added later].
IM
• SYSTEM_RTC_FASTMEM_CONFIG_REG: configures the RTC CRC check.
• SYSTEM_RTC_FASTMEM_CRC_REG: configures the CRC check value.
13.3.5 Peripheral Clock Gating and Reset Registers
EL
The following registers are used for controlling the clock gating and reset of different peripherals. Details can be
seen in Table 13-2.
• SYSTEM_CACHE_CONTROL_REG
PR
• SYSTEM_PERIP_CLK_EN0_REG
• SYSTEM_PERIP_RST_EN0_REG
• SYSTEM_PERIP_CLK_EN1_REG
• SYSTEM_PERIP_RST_EN1_REG
Table 132. Clock Gating and Reset Bits
Component Clock Enabling Bit 1 Reset Controlling Bit 23
CACHE Control SYSTEM_CACHE_CONTROL_REG
DCACHE SYSTEM_DCACHE_CLK_ON SYSTEM_DCACHE_RESET
ICACHE SYSTEM_ICACHE_CLK_ON SYSTEM_ICACHE_RESET
Cont’d on next page
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Table 132 – cont’d from previous page
Component Clock Enabling Bit 1 Reset Controlling Bit 23
CPU SYSTEM_CPU_PERI_CLK_EN_REG SYSTEM_CPU_PERI_RST_EN_REG
DEBUG_ASSIST SYSTEM_CLK_EN_ASSIST_DEBUG SYSTEM_RST_EN_ASSIST_DEBUG
Peripherals SYSTEM_PERIP_CLK_EN0_REG SYSTEM_PERIP_RST_EN0_REG
TIMER SYSTEM_TIMERS_CLK_EN SYSTEM_TIMERS_RST
SPI0 / SPI1 SYSTEM_SPI01_CLK_EN SYSTEM_SPI01_RST
UART0 SYSTEM_UART_CLK_EN SYSTEM_UART_RST
UART1 SYSTEM_UART1_CLK_EN SYSTEM_UART1_RST
SPI2 SYSTEM_SPI2_CLK_EN SYSTEM_SPI2_RST
I2C0 SYSTEM_EXT0_CLK_EN SYSTEM_EXT0_RST
RY
UHCI0 SYSTEM_UHCI0_CLK_EN SYSTEM_UHCI0_RST
RMT SYSTEM_RMT_CLK_EN SYSTEM_RMT_RST
LED PWM Controller SYSTEM_LEDC_CLK_EN SYSTEM_LEDC_RST
Timer Group0 SYSTEM_TIMERGROUP_CLK_EN SYSTEM_TIMERGROUP_RST
Timer Group1 SYSTEM_TIMERGROUP1_CLK_EN SYSTEM_TIMERGROUP1_RST
A
TWAI Controller SYSTEM_CAN_CLK_EN SYSTEM_CAN_RST
USB_DEVICE SYSTEM_USB_DEVICE_CLK_EN SYSTEM_USB_DEVICE_RST
4
UART MEM SYSTEM_UART_MEM_CLK_EN SYSTEM_UART_MEM_RST
APB SARADC
ADC Controller
SYSTEM_APB_SARADC_CLK_EN
SYSTEM_ADC2_ARB_CLK_EN
IN SYSTEM_APB_SARADC_RST
SYSTEM_ADC2_ARB_RST
System Timer SYSTEM_SYSTIMER_CLK_EN SYSTEM_SYSTIMER_RST
Accelerators SYSTEM_PERIP_CLK_EN1_REG SYSTEM_PERIP_RST_EN1_REG
IM
TSENS SYSTEM_TSENS_CLK_EN SYSTEM_TSENS_RST
DMA SYSTEM_DMA_CLK_EN SYSTEM_DMA_RST5
HMAC SYSTEM_CRYPTO_HMAC_CLK_EN SYSTEM_CRYPTO_HMAC_RST 6
Digital Signature SYSTEM_CRYPTO_DS_CLK_EN SYSTEM_CRYPTO_DS_RST 7
RSA Accelerator SYSTEM_CRYPTO_RSA_CLK_EN SYSTEM_CRYPTO_RSA_RST
EL
SHA Accelerator SYSTEM_CRYPTO_SHA_CLK_EN SYSTEM_CRYPTO_SHA_RST
AES Accelerator SYSTEM_CRYPTO_AES_CLK_EN SYSTEM_CRYPTO_AES_RST
1
Set the clock enable bit to 1 to enable the clock, and to 0 to disable the clock;
2
Set the reset enabling bit to 1 to reset a peripheral, and to 0 to disable the reset.
3
Reset registers cannot be cleared by hardware. Therefore, SW reset clear is required after setting the
PR
reset registers.
4
UART memory is shared by all UART peripherals, meaning having any active UART peripherals will
prevent the UART memory from entering the clock-gated state.
5
When DMA is required for periphral communications, for example, UCHI0, SPI, I2S, LCD_CAM, AES,
SHA and ADC, DMA clock should also be enabled.
6
Resetting this bit also resets the SHA accelerator.
7
Resetting this bit also resets the AES, SHA, and RSA accelerators.
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13.4 Register Summary
The addresses in this section are relative to the base address of system registers provided in Table 3-4 in Chapter
3 System and Memory.
Name Description Address Access
Peripheral Clock Control Registers
SYSTEM_CPU_PERI_CLK_EN_REG CPU peripheral clock enable register 0x0000 R/W
SYSTEM_CPU_PERI_RST_EN_REG CPU peripheral clock reset register 0x0004 R/W
SYSTEM_PERIP_CLK_EN0_REG System peripheral clock enable register 0 0x0010 R/W
SYSTEM_PERIP_CLK_EN1_REG System peripheral clock enable register 1 0x0014 R/W
SYSTEM_PERIP_RST_EN0_REG System peripheral clock reset register 0 0x0018 R/W
RY
SYSTEM_PERIP_RST_EN1_REG System peripheral clock reset register 1 0x001C R/W
SYSTEM_CACHE_CONTROL_REG Cache clock control register 0x0040 R/W
Clock Configuration Registers
SYSTEM_CPU_PER_CONF_REG CPU clock configuration register 0x0008 R/W
SYSTEM_SYSCLK_CONF_REG System clock configuration register 0x0058 varies
A
Lowpower Management Registers
SYSTEM_BT_LPCK_DIV_FRAC_REG Low-power clock configuration register 1 0x0024 R/W
SYSTEM_RTC_FASTMEM_CONFIG_REG Fast memory CRC configuration register 0x0048 varies
SYSTEM_RTC_FASTMEM_CRC_REG
CPU Interrupt Control Registers
IN
Fast memory CRC result register 0x004C RO
SYSTEM_CPU_INTR_FROM_CPU_0_REG CPU interrupt control register 0 0x0028 R/W
SYSTEM_CPU_INTR_FROM_CPU_1_REG CPU interrupt control register 1 0x002C R/W
IM
SYSTEM_CPU_INTR_FROM_CPU_2_REG CPU interrupt control register 2 0x0030 R/W
SYSTEM_CPU_INTR_FROM_CPU_3_REG CPU interrupt control register 3 0x0034 R/W
System and Memory Control Registers
SYSTEM_RSA_PD_CTRL_REG RSA memory power control register 0x0038 R/W
SYSTEM_EXTERNAL_DEVICE_ENCRYPT_ External memory encryption and decryption 0x0044 R/W
EL
DECRYPT_CONTROL_REG control register
Clock Gate Control Register
SYSTEM_CLOCK_GATE_REG Clock gate control register 0x0054 R/W
Date Register
SYSTEM_DATE_REG Version register 0x0FFC R/W
PR
The addresses below are relative to the base address of apb control provided in Table 3-4 in Chapter 3 System
and Memory.
Name Description Address Access
Configuration Register
APB_CTRL_CLKGATE_FORCE_ON_REG Internal memory clock gate enable register 0x00A4 R/W
APB_CTRL_MEM_POWER_DOWN_REG Internal memory control register 0x00A8 R/W
APB_CTRL_MEM_POWER_UP_REG Internal memory control register 0x00AC R/W
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13.5 Registers
The addresses below are relative to the base address of system register provided in Table 3-4 in Chapter 3
System and Memory.
Register 13.1. SYSTEM_CPU_PERI_CLK_EN_REG (0x0000)
G
BU
E
T_D
IS
ASS
N_
_E
LK
_C
d)
)
ed
EM
ve
RY rv
r
ST
se
se
SY
(re
(re
30 7 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CLK_EN_ASSIST_DEBUG Set this bit to enable the ASSIST_DEBUG clock. Please see
Chapter 14 Debug Assist for more information about ASSIST_DEBUG. (R/W)
A
IN
Register 13.2. SYSTEM_CPU_PERI_RST_EN_REG (0x0004)
G
BU
E
_D
ST
SI
AS
IM
N_
_E
ST
_R
)
)
ed
ed
EM
rv
rv
ST
se
se
SY
(re
(re
31 8 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Reset
EL
SYSTEM_RST_EN_ASSIST_DEBUG Set this bit to reset the ASSIST_DEBUG clock. Please see
Chapter 14 Debug Assist for more information about ASSIST_DEBUG. (R/W)
PR
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13 System Registers (SYSREG)
Register 13.3. SYSTEM_PERIP_CLK_EN0_REG (0x0010)
EN
EN N
N
N
K_ _E
_E
K_
_C EN
_E
R L N
M C N
CL LK
LK
CL
SP SA C _E
LK
ed 3_D AD K_E
CE K_
EN
A_ _C
_C
(re M_ B_ ER_ LK
1_
EN
(re M_ I2_ LK_ N
VI CL
CL N
IM C EN
EN
RT LK_ N
K_
E P C _E
UP
P
E P M _C
SY TEM EXT 0_C EN
EN
1_ EN
N
S_ _E
K_
DE _
UA C E
U
E
_T I01_ LK_
K_
S d) B_ EM
ST _S 0_ LK
ST _A STI RB
RO
ER LK
S _ CI K_
K_
K_
CL
R
CL
SY rve US _M
SY EM H L
CL
EM P _C
SY TEM SY _A
CL
C
_
S d) ER
ST d) ER
S _ C2
ST _U T_
se _ T
ST _S T
_
ST d) C
ST d) 1_
AN
R
R
SY e ED
SY rve TIM
SY ve IM
SY TEM RM
I
SY rve I2S
SY TEM AD
(re EM A
SY EM A
_C
ST _U
ST _U
T
L
S _
se _
se _
se _
se _
S _
S d)
)
ed
ed
SY TEM
SY TEM
(re TEM
EM
(re EM
(re TEM
(re EM
SY EM
SY EM
SY rve
rv
rv
rv
r
r
ST
ST
se
se
se
se
S
SY
SY
SY
(re
(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 Reset
SYSTEM_TIMERS_CLK_EN Set this bit to enable TIMERS clock. (R/W)
RY
SYSTEM_SPI01_CLK_EN Set this bit to enable SPI0 / SPI1 clock. (R/W)
SYSTEM_UART_CLK_EN Set this bit to enable UART clock. (R/W)
SYSTEM_UART1_CLK_EN Set this bit to enable UART1 clock. (R/W)
SYSTEM_SPI2_CLK_EN Set this bit to enable SPI2 clock. (R/W)
A
SYSTEM_EXT0_CLK_EN Set this bit to enable I2C_EXT0 clock. (R/W) IN
SYSTEM_UHCI0_CLK_EN Set this bit to enable UHCI0 clock. (R/W)
SYSTEM_RMT_CLK_EN Set this bit to enable RMT clock. (R/W)
SYSTEM_LEDC_CLK_EN Set this bit to enable LEDC clock. (R/W)
IM
SYSTEM_TIMERGROUP_CLK_EN Set this bit to enable TIMER GROUP clock. (R/W)
SYSTEM_TIMERGROUP1_CLK_EN Set this bit to enable TIMERGROUP1 clock. (R/W)
SYSTEM_CAN_CLK_EN Set this bit to enable TWAI clock. (R/W)
EL
SYSTEM_I2S1_CLK_EN Set this bit to enable I2S1 clock. (R/W)
SYSTEM_USB_DEVICE_CLK_EN Set this bit to enable USB DEVICE clock. (R/W)
SYSTEM_UART_MEM_CLK_EN Set this bit to enable UART_MEM clock. (R/W)
SYSTEM_SPI3_DMA_CLK_EN Set this bit to enable SPI3 DMA clock. (R/W)
PR
SYSTEM_APB_SARADC_CLK_EN Set this bit to enable APB_SARADC clock. (R/W)
SYSTEM_SYSTIMER_CLK_EN Set this bit to enable SYSTEMTIMER clock. (R/W)
SYSTEM_ADC2_ARB_CLK_EN Set this bit to enable ADC2_ARB clock. (R/W)
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13 System Registers (SYSREG)
Register 13.4. SYSTEM_PERIP_CLK_EN1_REG (0x0014)
ed Y _ _ E N
rv CR TO SA K_ _E
LK N
ES LK N
N
) PT SH CL N
_C _E
_A _C E
_E
se _ YP _R CL K
O A K_
(re TEM CR TO S_ _CL
EN
S _ YP _D C
SY TEM CR TO MA
SY TEM CR TO EN
K_
S _ YP _H
S _ YP K_
CL
SY TEM CR CL
_
NS
S _ A_
SE
SY EM M
ST _D
_T
d)
)
ed
EM
SY TEM
ve
rv
er
ST
se
S
s
SY
SY
(re
(re
31 11 10 9 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CRYPTO_AES_CLK_EN Set this bit to enable AES clock. (R/W)
RY
SYSTEM_CRYPTO_SHA_CLK_EN Set this bit to enable SHA clock. (R/W)
SYSTEM_CRYPTO_RSA_CLK_EN Set this bit to enable RSA clock. (R/W)
SYSTEM_CRYPTO_DS_CLK_EN Set this bit to enable DS clock. (R/W)
A
SYSTEM_CRYPTO_HMAC_CLK_EN Set this bit to enable HMAC clock. (R/W)
SYSTEM_DMA_CLK_EN Set this bit to enable DMA clock. (R/W) IN
SYSTEM_TSENS_CLK_EN Set this bit to enable TSENS clock. (R/W)
IM
EL
PR
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13 System Registers (SYSREG)
Register 13.5. SYSTEM_PERIP_RST_EN0_REG (0x0018)
T
RS ST
RS
ST
ST
CE T
A_ _R
_R
(re M_ B_ ER_ ST
1_
VI RS
ed 3_D AD T
_R
R S
M C
UP
P
E P M _R
SP SA R
T
DE _
T
S d) B_ EM
RS
ST _S 0_ ST
ST _A STI RB
RO
ER ST
RS
_T I01_ ST
T
(re M_ I2_ ST
S _ CI T
ST
RT ST
T
S
R
SY TEM EXT 0_R
S_
SY rve US _M
SY TEM UH RS
RS
IM R
EM P _R
SY EM Y _A
_R
G
1_
E P R
_R
UA R
S d) ER
ST d) ER
ST _S C2
S _ T_
se _ T
ST _S RT
S d) C
ST d) 1_
AN
R
SY e ED
SY rve TIM
SY ve IM
SY TEM RM
I
SY rve I2S
SY TEM AD
(re EM A
SY EM A
_C
ST _U
ST _U
T
L
S _
se _
se _
se _
se _
S _
S d)
)
ed
ed
SY TEM
SY TEM
(re TEM
EM
(re TEM
(re TEM
(re EM
SY TEM
SY EM
SY rve
rv
rv
rv
r
ST
se
se
se
se
S
S
SY
SY
SY
(re
(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_TIMERS_RST Set this bit to reset TIMERS. (R/W)
RY
SYSTEM_SPI01_RST Set this bit to reset SPI0 / SPI1. (R/W)
SYSTEM_UART_RST Set this bit to reset UART. (R/W)
SYSTEM_UART1_RST Set this bit to reset UART1. (R/W)
SYSTEM_SPI2_RST Set this bit to reset SPI2. (R/W)
A
SYSTEM_EXT0_RST Set this bit to reset I2C_EXT0. (R/W)
SYSTEM_UHCI0_RST Set this bit to reset UHCI0. (R/W)
SYSTEM_RMT_RST Set this bit to reset RMT. (R/W)
IN
SYSTEM_LEDC_RST Set this bit to reset LEDC. (R/W)
SYSTEM_TIMERGROUP_RST Set this bit to reset TIMERGROUP. (R/W)
IM
SYSTEM_TIMERGROUP1_RST Set this bit to reset TIMERGROUP1. (R/W)
SYSTEM_CAN_RST Set this bit to reset CAN. (R/W)
SYSTEM_I2S1_RST Set this bit to reset I2S1. (R/W)
EL
SYSTEM_USB_DEVICE_RST Set this bit to reset USB DEVICE. (R/W)
SYSTEM_UART_MEM_RST Set this bit to reset UART_MEM. (R/W)
SYSTEM_SPI3_DMA_RST Set this bit to reset SPI3. (R/W)
PR
SYSTEM_APB_SARADC_RST Set this bit to reset APB_SARADC. (R/W)
SYSTEM_SYSTIMER_RST Set this bit to reset SYSTIMER. (R/W)
SYSTEM_ADC2_ARB_RST Set this bit to reset ADC2_ARB. (R/W)
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13 System Registers (SYSREG)
Register 13.6. SYSTEM_PERIP_RST_EN1_REG (0x001C)
se _ YP _R RS T
(re TEM CR TO S_ _RS
ES ST
O A T
ST
) PT SH RS
rv CR TO SA T
_A _R
_R
S _ YP _D C
ed Y _ _
SY TEM CR TO MA
T
S _ YP _H
RS
S _ YP T
SY EM R RS
SY TEM CR TO
_
NS
ST _C A_
SE
SY TEM DM
_T
S _
d)
)
ed
EM
SY TEM
ve
rv
er
ST
se
S
s
SY
SY
(re
(re
31 11 10 9 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Reset
SYSTEM_CRYPTO_AES_RST Set this bit to reset CRYPTO_AES. (R/W)
RY
SYSTEM_CRYPTO_SHA_RST Set this bit to reset CRYPTO_SHA. (R/W)
SYSTEM_CRYPTO_RSA_RST Set this bit to reset CRYPTO_RSA. (R/W)
SYSTEM_CRYPTO_DS_RST Set this bit to reset CRYPTO_DS. (R/W)
SYSTEM_CRYPTO_HMAC_RST Set this bit to reset CRYPTO_HMAC. (R/W)
A
SYSTEM_DMA_RST Set this bit to reset DMA. (R/W)
SYSTEM_TSENS_RST Set this bit to reset TSENS. (R/W)
IN
Register 13.7. SYSTEM_CACHE_CONTROL_REG (0x0040)
IM
E_ ESE N
N
CH _R _O
_I CH _C ET
O
CL T
K_
EM CA HE ES
CA E LK
ST _I AC _R
SY TEM DC HE
S _ AC
SY TEM DC
S _
d)
SY TEM
e
rv
se
S
SY
(re
EL
31 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Reset
SYSTEM_ICACHE_CLK_ON Set this bit to enable i-cache clock. (R/W)
SYSTEM_ICACHE_RESET Set this bit to reset i-cache. (R/W)
PR
SYSTEM_DCACHE_CLK_ON Set this bit to enable d-cache clock. (R/W)
SYSTEM_DCACHE_RESET Set this bit to reset d-cache. (R/W)
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13 System Registers (SYSREG)
Register 13.8. SYSTEM_CPU_PER_CONF_REG (0x0008)
N
O
E_
RC
UM
O
_N
PE SE E_F
AY
L
_ D
EL
SE
L
EQ MO
_D
D_
_F IT_
TI
O
AI
RI
LL A
_W
_P _W
R
PU
PU
EM P
_C
ST _C
_C
)
ed
EM
SY EM
EM
rv
ST
ST
ST
se
SY
SY
SY
(re
31 8 7 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 1 1 0 Reset
RY
SYSTEM_CPUPERIOD_SEL Set this field to select the CPU clock frequency. For details, please refer
to Table 6-4 in Chapter 6 Reset and Clock.(R/W)
SYSTEM_PLL_FREQ_SEL Set this bit to select the PLL clock frequency. For details, please refer to
Table 6-4 in Chapter 6 Reset and Clock. (R/W)
SYSTEM_CPU_WAIT_MODE_FORCE_ON Set this bit to force on the clock gate of CPU wait mode.
A
Usually, after executing the WFI instruction, CPU enters the wait mode, during which the clock gate
of CPU is turned off until any interrupts occur. In this way, power consumption is saved. However,
IN
if this bit is set, the clock gate of CPU is always on and will not be turned off by the WFI instruction.
(R/W)
SYSTEM_CPU_WAITI_DELAY_NUM Sets the number of delay cycles to turn off the CPU clock gate
after the CPU enters the wait mode because of a WFI instruction. (R/W)
IM
Register 13.9. SYSTEM_BT_LPCK_DIV_FRAC_REG (0x0024)
W
EL
LO
LK EL TA 2K
_S
PC _S _X L3
_S _8 L
TC
_L LK EL TA
ST _L LK EL N
EL M
SY TEM LPC K_S C_E
_R
EM PC _S _X
S _ L T
SY TEM LPC K_R
S _ L
SY TEM LPC
S _
)
)
d
ed
SY TEM
ve
rv
r
se
se
S
SY
(re
(re
PR
31 29 28 27 26 25 24 23 0
0 0 0 0 0 0 1 0 Reset
SYSTEM_LPCLK_SEL_RTC_SLOW Set this bit to select RTC slow clock as the low-power clock.
(R/W)
SYSTEM_LPCLK_SEL_8M Set this bit to select 8 MHz clock as the low-power clock. (R/W)
SYSTEM_LPCLK_SEL_XTAL Set this bit to select XTAL clock as the low-power clock. (R/W)
SYSTEM_LPCLK_SEL_XTAL32K Set this bit to select xtal32k clock as the low-power clock. (R/W)
SYSTEM_LPCLK_RTC_EN Set this bit to enable the RTC low-power clock. (R/W)
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13 System Registers (SYSREG)
Register 13.10. SYSTEM_SYSCLK_CONF_REG (0x0058)
E Q
NT
FR
SE
L_
_C
K_
TA
V
CL
DI
_X
C_
_
LK
RE
O
_C
_S
_P
d)
EM
EM
EM
ve
er
ST
ST
ST
s
SY
SY
SY
(re
31 19 18 12 11 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1 Reset
SYSTEM_PRE_DIV_CNT This field is used to set the count of prescaler of XTAL_CLK. For details,
please refer to Table 6-4 in Chapter 6 Reset and Clock. (R/W)
RY
SYSTEM_SOC_CLK_SEL This field is used to select SOC clock. For details, please refer to Table
6-2 in Chapter 6 Reset and Clock. (R/W)
SYSTEM_CLK_XTAL_FREQ This field is used to read XTAL frequency in MHz. (RO)
A
Register 13.11. SYSTEM_RTC_FASTMEM_CONFIG_REG (0x0048)
IN
SH
T
R
R
DD
EN
TA
NI
FI
_A
_S
_L
C_
RC
RC
RC
R
_C
_C
_C
_C
EM
EM
EM
EM
M
_M
_M
C_
C_
TC
TC
T
T
_R
_R
_R
_R
)
ed
EM
EM
EM
EM
IM
rv
ST
ST
ST
ST
se
SY
SY
SY
SY
31 30 20 19 9 8 7
(re 0
0 0x7ff 0x0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_RTC_MEM_CRC_START Set this bit to start the CRC of RTC memory. (R/W)
EL
SYSTEM_RTC_MEM_CRC_ADDR This field is used to set address of RTC memory for CRC. (R/W)
SYSTEM_RTC_MEM_CRC_LEN This field is used to set length of RTC memory for CRC based on
start address. (R/W)
SYSTEM_RTC_MEM_CRC_FINISH This bit stores the status of RTC memory CRC. High level means
PR
finished while low level means not finished. (RO)
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13 System Registers (SYSREG)
Register 13.12. SYSTEM_RTC_FASTMEM_CRC_REG (0x004C)
S
RE
_
RC
_C
EM
M
T C_
_R
EM
ST
SY
31 0
0 Reset
SYSTEM_RTC_MEM_CRC_RES This field stores the CRC result of RTC memory. (RO)
RY
Register 13.13. SYSTEM_CPU_INTR_FROM_CPU_0_REG (0x0028)
0
U_
P
_C
M
A
RO
_F
TR
N
_I
PU
_C
)
IN d
EM
ve
er
ST
s
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IM
SYSTEM_CPU_INTR_FROM_CPU_0 Set this bit to generate CPU interrupt 0. This bit needs to be
reset by software in the ISR process. (R/W)
Register 13.14. SYSTEM_CPU_INTR_FROM_CPU_1_REG (0x002C)
EL
1
U_
P
_C
M
RO
_F
TR
N
_I
PR
PU
_C
d)
EM
e
rv
ST
se
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CPU_INTR_FROM_CPU_1 Set this bit to generate CPU interrupt 1. This bit needs to be
reset by software in the ISR process. (R/W)
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13 System Registers (SYSREG)
Register 13.15. SYSTEM_CPU_INTR_FROM_CPU_2_REG (0x0030)
_2
PU
_C
M
O
FR
R_
NT
_I
PU
_C
d)
EM
ve
er
ST
s
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CPU_INTR_FROM_CPU_2 Set this bit to generate CPU interrupt 2. This bit needs to be
RY
reset by software in the ISR process. (R/W)
Register 13.16. SYSTEM_CPU_INTR_FROM_CPU_3_REG (0x0034)
A
3
U_
P
_C
M
O
FR
R_
IN
NT
_I
PU
_C
d)
EM
r ve
ST
se
SY
(re
31 1 0
IM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CPU_INTR_FROM_CPU_3 Set this bit to generate CPU interrupt 3. This bit needs to be
reset by software in the ISR process. (R/W)
EL
PR
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13 System Registers (SYSREG)
Register 13.17. SYSTEM_RSA_PD_CTRL_REG (0x0038)
_P RC PD
U
D E_P
EM FO E_
_M M_ RC
SA E FO
_R A_M M_
EM S E
ST _R A_M
SY TEM RS
S _
d)
SY TEM
ve
er
S
s
SY
(re
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
SYSTEM_RSA_MEM_PD Set this bit to send the RSA memory into retention state. This bit has the
RY
lowest priority, meaning it can be masked by the SYSTEM_RSA_MEM_FORCE_PU field. When
Digital Signature occupies the RSA, this bit is invalid. (R/W)
SYSTEM_RSA_MEM_FORCE_PU Set this bit to force the RSA memory to work as normal when
the chip enters light sleep. This bit has the second highest priority, meaning it overrides the SYS-
TEM_RSA_MEM_PD field. (R/W)
A
SYSTEM_RSA_MEM_FORCE_PD Set this bit to send the RSA memory into retention state. This bit
has the highest priority, meaning it sends the RSA memory into retention state regardless of the
SYSTEM_RSA_MEM_FORCE_PU field. (R/W)
IN
Register 13.18. SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (0x0044)
IM
EC YPT
T
R
UA _EN RYP
CB ENC
CR PT
Y
T
_
CR
YP
AL
_D
AD NU
EN
A
AN DB
NL _G0
NL _M
L_
_
AD
AD
O
O
NL
M
W
I_
O
DO
SP
_D
_D
E_
E_
LE
E
EM ABL
BL
BL
B
)
ed
NA
NA
NA
EL
N
_E
_E
_E
_E
rv
EM
EM
EM
se
ST
ST
ST
ST
(re
SY
SY
SY
SY
31 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT Set this bit to enable Manual Encryption under SPI
PR
Boot mode. (R/W)
SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT Set this bit to enable Auto Encryption under
Download Boot mode. (R/W)
SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT Set this bit to enable Auto Decryption under
Download Boot mode. (R/W)
SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT Set this bit to enable Manual Encryption
under Download Boot mode. (R/W)
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13 System Registers (SYSREG)
Register 13.19. SYSTEM_CLOCK_GATE_REG (0x0054)
N
_E
LK
_C
d)
EM
ver
ST
se
SY
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
SYSTEM_CLK_EN Set this bit to enable the system clock. (R/W)
RY
Register 13.20. SYSTEM_DATE_REG (0x0FFC)
E
AT
_D
d)
M
ve
E
r
ST
se
SY
(re
31 28 27 0
A
0 0 0 0 0x2007150 Reset
SYSTEM_DATE Version control register. (R/W) IN
The addresses below are relative to the base address of apb control provided in Table 3-4 in Chapter 3 System
and Memory.
IM
Register 13.21. APB_CTRL_CLKGATE_FORCE_ON_REG (0x00A4)
N
O
O
E_
E_
RC
RC
FO
FO
E_
E_
EL
AT
AT
G
G
LK
LK
_C
_C
M
M
RA
O
_R
_S
RL
RL
)
ed
CT
CT
rv
B_
B_
se
AP
AP
(re
31 6 5 2 1 0
PR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xf 3 Reset
APB_CTRL_ROM_CLKGATE_FORCE_ON Set 1 to configure the ROM clock gate to be always on;
Set 0 to configure the clock gate to turn on automatically when ROM is accessed and turn off
automatically when ROM is not accessed. (R/W)
APB_CTRL_SRAM_CLKGATE_FORCE_ON Set 1 to configure the SRAM clock gate to be always
on; Set 0 to configure the clock gate to turn on automatically when SRAM is accessed and turn
off automatically when SRAM is not accessed. (R/W)
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Register 13.22. APB_CTRL_MEM_POWER_DOWN_REG (0x00A8)
N
W
W
O
O
_D
_D
ER
ER
W
W
O
O
_P
_P
AM
M
RO
SR
L_
L_
R
R
)
ed
CT
CT
rv
B_
B_
se
AP
AP
(re
31 6 5 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_CTRL_ROM_POWER_DOWN Set this field to send the internal ROM into retention state. (R/W)
RY
APB_CTRL_SRAM_POWER_DOWN Set this field to send the internal SRAM into retention state.
(R/W)
A
Register 13.23. APB_CTRL_MEM_POWER_UP_REG (0x00AC)
P
IN
P
_U
_U
ER
ER
W
W
O
O
_P
_P
AM
M
O
R
_R
_S
RL
RL
d)
CT
CT
e
rv
B_
B_
se
IM
AP
AP
(re
31 6 5 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xf 3 Reset
APB_CTRL_ROM_POWER_UP Set this field to force the internal ROM to work as normal (do not
EL
enter the retention state) when the chip enters light sleep. (R/W)
APB_CTRL_SRAM_POWER_UP Set this field to force the internal SRAM to work as normal (do not
enter the retention state) when the chip enters light sleep. (R/W)
PR
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14 Debug Assist
14.1 Overview
Debug Assist is an auxiliary module that features a set of functions to help locate bugs and issues during
software debugging.
14.2 Features
• Read/write monitoring: Monitors whether the CPU bus has read from or written to a specified address
space. A detected read or write will trigger an interrupt.
RY
• Stack pointer (SP) monitoring: Monitors whether the SP exceeds the specified address space. A bounds
violation will trigger an interrupt.
• Program counter (PC) logging: Records PC value. The developer can get the last PC value at the most
recent CPU reset.
• Bus access logging: Records the information about bus access. When the CPU or DMA writes a
A
specified value, the Debug Assist module will record the address and PC value of this write operation, and
push the data to the SRAM.
14.3 Functional Description
IN
14.3.1 Region Read/Write Monitoring
IM
The Debug Assist module can monitor reads/writes performed by the CPU’s Data bus and Peripheral bus in a
certain address space, i.e., memory region. Whenever the Data bus reads or writes in the specified address
space, an interrupt will be triggered. The Data bus can monitor two memory regions (assuming they are region 0
and region 1, defined by developer’s needs) at the same time, so can the Peripheral bus.
EL
14.3.2 SP Monitoring
The Debug Assist module can monitor the SP so as to prevent stack overflow or erroneous push/pop. When the
stack pointer exceeds the minimum or maximum threshold, Debug Assist will record the PC pointer and generate
an interrupt. The threshold is configured by software.
PR
14.3.3 PC Logging
In some cases, software developers want to know the PC at the last CPU reset. For instance, when the program
is stuck and can only be reset, the developer may want to know where the program got stuck in order to debug.
The Debug Assist module can record the PC at the last CPU reset, which can be then read for software
debugging.
14.3.4 CPU/DMA Bus Access Logging
The Debug Assist module can record the information about the CPU Data bus’s and DMA bus’s write behaviors
in real time. When a write operation occurs in or a specific value is written to a specified address space, the
Debug Assist will record the bus type, PC, and the address, and then store the data in the SRAM in a certain
format.
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14.4 Recommended Operation
14.4.1 Region Monitoring and SP Monitoring Configuration Process
The Debug Assist module can monitor reads and writes performed by the CPU’s Data bus and Peripheral bus.
Two memory regions on each bus can be monitored at the same time. All the monitoring modes supported by
the Debug Assist module are listed below:
• Monitoring of the read/write operations on Data bus
– Data bus reads in region 0
– Data bus writes in region 0
RY
– Data bus reads in region 1
– Data bus writes in region 1
• Monitoring of the read/write operations on Peripheral bus
– Peripheral bus reads in region 0
A
– Peripheral bus writes in region 0
– Peripheral bus reads in region 1 IN
– Peripheral bus writes in region 1
• Monitoring of exceeding the SP bounds
– SP exceeds the upper bound address
IM
– SP exceeds the lower bound address
The configuration process for region monitoring and SP monitoring is as follows:
1. Configure monitored region and SP threshold.
• Configure Data bus region 0 with ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG and
EL
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG.
• Configure Data bus region 1 with ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG and
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG.
• Configure Peripheral bus region 0 with ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG and
PR
ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG.
• Configure Peripheral bus region 1 with ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG and
ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG.
• Configure SP threshold with ASSIST_DEBUG_CORE_0_SP_MIN_REG and
ASSIST_DEBUG_CORE_0_SP_MAX_REG.
2. Configure interrupts.
• Configure ASSIST_DEBUG_CORE_0_INTR_ENA_REG to enable the interrupt of a monitoring mode.
• Configure ASSIST_DEBUG_CORE_0_INTR_RAW_REG to get the interrupt status of a monitoring
mode.
• Configure ASSIST_DEBUG_CORE_0_INTR_CLR_REG to clear the interrupt of a monitoring mode.
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3. Configure ASSIST_DEBUG_CORE_0_MONTR_ENA_REG to enable the monitoring mode(s). Various
monitoring modes can be enabled at the same time.
Assuming that Debug Assist needs to monitor whether Data bus has written to [A ~ B] address space, the user
can enable monitoring in either Data bus region 0 or region 1. The following configuration process is based on
region 0:
1. Configure ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG to A.
2. Configure ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG to B.
3. Configure ASSIST_DEBUG_CORE_0_INTR_ENA_REG bit[1] to enable the interrupt for write operations by
Data bus in region 0.
RY
4. Configure ASSIST_DEBUG_CORE_0_MONTR_ENA_REG bit[1] to enable monitoring write operations by
Data bus in region 0.
5. Configure interrupt matrix to map ASSIST_DEBUG_INT into CPU interrupt (please refer to Chapter 8
Interrupt Matrix (INTMTRX)).
6. After the interrupt is triggered:
A
• Read ASSIST_DEBUG_CORE_0_INTR_RAW_REG to learn which operation triggered interrupt.
• If the interrupt is triggered by region monitoring, read ASSIST_DEBUG_CORE_0_AREA_PC_REG for
IN
the PC value, and ASSIST_DEBUG_CORE_0_AREA_SP_REG for the SP.
• If the interrupt is triggered by stack monitoring, read ASSIST_DEBUG_CORE_0_SP_PC_REG for the
PC value.
• Write ‘1’ to the corresponding bits of ASSIST_DEBUG_CORE_0_INTR_RAW_REG to clear the
IM
interrupts.
14.4.2 PC Logging Configuration Process
The CPU sends PC signals to Debug Assist. Only when ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN is 1, the
EL
PC signal is valid, otherwise, it is always 0.
Only when ASSIST_DEBUG_CORE_0_RCD_RECORDEN is 1,
ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG samples the CPU’s PC signals, otherwise, it keeps the
original value.
PR
The description of ASSIST_DEBUG_CORE_0_RCD_EN_REG and
ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG can be found in section 14.18 and 14.19.
When the CPU resets, ASSIST_DEBUG_CORE_0_RCD_EN_REG will reset, while
ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG will not. Therefore, the latter will keep the PC value at the
CPU reset.
14.4.3 CPU/DMA Bus Access Logging Configuration Process
The configuration process for CPU/DMA bus access logging is described below.
1. Configure monitored address space.
• Configure ASSIST_DEBUG_LOG_MIN_REG and ASSIST_DEBUG_LOG_MAX_REG to specify
monitored address space.
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2. Configure monitoring mode with ASSIST_DEBUG_LOG_MODE:
• write monitoring (whether the bus has write operations)
• word monitoring (whether the bus writes a specific word)
• halfword monitoring (whether the bus writes a specific halfword)
• byte monitoring (whether the bus writes a specific byte)
3. Configure the specific values to be monitored.
• In word monitoring mode, ASSIST_DEBUG_LOG_DATA_0_REG specifies the monitored word.
• In halfword monitoring mode, ASSIST_DEBUG_LOG_DATA_0_REG[15:0] specifies the monitored
RY
halfword.
• In byte monitoring mode, ASSIST_DEBUG_LOG_DATA_0_REG[7:0] specifies the monitored byte.
• ASSIST_DEBUG_LOG_DATA_MASK_REG is used to mask the byte specified in
ASSIST_DEBUG_LOG_DATA_0_REG. A masked byte can be any value. For example, in word
monitoring, ASSIST_DEBUG_LOG_DATA_0_REG is configured to 0x01020304, and
A
ASSIST_DEBUG_LOG_DATA_MASK_REG is configured to 0x1, then bus writes with data matching to
0x010203XX pattern will be recorded.
4. Configure the storage space for recorded data.
IN
• ASSIST_DEBUG_LOG_MEM_START_REG and ASSIST_DEBUG_LOG_MEM_END_REG specify the
storage space for recorded data. The storage space must be in the range of 0x3FCC_0000 ~
0x3FCD_FFFF.
IM
• Configure the permission for the Debug Assist module to access the internal SRAM. Only if the access
permission is enabled, the Debug Assist module is able to access the internal SRAM. For more
information please refer to Chapter 2 Permission Control (PMS) [to be added later]).
5. Configure the writing mode for recorded data: loop mode and non-loop mode.
EL
• In loop mode, writing to specified address space is performed in loops. When writing reaches the end
address, it will return to the starting address and continue, overwriting the previously recorded data.
For example, 10 writes (1 ~ 10) write to address space 0 ~ 4. After the 5th write writes to address 4,
the 6th write will start writing from address 0. The 6th to 10th writes will overwrite the previous data
written by 0 ~ 4 writes.
PR
• In non-loop mode, when writing reaches the end address, it will stop at the end address, not
overwriting the previously recorded data.
For example, 10 writes (1 ~ 10) write to address space 0 ~ 4. After the 5th write writes to address 4,
the 6th to 10th writes will write at address 4. Only the data written by the last (10th) write will be
retained at address 4.
6. Configure bus enable registers.
• Enable CPU or DMA bus access logging with ASSIST_DEBUG_LOG_ENA. CPU and DMA bus
access logging can be enabled at the same time.
When bus access logging is finished, the recorded data can be read from memory for decoding. The recorded
data is in two packet formats, namely CPU packet (corresponding to CPU bus) and DMA packet (corresponding
to DMA bus). The packet formats are shown in Table 14-1 and 14-2:
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Table 141. CPU Packet Format
Bit[49:29] Bit[28:2] Bit[1:0]
addr_offset pc_offset format
Table 142. DMA Packet Format
Bit[24:6] Bit[5:2] Bit[1:0]
addr_offset dma_source format
It can be seen from the data packet formats that the CPU packet size is 50 bits and DMA packet size 25 bits.
RY
The packet formats contain the following fields:
• format – the packet type. 1: CPU packet; 3: DMA packet; other values: reserved.
• pc_offset – the offset of the PC register at time of access. Actual PC = pc_offset + 0x4000_0000.
• addr_offset – the address offset of a write operation. Actual adddress = addr_offset +
A
ASSIST_DEBUG_LOG_MIN_REG.
• dma_source – the source of DMA access. Refer to Table 14-3.
IN
Table 143. DMA Source
Value Source
1 SPI2
2 reserved
IM
3 reserved
4 AES
5 SHA
6 ADC
EL
7 I2S0
8 reserved
9 LCD_CAM
10 reserved
11 UHCI0
PR
12 reserved
13 LC
14 reserved
15 reserved
The packets are stored in the internal buffer first. When the buffered data reaches 125 bits, it will be expanded to
128 bits and written to the internal SRAM. The written data format is shown in Table 14-4.
Table 144. Written Data Format
Bit[127:3] Bit[2:0]
Valid packets START_FLAG
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Since the CPU packet size is 50 bits and the DMA packet size 25 bits, the recorded data in each record is at
least 25 bits and at most 75 bits. When the data stored in the internal buffer reaches 125 bits, it will be popped
into memory. There are cases where a packet is divided into two portions: the first portion is written to memory,
and the second portion is left in the buffer and will be popped into memory in the next write. The data left in the
buffer is called residual data. The value of START_FLAG records the number of residual bits left from the last
write to memory. The number of residual bits is START_FLAG * 25. START_FLAG also indicates the starting bit of
the first valid packet in the current write. As an example: Assume that four DMA writes have generated four DMA
packets to be stored in the buffer with a total of 100-bit data. Then, one CPU write occurs and generates one
50-bit CPU packet. The buffer will pop the previously-recorded 100-bit data plus the first 25 bits in the CPU
packet into SRAM. The remaining 25 bits in the CPU packet is left in the buffer, waiting for the next write.
START_FLAG in the next write will indicate that 25 bits in this write is from the last write.
RY
In loop writing mode, if data is looped several times in the storage memory, the residual data will interfere with
packet parsing. Therefore, users need to filter out the residual data in order to determine the starting position of
the first valid packet with START_FLAG and ASSIST_DEBUG_LOG_MEM_CURRENT_ADDR_REG. Once the
starting position of the packet is identified, the subsequent data is continuous and users do not need to care
about the value of START_FLAG.
A
Note that if data in the buffer does not reach 125 bits, it will not be written to memory. All data should be written
to memory for packet parsing. This can be done by disabling bus access logging. When
ASSIST_DEBUG_LOG_ENA is set to 0, if there is data in the buffer, it will be padded with zeros from the left until
it becomes 128 bits long and written to the memory.
The process of packet parsing is described below:
IN
• Determine whether there is a data overflow with ASSIST_DEBUG_LOG_MEM_FULL_FLAG. If there is no
IM
overflow, ASSIST_DEBUG_LOG_MEM_START_REG is the starting address of the first packet. If there is an
overflow and loop mode is enabled, ASSIST_DEBUG_LOG_MEM_CURRENT_ADDR_REG is the starting
address of the first packet.
• Read and parse data from the starting address. Read 128 bits each time.
EL
• Use START_FLAG to determine the starting bit of the first packet. Starting bit = START_FLAG * 25 + 3.
Note that START_FLAG is only used to locate the starting bit of the first packet. Once the starting bit is located,
START_FLAG should be filtered out in the subsequent data.
After packet parsing is completed, clear the ASSIST_DEBUG_LOG_MEM_FULL_FLAG flag bit by setting
ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG.
PR
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14.5 Register Summary
The addresses in this section are relative to Debug Assist base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
Monitor configuration registers
ASSIST_DEBUG_CORE_0_MONTR_ENA_REG Monitoring enable register 0x0000 R/W
Configures boundary ad-
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG dress of region 0 moni- 0x0010 R/W
tored on Data bus
Configures boundary ad-
RY
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG dress of region 0 moni- 0x0014 R/W
tored on Data bus
Configures boundary ad-
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG dress of region 1 moni- 0x0018 R/W
tored on Data bus
A
Configures boundary ad-
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG dress of region 1 moni- 0x001C R/W
tored on Data bus
ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
IN Configures boundary ad-
dress of region 0 moni- 0x0020 R/W
tored on Peripheral bus
Configures boundary ad-
IM
ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG dress of region 0 moni- 0x0024 R/W
tored on Peripheral bus
Configures boundary ad-
ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG dress of region 1 moni- 0x0028 R/W
tored on Peripheral bus
EL
Configures boundary ad-
ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG dress of region 1 moni- 0x002C R/W
tored on Peripheral bus
Region monitoring PC sta-
ASSIST_DEBUG_CORE_0_AREA_PC_REG 0x0030 RO
tus register
PR
Region monitoring SP sta-
ASSIST_DEBUG_CORE_0_AREA_SP_REG 0x0034 RO
tus register
Configures stack monitor-
ASSIST_DEBUG_CORE_0_SP_MIN_REG 0x0038 R/W
ing boundary address
Configures stack monitor-
ASSIST_DEBUG_CORE_0_SP_MAX_REG 0x003C R/W
ing boundary address
Stack monitoring PC sta-
ASSIST_DEBUG_CORE_0_SP_PC_REG 0x0040 RO
tus register
Interrupt configuration registers
ASSIST_DEBUG_CORE_0_INTR_RAW_REG Interrupt status register 0x0004 RO
ASSIST_DEBUG_CORE_0_INTR_ENA_REG Interrupt enable register 0x0008 R/W
ASSIST_DEBUG_CORE_0_INTR_CLR_REG Interrupt clear register 0x000C R/W
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Name Description Address Access
PC logging configuration register
ASSIST_DEBUG_CORE_0_RCD_EN_REG PC logging enable register 0x0044 R/W
PC logging status registers
ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG PC logging register 0x0048 RO
ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG PC logging register 0x004C RO
Bus access logging configuration registers
Bus access logging con-
ASSIST_DEBUG_LOG_SETTING_REG 0x0070 R/W
figuration register
Configures monitored data
ASSIST_DEBUG_LOG_DATA_0_REG 0x0074 R/W
in Bus access logging
RY
Configures masked data in
ASSIST_DEBUG_LOG_DATA_MASK_REG 0x0078 R/W
Bus access logging
Configures monitored ad-
ASSIST_DEBUG_LOG_MIN_REG dress space in Bus access 0x007C R/W
logging
A
Configures monitored ad-
ASSIST_DEBUG_LOG_MAX_REG dress space in Bus access 0x0080 R/W
logging
ASSIST_DEBUG_LOG_MEM_START_REG
IN Configures the starting ad-
dress of the storage mem- 0x0084 R/W
ory for recorded data
Configures the end ad-
IM
ASSIST_DEBUG_LOG_MEM_END_REG dress of the storage mem- 0x0088 R/W
ory for recorded data
The current address of
ASSIST_DEBUG_LOG_MEM_CURRENT_ADDR_REG the storage memory for 0x008C RO
recorded data
EL
Logging overflow status
ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG 0x0090 varies
register
CPU status registers
PC of the last command
ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG before CPU enters excep- 0x0094 RO
PR
tion
CPU debug mode status
ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG 0x0098 RO
register
Version register
ASSIST_DEBUG_DATE_REG Version control register 0x01FC R/W
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14.6 Registers
The addresses in this section are relative to Debug Assist base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 14.1. ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (0x0000)
A_ AM0 RD_ A
0_ _ENA
A
NA
EN
EN
_E
A_ AM0 WR_
AR _PIF_ RD_E A
NA
SIS DEB _COR 0_AR _PIF WR A
R
N
RD
A
N
A
AM _W
UG ORE ARE LL_M _EN
_E
_E
RA D_E
IF_ _EN
1_
_
SIS DEB _COR 0_AR _PIF WR
_1
_0
0_
0_
AX
DE G_C E_0_ EA_D 0_R
IN
_
_
_
M
RE SP_ LL_M
1
_1
0
_
R
DR
DR
_D
_P
PI
PI
A
A
EA
EA
_S
S
RE ARE
RE ARE
RE
RY
AR
SIS DEB _COR 0_SP
_A
0_
_
0_
0_
0_
0
_0
_
E_
_
_
_
E_
E_
RE
R E
OR
EB _CO
CO
EB _CO
CO
CO
C
G_
G_
UG
UG
G
UG
G
U
U
U
U
BU
EB
EB
EB
EB
AS T_D
AS T_D
AS T_D
_D
AS T_D
AS T_D
)
ed
_
T_
T
T
rv
SIS
SIS
SIS
SIS
SIS
SIS
SIS
se
AS
AS
AS
AS
AS
(re
A
31 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA Monitoring enable bit for read operations in
region 0 by the Data bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA Monitoring enable bit for write operations
in region 0 by the Data bus. (R/W)
IM
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA Monitoring enable bit for read operations in
region 1 by the Data bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA Monitoring enable bit for write operations
EL
in region 1 by the Data bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA Monitoring enable bit for read operations in re-
gion 0 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA Monitoring enable bit for write operations in re-
PR
gion 0 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA Monitoring enable bit for read operations in re-
gion 1 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA Monitoring enable bit for write operations in re-
gion 1 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA Monitoring enable bit for SP exceeding the lower
bound address of SP monitored region. (R/W)
ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA Monitoring enable bit for SP exceeding the upper
bound address of SP monitored region. (R/W)
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Register 14.2. ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (0x0010)
IN
M
0_
0_
AM
DR
A_
RE
_A
_0
RE
O
_C
UG
EB
_D
ST
SI
AS
31 0
RY
0xffffffff Reset
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN The lower bound address of Data bus region 0.
(R/W)
A
Register 14.3. ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (0x0014)
AX
M
IN O
_0
RE
_AR
_D
EA
M
RA
0_
0_
IM
_C
UG
EB
_D
ST
SI
AS
31 0
0 Reset
EL
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX The upper bound address of Data bus region
0. (R/W)
PR
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Register 14.4. ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (0x0018)
IN
M
1_
0_
AM
DR
A_
RE
_A
_0
RE
O
_C
UG
EB
_D
ST
SI
AS
31 0
RY
0xffffffff Reset
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN The lower bound address of Data bus region 1.
(R/W)
A
Register 14.5. ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (0x001C)
AX
M
IN O
_0
RE
_AR
_D
EA
M
RA
0_
1_
IM
_C
UG
EB
_D
ST
SI
AS
31 0
0 Reset
EL
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX The upper bound address of Data bus region
1. (R/W)
PR
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Register 14.6. ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (0x0020)
IN
M
0_
F_
I
A_P
RE
_A
_0
RE
O
_C
UG
EB
_D
ST
SI
AS
31 0
0xffffffff Reset
RY
ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN The lower bound address of Peripheral bus region 0.
(R/W)
Register 14.7. ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (0x0024)
A F_
0_
AX
M
IN EB
UG
_C
O
RE
_0
_A
EA
R
_P
I
IM AS
SI
ST
_D
31 0
0 Reset
EL
ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX The upper bound address of Peripheral bus region
0. (R/W)
PR
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Register 14.8. ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (0x0028)
IN
M
1_
IF_
_P
A
RE
_A
_0
RE
O
_C
UG
EB
_D
ST
SI
AS
31 0
0xffffffff Reset
RY
ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN The lower bound address of Peripheral bus region 1.
(R/W)
Register 14.9. ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (0x002C)
A _M
_1
AX
IN EB
UG
_C
O
RE
_0
AR
_
_P
EA
IF
IM AS
SI
ST
_D
31 0
0 Reset
EL
ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX The upper bound address of Peripheral bus region
1. (R/W)
Register 14.10. ASSIST_DEBUG_CORE_0_AREA_PC_REG (0x0030)
PR
PC
A_
RE
_A
_0
RE
O
_C
G
BU
DE
ST_
SI
AS
31 0
0 Reset
ASSIST_DEBUG_CORE_0_AREA_PC Records the PC value when interrupt triggers during region
monitoring. (RO)
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Register 14.11. ASSIST_DEBUG_CORE_0_AREA_SP_REG (0x0034)
P
_S
A
RE
_A
_0
RE
O
_C
UG
EB
_D
ST
SI
AS
31 0
0 Reset
ASSIST_DEBUG_CORE_0_AREA_SP Records SP when interrupt triggers during region monitoring.
RY
(RO)
Register 14.12. ASSIST_DEBUG_CORE_0_SP_MIN_REG (0x0038)
A _M
IN
P
_S
_0
RE
O
IN ST
EB
_D
_C
UG
SI
AS
31 0
IM
0 Reset
ASSIST_DEBUG_CORE_0_SP_MIN The lower bound address of SP. (R/W)
EL
Register 14.13. ASSIST_DEBUG_CORE_0_SP_MAX_REG (0x003C)
AX
_M
P
_S
_0
RE
O
_C
PR
UG
EB
_D
ST
SI
AS
31 0
0xffffffff Reset
ASSIST_DEBUG_CORE_0_SP_MAX The upper bound address of SP. (R/W)
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Register 14.14. ASSIST_DEBUG_CORE_0_SP_PC_REG (0x0040)
C
_P
P
_S
_0
RE
O
_C
UG
EB
_D
ST
SI
AS
31 0
0 Reset
ASSIST_DEBUG_CORE_0_SP_PC Records the PC value during stack monitoring. (RO)
A RY
IN
IM
EL
PR
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Register 14.15. ASSIST_DEBUG_CORE_0_INTR_RAW_REG (0x0004)
AW
_0_ _RAW
W
0_1 R_RA
_RA
M0 WR_R
_1_ _RAW
AW
AW
AW
L_M _RAW
_RD
RD
F_1 RAW
_W
T_D UG_C E_0_A A_PIF WR_R
T_D UG_C E_0_A A_PIF RD_R
T_D UG_C E_0_A A_DR RD_R
_0_
R
0_1
_
_W
X
N
M0
P_S L_MA
_0_
_0_
I
AM
M
RA
_AR _DRA
RA
PIF
_PI
PIL
PIL
A_D
_D
_
A
EA
A
EA
P_S
RE
OR _ARE
RE
RE
RE
OR _ARE
AR
T_D UG_C E_0_S
T_D UG_C E_0_S
0_A
_0_
0
E_0
E_0
_
_
E
RE
RE
OR
OR
OR
OR
OR
OR
CO
CO
T_D UG_C
_C
_C
G_
G_
G
UG
U
U
U
EB
EB
B
EB
EB
EB
EB
EB
EB
EB
E
RY
T_D
T_D
T_D
T_D
e d)
erv
SIS
SIS
SIS
SIS
SIS
SIS
SIS
SIS
SIS
SIS
(res
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
31 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW Interrupt status bit for read operations in
A
region 0 by the Data bus. (RO)
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW Interrupt status bit for write operations in
region 0 by the Data bus. (RO)
IN
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW Interrupt status bit for read operations in
region 1 by the Data bus. (RO)
IM
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW Interrupt status bit for write operations in
region 1 by the Data bus. (RO)
ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW Interrupt status bit for read operations in region
0 by the Peripheral bus. (RO)
EL
ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW Interrupt status bit for write operations in re-
gion 0 by the Peripheral bus. (RO)
ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW Interrupt status bit for read operations in region
1 by the Peripheral bus. (RO)
PR
ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW Interrupt status bit for write operations in re-
gion 1 by the Peripheral bus. (RO)
ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW Interrupt status bit for SP exceeding the lower
bound address of SP monitored region. (RO)
ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW Interrupt status bit for SP exceeding the upper
bound address of SP monitored region. (RO)
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Register 14.16. ASSIST_DEBUG_CORE_0_INTR_ENA_REG (0x0008)
M0 RD_IN _ENA
NA
M0 WR_IN _ENA
A
_EN
RD TR_E
A
T_D UG_C E_0_A A_DR RD_IN _ENA
NA
WR NA
R
EN
TR
_IN _ENA
NA
INT
T
R_E
_E
_IN
_
R_E
TR
_
TR
NT
R
INT
N
NT
T
T_D UG_C E_0_A A_PIF WR_I
_ I
_1_
_
_0_
_0_
D_
X_I
0_1
_W
R
N
0
P_S L_MA
1_
_
_0_
I
AM
M
_M
1
F_0
RA
_AR _DRA
RA
_
_
F
PIF
ILL
_PI
_PI
PIL
_D
_D
P
_
A
EA
EA
A
A
EA
P_S
RE
RE
RE
RE
OR _ARE
R
AR
T_D UG_C E_0_S
T_D UG_C E_0_S
0_A
0_A
_0_
_0_
_0
E_0
_
_
E
RE
RE
RE
E
OR
R
OR
OR
OR
OR
O
CO
O
CO
T_D UG_C
_C
G_
G_
G_
_
RY G
UG
U
U
BU
U
EB
B
B
EB
EB
EB
EB
EB
EB
E
E
E
T_D
T_D
T_D
T_D
T_D
ed)
erv
SIS
SIS
SIS
SIS
SIS
SIS
SIS
SIS
SIS
SIS
(res
AS
AS
AS
AS
AS
AS
AS
AS
AS
AS
31 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
A
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA Interrupt enable bit for read opera-
tions in region 0 by the Data bus. (R/W) IN
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA Interrupt enable bit for write opera-
tions in region 0 by the Data bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA Interrupt enable bit for read opera-
tions in region 1 by the Data bus. (R/W)
IM
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA Interrupt enable bit for write opera-
tions in region 1 by the Data bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA Interrupt enable bit for read operations in
EL
region 0 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA Interrupt enable bit for write operations
in region 0 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA Interrupt enable bit for read operations in
region 1 by the Peripheral bus. (R/W)
PR
ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA Interrupt enable bit for write operations
in region 1 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA Interrupt enable bit for SP exceeding the
lower bound address of SP monitored region. (R/W)
ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA Interrupt enable bit for SP exceeding the
upper bound address of SP monitored region. (R/W)
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14 Debug Assist
Register 14.17. ASSIST_DEBUG_CORE_0_INTR_CLR_REG (0x000C)
LR
LR
LR
A_D M0_1 R_CL
M0 WR_C
M0 RD_C
_C
LR
R
R
LR
RD
CL
CL
R
LR
_W
_C
T_D UG_C E_0_A A_DR RD_C
CL
_PI _WR_
_
_ 0_
_0_
_PI _RD_
_C
WR
0_1
IN_
_SP MAX
_1_
_
AM
_M
1
F_0
F_0
RA
RA
RA
_AR _PIF_
0_S PILL_
PIF
ILL
A_D
_D
_
EA
A
EA
EA
EA
_S
RE
E
RE
OR _ARE
AR
AR
AR
_AR
P
_SP
A
_0_
_0_
_0_
0
E_0
E_0
E_0
E_0
_
E
RE
RE
RE
RE
OR
OR
R
OR
OR
O
CO
O
CO
CO
_C
_C
_C
_C
_C
_C
G_
G_
G_
G
G
G
UG
UG
SIS EBUG
BU
U
BU
BU
BU
BU
EB
EB
B
EB
(AS T_DE
(AS T_DE
(AS T_DE
(AS T_DE
(AS T_DE
(AS T_DE
RY _D
_D
T_D
ed)
T
SIS
SIS
SIS
SIS
SIS
SIS
SIS
SIS
erv
SIS
(res
(AS
(AS
(AS
AS
31 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR Interrupt clear bit for read operations in re-
A
gion 0 by the Data bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR Interrupt clear bit for write operations in re-
gion 0 by the Data bus. (R/W)
IN
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR Interrupt clear bit for read operations in re-
gion 1 by the Data bus. (R/W)
IM
ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR Interrupt clear bit for write operations in re-
gion 1 by the Data bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR Interrupt clear bit for read operations in region 0
by the Peripheral bus. (R/W)
EL
ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR Interrupt clear bit for write operations in region
0 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR Interrupt clear bit for read operations in region 1
by the Peripheral bus. (R/W)
PR
ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR Interrupt clear bit for write operations in region
1 by the Peripheral bus. (R/W)
ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR Interrupt clear bit for SP exceeding the lower
bound address of SP monitored region. (R/W)
ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR Interrupt clear bit for SP exceeding the upper
bound address of SP monitored region. (R/W)
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14 Debug Assist
Register 14.18. ASSIST_DEBUG_CORE_0_RCD_EN_REG (0x0044)
N
EC GEN
DE
OR
BU
_R _PDE
_R
RE RCD
CD
0_
_0
G_ RE_
O
CO
DE G_C
U
BU
EB
AS T_D
)
ed
T_
rv
SIS
SIS
se
AS
(re
RY
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ASSIST_DEBUG_CORE_0_RCD_RECORDEN Set to 1 to enable AS-
SIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG to record PC in real time. (R/W)
ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN Set to 1 to enable CPU debug function. The CPU
A
outputs PC only when this field is set to 1. (R/W)
IN
Register 14.19. ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (0x0048) UG
EB
PC
IM
PD
D_
_RC
_0
RE
O
_C
UG
EB
_D
EL
ST
SI
AS
31 0
0x000000 Reset
ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC Records the PC value at CPU reset. (RO)
PR
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Register 14.20. ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (0x004C)
SP
G
BU
DE
_P
CD
_R
_0
RE
O
_C
UG
EB
_D
ST
SI
AS
31 0
0x000000 Reset
RY
ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP Records SP. (RO)
Register 14.21. ASSIST_DEBUG_LOG_SETTING_REG (0x0070)
A
LE
AB
EN
P_
O
O
IN
_L
DE
EM
NA
O
_M
_M
_E
G
G
O
O
_L
_L
_L
UG
UG
BU
EB
EB
E
_D
_D
_D
d)
ve
ST
ST
ST
r
IM se
SI
SI
SI
AS
AS
AS
(re
31 8 7 6 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Reset
ASSIST_DEBUG_LOG_ENA Enables the CPU bus or DMA bus access logging. bit[0]: CPU bus
EL
access logging; bit[1]: reserved; bit[2]: DMA bus access logging. (R/W)
ASSIST_DEBUG_LOG_MODE Configures monitoring mode. bit[0]: write monitoring; bit[1]: word
monitoring; bit[2]: halfword monitoring; bit[3]: byte monitoring. (R/W)
ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE Configures the writing mode for recorded data. 1:
PR
loop mode; 0: non-loop mode. (R/W)
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Register 14.22. ASSIST_DEBUG_LOG_DATA_0_REG (0x0074)
A _0
AT
_D
G
O
_L
UG
EB
_D
ST
SI
AS
31 0
0 Reset
ASSIST_DEBUG_LOG_DATA_0 Specifies the monitored data. (R/W)
RY
Register 14.23. ASSIST_DEBUG_LOG_DATA_MASK_REG (0x0078)
ZE
SI
A_
AT
_D
A _D
EB
UG
_L
G
O
)
ed
ST
IN
rv
se
SI
AS
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ASSIST_DEBUG_LOG_DATA_SIZE Masks the byte specified in AS-
IM
SIST_DEBUG_LOG_DATA_0_REG. (R/W)
Register 14.24. ASSIST_DEBUG_LOG_MIN_REG (0x007C)
EL
IN
_M
G
O
_L
G
BU
DE
S T_
SI
PR
AS
31 0
0 Reset
ASSIST_DEBUG_LOG_MIN Configures the lower bound address of monitored address space. (R/W)
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Register 14.25. ASSIST_DEBUG_LOG_MAX_REG (0x0080)
AX
_M
G
O
_L
UG
EB
_D
ST
SI
AS
31 0
0 Reset
ASSIST_DEBUG_LOG_MAX Configures the upper bound address of monitored address space.
(R/W)
RY
Register 14.26. ASSIST_DEBUG_LOG_MEM_START_REG (0x0084)
TR
TA
_S
A
EM
_M
G
O
_L
UG
EB
IN ST
_D
SI
AS
31 0
0 Reset
IM
ASSIST_DEBUG_LOG_MEM_START Configures the starting address of the storage space for
recorded data. (R/W)
EL
Register 14.27. ASSIST_DEBUG_LOG_MEM_END_REG (0x0088)
ND
_E
EM
_M
G
O
_L
G
PR
BU
DE
T_
S
SI
AS
31 0
0 Reset
ASSIST_DEBUG_LOG_MEM_END Configures the end address of the storage space for recorded
data. (R/W)
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14 Debug Assist
Register 14.28. ASSIST_DEBUG_LOG_MEM_CURRENT_ADDR_REG (0x008C)
R
DD
_A
G
TIN
RI
_W
EM
_M
G
O
_L
UG
EB
_D
ST
SI
AS
31 0
0 Reset
RY
ASSIST_DEBUG_LOG_MEM_WRITING_ADDR Indicates the address of the next write. (RO)
Register 14.29. ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (0x0090)
A
LA AG
_F _FL
G
L
FU FUL
IN
_
LL
ME MEM
M_
_
LO LOG
G_
_
BU CLR
DE G_
G_
U
IM
SIS EB
AS T_D
d)
T_
rve
SIS
se
AS
( re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EL
ASSIST_DEBUG_LOG_MEM_FULL_FLAG The value “1” means there is a data overflow that ex-
ceeds the storage space. (RO)
ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG Set to 1 to clear AS-
SIST_DEBUG_LOG_MEM_FULL_FLAG flag bit. Default value is “0”. (R/W)
PR
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14 Debug Assist
Register 14.30. ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (0x0094)
C
X
_E
RE
FO
BE
C_
TP
AS
_L
_0
RE
O
_C
UG
EB
_D
ST
SI
AS
31 0
RY
0 Reset
ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC Records the PC of the last command before
the CPU enters exception. (RO)
A
Register 14.31. ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (0x0098)
IVE
IN
CT
OD E_A
_M UL
E
UG OD
EB _M
G
_0 BU
RE DE
IM
_D
CO _0_
G_ RE
BU CO
DE G_
U
SIS EB
AS T_D
d)
T_
rve
SIS
se
EL
AS
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ASSIST_DEBUG_CORE_0_DEBUG_MODE Indicates whether the RISC-V CPU is in debug mode.
1: in debug mode; 0: not in debug mode. (RO)
PR
ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE Indicates the status of the RISC-V CPU de-
bug module. 1: active status; 0: inactive status. (RO)
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14 Debug Assist
Register 14.32. ASSIST_DEBUG_DATE_REG (0x01FC)
E
AT
D
__
G
BU
E
_D
d)
ve
ST
er
SI
s
AS
(re
31 28 27 0
0 0 0 0 0x2008010 Reset
ASSIST_DEBUG__DATE Version control register. (R/W)
A RY
IN
IM
EL
PR
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15 SHA Accelerator (SHA)
15 SHA Accelerator (SHA)
15.1 Introduction
ESP32-C3 integrates an SHA accelerator, which is a hardware device that speeds up SHA algorithm significantly,
compared to SHA algorithm implemented solely in software. The SHA accelerator integrated in ESP32-C3 has
two working modes, which are Typical SHA and DMA-SHA.
15.2 Features
The following functionality is supported:
RY
• The following hash algorithms introduced in FIPS PUB 180-4 Spec.
– SHA-1
– SHA-224
– SHA-256
A
• Two working modes
– Typical SHA
– DMA-SHA
IN
• Interleaved function when working in Typical SHA working mode
• Interrupt function when working in DMA-SHA working mode
IM
15.3 Working Modes
The SHA accelerator integrated in ESP32-C3 has two working modes.
• Typical SHA Working Mode: all the data is written and read via CPU directly.
EL
• DMA-SHA Working Mode: all the data is read via DMA. That is, users can configure the DMA controller to
read all the data needed for hash operation, thus releasing CPU for completing other tasks.
Users can start the SHA accelerator with different working modes by configuring registers SHA_START_REG and
SHA_DMA_START_REG. For details, please see Table 15-1.
PR
Table 151. SHA Accelerator Working Mode
Working Mode Configuration Method
Typical SHA Set SHA_START_REG to 1
DMA-SHA Set SHA_DMA_START_REG to 1
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15 SHA Accelerator (SHA)
Users can choose hash algorithms by configuring the SHA_MODE_REG register. For details, please see Table
15-2.
Table 152. SHA Hash Algorithm Selection
Hash Algorithm SHA_MODE_REG Configuration
SHA-1 0
SHA-224 1
SHA-256 2
Notice:
RY
ESP32-C3’s Digital Signature (DS) and HMAC Accelerator (HMAC) modules also call the SHA accelerator.
Therefore, users cannot access the SHA accelerator when these modules are working.
15.4 Function Description
A
SHA accelerator can generate the message digest via two steps: Preprocessing and Hash operation.
15.4.1 Preprocessing
IN
Preprocessing consists of three steps: padding the message, parsing the message into message blocks and
setting the initial hash value.
IM
15.4.1.1 Padding the Message
The SHA accelerator can only process message blocks of 512 bits. Thus, all the messages should be padded to
a multiple of 512 bits before the hash task.
Suppose that the length of the message M is m bits. Then M shall be padded as introduced below:
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1. First, append the bit “1” to the end of the message;
2. Second, append k bits of zeros, where k is the smallest, non-negative solution to the equation
m + 1 + k ≡ 448 mod 512;
3. Last, append the 64-bit block of value equal to the number m expressed using a binary representation.
PR
For more details, please refer to Section “5.1 Padding the Message” in FIPS PUB 180-4 Spec.
15.4.1.2 Parsing the Message
The message and its padding must be parsed into N 512-bit blocks, M (1) , M (2) , …, M (N ) . Since the 512 bits
of the input block may be expressed as sixteen 32-bit words, the first 32 bits of message block i are denoted
(i) (i) (i)
M0 , the next 32 bits are M1 , and so on up to M15 .
(i)
During the task, all the message blocks are written into the SHA_M_n_REG: M0 is stored in SHA_M_0_REG,
(i) (i)
M1 stored in SHA_M_1_REG, …, and M15 stored in SHA_M_15_REG.
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Note:
For more information about “message block”, please refer to Section “2.1 Glossary of Terms and Acronyms” in FIPS PUB
180-4 Spec.
15.4.1.3 Setting the Initial Hash Value
Before hash task begins for any secure hash algorithms, the initial Hash value H(0) must be set based on different
algorithms. However, the SHA accelerator uses the initial Hash values (constant C) stored in the hardware for
hash tasks.
15.4.2 Hash Operation
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After the preprocessing, the ESP32-C3 SHA accelerator starts to hash a message M and generates message
digest of different lengths, depending on different hash algorithms. As described above, the ESP32-C3 SHA
accelerator supports two working modes, which are Typical SHA and DMA-SHA. The operation process for the
SHA accelerator under two working modes is described in the following subsections.
A
15.4.2.1 Typical SHA Mode Process
Usually, the SHA accelerator will process all blocks of a message and produce a message digest before starting
the computation of the next message digest.
IN
However, ESP32-C3 SHA also supports optional “interleaved” message digest calculation. Users can insert new
calculation (both Typical SHA and DMA-SHA) each time the SHA accelerator completes a sequence of
operations.
IM
• In Typical SHA mode, this can be done after each individual message block.
• In DMA-SHA mode, this can be done after a full sequence of DMA operations is complete.
Specifically, users can read out the message digest from registers SHA_H_n_REG after completing part of a
EL
message digest calculation, and use the SHA accelerator for a different calculation. After the different calculation
completes, users can restore the previous message digest to registers SHA_H_n_REG, and resume the
accelerator with the previously paused calculation.
Typical SHA Process
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1. Select a hash algorithm.
• Configure the SHA_MODE_REG register based on Table 15-2.
2. Process the current message block 1 .
• Write the message block in registers SHA_M_n_REG.
3. Start the SHA accelerator.
• If this is the first time to execute this step, set the SHA_START_REG register to 1 to start the SHA
accelerator. In this case, the accelerator uses the initial hash value stored in hardware for a given
algorithm configured in Step 1 to start the calculation;
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• If this is not the first time to execute this step2 , set the SHA_CONTINUE_REG register to 1 to start the
SHA accelerator. In this case, the accelerator uses the hash value stored in the SHA_H_n_REG
register to start calculation.
4. Check the progress of the current message block.
• Poll register SHA_BUSY_REG until the content of this register becomes 0, indicating the accelerator
has completed the calculation for the current message block and now is in the “idle” status 3 .
5. Decide if you have more message blocks to process:
• If yes, please go back to Step 2.
• Otherwise, please continue.
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6. Obtain the message digest.
• Read the message digest from registers SHA_H_n_REG.
Note:
1. In this step, the software can also write the next message block (to be processed) in registers SHA_M_n_REG, if
A
any, while the hardware starts SHA calculation, to save time.
2. You are resuming the SHA accelerator with the previously paused calculation.
3. Here you can decide if you want to insert other calculations. If yes, please go to the process for interleaved
calculations for details.
IN
As mentioned above, ESP32-C3 SHA accelerator supports “interleaving” calculation under the Typical SHA
working mode.
IM
The process to implement interleaved calculation is described below.
1. Prepare to hand the SHA accelerator over for an interleaved calculation by storing the following data of the
previous calculation.
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• The selected hash algorithm stored in the SHA_MODE_REG register.
• The message digest stored in registers SHA_H_n_REG.
2. Perform the interleaved calculation. For the detailed process of the interleaved calculation, please refer to
Typical SHA process or DMA-SHA process, depending on the working mode of your interleaved calculation.
PR
3. Prepare to hand the SHA accelerator back to the previously paused calculation by restoring the following
data of the previous calculation.
• Write the previously stored hash algorithm back to register SHA_MODE_REG.
• Write the previously stored message digest back to registers SHA_H_n_REG.
4. Write the next message block from the previous paused calculation in registers SHA_M_n_REG, and set the
SHA_CONTINUE_REG register to 1 to restart the SHA accelerator with the previously paused calculation.
15.4.2.2 DMASHA Mode Process
ESP32-C3 SHA accelerator does not support “interleaving” message digest calculation at the level of individual
message blocks when using DMA, which means you cannot insert new calculation before a complete DMA-SHA
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process (of one or more message blocks) completes. In this case, users who need interleaved operation are
recommended to divide the message blocks and perform several DMA-SHA calculations, instead of trying to
compute all the messages in one go.
Single DMA-SHA calculation supports up to 63 data blocks.
In contrast to the Typical SHA working mode, when the SHA accelerator is working under the DMA-SHA mode,
all data read are completed via DMA. Therefore, users are required to configure the DMA controller following the
description in Chapter 2 GDMA Controller (GDMA).
DMASHA process
1. Select a hash algorithm.
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• Select a hash algorithm by configuring the SHA_MODE_REG register. For details, please refer to Table
15-2.
2. Configure the SHA_INT_ENA_REG register to enable or disable interrupt (Set 1 to enable).
3. Configure the number of message blocks.
A
• Write the number of message blocks M to the SHA_DMA_BLOCK_NUM_REG register.
4. Start the DMA-SHA calculation. IN
• If the current DMA-SHA calculation follows a previous calculation, firstly write the message digest from
the previous calculation to registers SHA_H_n_REG, then write 1 to register
SHA_DMA_CONTINUE_REG to start SHA accelerator;
• Otherwise, write 1 to register SHA_DMA_START_REG to start the accelerator.
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5. Wait till the completion of the DMA-SHA calculation, which happens when:
• The content of SHA_BUSY_REG register becomes 0, or
• An SHA interrupt occurs. In this case, please clear interrupt by writing 1 to the SHA_INT_CLEAR_REG
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register.
6. Obtain the message digest:
• Read the message digest from registers SHA_H_n_REG.
15.4.3 Message Digest
PR
After the hash task completes, the SHA accelerator writes the message digest from the task to registers
SHA_H_n_REG(n: 0~7). The lengths of the generated message digest are different depending on different hash
algorithms. For details, see Table 15-3 below:
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Table 153. The Storage and Length of Message Digest from Different Algorithms
Hash Algorithm Length of Message Digest (in bits) Storage1
SHA-1 160 SHA_H_0_REG ~ SHA_H_4_REG
SHA-224 224 SHA_H_0_REG ~ SHA_H_6_REG
SHA-256 256 SHA_H_0_REG ~ SHA_H_7_REG
1
The message digest is stored in registers from most significant bits to the least significant bits,
with the first word stored in register SHA_H_0_REG and the second word stored in register
SHA_H_1_REG... For details, please see subsection 15.4.1.2.
15.4.4 Interrupt
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SHA accelerator supports interrupt on the completion of message digest calculation when working in the
DMA-SHA mode. To enable this function, write 1 to register SHA_INT_ENA_REG. Note that the interrupt should
be cleared by software after use via setting the SHA_INT_CLEAR_REG register to 1.
15.5 Register Summary
A
The addresses in this section are relative to the SHA accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Name
IN
Description Address Access
Control/Status registers
Continues SHA operation (only effective in Typi-
SHA_CONTINUE_REG 0x0014 WO
IM
cal SHA mode)
SHA_BUSY_REG Indicates if SHA Accelerator is busy or not 0x0018 RO
Starts the SHA accelerator for DMA-SHA oper-
SHA_DMA_START_REG 0x001C WO
ation
Starts the SHA accelerator for Typical SHA op-
SHA_START_REG 0x0010 WO
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eration
Continues SHA operation (only effective in DMA-
SHA_DMA_CONTINUE_REG 0x0020 WO
SHA mode)
SHA_INT_CLEAR_REG DMA-SHA interrupt clear register 0x0024 WO
SHA_INT_ENA_REG DMA-SHA interrupt enable register 0x0028 R/W
PR
Version Register
SHA_DATE_REG Version control register 0x002C R/W
Configuration Registers
SHA_MODE_REG Defines the algorithm of SHA accelerator 0x0000 R/W
Data Registers
Block number register (only effective for DMA-
SHA_DMA_BLOCK_NUM_REG 0x000C R/W
SHA)
SHA_H_0_REG Hash value 0x0040 R/W
SHA_H_1_REG Hash value 0x0044 R/W
SHA_H_2_REG Hash value 0x0048 R/W
SHA_H_3_REG Hash value 0x004C R/W
SHA_H_4_REG Hash value 0x0050 R/W
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Name Description Address Access
SHA_H_5_REG Hash value 0x0054 R/W
SHA_H_6_REG Hash value 0x0058 R/W
SHA_H_7_REG Hash value 0x005C R/W
SHA_M_0_REG Message 0x0080 R/W
SHA_M_1_REG Message 0x0084 R/W
SHA_M_2_REG Message 0x0088 R/W
SHA_M_3_REG Message 0x008C R/W
SHA_M_4_REG Message 0x0090 R/W
SHA_M_5_REG Message 0x0094 R/W
SHA_M_6_REG Message 0x0098 R/W
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SHA_M_7_REG Message 0x009C R/W
SHA_M_8_REG Message 0x00A0 R/W
SHA_M_9_REG Message 0x00A4 R/W
SHA_M_10_REG Message 0x00A8 R/W
SHA_M_11_REG Message 0x00AC R/W
A
SHA_M_12_REG Message 0x00B0 R/W
SHA_M_13_REG Message 0x00B4 R/W
SHA_M_14_REG Message 0x00B8 R/W
SHA_M_15_REG Message
IN 0x00BC R/W
15.6 Registers
IM
The addresses in this section are relative to the SHA accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 15.1. SHA_START_REG (0x0010)
EL
T
AR
d)
ST
e
rv
A_
se
SH
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PR
SHA_START Write 1 to start Typical SHA calculation. (WO)
Register 15.2. SHA_CONTINUE_REG (0x0014)
E
INU
NT
)
ed
CO
rv
A_
se
SH
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_CONTINUE Write 1 to continue Typical SHA calculation. (WO)
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Register 15.3. SHA_BUSY_REG (0x0018)
TE
TA
_S
SY
d)
BU
ve
A_
r
se
SH
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_BUSY_STATE Indicates the states of SHA accelerator. (RO) 1’h0: idle 1’h1: busy
RY
Register 15.4. SHA_DMA_START_REG (0x001C)
T
AR
ST
A_
d)
DM
ve
A_
r
se
SH
(re
31 1 0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_DMA_START Write 1 to start DMA-SHA calculation. (WO)
IN
Register 15.5. SHA_DMA_CONTINUE_REG (0x0020)
IM
UE
IN
NT
CO
A_
d )
DM
ve
A_
ser
SH
(re
31 1 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_DMA_CONTINUE Write 1 to continue DMA-SHA calculation. (WO)
PR
Register 15.6. SHA_INT_CLEAR_REG (0x0024)
PT
RU
ER
NT
I
R_
EA
)
ed
CL
rv
A_
se
SH
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_CLEAR_INTERRUPT Clears DMA-SHA interrupt. (WO)
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Register 15.7. SHA_INT_ENA_REG (0x0028)
NA
_E
T
UP
RR
TE
)
ed
IN
rv
A_
se
SH
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_INTERRUPT_ENA Enables DMA-SHA interrupt. (R/W)
RY
Register 15.8. SHA_DATE_REG (0x002C)
TE
)
ed
DA
rv
A_
se
SH
(re
31 30 29 0
A
0 0 0x20190402 Reset
SHA_DATE Version control register. (R/W)
IN
Register 15.9. SHA_MODE_REG (0x0000)
IM
DE
)
O
ed
M
rv
A_
se
SH
(re
31 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
EL
SHA_MODE Defines the SHA algorithm. For details, please see Table 15-2. (R/W)
Register 15.10. SHA_DMA_BLOCK_NUM_REG (0x000C)
PR
UM
_N
CK
O
BL
A_
d)
M
ve
_D
r
se
A
SH
(re
31 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
SHA_DMA_BLOCK_NUM Defines the DMA-SHA block number. (R/W)
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Register 15.11. SHA_H_n_REG (n: 07) (0x0040+4*n)
n
H_
A_
SH
31 0
0x000000 Reset
SHA_H_n Stores the nth 32-bit piece of the Hash value. (R/W)
Register 15.12. SHA_M_n_REG (n: 015) (0x0080+4*n)
RY
_n
M
A_
SH
31 0
0x000000 Reset
SHA_M_n Stores the nth 32-bit piece of the message. (R/W)
A
IN
IM
EL
PR
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16 AES Accelerator (AES)
16.1 Introduction
ESP32-C3 integrates an Advanced Encryption Standard (AES) Accelerator, which is a hardware device that
speeds up AES Algorithm significantly, compared to AES algorithms implemented solely in software. The AES
Accelerator integrated in ESP32-C3 has two working modes, which are Typical AES and DMA-AES.
16.2 Features
The following functionality is supported:
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• Typical AES working mode
– AES-128/AES-256 encryption and decryption
• DMA-AES working mode
– AES-128/AES-256 encryption and decryption
A
– Block cipher mode
* ECB (Electronic Codebook)
* CBC (Cipher Block Chaining)
IN
* OFB (Output Feedback)
* CTR (Counter)
IM
* CFB8 (8-bit Cipher Feedback)
* CFB128 (128-bit Cipher Feedback)
– Interrupt on completion of computation
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16.3 AES Working Modes
The AES Accelerator integrated in ESP32-C3 has two working modes, which are Typical AES and
DMA-AES.
• Typical AES Working Mode:
PR
– Supports encryption and decryption using cryptographic keys of 128 and 256 bits, specified in NIST
FIPS 197.
In this working mode, the plaintext and ciphertext is written and read via CPU directly.
• DMA-AES Working Mode:
– Supports encryption and decryption using cryptographic keys of 128 and 256 bits, specified in NIST
FIPS 197;
– Supports block cipher modes ECB/CBC/OFB/CTR/CFB8/CFB128 under NIST SP 800-38A.
In this working mode, the plaintext and ciphertext are written and read via DMA. An interrupt will be
generated when operation completes.
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Users can choose the working mode for AES accelerator by configuring the AES_DMA_ENABLE_REG register
according to Table 16-1 below.
Table 161. AES Accelerator Working Mode
AES_DMA_ENABLE_REG Working Mode
0 Typical AES
1 DMA-AES
Users can choose the length of cryptographic keys and encryption / decryption by configuring the
AES_MODE_REG register according to Table 16-2 below.
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Table 162. Key Length and Encryption/Decryption
AES_MODE_REG[2:0] Key Length and Encryption / Decryption
0 AES-128 encryption
1 reserved
2 AES-256 encryption
A
3 reserved
4 AES-128 decryption
5 reserved
6
7
IN
AES-256 decryption
reserved
IM
For detailed introduction on these two working modes, please refer to Section 16.4 and Section 16.5
below.
Notice:
ESP32-C3’s Digital Signature (DS) module will call the AES accelerator. Therefore, users cannot access the
EL
AES accelerator when Digital Signature (DS) module is working.
PR
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16.4 Typical AES Working Mode
In the Typical AES working mode, users can check the working status of the AES accelerator by inquiring the
AES_STATE_REG register and comparing the return value against the Table 16-3 below.
Table 163. Working Status under Typical AES Working Mode
AES_STATE_REG Status Description
0 IDLE The AES accelerator is idle or completed operation.
1 WORK The AES accelerator is in the middle of an operation.
16.4.1 Key, Plaintext, and Ciphertext
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The encryption or decryption key is stored in AES_KEY_n_REG, which is a set of eight 32-bit registers.
• For AES-128 encryption/decryption, the 128-bit key is stored in AES_KEY_0_REG ~ AES_KEY_3_REG.
• For AES-256 encryption/decryption, the 256-bit key is stored in AES_KEY_0_REG ~ AES_KEY_7_REG.
The plaintext and ciphertext are stored in AES_TEXT_IN_m_REG and AES_TEXT_OUT_m_REG, which are two
A
sets of four 32-bit registers.
• For AES-128/AES-256 encryption, the AES_TEXT_IN_m_REG registers are initialized with plaintext. Then,
IN
the AES Accelerator stores the ciphertext into AES_TEXT_OUT_m_REG after operation.
• For AES-128/AES-256 decryption, the AES_TEXT_IN_m_REG registers are initialized with ciphertext. Then,
the AES Accelerator stores the plaintext into AES_TEXT_OUT_m_REG after operation.
IM
16.4.2 Endianness
Text Endianness
In Typical AES working mode, the AES Accelerator uses cryptographic keys to encrypt and decrypt data in
blocks of 128 bits. When filling data into AES_TEXT_IN_m_REG register or reading result from
EL
AES_TEXT_OUT_m_REG registers, users should follow the text endianness type specified in Table 16-4.
Table 164. Text Endianness Type for Typical AES
Plaintext/Ciphertext
c2
PR
State1
0 1 2 3
0 AES_TEXT_x_0_REG[7:0] AES_TEXT_x_1_REG[7:0] AES_TEXT_x_2_REG[7:0] AES_TEXT_x_3_REG[7:0]
1 AES_TEXT_x_0_REG[15:8] AES_TEXT_x_1_REG[15:8] AES_TEXT_x_2_REG[15:8] AES_TEXT_x_3_REG[15:8]
r
2 AES_TEXT_x_0_REG[23:16] AES_TEXT_x_1_REG[23:16] AES_TEXT_x_2_REG[23:16] AES_TEXT_x_3_REG[23:16]
3 AES_TEXT_x_0_REG[31:24] AES_TEXT_x_1_REG[31:24] AES_TEXT_x_2_REG[31:24] AES_TEXT_x_3_REG[31:24]
1
The definition of “State (including c and r)” is described in Section 3.4 The State in NIST FIPS
197.
2
Where x = IN or OUT.
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Key Endianness
AES Accelerator (AES)
In Typical AES working mode, when filling key into AES_KEY_m_REG registers, users should follow the key endianness type specified in Table 16-5 and Table 16-6.
Table 165. Key Endianness Type for AES128 Encryption and Decryption
PR
Bit1 w[0] w[1] w[2] w[3]2
[31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0]
[23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8]
[15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16]
[7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24]
1
Column “Bit” specifies the bytes of each word stored in w[0] ~ w[3].
EL
2
w[0] ~ w[3] are “the first Nk words of the expanded key” as specified in Section 5.2 Key Expansion in NIST FIPS 197.
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Table 166. Key Endianness Type for AES256 Encryption and Decryption
295
Bit1 w[0] w[1] w[2] w[3] w[4] w[5] w[6] w[7]2
IM
[31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_7_REG[7:0]
[23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_7_REG[15:8]
[15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_7_REG[23:16]
[7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_7_REG[31:24]
IN
1
Column “Bit” specifies the bytes of each word stored in w[0] ~ w[7].
ESP32-C3 TRM (Pre-release v0.4)
2
w[0] ~ w[7] are “the first Nk words of the expanded key” as specified in Chapter 5.2 Key Expansion in NIST FIPS 197.
A RY
16 AES Accelerator (AES)
16.4.3 Operation Process
Single Operation
1. Write 0 to the AES_DMA_ENABLE_REG register.
2. Initialize registers AES_MODE_REG, AES_KEY_n_REG, AES_TEXT_IN_m_REG.
3. Start operation by writing 1 to the AES_TRIGGER_REG register.
4. Wait till the content of the AES_STATE_REG register becomes 0, which indicates the operation is
completed.
5. Read results from the AES_TEXT_OUT_m_REG register.
RY
Consecutive Operations
In consecutive operations, primarily the input AES_TEXT_IN_m_REG and output AES_TEXT_OUT_m_REG
registers are being written and read, while the content of AES_DMA_ENABLE_REG, AES_MODE_REG,
AES_KEY_n_REG is kept unchanged. Therefore, the initialization can be simplified during the consecutive
operation.
A
1. Write 0 to the AES_DMA_ENABLE_REG register before starting the first operation.
2. Initialize registers AES_MODE_REG and AES_KEY_n_REG before starting the first operation.
IN
3. Update the content of AES_TEXT_IN_m_REG.
4. Start operation by writing 1 to the AES_TRIGGER_REG register.
5. Wait till the content of the AES_STATE_REG register becomes 0, which indicates the operation completes.
IM
6. Read results from the AES_TEXT_OUT_m_REG register, and return to Step 3 to continue the next
operation.
16.5 DMAAES Working Mode
EL
In the DMA-AES working mode, the AES accelerator supports six block cipher modes including
ECB/CBC/OFB/CTR/CFB8/CFB128. Users can choose the block cipher mode by configuring the
AES_BLOCK_MODE_REG register according to Table 16-7 below.
Table 167. Block Cipher Mode
PR
AES_BLOCK_MODE_REG[2:0] Block Cipher Mode
0 ECB (Electronic Codebook)
1 CBC (Cipher Block Chaining)
2 OFB (Output Feedback)
3 CTR (Counter)
4 CFB8 (8-bit Cipher Feedback)
5 CFB128 (128-bit Cipher Feedback)
6 reserved
7 reserved
Users can check the working status of the AES accelerator by inquiring the AES_STATE_REG register and
comparing the return value against the Table 16-8 below.
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Table 168. Working Status under DMAAES Working mode
AES_STATE_REG[1:0] Status Description
0 IDLE The AES accelerator is idle.
1 WORK The AES accelerator is in the middle of an operation.
2 DONE The AES accelerator completed operations.
When working in the DMA-AES working mode, the AES accelerator supports interrupt on the completion of
computation. To enable this function, write 1 to the AES_INT_ENA_REG register. By default, the interrupt
function is disabled. Also, note that the interrupt should be cleared by software after use.
RY
16.5.1 Key, Plaintext, and Ciphertext
Block Operation
During the block operations, the AES Accelerator reads source data from DMA, and write result data to DMA
after the computation.
A
• For encryption, DMA reads plaintext from memory, then passes it to AES as source data. After
computation, AES passes ciphertext as result data back to DMA to write into memory.
• For decryption, DMA reads ciphertext from memory, then passes it to AES as source data. After
IN
computation, AES passes plaintext as result data back to DMA to write into memory.
During block operations, the lengths of the source data and result data are the same. The total computation time
is reduced because the DMA data operation and AES computation can happen concurrently.
IM
The length of source data for AES Accelerator under DMA-AES working mode must be 128 bits or the integral
multiples of 128 bits. Otherwise, trailing zeros will be added to the original source data, so the length of source
data equals to the nearest integral multiples of 128 bits. Please see details in Table 16-9 below.
Table 169. TEXTPADDING
EL
Function : TEXTPADDING( )
Input : X, bit string.
Output : Y = TEXTPADDING(X), whose length is the nearest integral multiples of 128 bits.
Steps
Let us assume that X is a data-stream that can be split into n parts as following:
PR
X = X1 ||X2 || · · · ||Xn−1 ||Xn
Here, the lengths of X1 , X2 , · · · , Xn−1 all equal to 128 bits, and the length of Xn is t
(0<=t<=127).
If t = 0, then
TEXTPADDING(X) = X;
If 0 < t <= 127, define a 128-bit block, Xn∗ , and let Xn∗ = Xn ||0128−t , then
TEXTPADDING(X) = X1 ||X2 || · · · ||Xn−1 ||Xn∗ = X||0128−t
16.5.2 Endianness
Under the DMA-AES working mode, the transmission of source data and result data for AES Accelerator is solely
controlled by DMA. Therefore, the AES Accelerator cannot control the Endianness of the source data and result
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data, but does have requirement on how these data should be stored in memory and on the length of the
data.
For example, let us assume DMA needs to write the following data into memory at address 0x0280.
• Data represented in hexadecimal:
– 0102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F20
• Data Length:
– Equals to 2 blocks.
Then, this data will be stored in memory as shown in Table 16-10 below.
RY
Table 1610. Text Endianness for DMAAES
Address Byte Address Byte Address Byte Address Byte
0x0280 0x01 0x0281 0x02 0x0282 0x03 0x0283 0x04
0x0284 0x05 0x0285 0x06 0x0286 0x07 0x0287 0x08
0x0288 0x09 0x0289 0x0A 0x028A 0x0B 0x028B 0x0C
A
0x028C 0x0D 0x028D 0x0E 0x028E 0x0F 0x028F 0x10
0x0290 0x11 0x0291 0x12 0x0292 0x13 0x0293 0x14
0x0294 0x15 0x0295 0x16 0x0296 0x17 0x0297 0x18
0x0298
0x029C
0x19
0x1D
0x0299
0x029D
IN
0x1A
0x1E
0x029A
0x029E
0x1B
0x1F
0x029B
0x029F
0x1C
0x20
16.5.3 Standard Incrementing Function
IM
AES accelerator provides two Standard Incrementing Functions for the CTR block operation, which are INC32
and INC128 Standard Incrementing Functions. By setting the AES_INC_SEL_REG register to 0 or 1, users can
choose the INC32 or INC128 functions respectively. For details on the Standard Incrementing Function, please see
Chapter B.1 The Standard Incrementing Function in NIST SP 800-38A.
EL
16.5.4 Block Number
Register AES_BLOCK_NUM_REG stores the Block Number of plaintext P or ciphertext C. The length of this
register equals to length(TEXTPADDING(P ))/128 or length(TEXTPADDING(C))/128. The AES Accelerator only
PR
uses this register when working in the DMA-AES mode.
16.5.5 Initialization Vector
AES_IV_MEM is a 16-byte memory, which is only available for AES Accelerator working in block operations. For
CBC/OFB/CFB8/CFB128 operations, the AES_IV_MEM memory stores the Initialization Vector (IV). For the CTR
operation, the AES_IV_MEM memory stores the Initial Counter Block (ICB).
Both IV and ICB are 128-bit strings, which can be divided into Byte0, Byte1, Byte2 · · · Byte15 (from left to right).
AES_IV_MEM stores data following the Endianness pattern presented in Table 16-10, i.e. the most significant
(i.e., left-most) byte Byte0 is stored at the lowest address while the least significant (i.e., right-most) byte Byte15
at the highest address.
For more details on IV and ICB, please refer to NIST SP 800-38A.
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16.5.6 Block Operation Process
1. Select one of DMA channels to connect with AES, configure the DMA chained list, and then start DMA. For
details, please refer to Chapter 2 GDMA Controller (GDMA).
2. Initialize the AES accelerator-related registers:
• Write 1 to the AES_DMA_ENABLE_REG register.
• Configure the AES_INT_ENA_REG register to enable or disable the interrupt function.
• Initialize registers AES_MODE_REG and AES_KEY_n_REG.
• Select block cipher mode by configuring the AES_BLOCK_MODE_REG register. For details, see Table
16-7.
RY
• Initialize the AES_BLOCK_NUM_REG register. For details, see Section 16.5.4.
• Initialize the AES_INC_SEL_REG register (only needed when AES Accelerator is working under CTR
block operation).
• Initialize the AES_IV_MEM memory (This is always needed except for ECB block operation).
A
3. Start operation by writing 1 to the AES_TRIGGER_REG register.
4. Wait for the completion of computation, which happens when the content of AES_STATE_REG becomes 2
or the AES interrupt occurs.
IN
5. Check if DMA completes data transmission from AES to memory. At this time, DMA had already written the
result data in memory, which can be accessed directly. For details on DMA, please refer to Chapter 2
GDMA Controller (GDMA).
IM
6. Clear interrupt by writing 1 to the AES_INT_CLR_REG register, if any AES interrupt occurred during the
computation.
7. Release the AES Accelerator by writing 0 to the AES_DMA_EXIT_REG register. After this, the content of the
AES_STATE_REG register becomes 0. Note that, you can release DMA earlier, but only after Step 4 is
EL
completed.
16.6 Memory Summary
The addresses in this section are relative to the AES accelerator base address provided in Table 3-4 in Chapter 3
PR
System and Memory.
Name Description Size (byte) Starting Address Ending Address Access
AES_IV_MEM Memory IV 16 bytes 0x0050 0x005F R/W
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16.7 Register Summary
The addresses in this section are relative to the AES accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
Key Registers
AES_KEY_0_REG AES key data register 0 0x0000 R/W
AES_KEY_1_REG AES key data register 1 0x0004 R/W
AES_KEY_2_REG AES key data register 2 0x0008 R/W
AES_KEY_3_REG AES key data register 3 0x000C R/W
AES_KEY_4_REG AES key data register 4 0x0010 R/W
RY
AES_KEY_5_REG AES key data register 5 0x0014 R/W
AES_KEY_6_REG AES key data register 6 0x0018 R/W
AES_KEY_7_REG AES key data register 7 0x001C R/W
TEXT_IN Registers
AES_TEXT_IN_0_REG Source text data register 0 0x0020 R/W
A
AES_TEXT_IN_1_REG Source text data register 1 0x0024 R/W
AES_TEXT_IN_2_REG Source text data register 2 0x0028 R/W
AES_TEXT_IN_3_REG Source text data register 3 0x002C R/W
TEXT_OUT Registers
AES_TEXT_OUT_0_REG
IN
Result text data register 0 0x0030 RO
AES_TEXT_OUT_1_REG Result text data register 1 0x0034 RO
AES_TEXT_OUT_2_REG Result text data register 2 0x0038 RO
IM
AES_TEXT_OUT_3_REG Result text data register 3 0x003C RO
Configuration Registers
AES_MODE_REG Defines key length and encryption / decryp- 0x0040 R/W
tion
AES_DMA_ENABLE_REG Selects the working mode of the AES accel- 0x0090 R/W
EL
erator
AES_BLOCK_MODE_REG Defines the block cipher mode 0x0094 R/W
AES_BLOCK_NUM_REG Block number configuration register 0x0098 R/W
AES_INC_SEL_REG Standard incrementing function register 0x009C R/W
Controlling / Status Registers
PR
AES_TRIGGER_REG Operation start controlling register 0x0048 WO
AES_STATE_REG Operation status register 0x004C RO
AES_DMA_EXIT_REG Operation exit controlling register 0x00B8 WO
Interruption Registers
AES_INT_CLR_REG DMA-AES interrupt clear register 0x00AC WO
AES_INT_ENA_REG DMA-AES interrupt enable register 0x00B0 R/W
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16.8 Registers
The addresses in this section are relative to the AES accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 16.1. AES_KEY_n_REG (n: 07) (0x0000+4*n)
31 0
0x000000000 Reset
AES_KEY_n_REG (n: 07) Stores AES key data. (R/W)
RY
Register 16.2. AES_TEXT_IN_m_REG (m: 03) (0x0020+4*m)
31 0
0x000000000 Reset
A
AES_TEXT_IN_m_REG (m: 03) Stores the source text data when the AES Accelerator operates in
the Typical AES working mode. (R/W) IN
Register 16.3. AES_TEXT_OUT_m_REG (m: 03) (0x0030+4*m)
31 0
IM
0x000000000 Reset
AES_TEXT_OUT_m_REG (m: 03) Stores the result text data when the AES Accelerator operates in
the Typical AES working mode. (RO)
EL
Register 16.4. AES_MODE_REG (0x0040)
DE
d)
O
e
M
rv
S_
se
AE
(re
PR
31 3 2 0
0x00000000 0 Reset
AES_MODE Defines the key length and encryption / decryption of the AES Accelerator. For details,
see Table 16-2. (R/W)
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Register 16.5. AES_DMA_ENABLE_REG (0x0090)
LE
AB
EN
A_
d)
DM
ve
r
S_
se
AE
(re
31 1 0
0x00000000 0 Reset
AES_DMA_ENABLE Defines the working mode of the AES Accelerator. 0: Typical AES, 1: DMA-AES.
For details, see Table 16-1. (R/W)
RY
Register 16.6. AES_BLOCK_MODE_REG (0x0094)
DE
O
_M
CK
O
d)
BL
e
rv
A
S_
se
AE
(re
31 3 2 0
0x00000000 0 Reset
IN
AES_BLOCK_MODE Defines the block cipher mode of the AES Accelerator operating under the
DMA-AES working mode. For details, see Table 16-7. (R/W)
IM
Register 16.7. AES_BLOCK_NUM_REG (0x0098)
31 0
0x00000000 Reset
EL
AES_BLOCK_NUM Stores the Block Number of plaintext or ciphertext when the AES Accelerator
operates under the DMA-AES working mode. For details, see Section 16.5.4. (R/W)
PR
Register 16.8. AES_INC_SEL_REG (0x009C)
L
SE
C_
)
ed
IN
rv
S_
se
AE
(re
31 1 0
0x00000000 0 Reset
AES_INC_SEL Defines the Standard Incrementing Function for CTR block operation. Set this bit to
0 or 1 to choose INC32 or INC128 . (R/W)
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Register 16.9. AES_TRIGGER_REG (0x0048)
ER
G
IG
d)
TR
ve
r
S_
se
AE
(re
31 1 0
0x00000000 x Reset
AES_TRIGGER Set this bit to 1 to start AES operation. (WO)
Register 16.10. AES_STATE_REG (0x004C)
RY
E
AT
)
ed
ST
rv
S_
se
AE
(re
31 2 1 0
0x00000000 0x0 Reset
A
AES_STATE Stores the working status of the AES Accelerator. For details, see Table 16-3 for Typical
AES working mode and Table 16-8 for DMA AES working mode. (RO)
IN
Register 16.11. AES_DMA_EXIT_REG (0x00B8)
IT
IM
EX
A_
d)
DM
r ve
S_
se
AE
(re
31 1 0
0x00000000 x Reset
EL
AES_DMA_EXIT Set this bit to 1 to exit AES operation. This register is only effective for DMA-AES
operation. (WO)
Register 16.12. AES_INT_CLR_REG (0x00AC)
PR
LR
_C
)
ed
NT
rv
I
S_
se
AE
(re
31 1 0
0x00000000 x Reset
AES_INT_CLR Set this bit to 1 to clear AES interrupt. (WO)
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Register 16.13. AES_INT_ENA_REG (0x00B0)
A
EN
T_
d)
ve
IN
r
S_
se
AE
(re
31 1 0
0x00000000 0 Reset
AES_INT_ENA Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. (R/W)
A RY
IN
IM
EL
PR
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17 RSA Accelerator (RSA)
17 RSA Accelerator (RSA)
17.1 Introduction
The RSA Accelerator provides hardware support for high precision computation used in various RSA asymmetric
cipher algorithms by significantly reducing their software complexity. Compared with RSA algorithms
implemented solely in software, this hardware accelerator can speed up RSA algorithms significantly. Besides,
the RSA Accelerator also supports operands of different lengths, which provides more flexibility during the
computation.
17.2 Features
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The following functionality is supported:
• Large-number modular exponentiation with two optional acceleration options
• Large-number modular multiplication
• Large-number multiplication
A
• Operands of different lengths
• Interrupt on completion of computation
IN
17.3 Functional Description
The RSA Accelerator is activated by setting the SYSTEM_CRYPTO_RSA_CLK_EN bit in the
IM
SYSTEM_PERIP_CLK
_EN1_REG register and clearing the SYSTEM_RSA_MEM_PD bit in the SYSTEM_RSA_PD_CTRL_REG register.
This releases the RSA Accelerator from reset.
The RSA Accelerator is only available after the RSA-related memories are initialized. The content of the
EL
RSA_CLEAN
_REG register is 0 during initialization and will become 1 after the initialization is done. Therefore, it is advised to
wait until RSA_CLEAN_REG becomes 1 before using the RSA Accelerator.
The RSA_INTERRUPT_ENA_REG register is used to control the interrupt triggered on completion of
computation. Write 1 or 0 to this register to enable or disable interrupt. By default, the interrupt function of the
PR
RSA Accelerator is enabled.
Notice:
ESP32-C3’s Digital Signature (DS) module also calls the RSA accelerator. Therefore, users cannot access the
RSA accelerator when Digital Signature (DS) is working.
17.3.1 Large Number Modular Exponentiation
Large-number modular exponentiation performs Z = X Y mod M . The computation is based on Montgomery
multiplication. Therefore, aside from the X, Y , and M arguments, two additional ones are needed — r and M ′ ,
which need to be calculated in advance by software.
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RSA Accelerator supports operands of length N = 32 × x, where x ∈ {1, 2, 3, . . . , 96}. The bit lengths of
arguments Z, X, Y , M , and r can be arbitrary N , but all numbers in a calculation must be of the same length.
The bit length of M ′ must be 32.
To represent the numbers used as operands, let us define a base-b positional notation, as follows:
b = 232
Using this notation, each number is represented by a sequence of base-b digits:
N
n=
32
Z = (Zn−1 Zn−2 · · · Z0 )b
RY
X = (Xn−1 Xn−2 · · · X0 )b
Y = (Yn−1 Yn−2 · · · Y0 )b
M = (Mn−1 Mn−2 · · · M0 )b
r = (rn−1 rn−2 · · · r0 )b
A
Each of the n values in Zn−1 · · · Z0 , Xn−1 · · · X0 , Yn−1 · · · Y0 , Mn−1 · · · M0 , rn−1 · · · r0 represents one base-b
digit (a 32-bit word).
Zn−1 , Xn−1 , Yn−1 , Mn−1 and rn−1 are the most significant bits of Z, X, Y , M , while Z0 , X0 , Y0 , M0 and r0 are
the least significant bits.
IN
If we define R = bn , the additional arguments can be calculated as r = R2 mod M .
The following equation in the form compatible with the extended binary GCD algorithm can be written as�
IM
M −1 × M + 1 = R × R−1
M ′ = M −1 mod b
EL
Large-number modular exponentiation can be implemented as follows:
1. Write 1 or 0 to the RSA_INTERRUPT_ENA_REG register to enable or disable the interrupt function.
2. Configure relevant registers:
PR
N
(a) Write ( 32 − 1) to the RSA_MODE_REG register.
(b) Write M ′ to the RSA_M_PRIME_REG register.
(c) Configure registers related to the acceleration options, which are described later in Section 17.3.4.
3. Write Xi , Yi , Mi and ri for i ∈ {0, 1, . . . , n − 1} to memory blocks RSA_X_MEM, RSA_Y_MEM,
RSA_M_MEM and RSA_Z_MEM. The capacity of each memory block is 96 words. Each word of each
memory block can store one base-b digit. The memory blocks use the little endian format for storage, i.e.
the least significant digit of each number is in the lowest address.
Users need to write data to each memory block only according to the length of the number; data beyond
this length are ignored.
4. Write 1 to the RSA_MODEXP_START_REG register to start computation.
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5. Wait for the completion of computation, which happens when the content of RSA_IDLE_REG becomes 1
or the RSA interrupt occurs.
6. Read the result Zi for i ∈ {0, 1, . . . , n − 1} from RSA_Z_MEM.
7. Write 1 to RSA_CLEAR_INTERRUPT_REG to clear the interrupt, if you have enabled the interrupt function.
After the computation, the RSA_MODE_REG register, memory blocks RSA_Y_MEM and RSA_M_MEM, as well
as the RSA_M_PRIME_REG remain unchanged. However, Xi in RSA_X_MEM and ri in RSA_Z_MEM
computation are overwritten, and only these overwritten memory blocks need to be re-initialized before starting
another computation.
17.3.2 Large Number Modular Multiplication
RY
Large-number modular multiplication performs Z = X × Y mod M . This computation is based on Montgomery
multiplication. Therefore, similar to the large number modular exponentiation, two additional arguments are
needed – r and M ′ , which need to be calculated in advance by software.
The RSA Accelerator supports large-number modular multiplication with operands of 96 different lengths.
A
The computation can be executed as follows:
1. Write 1 or 0 to the RSA_INTERRUPT_ENA_REG register to enable or disable the interrupt function.
2. Configure relevant registers:
N
(a) Write ( 32 − 1) to the RSA_MODE_REG register.
IN
(b) Write M ′ to the RSA_M_PRIME_REG register.
3. Write Xi , Yi , Mi , and ri for i ∈ {0, 1, . . . , n − 1} to memory blocks RSA_X_MEM, RSA_Y_MEM,
IM
RSA_M_MEM and RSA_Z_MEM. The capacity of each memory block is 96 words. Each word of each
memory block can store one base-b digit. The memory blocks use the little endian format for storage, i.e.
the least significant digit of each number is in the lowest address.
Users need to write data to each memory block only according to the length of the number; data beyond
EL
this length are ignored.
4. Write 1 to the RSA_MODMULT_START_REG register.
5. Wait for the completion of computation, which happens when the content of RSA_IDLE_REG becomes 1
or the RSA interrupt occurs.
PR
6. Read the result Zi for i ∈ {0, 1, . . . , n − 1} from RSA_Z_MEM.
7. Write 1 to RSA_CLEAR_INTERRUPT_REG to clear the interrupt, if you have enabled the interrupt function.
After the computation, the length of operands in RSA_MODE_REG, the Xi in memory RSA_X_MEM, the Yi in
memory RSA_Y_MEM, the Mi in memory RSA_M_MEM, and the M ′ in memory RSA_M_PRIME_REG remain
unchanged. However, the ri in memory RSA_Z_MEM has already been overwritten, and only this overwritten
memory block needs to be re-initialized before starting another computation.
17.3.3 Large Number Multiplication
Large-number multiplication performs Z = X × Y . The length of result Z is twice that of operand X and operand
Y . Therefore, the RSA Accelerator only supports Large Number Multiplication with operand length N = 32 × x,
where x ∈ {1, 2, 3, . . . , 48}. The length N̂ of result Z is 2 × N .
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The computation can be executed as follows:
1. Write 1 or 0 to the RSA_INTERRUPT_ENA_REG register to enable or disable the interrupt function.
N̂
2. Write ( 32 − 1), i.e. ( 16
N
− 1) to the RSA_MODE_REG register.
3. Write Xi and Yi for ∈ {0, 1, . . . , n − 1} to memory blocks RSA_X_MEM and RSA_Z_MEM. Each word of
each memory block can store one base-b digit. The memory blocks use the little endian format for storage,
N
i.e. the least significant digit of each number is in the lowest address. n is 32 .
Write Xi for i ∈ {0, 1, . . . , n − 1} to the address of the i words of the RSA_X_MEM memory block. Note
that Yi for i ∈ {0, 1, . . . , n − 1} will not be written to the address of the i words of the RSA_Z_MEM register,
but the address of the n + i words, i.e. the base address of the RSA_Z_MEM memory plus the address
offset 4 × (n + i).
RY
Users need to write data to each memory block only according to the length of the number; data beyond
this length are ignored.
4. Write 1 to the RSA_MULT_START_REG register.
5. Wait for the completion of computation, which happens when the content of RSA_IDLE_REG becomes 1
A
or the RSA interrupt occurs.
6. Read the result Zi for i ∈ {0, 1, . . . , n̂ − 1} from the RSA_Z_MEM register. n̂ is 2 × n.
IN
7. Write 1 to RSA_CLEAR_INTERRUPT_REG to clear the interrupt, if you have enabled the interrupt function.
After the computation, the length of operands in RSA_MODE_REG and the Xi in memory RSA_X_MEM remain
unchanged. However, the Yi in memory RSA_Z_MEM has already been overwritten, and only this overwritten
memory block needs to be re-initialized before starting another computation.
IM
17.3.4 Options for Acceleration
The ESP32-C3 RSA accelerator also provides SEARCH and CONSTANT_TIME options that can be configured to
accelerate the large-number modular exponentiation. By default, both options are configured for no acceleration.
EL
Users can choose to use one or two of these options to accelerate the computation.
To be more specific, when neither of these two options are configured for acceleration, the time required to
calculate Z = X Y mod M is solely determined by the lengths of operands. When either or both of these two
options are configured for acceleration, the time required is also correlated with the 0/1 distribution of Y .
To better illustrate how these two options work, first assume Y is represented in binaries as
PR
Y = (YeN −1 YeN −2 · · · Yet+1 Yet Yet−1 · · · Ye0 )2
where,
• N is the length of Y ,
• Yet is 1,
• YeN −1 , YeN −2 , …, Yet+1 are all equal to 0,
• and Yet−1 , Yet−2 , …, Ye0 are either 0 or 1 but exactly m bits should be equal to 0 and t-m bits 1, i.e. the
Hamming weight of Yet−1 Yet−2 , · · · , Ye0 is t − m.
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When either of these two options is configured for acceleration:
• SEARCH Option (Configuring RSA_SEARCH_ENABLE to 1 for acceleration)
– The accelerator ignores the bit positions of Yei , where i > α. Search position α is set by configuring
the RSA_SEARCH_POS_REG register. The maximum value of α is N -1, which leads to the same
result when this option is not used for acceleration. The best acceleration performance can be
achieved by setting α to t, in which case, all the YeN −1 , YeN −2 , …, Yet+1 of 0s are ignored during the
calculation. Note that if you set α to be less than t, then the result of the modular exponentiation
Z = X Y mod M will be incorrect.
• CONSTANT_TIME Option (Configuring RSA_CONSTANT_TIME_REG to 0 for acceleration)
– The accelerator speeds up the calculation by simplifying the calculation concerning the 0 bits of Y .
RY
Therefore, the higher the proportion of bits 0 against bits 1, the better the acceleration performance is.
We provide an example to demonstrate the performance of the RSA Accelerator under different combinations of
SEARCH and CONSTANT_TIME configuration. Here we perform Z = X Y mod M with N = 3072 and Y =
65537. Table 17-1 below demonstrates the time costs under different combinations of SEARCH and
CONSTANT_TIME configuration. Here, we should also mention that, α is set to 16 when the SEARCH option is
A
enabled.
Table 171. Acceleration Performance
SEARCH Option
No acceleration
IN
CONSTANT_TIME Option
No acceleration
Time Cost
376.405 ms
Accelerated No acceleration 2.260 ms
No acceleration Acceleration 1.203 ms
IM
Acceleration Acceleration 1.165 ms
It’s obvious that:
• The time cost is the biggest when none of these two options is configured for acceleration.
EL
• The time cost is the smallest when both of these two options are configured for acceleration.
• The time cost can be dramatically reduced when either or both option(s) are configured for acceleration.
17.4 Memory Summary
PR
The addresses in this section are relative to the RSA accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Table 172. RSA Accelerator Memory Blocks
Name Description Size (byte) Starting Address Ending Address Access
RSA_M_MEM Memory M 384 0x0000 0x017F R/W
RSA_Z_MEM Memory Z 384 0x0200 0x037F R/W
RSA_Y_MEM Memory Y 384 0x0400 0x057F R/W
RSA_X_MEM Memory X 384 0x0600 0x077F R/W
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17.5 Register Summary
The addresses in this section are relative to the RSA accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
Configuration Registers
RSA_M_PRIME_REG Register to store M’ 0x0800 R/W
RSA_MODE_REG RSA length mode 0x0804 R/W
RSA_CONSTANT_TIME_REG The constant_time option 0x0820 R/W
RSA_SEARCH_ENABLE_REG The search option 0x0824 R/W
RSA_SEARCH_POS_REG The search position 0x0828 R/W
RY
Status/Control Registers
RSA_CLEAN_REG RSA clean register 0x0808 RO
RSA_MODEXP_START_REG Modular exponentiation starting bit 0x080C WO
RSA_MODMULT_START_REG Modular multiplication starting bit 0x0810 WO
RSA_MULT_START_REG Normal multiplication starting bit 0x0814 WO
A
RSA_IDLE_REG RSA idle register 0x0818 RO
Interrupt Registers
RSA_CLEAR_INTERRUPT_REG RSA clear interrupt register 0x081C WO
RSA_INTERRUPT_ENA_REG
Version Register
IN
RSA interrupt enable register 0x082C R/W
RSA_DATE_REG Version control register 0x0830 R/W
IM
EL
PR
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17.6 Registers
The addresses in this section are relative to the RSA accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 17.1. RSA_M_PRIME_REG (0x0800)
31 0
0x000000000 Reset
RSA_M_PRIME_REG Stores M’.(R/W)
RY
Register 17.2. RSA_MODE_REG (0x0804)
DE
d)
O
ve
M
r
A_
se
RS
(re
31 7 6 0
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MODE Stores the mode of modular exponentiation. (R/W)
IN
Register 17.3. RSA_CLEAN_REG (0x0808)
IM
N
EA
d)
CL
rve
A_
se
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EL
RSA_CLEAN The content of this bit is 1 when memories complete initialization. (RO)
Register 17.4. RSA_MODEXP_START_REG (0x080C)
PR
RT
TA
_S
XP
DE
)
O
ed
M
rv
A_
se
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MODEXP_START Set this bit to 1 to start the modular exponentiation. (WO)
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Register 17.5. RSA_MODMULT_START_REG (0x0810)
T
AR
ST
T_
UL
DM
d)
O
ve
M
er
A_
s
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MODMULT_START Set this bit to 1 to start the modular multiplication. (WO)
RY
Register 17.6. RSA_MULT_START_REG (0x0814)
T
AR
ST
T_
UL
d )
ve
M
r
A_
se
RS
A
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MULT_START Set this bit to 1 to start the multiplication. (WO)
Register 17.7. RSA_IDLE_REG (0x0818)
IM
LE
d)
ve
ID
r
A_
se
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EL
RSA_IDLE The content of this bit is 1 when the RSA accelerator is idle. (RO)
Register 17.8. RSA_CLEAR_INTERRUPT_REG (0x081C)
PR
PT
RU
ER
INT
R_
EA
)
ed
CL
rv
A_
se
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_CLEAR_INTERRUPT Set this bit to 1 to clear the RSA interrupts. (WO)
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Register 17.9. RSA_CONSTANT_TIME_REG (0x0820)
E
M
TI
_
NT
TA
NS
d)
CO
ve
er
A_
s
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
RSA_CONSTANT_TIME_REG Controls the constant_time option. 0: acceleration. 1: no accelera-
tion (by default). (R/W)
RY
Register 17.10. RSA_SEARCH_ENABLE_REG (0x0824)
E
BL
NA
_E
CH
A
AR
d )
SE
ve
er
A_
s
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_SEARCH_ENABLE Controls the search option. 0: no acceleration (by default). 1: acceleration.
(R/W)
IM
Register 17.11. RSA_SEARCH_POS_REG (0x0828) O
S
_P
EL
CH
AR
)
ed
SE
rv
A_
se
RS
(re
31 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000 Reset
PR
RSA_SEARCH_POS Is used to configure the starting address when the acceleration option of search
is used. (R/W)
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Register 17.12. RSA_INTERRUPT_ENA_REG (0x082C)
NA
_E
T
UP
RR
TE
d)
ve
IN
er
A_
s
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
RSA_INTERRUPT_ENA Set this bit to 1 to enable the RSA interrupt. This option is enabled by default.
(R/W)
RY
Register 17.13. RSA_DATE_REG (0x0830)
TE
)
ed
DA
rv
A_
se
RS
(re
A
31 30 29 0
0 0 0x20200618 Reset
RSA_DATE Version control register. (R/W)
IN
IM
EL
PR
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18 HMAC Accelerator (HMAC)
18 HMAC Accelerator (HMAC)
The Hash-based Message Authentication Code (HMAC) module computes Message Authentication Codes
(MACs) using Hash algorithm and keys as described in RFC 2104. The hash algorithm is SHA-256, the 256-bit
HMAC key is stored in an eFuse key block and can be set as read-protected, i. e., the key is not accessible from
outside the HMAC accelerator itself.
18.1 Main Features
• Standard HMAC-SHA-256 algorithm
• Hash result only accessible by configurable hardware peripheral (in downstream mode)
RY
• Compatible to challenge-response authentication algorithm
• Generates required keys for the Digital Signature (DS) peripheral (in downstream mode)
• Re-enables soft-disabled JTAG (in downstream mode)
A
18.2 Functional Description
The HMAC module operates in two modes: upstream mode and downstream mode. In upstream mode, the
IN
HMAC message is provided by users and the calculation result is read back by them; in downstream mode, the
HMAC module is used as a Key Derivation Function (KDF) for other internal hardware. For instance, the JTAG
can be temporarily disabled by burning odd number bits of EFUSE_SOFT_DIS_JTAG in eFuse. In this case,
users can temporarily re-enable JTAG using the HMAC module in downstream mode.
IM
After the reset signal being released, the HMAC module will check whether the DS key exists in the eFuse. If the
key exists, the HMAC module will enter downstream digital signature mode and finish the DS key calculation
automatically.
18.2.1 Upstream Mode
EL
Common use cases for the upstream mode are challenge-response protocols supporting HMAC-SHA-256.
Assume the two entities in the challenge-response protocol are A and B respectively, and the data message they
expect to exchange is M. The general process of this protocol is as follows:
• A calculates a unique random number M
PR
• A sends M to B
• B calculates the HMAC (through M and KEY) and sends the result to A
• A calculates the HMAC (through M and KEY) internally
• A compares the two results. If they are the same, then the identity of B is authenticated
To calculate the HMAC value (the following steps should be done by the user):
1. Initialize the HMAC module, and enter upstream mode.
2. Write the correctly padded message to the HMAC, one block at a time.
3. Read back the result from HMAC.
For details of this process, please see Section 18.2.5.
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18.2.2 Downstream JTAG Enable Mode
JTAG debugging can be disabled in a way which allows later re-enabling using the HMAC module. The HMAC
module will expect the user to supply the HMAC result for one of the eFuse keys. The HMAC module will check
whether the supplied HMAC matches the one calculated from the chosen key. If both HMACs are the same,
JTAG will be enabled until the user calls the HMAC module to clear the results and consequently disable JTAG
again.
There are two parameters in eFuse memory to disable JTAG: EFUSE_HARD_DIS_JTAG and
EFUSE_SOFT_DIS_JTAG. Write 1 to EFUSE_DIS_PAD_JTAG to disable JTAG permanently, and write odd
numbers of 1 to EFUSE_SOFT_DIS_JTAG to disable JTAG temporarily. For more details, please see Chapter 4
eFuse Controller (EFUSE). After bit EFUSE_SOFT_DIS_JTAG is set, the key to re-enable JTAG can be calculated
RY
in HMAC module’s downstream mode. JTAG is re-enabled when the result configured by the user is the same as
the HMAC result.
To re-enable JTAG:
1. Users enable the HMAC module by initializing clock and reset signals of HMAC, and enter downstream
JTAG enable mode by configuring HMAC_SET_PARA_PURPOSE_REG, then Wait for the calculation to
A
complete. Please see Section 18.2.5 for more details.
2. Users write 1 to the HMAC_SOFT_JTAG_CTRL_REG register to enter JTAG re-enable compare mode.
IN
3. Users write the 256-bit HMAC value which is calculated locally from the 32-byte 0x00 using SHA-256 and
the generated key to register HMAC_WR_JTAG_REG by writing 8 times and 32-bit each time in big-endian
word order.
4. If the HMAC result matches the value that users calculated locally, then JTAG is re-enabled. Otherwise,
IM
JTAG remains disabled.
5. After writing 1 to HMAC_SET_INVALIDATE_JTAG_REG or resetting the chip, JTAG will be disabled. If users
want to re-enable JTAG again, they need to repeat the above steps again.
EL
18.2.3 Downstream Digital Signature Mode
The Digital Signature (DS) module encrypts its parameters using the AES-CBC algorithm. The HMAC module is
used as a Key Derivation Function (KDF) to derive the AES key to decrypt these parameters (parameter
decryption key). The key used for the HMAC as KDF is stored in one of the eFuse key blocks.
Before starting the DS module, users need to obtain the parameter decryption key for the DS module through
PR
HMAC calculation. For more information, please see Chapter 19 Digital Signature (DS). After the chip is powered
on, the HMAC module will check whether the key required to calculate the parameter decryption key has been
burned in the eFuse block. If the key has been burned, HMAC module will automatically enter the downstream
digital signature mode and complete the HMAC calculation based on the chosen key.
18.2.4 HMAC eFuse Configuration
Each HMAC key burned into an eFuse block has a key purpose, also burned into the eFuse section. This
purpose specifies for which functionality the key can be used. The HMAC module will not accept a key with a
non-matching purpose for any functionality. The HMAC module provides three different functionalities:
re-enabling JTAG and serving as DS KDF in downstream mode as well as pure HMAC calculation in upstream
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mode. For each functionality, there exists a corresponding key purpose, listed in Table 18-1. Additionally, another
purpose specifies a key which may be used for re-enabling JTAG as well as for serving as DS KDF.
Before enabling HMAC to do calculations, user should make sure the key to be used has been burned in eFuse
by reading EFUSE_KEY_PURPOSE_x (We totally have 6 keys in eFuse, so x = 0,1,2,..,5), registers from 4 eFuse
Controller (EFUSE). Take upstream as example, if there is no EFUSE_KEY_PURPOSE_HMAC_UP in
EFUSE_KEY_PURPOSE_0~5, means there is no upstream used key in efuse. You can burn key to efuse as
follows:
1. Prepare a secret 256-bit HMAC key and burn the key to an empty eFuse block y (there are six blocks for
storing a key in eFuse. The numbers of those blocks range from 4 to 9, so y = 4,5,..,9. Hence, if we are
talking about key0, we mean eFuse block4), and then program the purpose to
EFUSE_KEY_PURPOSE_(y − 4). Take upstream mode as an example: after programming the key, the
RY
user should program EFUSE_KEY_PURPOSE_HMAC_UP (corresponding value is 6) to
EFUSE_KEY_PURPOSE_(y − 4). Please see Chapter 4 eFuse Controller (EFUSE) on how to program eFuse
keys.
2. Configure this eFuse key block to be read protected, so that software cannot read its value. A copy of this
key should be kept by any party who needs to verify this device.
A
Please note that the key whose purpose is EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL can be used for both
re-enabling JTAG or DS.
IN
Table 181. HMAC Purposes and Configuration Value
Purpose Mode Value Description
JTAG Re-enable Downstream 6 EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
IM
DS Key Derivation Downstream 7 EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
HMAC Calculation Upstream 8 EFUSE_KEY_PURPOSE_HMAC_UP
Both JTAG Re- Downstream 5 EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL
enable and DS
KDF
EL
Configure HMAC Purposes
The correct purpose has to be written to register HMAC_SET_PARA_PURPOSE_REG (see Section 18.2.5). If
there is no valid value in efuse purpose section, HMAC will terminate calculation.
PR
Select eFuse Key Blocks
The eFuse controller provides six key blocks, i.e., KEY0 ~ 5. To select a particular KEYn for an HMAC calculation,
write the key number n to register HMAC_SET_PARA_KEY_REG.
Note that the purpose of the key has also been programmed to eFuse memory. Only when the configured HMAC
purpose matches the defined purpose of KEYn, will the HMAC module execute the configured calculation.
Otherwise, it will return a matching error and stop the current calculation. For example, suppose a user selects
KEY3 for HMAC calculation, and the value programmed to KEY_PURPOSE_3 is 6
(EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG). Based on Table 18-1, KEY3 can be used to re-enable JTAG. If
the value written to register HMAC_SET_PARA_PURPOSE_REG is also 6, then the HMAC module will start the
process to re-enable JTAG.
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18.2.5 HMAC Process (Detailed)
The process to call HMAC is as follows:
1. Enable HMAC module
(a) Set the peripheral clock bits for HMAC and SHA peripherals in register
SYSTEM_PERIP_CLK_EN1_REG, and clear the corresponding peripheral reset bits in register
SYSTEM_PERIP_RST_EN1_REG. For information on those registers, please see Chapter 3 System
and Memory.
(b) Write 1 to register HMAC_SET_START_REG.
2. Configure HMAC keys and key purposes
RY
(a) Write the key purpose m to register HMAC_SET_PARA_PURPOSE_REG. The possible key purpose
values are shown in Table 18-1. For more information, please refer to Section 18.2.4.
(b) Select KEYn in eFuse memory as the key by writing n (ranges from 0 to 5) to register
HMAC_SET_PARA_KEY_REG. For more information, please refer to Section 18.2.4.
(c) Write 1 to register HMAC_SET_PARA_FINISH_REG to complete the configuration.
A
(d) Read register HMAC_QUERY_ERROR_REG. If its value is 1, it means the purpose of the selected
block does not match the configured key purpose and the calculation will not proceed. If its value is 0,
IN
it means the purpose of the selected block matches the configured key purpose, and then the
calculation can proceed.
(e) When the value of HMAC_SET_PARA_PURPOSE_REG is not 8, it means the HMAC module is in
downstream mode, proceed with step 3. When the value is 8, it means the HMAC module is in
IM
upstream mode, proceed with step 4.
3. Downstream mode
(a) Poll Status register HMAC_QUERY_BUSY_REG until it reads 0.
EL
(b) To clear the result and make further usage of the dependent hardware (JTAG or DS) impossible, write
1 to either register HMAC_SET_INVALIDATE_JTAG_REG to clear the result generated by the JTAG
key; or to register HMAC_SET_INVALIDATE_DS_REG to clear the result generated by DS key.
Afterwards, the HMAC Process needs to be restarted to re-enable any of the dependent peripherals.
4. Transmit message block Block_n (n >= 1) in upstream mode
PR
(a) Poll Status register HMAC_QUERY_BUSY_REG until it reads 0.
(b) Write the 512-bit Block_n to register HMAC_WDATA0~15_REG. Write 1 to register
HMAC_SET_MESSAGE_ONE_REG, to trigger the processing of this message block.
(c) Poll Status register HMAC_QUERY_BUSY_REG until it reads 0.
(d) Different message blocks will be generated, depending on whether the size of the to-be-processed
message is a multiple of 512 bits.
• If the bit length of the message is a multiple of 512 bits, there are three possible options:
i. If Block_n+1 exists, write 1 to register HMAC_SET_MESSAGE_ING_REG to make n = n + 1,
and then jump to step 4.(b).
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ii. If Block_n is the last block of the message and users expects to apply SHA padding in
hardware, write 1 to register HMAC_SET_MESSAGE_END_REG, and then jump to step 6.
iii. If Block_n is the last block of the padded message and SHA padding has been applied in
software, write 1 to register HMAC_SET_MESSAGE_PAD_REG, and then jump to step 5.
• If the bit length of the message is not a multiple of 512 bits, there are three possible options as
follows. Note that in this case, the user is required to apply SHA padding to the message, after
which the padded message length should be a multiple of 512 bits.
i. If there is only one message block in total which has included all padding bits, write 1 to
register HMAC_ONE_BLOCK_REG, and then jump to step 6.
ii. If Block_n is the second last padded block, write 1 to register
RY
HMAC_SET_MESSAGE_PAD_REG, and then jump to step 5.
iii. If Block_n is neither the last nor the second last message block, write 1 to register
HMAC_SET_MESSAGE_ING_REG and define n = n + 1, and then jump to step 4.(b).
5. Apply SHA padding to message
A
(a) Users apply SHA padding to the last message block as described in Section 18.3.1, write this block
to register HMAC_WDATA0~15_REG, and then write 1 to register
HMAC_SET_MESSAGE_ONE_REG. Then the HMAC module will process this message block.
(b) Jump to step 6.
IN
6. Read hash result in upstream mode
(a) Poll Status register HMAC_QUERY_BUSY_REG until it reads 0.
IM
(b) Read hash result from register HMAC_RDATA0~7_REG.
(c) Write 1 to register HMAC_SET_RESULT_FINISH_REG to finish calculation. The result will be cleared
at the same time.
(d) Upstream mode operation is completed.
EL
Note:
The SHA accelerator can be called directly, or used internally by the DS module and the HMAC module. However, they
can not share the hardware resources simultaneously. Therefore, the SHA module must not be called neither by the CPU
nor by the DS module when the HMAC module is in use.
PR
18.3 HMAC Algorithm Details
18.3.1 Padding Bits
The HMAC module uses SHA-256 as hash algorithm. If the input message is not a multiple of 512 bits, the user
must apply a SHA-256 padding algorithm in software. The SHA-256 padding algorithm is the same as described
in Section Padding the Message of FIPS PUB 180-4. In downstream mode, users do not need to input any
message or apply padding. The HMAC module uses a default 32-byte pattern of 0x00 for re-enabling JTAG and
a 32-byte pattern of 0xff for deriving the AES key for the DS module.
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As shown in Figure 18-1, suppose the length of the unpadded message is m bits. Padding steps are as
follows:
1. Append one bit of value “1” to the end of the unpadded message;
2. Append k bits of value “0”, where k is the smallest non-negative number which satisfies
m + 1 + k≡448(mod512);
3. Append a 64-bit integer value as a binary block. This block consists of the length of the unpadded
message as a big-endian binary integer value m.
RY
Figure 181. HMAC SHA256 Padding Diagram
A
In upstream mode, if the length of the unpadded message is a multiple of 512 bits, users can configure hardware
to apply SHA padding by writing 1 to HMAC_SET_MESSGAE_END_REG or do padding work themselves by
writing 1 to HMAC_SET_MESSAGE_PAD_REG. If the length is not a multiple of 512 bits, SHA padding must be
IN
manually applied by the user. After the user prepared the padding data, they should complete the subsequent
configuration according to the Section 18.2.5.
18.3.2 HMAC Algorithm Structure
IM
The structure of the implemented algorithm in the HMAC module is shown in Figure 18-2. This is the standard
HMAC algorithm as described in RFC 2104.
EL
PR
Figure 182. HMAC Structure Schematic Diagram
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In Figure 18-2:
1. ipad is a 512-bit message block composed of 64 bytes of 0x36.
2. opad is a 512-bit message block composed of 64 bytes of 0x5c.
The HMAC module appends a 256-bit 0 sequence after the bit sequence of the 256-bit key k in order to get a
512-bit K0 . Then, the HMAC module XORs K0 with ipad to get the 512-bit S1. Afterwards, the HMAC module
appends the input message (multiple of 512 bits) after the 512-bit S1, and exercises the SHA-256 algorithm to
get the 256-bit H1.
The HMAC module appends the 256-bit SHA-256 hash result H1 to the 512-bit S2 value, which is calculated
using the XOR operation of K0 and opad. A 768-bit sequence will be generated. Then, the HMAC module uses
the SHA padding algorithm described in Section 18.3.1 to pad the 768-bit sequence to a 1024-bit sequence,
RY
and applies the SHA-256 algorithm to get the final hash result (256-bit).
A
IN
IM
EL
PR
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18.4 Register Summary
The addresses in this section are relative to HMAC Accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
Control/Status Registers
HMAC_SET_START_REG HMAC start control register 0x0040 WO
HMAC_SET_PARA_FINISH_REG HMAC configuration completion register 0x004C WO
HMAC_SET_MESSAGE_ONE_REG HMAC message control register 0x0050 WO
HMAC_SET_MESSAGE_ING_REG HMAC message continue register 0x0054 WO
HMAC_SET_MESSAGE_END_REG HMAC message end register 0x0058 WO
RY
HMAC_SET_RESULT_FINISH_REG HMAC result reading finish register 0x005C WO
HMAC_SET_INVALIDATE_JTAG_REG Invalidate JTAG result register 0x0060 WO
HMAC_SET_INVALIDATE_DS_REG Invalidate digital signature result register 0x0064 WO
HMAC_QUERY_ERROR_REG Stores matching results between keys gener- 0x0068 RO
ated by users and corresponding purposes
A
HMAC_QUERY_BUSY_REG Busy state of HMAC module 0x006C RO
configuration Registers
HMAC_SET_PARA_PURPOSE_REG HMAC parameter configuration register 0x0044 WO
HMAC_SET_PARA_KEY_REG
HMAC_SOFT_JTAG_CTRL_REG
IN
HMAC parameters configuration register
Re-enable JTAG register 0
0x0048
0x00F8
WO
WO
HMAC_WR_JTAG_REG Re-enable JTAG register 1 0x00FC WO
HMAC Message Block
IM
HMAC_WR_MESSAGE_0_REG Message register 0 0x0080 WO
HMAC_WR_MESSAGE_1_REG Message register 1 0x0084 WO
HMAC_WR_MESSAGE_2_REG Message register 2 0x0088 WO
HMAC_WR_MESSAGE_3_REG Message register 3 0x008C WO
HMAC_WR_MESSAGE_4_REG Message register 4 0x0090 WO
EL
HMAC_WR_MESSAGE_5_REG Message register 5 0x0094 WO
HMAC_WR_MESSAGE_6_REG Message register 6 0x0098 WO
HMAC_WR_MESSAGE_7_REG Message register 7 0x009C WO
HMAC_WR_MESSAGE_8_REG Message register 8 0x00A0 WO
HMAC_WR_MESSAGE_9_REG Message register 9 0x00A4 WO
PR
HMAC_WR_MESSAGE_10_REG Message register 10 0x00A8 WO
HMAC_WR_MESSAGE_11_REG Message register 11 0x00AC WO
HMAC_WR_MESSAGE_12_REG Message register 12 0x00B0 WO
HMAC_WR_MESSAGE_13_REG Message register 13 0x00B4 WO
HMAC_WR_MESSAGE_14_REG Message register 14 0x00B8 WO
HMAC_WR_MESSAGE_15_REG Message register 15 0x00BC WO
HMAC Upstream Result
HMAC_RD_RESULT_0_REG Hash result register 0 0x00C0 RO
HMAC_RD_RESULT_1_REG Hash result register 1 0x00C4 RO
HMAC_RD_RESULT_2_REG Hash result register 2 0x00C8 RO
HMAC_RD_RESULT_3_REG Hash result register 3 0x00CC RO
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Name Description Address Access
HMAC_RD_RESULT_4_REG Hash result register 4 0x00D0 RO
HMAC_RD_RESULT_5_REG Hash result register 5 0x00D4 RO
HMAC_RD_RESULT_6_REG Hash result register 6 0x00D8 RO
HMAC_RD_RESULT_7_REG Hash result register 7 0x00DC RO
Control/Status Registers
HMAC_SET_MESSAGE_PAD_REG Software padding register 0x00F0 WO
HMAC_ONE_BLOCK_REG One block message register 0x00F4 WO
Version Register
HMAC_DATE_REG Version control register 0x00F8 R/W
A RY
IN
IM
EL
PR
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18.5 Registers
The addresses in this section are relative to HMAC Accelerator base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 18.1. HMAC_SET_START_REG (0x0040)
TR
TA
_S
ET
d)
_S
ve
AC
ser
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
HMAC_SET_START Set this bit to enable HMAC. (WO)
Register 18.2. HMAC_SET_PARA_FINISH_REG (0x004C)
A
D
EN
A_
AR
_P
IN
ET
)
_S
d
ve
AC
r
se
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IM
HMAC_SET_PARA_END Set this bit to finish HMAC configuration. (WO)
Register 18.3. HMAC_SET_MESSAGE_CALC_BLOCK_REG (0x0050)
EL
NE
O
T_
EX
_T
ET
d)
_S
e
rv
AC
se
HM
(re
PR
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_TEXT_ONE Call SHA to calculate one message block. (WO)
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Register 18.4. HMAC_SET_MESSAGE_ING_REG (0x0054)
G
_ IN
EXT
_T
ET
d)
_S
ve
AC
ser
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_TEXT_ING Set this bit to show there are still some message blocks to be processed.
(WO)
RY
Register 18.5. HMAC_SET_MESSAGE_END_REG (0x0058)
D
_ EN
EXT
_T
A
ET
d)
_S
ve
AC
r
se
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_TEXT_END Set this bit to start hardware padding. (WO)
IM
Register 18.6. HMAC_SET_RESULT_FINISH_REG (0x005C)
D
EN
_
LT
SU
EL
E
_R
ET
d)
_S
e
rv
AC
se
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PR
HMAC_SET_RESULT_END Set this bit to exit upstream mode and clear calculation results. (WO)
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Register 18.7. HMAC_SET_INVALIDATE_JTAG_REG (0x0060)
G
TA
_J
E
AT
ID
AL
NV
_I
ET
d)
_S
ve
AC
ser
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_INVALIDATE_JTAG Set this bit to clear calculation results when re-enabling JTAG in
RY
downstream mode. (WO)
Register 18.8. HMAC_SET_INVALIDATE_DS_REG (0x0064)
S
_D
A
E
AT
ID
AL
NV
_I
ET
)
_S
d
IN
ve
AC
ser
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IM
HMAC_SET_INVALIDATE_DS Set this bit to clear calculation results of the DS module in downstream
mode. (WO)
Register 18.9. HMAC_QUERY_ERROR_REG (0x0068)
EL
CK
HE
_C
EY
UR
)
_Q
ed
rv
AC
se
HM
(re
PR
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_QUREY_CHECK Indicates whether an HMAC key matches the purpose.(RO)
• 0: HMAC key and purpose match.
• 1: error.
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18 HMAC Accelerator (HMAC)
Register 18.10. HMAC_QUERY_BUSY_REG (0x006C)
TE
TA
Y _S
US
d)
_B
ve
AC
r
se
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_BUSY_STATE Indicates whether HMAC is in busy state. Before configuring HMAC, please
make sure HMAC is in IDLE state. (RO)
RY
• 0: idle.
• 1: HMAC is still working on calculation.
Register 18.11. HMAC_SET_PARA_PURPOSE_REG (0x0044)
A
ET
_S
SE
PO
UR
IN
)
_P
ed
rv
AC
se
HM
(re
31 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IM
HMAC_PURPOSE_SET Determines the HMAC purpose, refer to the Table 18-1. (WO)
Register 18.12. HMAC_SET_PARA_KEY_REG (0x0048)
EL
T
SE
E Y_
d)
_K
e
rv
AC
se
HM
(re
31 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PR
HMAC_KEY_SET Selects HMAC key. There are six keys with index 0~5. Write the index of the
selected key to this field. (WO)
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Register 18.13. HMAC_WR_MESSAGE_n_REG (n: 015) (0x0080+4*n)
0_
TA
DA
_W
AC
HM
31 0
0 Reset
HMAC_WDATA_n Store the nth 32-bit of message. (WO)
RY
Register 18.14. HMAC_RD_RESULT_n_REG (n: 07) (0x00C0+4*n)
_0
TA
DA
_R
AC
HM
31 0
A
0 Reset
HMAC_RDATA_n Read the nth 32-bit of hash result. (RO)
IN
Register 18.15. HMAC_SET_MESSAGE_PAD_REG (0x00F0)
IM
D
_ PA
XT
E
_T
ET
d)
_S
ve
AC
r
se
HM
(re
31 1 0
EL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_TEXT_PAD Set this bit to indicate that padding is applied by software. (WO)
PR
Register 18.16. HMAC_ONE_BLOCK_REG (0x00F4)
CK
LO
_B
NE
_O
ET
)
_S
ed
rv
AC
se
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_ONE_BLOCK Set this bit when there is only one block which already contins padding
bits. (WO)
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Register 18.17. HMAC_SOFT_JTAG_CTRL_REG (0x00F8)
L
TR
_C
G
TA
_J
FT
O
d)
_S
ve
AC
ser
HM
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SOFT_JTAG_CTRL Set this bit to enable JTAG authentication mode. (WO)
RY
Register 18.18. HMAC_WR_JTAG_REG (0x00FC)
AG
JT
R_
_W
AC
A
HM
31 0
IN x Reset
HMAC_WR_JTAG Set this field to re-enable the JTAG comparing input register. (WO)
Register 18.19. HMAC_DATE_REG (0x00F8)
IM
E
AT
)
_D
ed
rv
AC
se
HM
(re
31 30 29 0
EL
0 0 0x20200618 Reset
HMAC_DATE Version control register. (R/W)
PR
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19 Digital Signature (DS)
19 Digital Signature (DS)
19.1 Overview
A Digital Signature is used to verify the authenticity and integrity of a message using a cryptographic algorithm.
This can be used to validate a device’s identity to a server, or to check the integrity of a message.
The ESP32-C3 includes a Digital Signature (DS) module providing hardware acceleration of messages’ signatures
based on RSA. It uses pre-encrypted parameters to calculate a signature. The parameters are encrypted using
HMAC as a key-derivation function. In turn, the HMAC uses eFuses as an input key. The whole process happens
in hardware so that neither the decryption key for the RSA parameters nor the input key for the HMAC key
RY
derivation function can be seen by the software while calculating the signature.
19.2 Features
• RSA digital signatures with key length up to 3072 bits
• Encrypted private key data, only decryptable by DS module
A
• SHA-256 digest to protect private key data against tampering by an attacker
19.3 Functional Description
IN
19.3.1 Overview
The DS peripheral calculates RSA signature as Z = X Y mod M where Z is the signature, X is the input
IM
message, and Y and M are the RSA private key parameters.
Private key parameters are stored in flash as ciphertext. They are decrypted using a key (DS_KEY ) which can
only be calculated by the DS peripheral via the HMAC peripheral. The required inputs (HM AC_KEY ) to
generate the key are only stored in eFuse and can only be accessed by the HMAC peripheral. That is to say, the
EL
DS peripheral hardware can decrypt the private key, and the private key in plaintext is never accessed by the
software. For more detailed information about eFuse and HMAC peripherals, please refer to Chapter 4 eFuse
Controller (EFUSE) and 18 HMAC Accelerator (HMAC) peripheral.
The input message X will be sent directly to the DS peripheral by the software each time a signature is needed.
After the RSA signature operation, the signature Z is read back by the software.
PR
For better understanding, we define some symbols and functions here, which are only applicable to this
chapter:
• 1s A bit string consist of s bits with the value of “1”.
• [x]s A bit string of s bits, in which s should be an integer multiple of 8 bits. If x is a number (x < 2s ), it is
represented in little endian byte order in the bit string. x may be a variable such as [Y ]4096 or as a
hexadecimal constant such as [0x0C]8 . If necessary, the value [x]t can be right-padded with (s − t)
number of 0 to reach s bits in length, and finally get [x]s . For example, [0x05]8 = 00000101,
[0x05]16 = 0000010100000000, [0x0005]16 = 0000000000000101, [0x13]8 = 00010011,
[0x13]16 = 0001001100000000, [0x0013]16 = 0000000000010011.
• || A bit string concatenation operator for joining multiple bit strings into a longer bit string.
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19 Digital Signature (DS)
19.3.2 Private Key Operands
Private key operands Y (private key exponent) and M (key modulus) are generated by you. They have a
particular RSA key length (up to 3072 bits). Two additional private key operands are needed: r and M ′ . These
two operands are derived from Y and M .
Operands Y , M , r and M ′ are encrypted by you along with an authentication digest and stored as a single
ciphertext C. C is input to the DS peripheral in this encrypted format, decrypted by the hardware, and then used
for RSA signature calculation. Detailed description of how to generate C is provided in Section 19.3.3.
The DS peripheral supports RSA signature calculation Z = X Y mod M , in which the length of operands should
be N = 32 × x where x ∈ {1, 2, 3, . . . , 96}. The bit lengths of arguments Z, X, Y , M and r should be an
arbitrary value in N , and all of them in a calculation must be of the same length, while the bit length of M ′ should
RY
always be 32. For more detailed information about RSA calculation, please refer to Section 17.3.1 Large Number
Modular Exponentiation in Chapter 17 RSA Accelerator (RSA).
19.3.3 Software Prerequisites
If you want to use the DS module for digital signature, the software and hardware must work closely to implement
A
this successfully, and the software needs to do a series of preparations, as shown in Figure 19-1. The left side
lists preparations required by the software before the hardware starts RSA signature calculation, while the right
side lists the hardware workflow during the entire calculation procedure.
IN
IM
EL
PR
Figure 191. Software Preparations and Hardware Working Process
Note:
1. The software preparation (left side in the Figure 19-1) is a one-time operation before any signature is calculated,
while the hardware calculation (right side in the Figure 19-1) repeats for every signature calculation.
You need to follow the steps shown in the left part of Figure 19-1 to calculate C. Detailed instructions are as
follows:
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• Step 1: Prepare operands Y and M whose lengths should meet the requirements in Section 19.3.2.
N
Define [L]32 = 32 (i.e., for RSA 3072, [L]32 == [0x60]32 ). Prepare [HM AC_KEY ]256 and calculate
[DS_KEY ]256 based on DS_KEY = HMAC-SHA256 ([HM AC_KEY ]256 , 1256 ). Generate a random
[IV ]128 which should meet the requirements of the AES-CBC block encryption algorithm. For more
information on AES, please refer to Chapter 16 AES Accelerator (AES).
• Step 2: Calculate r and M ′ based on M .
• Step 3: Extend Y , M and r, in order to get [Y ]3072 , [M ]3072 and [r]3072 , respectively. This step is only
required for Y , M and r whose length are less than 3072 bits, since their largest length are 3072 bits.
• Step 4: Calculate MD authentication code using the SHA-256:
[M D]256 = SHA256 ([Y ]3072 ||[M ]3072 ||[r]3072 ||[M ′ ]32 ||[L]32 ||[IV ]128 )
RY
• Step 5: Build [P ]9600 = ( [Y ]3072 ||[M ]3072 ||[r]3072 ||[Box]384 ), where [Box]384 = (
[M D]256 ||[M ′ ]32 ||[L]32 ||[β]64 ) and [β]64 is a PKCS#7 padding value, i.e., a [0x0808080808080808]64
string composed of 8 bytes (0x80). The purpose of [β]64 is to make the bit length of P a multiple of 128.
• Step 6: Calculate C = [C]9600 = AES-CBC-ENC ([P ]9600 , [DS_KEY ]256 , [IV ]128 ), where C is the
ciphertext with a length of 1200 bytes. C can also be calculated as C = [C]9600 =
A
([Yb ]3072 ||[M
c]3072 ||[b d 384 ), where [Yb ]3072 , [M
r]3072 ||[Box] c]3072 , [b d 384 are the four sub-parameters of
r]3072 , [Box]
C, and correspond to the ciphertext of [Y ]3072 , [M ]3072 , [r]3072 , [Box]384 respectively.
IN
19.3.4 DS Operation at the Hardware Level
The hardware operation is triggered each time a digital signature needs to be calculated. The inputs are the
pre-generated private key ciphertext C, a unique message X, and IV .
IM
The DS operation at the hardware level can be divided into the following three stages:
1. Decryption: Step 7 and 8 in Figure 191
The decryption process is the inverse of Step 6 in figure 19-1. The DS module will call AES accelerator to
decrypt C in CBC block mode and get the resulted plaintext. The decryption process can be represented
EL
by P = AES-CBC-DEC (C, DS_KEY , IV ), where IV (i.e., [IV ]128 ) is defined by you. [DS_KEY ]256 is
provided by HMAC module, derived from HM AC_KEY stored in eFuse. [DS_KEY ]256 , as well as
[HM AC_KEY ]256 are not readable by the software.
With P, the DS module can derive [Y ]3072 , [M ]3072 , [r]3072 , [M ′ ]32 , [L]32 , MD authentication code, and the
padding value [β]64 . This process is the inverse of Step 5.
PR
2. Check: Step 9 and 10 in Figure 191
The DS module will perform two checks: MD check and padding check. Padding check is not shown in
Figure 19-1, as it happens at the same time with MD check.
• MD check: The DS module calls SHA-256 to calculate the hash value [CALC_M D]256 (i.e., step 4).
Then, [CALC_M D]256 is compared against the MD authentication code [M D]256 from step 4. Only
when the two match does the MD check pass.
• Padding check: The DS module checks if [β]64 complies with the aforementioned PKCS#7 format.
Only when [β]64 complies with the format does the padding check pass.
The DS module will only perform subsequent operations if MD check passes. If padding check fails, a
warning message is generated, but it does not affect the subsequent operations.
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3. Calculation: Step 11 and 12 in Figure 191
The DS module treats X (input by you) and Y , M , r (compiled) as big numbers. With M ′ , all operands to
perform X Y mod M are in place. The operand length is defined by L only. The DS module will get the
signed result Z by calling RSA to perform Z = X Y mod M .
19.3.5 DS Operation at the Software Level
The software steps below should be followed each time a digital signature needs to be calculated. The inputs are
the pre-generated private key ciphertext C, a unique message X, and IV . These software steps trigger the
hardware steps described in Section 19.3.4.
We assume that the software has called the HMAC peripheral and HMAC on the hardware has calculated
RY
DS_KEY based on HM AC_KEY .
1. Prerequisites: Prepare operands C, X, IV according to Section 19.3.3.
2. Activate the DS peripheral: Write 1 to DS_SET_START_REG.
3. Check if DS_KEY is ready: Poll DS_QUERY_BUSY_REG until the software reads 0.
A
If the software does not read 0 in DS_QUERY_BUSY_REG after approximately 1 ms, it indicates a problem
with HMAC initialization. In such a case, the software can read register DS_QUERY_KEY_WRONG_REG to
get more information:
IN
• If the software reads 0 in DS_QUERY_KEY_WRONG_REG, it indicates that the HMAC peripheral has
not been called.
• If the software reads any value from 1 to 15 in DS_QUERY_KEY_WRONG_REG, it indicates that
IM
HMAC was called, but the DS module did not successfully get the DS_KEY value from the HMAC
peripheral. This may indicate that the HMAC operation has been interrupted due to a software
concurrency problem.
4. Configure register: Write IV block to register DS_IV_m_REG (m: 0 ~ 3). For more information on the IV
block, please refer to Chapter 16 AES Accelerator (AES).
EL
5. Write X to memory block DS_X_MEM: Write Xi (i ∈ {0, 1, . . . , n − 1}), where n = N
32 , to memory block
DS_X_MEM whose capacity is 96 words. Each word can store one base-b digit. The memory block uses
the little endian format for storage, i.e., the least significant digit of the operand is in the lowest address.
Words in DS_X_MEM block after the configured length of X (N bits, as described in Section 19.3.2), are
PR
ignored.
6. Write C to corresponding memory blocks: Write the four sub-parameters of C to corresponding
memory blocks:
• Write Ybi (i ∈ {0, 1, . . . , 95}) to DS_Y_MEM.
ci (i ∈ {0, 1, . . . , 95}) to DS_M_MEM.
• Write M
• Write b
ri (i ∈ {0, 1, . . . , 95}) to DS_RB_MEM.
d i (i ∈ {0, 1, . . . , 11}) to DS_BOX_MEM.
• write Box
The capacity of DS_Y_MEM, DS_M_MEM, and DS_RB_MEM is 96 words, whereas the capacity of
DS_BOX_MEM is only 12 words. Each word can store one base-b digit. The memory blocks use the
little endian format for storage, i.e., the least significant digit of the operand is in the lowest address.
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7. Start DS operation: Write 1 to register DS_SET_ME_REG.
8. Wait for the operation to be completed: Poll register DS_QUERY_BUSY_REG until the software reads 0.
9. Query check result: Read register DS_QUERY_CHECK_REG and conduct subsequent operations as
illustrated below based on the return value:
• If the value is 0, it indicates that both padding check and MD check pass. You can continue to get the
signed result Z.
• If the value is 1, it indicates that the padding check passes but MD check fails. The signed result Z is
invalid. The operation will resume directly from Step 11.
• If the value is 2, it indicates that the padding check fails but MD check passes. You can continue to
RY
get the signed result Z. But please note that the data does not comply with the aforementioned
PKCS#7 padding format, which may not be what you want.
• If the value is 3, it indicates that both padding check and MD check fail. In this case, some fatal errors
have occurred and the signed result Z is invalid. The operation will resume directly from Step 11.
10. Read the signed result: Read the signed result Zi (i ∈ {0, 1, . . . , n − 1}), where n = N
32 , from memory
A
block DS_Z_MEM. The memory block stores Z in little-endian byte order.
11. Exit the operation: Write 1 to DS_SET_FINISH_REG, and then poll DS_QUERY_BUSY_REG until the
software reads 0.
IN
After the operation, all the input/output registers and memory blocks are cleared.
IM
EL
PR
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19.4 Memory Summary
The addresses in this section are relative to the Digital Signature base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Size (byte) Starting Address Ending Address Access
DS_Y_MEM Memory block Y 384 0x0000 0x017F WO
DS_M_MEM Memory block M 384 0x0200 0x037F WO
DS_RB_MEM Memory block r 384 0x0400 0x057F WO
DS_BOX_MEM Memory block Box 48 0x0600 0x062F WO
DS_X_MEM Memory block X 384 0x0800 0x097F WO
DS_Z_MEM Memory block Z 384 0x0A00 0x0B7F RO
A RY
IN
IM
EL
PR
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19.5 Register Summary
The addresses in this section are relative to Digital Signature base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
Configuration Registers
DS_IV_0_REG IV block data 0x0630 WO
DS_IV_1_REG IV block data 0x0634 WO
DS_IV_2_REG IV block data 0x0638 WO
DS_IV_3_REG IV block data 0x063C WO
Status/Control Registers
RY
DS_SET_START_REG Activates the DS module 0x0E00 WO
DS_SET_ME_REG Starts DS operation 0x0E04 WO
DS_SET_FINISH_REG Ends DS operation 0x0E08 WO
DS_QUERY_BUSY_REG Status of the DS module 0x0E0C RO
DS_QUERY_KEY_WRONG_REG Checks the reason why DS_KEY is not 0x0E10 RO
A
ready
DS_QUERY_CHECK_REG Queries DS check result 0x0814 RO
Version control register
DS_DATE_REG
IN
Version control register 0x0820 W/R
IM
EL
PR
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19.6 Registers
The addresses in this section are relative to Digital Signature base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 19.1. DS_IV_m_REG (m: 03) (0x0630+4*m)
31 0
0x000000000 Reset
DS_IV_m_REG (m: 03) IV block data. (WO)
RY
Register 19.2. DS_SET_START_REG (0x0E00)
RT
TA
_S
d )
ET
ve
_S
r
se
DS
(re
A
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IN
DS_SET_START Write 1 to this register to activate the DS peripheral. (WO)
Register 19.3. DS_SET_ME_REG (0x0E04)
IM
E
_M
d)
ET
ve
_S
r
se
DS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EL
DS_SET_ME Write 1 to this register to start DS operation. (WO)
Register 19.4. DS_SET_FINISH_REG (0x0E08)
PR
SH
I NI
_F
)
ed
ET
rv
_S
se
DS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DS_SET_FINISH Write 1 to this register to end DS operation. (WO)
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Register 19.5. DS_QUERY_BUSY_REG (0x0E0C)
SY
_ BU
RY
d)
UE
ve
Q
r
se
_
DS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DS_QUERY_BUSY 1: The DS module is busy; 0: The DS module is idle. (RO)
RY
Register 19.6. DS_QUERY_KEY_WRONG_REG (0x0E10)
NG
RO
W
Y_
_ KE
RY
)
ed
UE
rv
_Q
se
A
DS
(re
31 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
DS_QUERY_KEY_WRONG 1-15: HMAC was activated, but the DS peripheral did not successfully
receive the DS_KEY from the HMAC peripheral. (The biggest value is 15); 0: HMAC is not called.
(RO)
IM
Register 19.7. DS_QUERY_CHECK_REG (0x0E14)
RO AD
ER _B
R
D_ NG
EL
_M DI
d)
DS PAD
e
rv
se
_
DS
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DS_PADDING_BAD 1: The padding check fails; 0: The padding check passes. (RO)
PR
DS_MD_ERROR 1: The MD check fails; 0: The MD check passes. (RO)
Register 19.8. DS_DATE_REG (0x0E20)
)
E
ed
AT
rv
_D
se
DS
(re
31 30 29 0
0 0 0x20200618 Reset
DS_DATE Version control register. (R/W)
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20 Clock Glitch Detection
20 Clock Glitch Detection
时钟毛刺检测
20.1 Overview
1.
The概述
Clock Glitch Detection module on ESP32-C3 detects glitches in external crystal XTAL_CLK signals, and
为提升a ESP32-S2
generates system reset的安全性能，防止攻击者通过给外部晶振 XTAL
signal when detecting glitches to reset the whole 附加毛刺，使芯片进入异常状态，
digital circuit including RTC. By doing
从而实施对芯片的攻击， ESP32-S2
so, it prevents attackers from injecting glitches
搭载了毛刺检测模块 ,Glitch_Detect)
on external crystal XTAL_CLK clock to compromise ESP32-C3
，用于检测从外部晶振输入的
and thus strengthens
XTAL_CLK chip security.
是否携带毛刺，并在检测到毛刺后，发送中断或者产生系统复位信号。
20.2
2. Functional Description
功能描述
RY
20.2.1 Clock Glitch Detection
2.1 毛刺检测
The Clock Glitch Detection module on ESP32-C3 monitors input clock signals from XTAL_CLK. If it detects a
ESP32-S2
glitch, 的毛刺检测模块将对输入芯片的
namely a clock XTAL_CLK
pulse (a or b in the figure below) shorter than 3 ns, input clock signals ,a
with a width 时钟信号进行检测，当时钟的脉宽 或
from :)小
于 3ns 时，将认为检测到毛刺，触发毛刺检测信号
XTAL_CLK are blocked. ,屏蔽输入的 XTAL_CLK 时钟信号。
A
a a
IN
XTAL_CLK
b
IM
Figure 201. XTAL_CLK Pulse Width
2.2 中断及复位
20.2.2 Reset
EL
当毛刺检测信号触发后，毛刺检测模块将向系统发送中断,GLITCH_DET_INT)，如果
Once detecting a glitch on XTAL_CLK that affects the circuit’s normal operation, the Clock Glitch Detection
RTC_CNTL_GLITCH_RST_EN 使能，将触发系统级复位。
module triggers a system reset if RTC_CNTL_GLITCH_RST_EN bit is enabled. By default, this bit is set to enable
a reset.
PR
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21 Random Number Generator (RNG)
21 Random Number Generator (RNG)
21.1 Introduction
The ESP32-C3 contains a true random number generator, which generates 32-bit random numbers that can be
used for cryptographical operations, among other things.
21.2 Features
The random number generator in ESP32-C3 generates true random numbers, which means random number
generated from a physical process, rather than by means of an algorithm. No number generated within the
RY
specified range is more or less likely to appear than any other number.
21.3 Functional Description
Every 32-bit value that the system reads from the RNG_DATA_REG register of the random number generator is a
true random number. These true random numbers are generated based on the thermal noise in the system and
A
the asynchronous clock mismatch.
• Thermal noise comes from the high-speed ADC or SAR ADC or both. Whenever the high-speed ADC or
IN
SAR ADC is enabled, bit streams will be generated and fed into the random number generator through an
XOR logic gate as random seeds.
• RTC20M_CLK is an asynchronous clock source and it increases the RNG entropy by introducing circuit
metastability.
IM
Random bit
SAR ADC
seeds XOR
XOR
Random RNG_DATA_REG
Number
Generator
High Speed Random bit
seeds
EL
ADC
Random bit
RTC20M_CLK
seeds
Figure 211. Noise Source
PR
When there is noise coming from the SAR ADC, the random number generator is fed with a 2-bit entropy in one
clock cycle of RTC20M_CLK (20 MHz), which is generated from an internal RC oscillator (see Chapter 6 Reset
and Clock for details). Thus, it is advisable to read the RNG_DATA_REG register at a maximum rate of 1 MHz to
obtain the maximum entropy.
When there is noise coming from the high-speed ADC, the random number generator is fed with a 2-bit entropy
in one APB clock cycle, which is normally 80 MHz. Thus, it is advisable to read the RNG_DATA_REG register at a
maximum rate of 5 MHz to obtain the maximum entropy.
A data sample of 2 GB, which is read from the random number generator at a rate of 5 MHz with only the
high-speed ADC being enabled, has been tested using the Dieharder Random Number Testsuite (version 3.31.1).
The sample passed all tests.
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21.4 Programming Procedure
When using the random number generator, make sure at least either the SAR ADC, high-speed ADC1 , or
RTC20M_CLK2 is enabled. Otherwise, pseudo-random numbers will be returned.
• SAR ADC can be enabled by using the DIG ADC controller. For details, please refer to Chapter 28 On-Chip
Sensor and Analog Signal Processing.
• High-speed ADC is enabled automatically when the Wi-Fi or Bluetooth modules is enabled.
• RTC20M_CLK is enabled by setting the RTC_CNTL_DIG_CLK20M_EN bit in the
RTC_CNTL_CLK_CONF_REG register.
RY
Note:
1. Note that, when the Wi-Fi module is enabled, the value read from the high-speed ADC can be saturated in some
extreme cases, which lowers the entropy. Thus, it is advisable to also enable the SAR ADC as the noise source for
the random number generator for such cases.
2. Enabling RTC20M_CLK increases the RNG entropy. However, to ensure maximum entropy, it’s recommended to
always enable an ADC source as well.
A
When using the random number generator, read the RNG_DATA_REG register multiple times until sufficient
IN
random numbers have been generated. Ensure the rate at which the register is read does not exceed the
frequencies described in section 21.3 above.
21.5 Register Summary
IM
The address in the following table is relative to the random number generator base address provided in Table 3-4
in Chapter 3 System and Memory.
Name Description Address Access
EL
RNG_DATA_REG Random number data 0x00B0 RO
21.6 Register
The address in this section is relative to the random number generator base address provided in Table 3-4 in
PR
Chapter 3 System and Memory.
Register 21.1. RNG_DATA_REG (0x00B0)
31 0
0x00000000 Reset
RNG_DATA Random number source. (RO)
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22 UART Controller (UART)
22 UART Controller (UART)
22.1 Overview
In embedded system applications, data is required to be transferred in a simple way with minimal system
resources. This can be achieved by a Universal Asynchronous Receiver/Transmitter (UART), which flexibly
exchanges data with other peripheral devices in full-duplex mode. ESP32-C3 has two UART controllers
compatible with various UART devices. They support Infrared Data Association (IrDA) and RS485
transmission.
Each of the two UART controllers has a group of registers that function identically. In this chapter, the two UART
RY
controllers are referred to as UARTn, in which n denotes 0 or 1.
A UART is a character-oriented data link for asynchronous communication between devices. Such
communication does not add clock signals to data sent. Therefore, in order to communicate successfully, the
transmitter and the receiver must operate at the same baud rate with the same stop bit and parity bit.
A UART data frame usually begins with one start bit, followed by data bits, one parity bit (optional) and one or
A
more stop bits. UART controllers on ESP32-C3 support various lengths of data bits and stop bits. These
controllers also support software and hardware flow control as well as GDMA for seamless high-speed data
transfer. This allows developers to use multiple UART ports at minimal software cost.
22.2 Features
IN
Each UART controller has the following features:
IM
• Three clock sources that can be divided
• Programmable baud rate
• 512 x 8-bit RAM shared by TX FIFOs and RX FIFOs of the two UART controllers
• Full-duplex asynchronous communication
EL
• Automatic baud rate detection of input signals
• Data bits ranging from 5 to 8
• Stop bits whose length can be 1, 1.5, 2 or 3 bits
PR
• Parity bit
• Special character AT_CMD detection
• RS485 protocol
• IrDA protocol
• High-speed data communication using GDMA
• UART as wake-up source
• Software and hardware flow control
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22.3 UART Structure
A RY
IN
IM
Figure 221. UART Structure
Figure 22-1 shows the basic structure of a UART controller. A UART controller works in two clock domains,
namely APB_CLK domain and Core Clock domain (the UART Core’s clock domain). The UART Core has three
EL
clock sources: a 80 MHz APB_CLK, FOSC_CLK and external crystal clock XTAL_CLK (for details, please refer to
Chapter 6 Reset and Clock), which are selected by configuring UART_SCLK_SEL. The selected clock source is
divided by a divider to generate clock signals that drive the UART Core. The divisor is configured by
UART_CLKDIV_REG: UART_CLKDIV for the integral part, and UART_CLKDIV_FRAG for the fractional
part.
PR
A UART controller is broken down into two parts according to functions: a transmitter and a receiver.
The transmitter contains a TX FIFO, which buffers data to be sent. Software can write data to Tx_FIFO via the
APB bus, or move data to Tx_FIFO using GDMA. Tx_FIFO_Ctrl controls writing and reading Tx_FIFO. When
Tx_FIFO is not empty, Tx_FSM reads data bits in the data frame via Tx_FIFO_Ctrl, and converts them into a
bitstream. The levels of output signal txd_out can be inverted by configuring UART_TXD_INV field.
The receiver contains a RX FIFO, which buffers data to be processed. The levels of input signal rxd_in can be
inverted by configuring UART_RXD_INV field. Baudrate_Detect measures the baud rate of input signal rxd_in by
detecting its minimum pulse width. Start_Detect detects the start bit in a data frame. If the start bit is detected,
Rx_FSM stores data bits in the data frame into Rx_FIFO by Rx_FIFO_Ctrl. Software can read data from Rx_FIFO
via the APB bus, or receive data using GDMA.
HW_Flow_Ctrl controls rxd_in and txd_out data flows by standard UART RTS and CTS flow control signals
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22 UART Controller (UART)
(rtsn_out and ctsn_in). SW_Flow_Ctrl controls data flows by automatically adding special characters to outgoing
data and detecting special characters in incoming data. When a UART controller is Light-sleep mode (see
Chapter 4 Low-Power Management (RTC_CNTL) [to be added later] for more details), Wakeup_Ctrl counts up
rising edges of rxd_in. When the number reaches (UART_ACTIVE_THRESHOLD + 2), a wake_up signal is
generated and sent to RTC, which then wakes up the ESP32-C3 chip.
22.4 Functional Description
22.4.1 Clock and Reset
UART controllers are asynchronous. Their register configuration module, TX FIFO and RX FIFO are in APB_CLK
domain, while the UART Core that controls transmission and reception is in Core Clock domain. The three clock
RY
sources of the UART core, namely APB_CLK, FOSC_CLK and external crystal clock XTAL_CLK, are selected by
configuring UART_SCLK_SEL. The selected clock source is divided by a divider. This divider supports fractional
frequency division: UART_SCLK_DIV_NUM field is the integral part, UART_SCLK_DIV_B field is the numerator of
the fractional part, and UART_SCLK_DIV_A is the denominator of the fractional part. The divisor ranges from 1 ~
256.
A
In cases when UART baud rate meet the needs, the UART Core can work at a lower clock frequency by division,
to reduce power consumption. Usually the frequency of the UART Core’s clock is lower than that of APB_CLK,
and the UART Core’s clock divisor can be configured to the maximum when baud rate can meet the needs. The
IN
frequency of the UART Core’s clock can also be higher than that of APB_CLK, at most three times that of
APB_CLK. The clock for the UART transmitter and the UART receiver can be controlled independently. To enable
the clock for the UART transmitter, please set UART_TX_SCLK_EN; to enable the clock for the UART receiver,
set UART_RX_SCLK_EN.
IM
To ensure that the configured register values are synchronized from APB_CLK domain to Core Clock domain,
please follow procedures in Section22.5.
To reset the whole UART, please:
• enable the clock for UART RAM by setting SYSTEM_UART_MEM_CLK_EN to 1;
EL
• enable APB_CLK for UARTn by setting SYSTEM_UARTn_CLK_EN to 1
• clear SYSTEM_UARTn_RST to 0;
• write 1 to UART_RST_CORE;
PR
• write 1 to SYSTEM_UARTn_RST;
• clear SYSTEM_UARTn_RST to 0;
• clear UART_RST_CORE to 0.
Note that it is not recommended to reset the APB clock domain module or UART Core only.
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22.4.2 UART RAM
Figure 222. UART Controllers Sharing RAM
RY
The two UART controllers on ESP32-C3 share 512 × 8 bits of FIFO RAM. As Figure 22-2 illustrates, RAM is
divided into 4 blocks, each has 128 × 8 bits. Figure 22-2 shows how many RAM blocks are allocated to TX
FIFOs and RX FIFOs of the two UART controllers by default. UARTn Tx_FIFO can be expanded by configuring
UART_TX_SIZE, while UARTn Rx_FIFO can be expanded by configuring UART_RX_SIZE. The size of UART0
A
Tx_FIFO can be increased to 4 blocks (the whole RAM), the size of UART1 Tx_FIFO can be increased to 3 blocks
(from offset 128 to the end address), the size of UART0 Rx_FIFO can be increased to 2 blocks (from offset 256 to
the end address), but the size of UART1 Rx_FIFO cannot be increased. Please note that starting addresses of all
IN
FIFOs are fixed, so expanding one FIFO may take up the default space of other FIFOs. For example, by setting
UART_TX_SIZE of UART0 to 2, the size of UART0 Tx_FIFO is increased by 128 bytes (from offset 0 to offset 255).
In this case, UART0 Tx_FIFO takes up the default space for UART1 Tx_FIFO, and UART1’s transmitting function
cannot be used as a result.
IM
When neither of the two UART controllers is active, RAM could enter low-power mode by setting
UART_MEM_FORCE_PD.
UART0 Tx_FIFO and UART1 Tx_FIFO are reset by setting UART_TXFIFO_RST. UART0 Rx_FIFO and UART1
Rx_FIFO are reset by setting UART_RXFIFO_RST.
EL
Data to be sent is written to TX FIFO via the APB bus or using GDMA, read automatically and converted from a
frame into a bitstream by hardware Tx_FSM; data received is converted from a bitstream into a frame by
hardware Rx_FSM, written into RX FIFO, and then stored into RAM via the APB bus or using GDMA. The two
UART controllers share one GDMA channel.
PR
The empty signal threshold for Tx_FIFO is configured by setting UART_TXFIFO_EMPTY_THRHD. When data
stored in Tx_FIFO is less than UART_TXFIFO_EMPTY_THRHD, a UART_TXFIFO_EMPTY_INT interrupt is
generated. The full signal threshold for Rx_FIFO is configured by setting UART_RXFIFO_FULL_THRHD. When
data stored in Rx_FIFO is greater than UART_RXFIFO_FULL_THRHD, a UART_RXFIFO_FULL_INT interrupt is
generated. In addition, when Rx_FIFO receives more data than its capacity, a UART_RXFIFO_OVF_INT interrupt
is generated.
UARTn can access FIFO via register UART_FIFO_REG. You can put data into TX FIFO by writing
UART_RXFIFO_RD_BYTE, and get data in RX FIFO by reading UART_RXFIFO_RD_BYTE.
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22.4.3 Baud Rate Generation and Detection
22.4.3.1 Baud Rate Generation
Before a UART controller sends or receives data, the baud rate should be configured by setting corresponding
registers. The baud rate generator of a UART controller functions by dividing the input clock source. It can divide
the clock source by a fractional amount. The divisor is configured by UART_CLKDIV_REG: UART_CLKDIV for the
integral part, and UART_CLKDIV_FRAG for the fractional part. When using the 80 MHz input clock, the UART
controller supports a maximum baud rate of 5 Mbaud.
The divisor of the baud rate divider is equal to UART_CLKDIV + (UART_CLKDIV_FRAG/16), meaning that the
final baud rate is equal to INPUT_FREQ/(UART_CLKDIV + (UART_CLKDIV_FRAG/16)). For example, if
RY
UART_CLKDIV = 694 and UART_CLKDIV_FRAG = 7 then the divisor value is (694 + 7/16) = 694.4375. Note:
INPUT_FREQ is the frequency of UART Cores’ clock.
When UART_CLKDIV_FRAG is 0, the baud rate generator is an integer clock divider where an output pulse is
generated every UART_CLKDIV input pulses.
When UART_CLKDIV_FRAG is not 0, the divider is fractional and the output baud rate clock pulses are not
A
strictly uniform. As shown in Figure 22-3, for every 16 output pulses, the generator divides either (UART_CLKDIV
+ 1) input pulses or UART_CLKDIV input pulses per output pulse. A total of UART_CLKDIV_FRAG output pulses
are generated by dividing (UART_CLKDIV + 1) input pulses, and the remaining (16 - UART_CLKDIV_FRAG)
IN
output pulses are generated by dividing UART_CLKDIV input pulses.
The output pulses are interleaved as shown in Figure 22-3 below, to make the output timing more uniform:
IM
EL
Figure 223. UART Controllers Division
PR
To support IrDA (see Section 22.4.6 for details), the fractional clock divider for IrDA data transmission generates
clock signals divided by 16 × UART_CLKDIV_REG. This divider works similarly as the one elaborated above: it
takes UART_CLKDIV/16 as the integer value and the lowest four bits of UART_CLKDIV as the fractional
value.
22.4.3.2 Baud Rate Detection
Automatic baud rate detection (Autobaud) on UARTs is enabled by setting UART_AUTOBAUD_EN. The
Baudrate_Detect module shown in Figure 22-1 filters any noise whose pulse width is shorter than
UART_GLITCH_FILT.
Before communication starts, the transmitter could send random data to the receiver for baud rate detection.
UART_LOWPULSE_MIN_CNT stores the minimum low pulse width, UART_HIGHPULSE_MIN_CNT stores the
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minimum high pulse width, UART_POSEDGE_MIN_CNT stores the minimum pulse width between two rising
edges, and UART_NEGEDGE_MIN_CNT stores the minimum pulse width between two falling edges. These four
fields are read by software to determine the transmitter’s baud rate.
RY
Figure 224. The Timing Diagram of Weak UART Signals Along Falling Edges
Baud rate can be determined in the following three ways:
1. Normally, to avoid sampling erroneous data along rising or falling edges in metastable state, which results in
A
inaccuracy of UART_LOWPULSE_MIN_CNT or UART_HIGHPULSE_MIN_CNT, use a weighted average of
these two values to eliminate errors. In this case, baud rate is calculated as follows:
fclk
Buart =
IN
(UART_LOWPULSE_MIN_CNT + UART_HIGHPULSE_MIN_CNT + 2)/2
2. If UART signals are weak along falling edges as shown in Figure 22-4, which leads to inaccurate average of
UART_LOWPULSE_MIN_CNT and UART_HIGHPULSE_MIN_CNT, use UART_POSEDGE_MIN_CNT to
IM
determine the transmitter’s baud rate as follows:
fclk
Buart =
(UART_POSEDGE_MIN_CNT + 1)/2
3. If UART signals are weak along rising edges, use UART_NEGEDGE_MIN_CNT to determine the
EL
transmitter’s baud rate as follows:
fclk
Buart =
(UART_NEGEDGE_MIN_CNT + 1)/2
22.4.4 UART Data Frame
PR
Figure 225. Structure of UART Data Frame
Figure 22-5 shows the basic structure of a data frame. A frame starts with one START bit, and ends with STOP
bits which can be 1, 1.5, 2 or 3 bits long, configured by UART_STOP_BIT_NUM, UART_DL1_EN and
UART_DL0_EN. The START bit is logical low, whereas STOP bits are logical high.
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The actual data length can be anywhere between 5 ~ 8 bit, configured by UART_BIT_NUM. When
UART_PARITY_EN is set, a parity bit is added after data bits. UART_PARITY is used to choose even parity or
odd parity. When the receiver detects a parity bit error in data received, a UART_PARITY_ERR_INT interrupt is
generated, and the data received is still stored into RX FIFO. When the receiver detects a data frame error, a
UART_FRM_ERR_INT interrupt is generated, and the data received by default is stored into RX FIFO.
If all data in Tx_FIFO has been sent, a UART_TX_DONE_INT interrupt is generated. After this, if the
UART_TXD_BRK bit is set then the transmitter will send several NULL characters in which the TX data line is
logical low. The number of NULL characters is configured by UART_TX_BRK_NUM. Once the transmitter has
sent all NULL characters, a UART_TX_BRK_DONE_INT interrupt is generated. The minimum interval between
data frames can be configured using UART_TX_IDLE_NUM. If the transmitter stays idle for UART_TX_IDLE_NUM
or more time, a UART_TX_BRK_IDLE_DONE_INT interrupt is generated.
A RY
Figure 226. AT_CMD Character Structure
Figure 22-6 is the structure of a special character AT_CMD. If the receiver constantly receives AT_CMD_CHAR
IN
and the following conditions are met, a UART_AT_CMD_CHAR_DET_INT interrupt is generated.
• The interval between the first AT_CMD_CHAR and the last non-AT_CMD_CHAR character is at least UART
_PRE_IDLE_NUM cycles.
IM
• The interval between two AT_CMD_CHAR characters is less than UART_RX_GAP_TOUT cycles.
• The number of AT_CMD_CHAR characters is equal to or greater than UART_CHAR_NUM.
• The interval between the last AT_CMD_CHAR character and next non-AT_CMD_CHAR character is at least
UART_POST_IDLE_NUM cycles.
EL
22.4.5 RS485
The two UART controllers support RS485 protocol. This protocol uses differential signals to transmit data, so it
can communicate over longer distances at higher bit rates than RS232. RS485 has two-wire half-duplex mode
and four-wire full-duplex mode. UART controllers support two-wire half-duplex transmission and bus snooping.
PR
In a two-wire RS485 multidrop network, there can be 32 slaves at most.
22.4.5.1 Driver Control
As shown in Figure 22-7, in a two-wire multidrop network, an external RS485 transceiver is needed for differential
to single-ended conversion. A RS485 transceiver contains a driver and a receiver. When a UART controller is not
in transmitter mode, the connection to the differential line can be broken by disabling the driver. When DE is 1,
the driver is enabled; when DE is 0, the driver is disabled.
The UART receiver converts differential signals to single-ended signals via an external receiver. RE is the enable
control signal for the receiver. When RE is 0, the receiver is enabled; when RE is 1, the receiver is disabled. If RE
is configured as 0, the UART controller is allowed to snoop data on the bus, including data sent by itself.
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DE can be controlled by either software or hardware. To reduce the cost of software, in our design DE is
controlled by hardware. As shown in Figure 22-7, DE is connected to dtrn_out of UART (please refer to Section
22.4.8.1 for more details).
RY
Figure 227. Driver Control Diagram in RS485 Mode
22.4.5.2 Turnaround Delay
By default, the two UART controllers work in receiver mode. When a UART controller is switched from transmitter
A
mode to receiver mode, the RS485 protocol requires a turnaround delay of one cycle after the stop bit. The
UART transmitter supports adding a turnaround delay of one cycle before the start bit or after the stop bit. When
UART_DL0_EN is set, a turnaround delay of one cycle is added before the start bit; when UART_DL1_EN is set,
IN
a turnaround delay of one cycle is added after the stop bit.
22.4.5.3 Bus Snooping
In a two-wire multidrop network, UART controllers support bus snooping if RE of the external RS485 transceiver
IM
is 0. By default, a UART controller is not allowed to transmit and receive data simultaneously. If
UART_RS485TX_RX_EN is set and the external RS485 transceiver is configured as in Figure 22-7, a UART
controller may receive data in transmitter mode and snoop the bus. If UART_RS485RXBY_TX_EN is set, a UART
controller may transmit data in receiver mode.
EL
The two UART controllers can snoop data sent by themselves. In transmitter mode, when a UART controller
monitors a collision between data sent and data received, a UART_RS485_CLASH_INT is generated; when a
UART controller monitor a data frame error, a UART_RS485_FRM_ERR_INT interrupt is generated; when a UART
controller monitors a polarity error, a UART_RS485_PARITY_ERR_INT is generated.
PR
22.4.6 IrDA
IrDA protocol consists of three layers, namely the physical layer, the link access protocol, and the link
management protocol. The two UART controllers implement IrDA’s physical layer. In IrDA encoding, a UART
controller supports data rates up to 115.2 kbit/s (SIR, or serial infrared mode). As shown in Figure 22-8, the IrDA
encoder converts a NRZ (non-return to zero code) signal to a RZI (return to zero code) signal and sends it to the
external driver and infrared LED. This encoder uses modulated signals whose pulse width is 3/16 bits to indicate
logic “0”, and low levels to indicate logic “1”. The IrDA decoder receives signals from the infrared receiver and
converts them to NRZ signals. In most cases, the receiver is high when it is idle, and the encoder output polarity
is the opposite of the decoder input polarity. If a low pulse is detected, it indicates that a start bit has been
received.
When IrDA function is enabled, one bit is divided into 16 clock cycles. If the bit to be sent is zero, then the 9th,
10th and 11th clock cycle is high.
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RY
Figure 228. The Timing Diagram of Encoding and Decoding in SIR mode
A
The IrDA transceiver is half-duplex, meaning that it cannot send and receive data simultaneously. As shown in
Figure 22-9, IrDA function is enabled by setting UART_IRDA_EN. When UART_IRDA_TX_EN is set (high), the
IrDA transceiver is enabled to send data and not allowed to receive data; when UART_IRDA_TX_EN is reset (low),
IN
the IrDA transceiver is enabled to receive data and not allowed to send data.
IM
EL
Figure 229. IrDA Encoding and Decoding Diagram
22.4.7 Wakeup
PR
UART0 and UART1 can be set as wake-up source. When a UART controller is in Light-sleep mode, Wakeup_Ctrl
counts up the rising edges of rxd_in. When the number of rising edges is greater than
(UART_ACTIVE_THRESHOLD + 2), a wake_up signal is generated and sent to RTC, which then wakes up
ESP32-C3.
22.4.8 Flow Control
UART controllers have two ways to control data flow, namely hardware flow control and software flow control.
Hardware flow control is achieved using output signal rtsn_out and input signal dsrn_in. Software flow control is
achieved by inserting special characters in data flow sent and detecting special characters in data flow
received.
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22.4.8.1 Hardware Flow Control
A RY
IN
Figure 2210. Hardware Flow Control Diagram
IM
Figure 22-10 shows hardware flow control of a UART controller. Hardware flow control uses output signal
rtsn_out and input signal dsrn_in. Figure 22-11 illustrates how these signals are connected between UART on
ESP32-C3 (hereinafter referred to as IU0) and the external UART (hereinafter referred to as EU0).
When rtsn_out of IU0 is low, EU0 is allowed to send data; when rtsn_out of IU0 is high, EU0 is notified to stop
EL
sending data until rtsn_out of IU0 returns to low. The output signal rtsn_out can be controlled in two ways.
• Software control: Enter this mode by clearing UART_RX_FLOW_EN to 0. In this mode, the level of rtsn_out
is changed by configuring UART_SW_RTS.
• Hardware control: Enter this mode by setting UART_RX_FLOW_EN to 1. In this mode, rtsn_out is pulled
high when data in Rx_FIFO exceeds UART_RX_FLOW_THRHD.
PR
Figure 2211. Connection between Hardware Flow Control Signals
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When ctsn_in of IU0 is low, IU0 is allowed to send data; when ctsn_in is high, IU0 is not allowed to send data.
When IU0 detects an edge change of ctsn_in, a UART_CTS_CHG_INT interrupt is generated.
If dtrn_out of IU0 is high, it indicates that IU0 is ready to transmit data. dtrn_out is generated by configuring the
UART_SW_DTR field. When the IU0 transmitter detects a edge change of dsrn_in, a UART_DSR_CHG_INT
interrupt is generated. After this interrupt is detected, software can obtain the level of input signal dsrn_in by
reading UART_DSRN. If dsrn_in is high, it indicates that EU0 is ready to transmit data.
In a two-wire RS485 multidrop network enabled by setting UART_RS485_EN, dtrn_out is generated by hardware
and used for transmit/receive turnaround. When data transmission starts, dtrn_out is pulled high and the external
driver is enabled; when data transmission completes, dtrn_out is pulled low and the external driver is disabled.
Please note that when there is turnaround delay of one cycle added after the stop bit, dtrn_out is pulled low after
RY
the delay.
UART loopback test is enabled by setting UART_LOOPBACK. In the test, UART output signal txd_out is
connected to its input signal rxd_in, rtsn_out is connected to ctsn_in, and dtrn_out is connected to dsrn_out. If
data sent matches data received, it indicates that UART controllers are working properly.
22.4.8.2 Software Flow Control
A
Instead of CTS/RTS lines, software flow control uses XON/XOFF characters to start or stop data transmission.
Such flow control is enabled by setting UART_SW_FLOW_CON_EN to 1.
IN
When using software flow control, hardware automatically detects if there are XON/XOFF characters in data flow
received, and generate a UART_SW_XOFF_INT or a UART_SW_XON_INT interrupt accordingly. If an XOFF
character is detected, the transmitter stops data transmission once the current byte has been transmitted; if an
XON character is detected, the transmitter starts data transmission. In addition, software can force the
IM
transmitter to stop sending data by setting UART_FORCE_XOFF, or to start sending data by setting
UART_FORCE_XON.
Software determines whether to insert flow control characters according to the remaining room in RX FIFO. When
UART_SEND_XOFF is set, the transmitter sends an XOFF character configured by UART_XOFF_CHAR after the
EL
current byte in transmission; when UART_SEND_XON is set, the transmitter sends an XON character configured
by UART_XON_CHAR after the current byte in transmission. If the RX FIFO of a UART controller stores more data
than UART_XOFF_THRESHOLD, UART_SEND_XOFF is set by hardware. As a result, the transmitter sends an
XOFF character configured by UART_XOFF_CHAR after the current byte in transmission. If the RX FIFO of a
UART controller stores less data than UART_XON_THRESHOLD, UART_SEND_XON is set by hardware. As a
PR
result, the transmitter sends an XON character configured by UART_XON_CHAR after the current byte in
transmission.
22.4.9 GDMA Mode
The two UART controllers on ESP32-C3 share one TX/RX GDMA (general direct memory access) channel via
UHCI. In GDMA mode, UART controllers support the decoding and encoding of HCI data packets. The
UHCI_UARTn_CE field determines which UART controller occupies the GDMA TX/RX channel.
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Figure 2212. Data Transfer in GDMA Mode
RY
Figure 22-12 shows how data is transferred using GDMA. Before GDMA receives data, software prepares an
inlink. GDMA_INLINK_ADDR_CHn points to the first receive descriptor in the inlink. After
GDMA_INLINK_START_CHn is set, UHCI sends data that UART has received to the decoder. The decoded data
is then stored into the RAM pointed by the inlink under the control of GDMA.
Before GDMA sends data, software prepares an outlink and data to be sent. GDMA_OUTLINK_ADDR_CHn
A
points to the first transmit descriptor in the outlink. After GDMA_OUTLINK_START_CHn is set, GDMA reads data
from the RAM pointed by outlink. The data is then encoded by the encoder, and sent sequentially by the UART
transmitter.
IN
HCI data packets have separators at the beginning and the end, with data bits in the middle (separators + data
bits + separators). The encoder inserts separators in front of and after data bits, and replaces data bits identical
to separators with special characters. The decoder removes separators in front of and after data bits, and
replaces special characters with separators. There can be more than one continuous separator at the beginning
IM
and the end of a data packet. The separator is configured by UHCI_SEPER_CHAR, 0xC0 by default. The special
character is configured by UHCI_ESC_SEQ0_CHAR0 (0xDB by default) and UHCI_ESC_SEQ0_CHAR1 (0xDD by
default). When all data has been sent, a GDMA_OUT_TOTAL_EOF_CHn_INT interrupt is generated. When all
data has been received, a GDMA_IN_SUC_EOF_CHn_INT is generated.
EL
22.4.10 UART Interrupts
• UART_AT_CMD_CHAR_DET_INT: Triggered when the receiver detects an AT_CMD character.
• UART_RS485_CLASH_INT: Triggered when a collision is detected between the transmitter and the receiver
in RS485 mode.
PR
• UART_RS485_FRM_ERR_INT: Triggered when an error is detected in the data frame sent by the
transmitter in RS485 mode.
• UART_RS485_PARITY_ERR_INT: Triggered when an error is detected in the parity bit sent by the
transmitter in RS485 mode.
• UART_TX_DONE_INT: Triggered when all data in the transmitter’s TX FIFO has been sent.
• UART_TX_BRK_IDLE_DONE_INT: Triggered when the transmitter stays idle for the minimum interval
(threshold) after sending the last data bit.
• UART_TX_BRK_DONE_INT: Triggered when the transmitter has sent all NULL characters after all data in TX
FIFO had been sent.
• UART_GLITCH_DET_INT: Triggered when the receiver detects a glitch in the middle of the start bit.
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• UART_SW_XOFF_INT: Triggered when UART_SW_FLOW_CON_EN is set and the receiver receives a XOFF
character.
• UART_SW_XON_INT: Triggered when UART_SW_FLOW_CON_EN is set and the receiver receives a XON
character.
• UART_RXFIFO_TOUT_INT: Triggered when the receiver takes more time than UART_RX_TOUT_THRHD to
receive one byte.
• UART_BRK_DET_INT: Triggered when the receiver detects a NULL character after stop bits.
• UART_CTS_CHG_INT: Triggered when the receiver detects an edge change of CTSn signals.
• UART_DSR_CHG_INT: Triggered when the receiver detects an edge change of DSRn signals.
RY
• UART_RXFIFO_OVF_INT: Triggered when the receiver receives more data than the capacity of RX FIFO.
• UART_FRM_ERR_INT: Triggered when the receiver detects a data frame error.
• UART_PARITY_ERR_INT: Triggered when the receiver detects a parity error.
• UART_TXFIFO_EMPTY_INT: Triggered when TX FIFO stores less data than what
A
UART_TXFIFO_EMPTY_THRHD specifies.
• UART_RXFIFO_FULL_INT: Triggered when the receiver receives more data than what
UART_RXFIFO_FULL_THRHD specifies.
IN
• UART_WAKEUP_INT: Triggered when UART is woken up.
22.4.11 UHCI Interrupts
IM
• UHCI_APP_CTRL1_INT: Triggered when software sets UHCI_APP_CTRL1_INT_RAW.
• UHCI_APP_CTRL0_INT: Triggered when software sets UHCI_APP_CTRL0_INT_RAW.
• UHCI_OUTLINK_EOF_ERR_INT: Triggered when an EOF error is detected in a transmit descriptor.
• UHCI_SEND_A_REG_Q_INT: Triggered when UHCI has sent a series of short packets using always_send.
EL
• UHCI_SEND_S_REG_Q_INT: Triggered when UHCI has sent a series of short packets using single_send.
• UHCI_TX_HUNG_INT: Triggered when UHCI takes too long to read RAM using a GDMA transmit channel.
• UHCI_RX_HUNG_INT: Triggered when UHCI takes too long to receive data using a GDMA receive channel.
PR
• UHCI_TX_START_INT: Triggered when GDMA detects a separator character.
• UHCI_RX_START_INT: Triggered when a separator character has been sent.
22.5 Programming Procedures
22.5.1 Register Type
All UART registers are in APB_CLK domain. According to whether clock domain crossing and synchronization
are required, UART registers that can be configured by software are classified into three types, namely immediate
registers, synchronous registers, and static registers. Immediate registers are read in APB_CLK domain, and take
effect after configured via the APB bus. Synchronous registers are read in Core Clock domain, and take effect
after synchronization. Static registers are also read in Core Clock domain, but would not change dynamically.
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Therefore, for static registers clock domain crossing is not required, and software can turn on and off the clock for
the UART transmitter or receiver to ensure that the configuration sampled in Core Clock domain is correct.
22.5.1.1 Synchronous Registers
Read in Core Clock domain, synchronous registers implement the clock domain crossing design to ensure that
their values sampled in Core Clock domain are correct. These registers as listed in Table 22-1 are configured as
follows:
• Enable register synchronization by clearing UART_UPDATE_CTRL to 0;
• Wait for UART_REG_UPDATE to become 0, which indicates the completion of last synchronization;
RY
• Configure synchronous registers;
• Synchronize the configured values to Core Clock domain by writting 1 to UART_REG_UPDATE.
Table 221. UARTn Synchronous Registers
Register Field
A
UART_CLKDIV_REG UART_CLKDIV_FRAG[3:0]
UART_CLKDIV[11:0]
UART_CONF0_REG UART_AUTOBAUD_EN
IN UART_ERR_WR_MASK
UART_TXD_INV
UART_RXD_INV
UART_IRDA_EN
IM
UART_TX_FLOW_EN
UART_LOOPBACK
UART_IRDA_RX_INV
UART_IRDA_TX_EN
UART_IRDA_WCTL
EL
UART_IRDA_TX_EN
UART_IRDA_DPLX
UART_STOP_BIT_NUM
UART_BIT_NUM
UART_PARITY_EN
PR
UART_PARITY
UART_FLOW_CONF_REG UART_SEND_XOFF
UART_SEND_XON
UART_FORCE_XOFF
UART_FORCE_XON
UART_XONOFF_DEL
UART_SW_FLOW_CON_EN
UART_TXBRK_CONF_REG UART_RS485_TX_DLY_NUM[3:0]
UART_RS485_RX_DLY_NUM
UART_RS485RXBY_TX_EN
UART_RS485TX_RX_EN
UART_DL1_EN
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UART_DL0_EN
UART_RS485_EN
22.5.1.2 Static Registers
Static registers, though also read in Core Clock domain, would not change dynamically when UART controllers
are at work, so they do not implement the clock domain crossing design. These registers must be configured
when the UART transmitter or receiver is not at work. In this case, software can turn off the clock for the UART
transmitter or receiver, so that static registers are not sampled in their metastable state. When software turns on
the clock, the configured values are stable to be correctly sampled. Static registers as listed in Table 22-2 are
configured as follows:
RY
• Turn off the clock for the UART transmitter by clearing UART_TX_SCLK_EN, or the clock for the UART
receiver by clearing UART_RX_SCLK_EN, depending on which one (transmitter or receiver) is not at work;
• Configure static registers;
• Turn on the clock for the UART transmitter by writing 1 to UART_TX_SCLK_EN, or the clock for the UART
A
receiver by writing 1 to UART_RX_SCLK_EN.
Table 222. UARTn Static Registers
IN
Register Field
UART_RX_FILT_REG UART_GLITCH_FILT_EN
UART_GLITCH_FILT[7:0]
UART_SLEEP_CONF_REG UART_ACTIVE_THRESHOLD[9:0]
IM
UART_SWFC_CONF0_REG UART_XOFF_CHAR[7:0]
UART_SWFC_CONF1_REG UART_XON_CHAR[7:0]
UART_IDLE_CONF_REG UART_TX_IDLE_NUM[9:0]
UART_AT_CMD_PRECNT_REG UART_PRE_IDLE_NUM[15:0]
UART_AT_CMD_POSTCNT_REG UART_POST_IDLE_NUM[15:0]
EL
UART_AT_CMD_GAPTOUT_REG UART_RX_GAP_TOUT[15:0]
UART_AT_CMD_CHAR_REG UART_CHAR_NUM[7:0]
UART_AT_CMD_CHAR[7:0]
PR
22.5.1.3 Immediate Registers
Except those listed in Table 22-1 and Table 22-2, registers that can be configured by software are immediate
registers read in APB_CLK domain, such as interrupt and FIFO configuration registers.
22.5.2 Detailed Steps
Figure 22-13 illustrates the process to program UART controllers, namely initialize UART, configure registers,
enable the UART transmitter or receiver, and finish data transmission.
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A RY
IN
IM
EL
PR
Figure 2213. UART Programming Procedures
22.5.2.1 Initializing URATn
To initialize URATn:
• enable the clock for UART RAM by setting SYSTEM_UART_MEM_CLK_EN to 1;
• enable APB_CLK for UARTn by setting SYSTEM_UARTn_CLK_EN to 1;
• clear SYSTEM_UARTn_RST;
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• write 1 to UART_RST_CORE;
• write 1 to SYSTEM_UARTn_RST;
• clear SYSTEM_UARTn_RST;
• clear UART_RST_CORE;
• enable register synchronization by clearing UART_UPDATE_CTRL.
22.5.2.2 Configuring URATn Communication
To configure URATn communication:
• wait for UART_REG_UPDATE to become 0, which indicates the completion of last synchronization;
RY
• configure static registers (if any) following Section 22.5.1.2;
• select the clock source via UART_SCLK_SEL;
• configure divisor of the divider via UART_SCLK_DIV_NUM, UART_SCLK_DIV_A, and UART_SCLK_DIV_B;
• configure the baud rate for transmission via UART_CLKDIV and UART_CLKDIV_FRAG;
A
• configure data length via UART_BIT_NUM;
• configure odd or even parity check via UART_PARITY_EN and UART_PARITY;
• optional steps depending on application ...
IN
• synchronize the configured values to Core Clock domain by writing 1 to UART_REG_UPDATE.
IM
22.5.2.3 Enabling UARTn
To enable UARTn transmitter:
• configure TXFIFO’s empty threshold via UART_TXFIFO_EMPTY_THRHD;
EL
• disable UART_TXFIFO_EMPTY_INT interrupt by clearing UART_TXFIFO_EMPTY_INT_ENA;
• write data to be sent to UART_RXFIFO_RD_BYTE;
• clear UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_CLR;
• enable UART_TXFIFO_EMPTY_INT interrupt by setting UART_TXFIFO_EMPTY_INT_ENA;
PR
• detect UART_TXFIFO_EMPTY_INT and wait for the completion of data transmission.
To enable UARTn receiver:
• configure RXFIFO’s full threshold via UART_RXFIFO_FULL_THRHD;
• enable UART_RXFIFO_FULL_INT interrupt by setting UART_RXFIFO_FULL_INT_ENA;
• detect UART_TXFIFO_FULL_INT and wait until the RXFIFO is full;
• read data from RXFIFO via UART_RXFIFO_RD_BYTE, and obtain the number of bytes received in RXFIFO
via UART_RXFIFO_CNT.
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22.6 Register Summary
The addresses in this section are relative to UART Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
FIFO Configuration
UART_FIFO_REG FIFO data register 0x0000 RO
UART_MEM_CONF_REG UART threshold and allocation configuration 0x0060 R/W
Interrupt Register
UART_INT_RAW_REG Raw interrupt status 0x0004 R/WTC/SS
UART_INT_ST_REG Masked interrupt status 0x0008 RO
RY
UART_INT_ENA_REG Interrupt enable bits 0x000C R/W
UART_INT_CLR_REG Interrupt clear bits 0x0010 WT
Configuration Register
UART_CLKDIV_REG Clock divider configuration 0x0014 R/W
UART_RX_FILT_REG RX Filter configuration 0x0018 R/W
A
UART_CONF0_REG Configuration register 0 0x0020 R/W
UART_CONF1_REG Configuration register 1 0x0024 R/W
UART_FLOW_CONF_REG Software flow control configuration 0x0034 varies
UART_SLEEP_CONF_REG
UART_SWFC_CONF0_REG
IN
Sleep mode configuration
Software flow control character configuration
0x0038
0x003C
R/W
R/W
UART_SWFC_CONF1_REG Software flow control character configuration 0x0040 R/W
UART_TXBRK_CONF_REG TX break character configuration 0x0044 R/W
IM
UART_IDLE_CONF_REG Frame-end idle configuration 0x0048 R/W
UART_RS485_CONF_REG RS485 mode configuration 0x004C R/W
UART_CLK_CONF_REG UART core clock configuration 0x0078 R/W
Status Register
UART_STATUS_REG UART status register 0x001C RO
EL
UART_MEM_TX_STATUS_REG TX FIFO write and read offset address 0x0064 RO
UART_MEM_RX_STATUS_REG RX FIFO write and read offset address 0x0068 RO
UART_FSM_STATUS_REG UART transmit and receive status. 0x006C RO
Autobaud Register
UART_LOWPULSE_REG Autobaud minimum low pulse duration register 0x0028 RO
PR
Autobaud minimum high pulse duration
UART_HIGHPULSE_REG 0x002C RO
register
UART_RXD_CNT_REG Autobaud edge change count register 0x0030 RO
UART_POSPULSE_REG Autobaud high pulse register 0x0070 RO
UART_NEGPULSE_REG Autobaud low pulse register 0x0074 RO
AT Escape Sequence Selection Configuration
UART_AT_CMD_PRECNT_REG Pre-sequence timing configuration 0x0050 R/W
UART_AT_CMD_POSTCNT_REG Post-sequence timing configuration 0x0054 R/W
UART_AT_CMD_GAPTOUT_REG Timeout configuration 0x0058 R/W
UART_AT_CMD_CHAR_REG AT escape sequence detection configuration 0x005C R/W
Version Register
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Name Description Address Access
UART_DATE_REG UART version control register 0x007C R/W
UART_ID_REG UART ID register 0x0080 varies
Name Description Address Access
Configuration Register
UHCI_CONF0_REG UHCI configuration register 0x0000 R/W
UHCI_CONF1_REG UHCI configuration register 0x0014 varies
UHCI_ESCAPE_CONF_REG Escape character configuration 0x0020 R/W
UHCI_HUNG_CONF_REG Timeout configuration 0x0024 R/W
RY
UHCI_ACK_NUM_REG UHCI ACK number configuration 0x0028 varies
UHCI_QUICK_SENT_REG UHCI quick send configuration register 0x0030 varies
UHCI_REG_Q0_WORD0_REG Q0_WORD0 quick_sent register 0x0034 R/W
UHCI_REG_Q0_WORD1_REG Q0_WORD1 quick_sent register 0x0038 R/W
UHCI_REG_Q1_WORD0_REG Q1_WORD0 quick_sent register 0x003C R/W
UHCI_REG_Q1_WORD1_REG Q1_WORD1 quick_sent register 0x0040 R/W
A
UHCI_REG_Q2_WORD0_REG Q2_WORD0 quick_sent register 0x0044 R/W
UHCI_REG_Q2_WORD1_REG Q2_WORD1 quick_sent register 0x0048 R/W
UHCI_REG_Q3_WORD0_REG Q3_WORD0 quick_sent register 0x004C R/W
UHCI_REG_Q3_WORD1_REG
UHCI_REG_Q4_WORD0_REG
IN
Q3_WORD1 quick_sent register
Q4_WORD0 quick_sent register
0x0050
0x0054
R/W
R/W
UHCI_REG_Q4_WORD1_REG Q4_WORD1 quick_sent register 0x0058 R/W
UHCI_REG_Q5_WORD0_REG Q5_WORD0 quick_sent register 0x005C R/W
IM
UHCI_REG_Q5_WORD1_REG Q5_WORD1 quick_sent register 0x0060 R/W
UHCI_REG_Q6_WORD0_REG Q6_WORD0 quick_sent register 0x0064 R/W
UHCI_REG_Q6_WORD1_REG Q6_WORD1 quick_sent register 0x0068 R/W
UHCI_ESC_CONF0_REG Escape sequence configuration register 0 0x006C R/W
EL
UHCI_ESC_CONF1_REG Escape sequence configuration register 1 0x0070 R/W
UHCI_ESC_CONF2_REG Escape sequence configuration register 2 0x0074 R/W
UHCI_ESC_CONF3_REG Escape sequence configuration register 3 0x0078 R/W
UHCI_PKT_THRES_REG Configuration register for packet length 0x007C R/W
Interrupt Register
PR
UHCI_INT_RAW_REG Raw interrupt status 0x0004 varies
UHCI_INT_ST_REG Masked interrupt status 0x0008 RO
UHCI_INT_ENA_REG Interrupt enable bits 0x000C R/W
UHCI_INT_CLR_REG Interrupt clear bits 0x0010 WT
UHCI Status Register
UHCI_STATE0_REG UHCI receive status 0x0018 RO
UHCI_STATE1_REG UHCI transmit status 0x001C RO
UHCI_RX_HEAD_REG UHCI packet header register 0x002C RO
Version Register
UHCI_DATE_REG UHCI version control register 0x0080 R/W
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22.7 Registers
The addresses in this section are relative to UART Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 22.1. UART_FIFO_REG (0x0000)
E
B YT
D_
_R
FO
FI
RX
)
ed
T_
rv
se
R
UA
31
(re 8 7 0
RY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RXFIFO_RD_BYTE UARTn accesses FIFO via this register. (RO)
A
Register 22.2. UART_MEM_CONF_REG (0x0060)
HD
D
RC PU
PD
RH
HR
O E_
E_
IN _T
_F RC
_T
W
UT
EM FO
E
E
LO
IZ
IZ
TO
_M M_
_S
_F
S
X_
X_
RT E
X
)
d)
ed
UA T_M
_R
_R
_R
_T
ve
rv
RT
RT
RT
RT
er
se
s
UA
UA
UA
UA
UA
(re
(re
31 28 27 26 25 16 15 7 6 4 3 1 0
IM
0 0 0 0 0 0 0xa 0x0 0x1 1 0 Reset
UART_RX_SIZE This register is used to configure the amount of mem allocated for RX FIFO. The
default number is 128 bytes. (R/W)
UART_TX_SIZE This register is used to configure the amount of mem allocated for TX FIFO. The
EL
default number is 128 bytes. (R/W)
UART_RX_FLOW_THRHD This register is used to configure the maximum amount of data that can
be received when hardware flow control works. (R/W)
UART_RX_TOUT_THRHD This register is used to configure the threshold time that receiver takes
PR
to receive one byte, in the unit of bit time (the time it takes to transfer one bit). The
UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes more time to receive
one byte with UART RX_TOUT_EN set to 1. (R/W)
UART_MEM_FORCE_PD Set this bit to force power down UART memory. (R/W)
UART_MEM_FORCE_PU Set this bit to force power up UART memory. (R/W)
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Register 22.3. UART_INT_RAW_REG (0x0004)
R X N IT _ AW AW
RT XF ON NT _R AW AW
W
RA
UA T_G _BR _ID _R R_I AW
UA T_T _DO AR ERR _R _R
UA T_R _X F_I INT _R _R
R L K LE AW NT_
RA W
R X _P _ NT INT
R W F _ T T
R X K NT R _R
R X H IN AW W
N
W
T_ A
UA _B IF _IN _R AW
UL _I W
_R IFO RR _R AW
I
UA T_R R_C G_ _R RA
IN _R
UA T_T _BR E_I Y_E INT
UA T_T 485 RM H_I T_
UA T_S _X DE E_I E_
_F TY RA
UA T_T RIT R_ INT W
R R O_ IN AW
XF _E _I AW
R R O_ T AW
L_ NT
R S _F S DE
R S H NT T_
RT XF Y_E INT _R
R W H_ N N
R S _C HA W
R T E UT W
R A ER F_ A
N
O P _
UA T_S ITC _DO _DO
UA T_R 485 _C _RA
UA T_C K_D TO _RA
UA T_P M_ OV T_R
UA T_D S_C T_I _IN
UA T_F FIF G_ T_R
IF M NT
UA T_R 485 LA R_
R S D T
T
UA _R CM _IN
RT T_ UP
O
UA T_A KE
R A
d)
UA T_W
ve
er
R
s
UA
(re
31 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
RY
UART_RXFIFO_FULL_INT_RAW This interrupt raw bit turns to high level when receiver receives more
data than what UART_RXFIFO_FULL_THRHD specifies. (R/WTC/SS)
UART_TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data
in TX FIFO is less than what UART_TXFIFO_EMPTY_THRHD specifies. (R/WTC/SS)
UART_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity
A
error in the data. (R/WTC/SS)
UART_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data
frame error. (R/WTC/SS)
IN
UART_RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more
data than the FIFO can store. (R/WTC/SS)
IM
UART_DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge
change of DSRn signal. (R/WTC/SS)
UART_CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge
change of CTSn signal. (R/WTC/SS)
EL
UART_BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a 0 after
the stop bit. (R/WTC/SS)
UART_RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more
time than UART_RX_TOUT_THRHD to receive a byte. (R/WTC/SS)
PR
UART_SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver receives XON char-
acter when UART_SW_FLOW_CON_EN is set to 1. (R/WTC/SS)
UART_SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives XOFF
character when UART_SW_FLOW_CON_EN is set to 1. (R/WTC/SS)
UART_GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a
glitch in the middle of a start bit. (R/WTC/SS)
Continued on the next page...
Espressif Systems 362 ESP32-C3 TRM (Pre-release v0.4)
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22 UART Controller (UART)
Register 22.3. UART_INT_RAW_REG (0x0004)
Continued from the previous page...
UART_TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter com-
pletes sending NULL characters, after all data in TX FIFO are sent. (R/WTC/SS)
UART_TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter
has kept the shortest duration after sending the last data. (R/WTC/SS)
UART_TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has sent out
all data in FIFO. (R/WTC/SS)
RY
UART_RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver de-
tects a parity error from the echo of transmitter in RS485 mode. (R/WTC/SS)
UART_RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects
a data frame error from the echo of transmitter in RS485 mode. (R/WTC/SS)
A
UART_RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when detects a clash be-
tween transmitter and receiver in RS485 mode. (R/WTC/SS)
UART_AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver de-
IN
tects the configured UART_AT_CMD_CHAR. (R/WTC/SS)
UART_WAKEUP_INT_RAW This interrupt raw bit turns to high level when input RXD edge changes
more times than what UART_ACTIVE_THRESHOLD specifies in Light-sleep mode. (R/WTC/SS)
IM
EL
PR
Espressif Systems 363 ESP32-C3 TRM (Pre-release v0.4)
Submit Documentation Feedback
22 UART Controller (UART)
Register 22.4. UART_INT_ST_REG (0x0008)
R X ON NT _S T T
ST
UA T_T _DO AR ERR _ST _S
UA T_R _X F_I INT _S _S
RT LI K_ LE_ T NT_
UA T_G _BR _ID _S R_I T
R X _P _ NT INT
R W OF T_ NT INT
S
T_ T
_
I N _S
UA T_R R_C G_ _S ST
UA T_T _BR E_I Y_E INT
UA T_T 485 RM H_I T_
UA T_S _X DE E_I E_
ST
UA T_B FIF _IN _S T
_F TY ST
_R IFO RR _S T
L_ NT
R S _F S DE
R S H NT T_
R W H_ N N
RT XF Y_E INT _S
R
R X N IT _
R A E R F_ T
R R O_ IN T
O P _
XF _E _I T
R R O_ T T
UA _S TC DO DO
R X H INT T
UA T_R 485 _C _ST
UA T_P M_ OV T_S
UA T_D S_C T_I _IN
UA T_C K_D TO _ST
IF M NT
UA T_F FIF G_ _S
UA T_T RIT R_ INT
UL _I
UA T_R 485 LA R_
R S _C HA
R T E UT
R S D T
N
UA _R CM _IN
RT T_ UP
K
UA T_A KE
R A
d)
X
UA T_W
ve
er
R
s
UA
(re
31 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RXFIFO_FULL_INT_ST This is the status bit for UART_RXFIFO_FULL_INT_RAW when
RY
UART_RXFIFO_FULL_INT_ENA is set to 1. (RO)
UART_TXFIFO_EMPTY_INT_ST This is the status bit for UART_TXFIFO_EMPTY_INT_RAW when
UART_TXFIFO_EMPTY_INT_ENA is set to 1. (RO)
UART_PARITY_ERR_INT_ST This is the status bit for UART_PARITY_ERR_INT_RAW when
A
UART_PARITY_ERR_INT_ENA is set to 1. (RO)
UART_FRM_ERR_INT_ST This is the status bit for UART_FRM_ERR_INT_RAW when
UART_FRM_ERR_INT_ENA is set to 1. (RO)
IN
UART_RXFIFO_OVF_INT_ST This is the status bit for UART_RXFIFO_OVF_INT_RAW when
UART_RXFIFO_OVF_INT_ENA is set to 1. (RO)
UART_DSR_CHG_INT_ST This is the status bit for UART_DSR_CHG_INT_RAW when
IM
UART_DSR_CHG_INT_ENA is set to 1. (RO)
UART_CTS_CHG_INT_ST This is the status bit for UART_CTS_CHG_INT_RAW when
UART_CTS_CHG_INT_ENA is set to 1. (RO)
UART_BRK_DET_INT_ST This is the status bit for UART_BRK_DET_INT_RAW when
EL
UART_BRK_DET_INT_ENA is set to 1. (RO)
UART_RXFIFO_TOUT_INT_ST This is the status bit for UART_RXFIFO_TOUT_INT_RAW when
UART_RXFIFO_TOUT_INT_ENA is set to 1. (RO)
UART_SW_XON_INT_ST This is the status bit for UART_SW_XON_INT_RAW when
PR
UART_SW_XON_INT_ENA is set to 1. (RO)
UART_SW_XOFF_INT_ST This is the status bit for UART_SW_XOFF_INT_RAW when
UART_SW_XOFF_INT_ENA is set to 1. (RO)
UART_GLITCH_DET_INT_ST This is the status bit for UART_GLITCH_DET_INT_RAW when
UART_GLITCH_DET_INT_ENA is set to 1. (RO)
UART_TX_BRK_DONE_INT_ST This is the status bit for UART_TX_BRK_DONE_INT_RAW when
UART_TX_BRK_DONE_INT_ENA is set to 1. (RO)
Continued on the next page...
Espressif Systems 364 ESP32-C3 TRM (Pre-release v0.4)
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22 UART Controller (UART)
Register 22.4. UART_INT_ST_REG (0x0008)
Continued from the previous page...
UART_TX_BRK_IDLE_DONE_INT_ST This is the status bit for
UART_TX_BRK_IDLE_DONE_INT_RAW when UART_TX_BRK_IDLE_DONE_INT_ENA is set
to 1. (RO)
UART_TX_DONE_INT_ST This is the status bit for UART_TX_DONE_INT_RAW when
UART_TX_DONE_INT_ENA is set to 1. (RO)
UART_RS485_PARITY_ERR_INT_ST This is the status bit for UART_RS485_PARITY_ERR_INT_RAW
RY
when UART_RS485_PARITY_INT_ENA is set to 1. (RO)
UART_RS485_FRM_ERR_INT_ST This is the status bit for UART_RS485_FRM_ERR_INT_RAW
when UART_RS485_FRM_ERR_INT_ENA is set to 1. (RO)
UART_RS485_CLASH_INT_ST This is the status bit for UART_RS485_CLASH_INT_RAW when
UART_RS485_CLASH_INT_ENA is set to 1. (RO)
A
UART_AT_CMD_CHAR_DET_INT_ST This is the status bit for
UART_AT_CMD_CHAR_DET_INT_RAW when UART_AT_CMD_CHAR_DET_INT_ENA is set
to 1. (RO)
UART_WAKEUP_INT_ST This is the
IN
status bit for UART_WAKEUP_INT_RAW when
UART_WAKEUP_INT_ENA is set to 1. (RO)
IM
EL
PR
Espressif Systems 365 ESP32-C3 TRM (Pre-release v0.4)
Submit Documentation Feedback
22 UART Controller (UART)
Register 22.5. UART_INT_ENA_REG (0x000C)
R X N IT _ A NA
RT XF ON NT _E NA NA
A
EN
UA T_T _DO AR ERR _EN _E
UA T_R _X F_I INT _E _E
UA T_G _BR _ID _E R_I NA
R L K LE NA NT_
R X _P _ NT INT
R W F _ T T
EN A
R X K NT R _E
R X H IN NA A
T_ N
A
UA _B IF _IN _E NA
I
UA T_R R_C G_ _E EN
UL _I A
_R IFO RR _E NA
IN _E
UA T_T _BR E_I Y_E INT
UA T_T 485 RM H_I T_
UA T_S _X DE E_I E_
_F TY EN
UA T_T RIT R_ INT A
R R O_ IN NA
XF _E _I NA
L_ NT
R R O_ T NA
R S _F S DE
R S H NT T_
R W H_ N N
RT XF Y_E INT _E
R S _C HA A
R T E UT A
R A ER F_ N
N
O P _
UA T_S ITC _DO _DO
UA T_R 485 _C _EN
UA T_C K_D TO _EN
UA T_D S_C T_I _IN
UA T_P M_ OV T_E
IF M NT
UA T_F FIF G_ T_E
UA T_R 485 LA R_
R S D T
T
UA _R CM _IN
RT T_ UP
O
UA T_A KE
R A
d)
UA T_W
ve
er
R
s
UA
(re
31 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
UART_RXFIFO_FULL_INT_ENA This is the enable bit for UART_RXFIFO_FULL_INT_ST register.
(R/W)
UART_TXFIFO_EMPTY_INT_ENA This is the enable bit for UART_TXFIFO_EMPTY_INT_ST register.
(R/W)
UART_PARITY_ERR_INT_ENA This is the enable bit for UART_PARITY_ERR_INT_ST register. (R/W)
A
UART_FRM_ERR_INT_ENA This is the enable bit for UART_FRM_ERR_INT_ST register. (R/W)
IN
UART_RXFIFO_OVF_INT_ENA This is the enable bit for UART_RXFIFO_OVF_INT_ST register. (R/W)
UART_DSR_CHG_INT_ENA This is the enable bit for UART_DSR_CHG_INT_ST register. (R/W)
IM
UART_CTS_CHG_INT_ENA This is the enable bit for UART_CTS_CHG_INT_ST register. (R/W)
UART_BRK_DET_INT_ENA This is the enable bit for UART_BRK_DET_INT_ST register. (R/W)
UART_RXFIFO_TOUT_INT_ENA This is the enable bit for UART_RXFIFO_TOUT_INT_ST register.
(R/W)
EL
UART_SW_XON_INT_ENA This is the enable bit for UART_SW_XON_INT_ST register. (R/W)
UART_SW_XOFF_INT_ENA This is the enable bit for UART_SW_XOFF_INT_ST register. (R/W)
UART_GLITCH_DET_INT_ENA This is the enable bit for UART_GLITCH_DET_INT_ST register. (R/W)
PR
UART_TX_BRK_DONE_INT_ENA This is the enable bit for UART_TX_BRK_DONE_INT_ST register.
(R/W)
UART_TX_BRK_IDLE_DONE_INT_ENA This is the enable bit for
UART_TX_BRK_IDLE_DONE_INT_ST register. (R/W)
UART_TX_DONE_INT_ENA This is the enable bit for UART_TX_DONE_INT_ST register. (R/W)
Continued on the next page...
Espressif Systems 366 ESP32-C3 TRM (Pre-release v0.4)
Submit Documentation Feedback
22 UART Controller (UART)
Register 22.5. UART_INT_ENA_REG (0x000C)
Continued from the previous page...
UART_RS485_PARITY_ERR_INT_ENA This is the enable bit for
UART_RS485_PARITY_ERR_INT_ST register. (R/W)
UART_RS485_FRM_ERR_INT_ENA This is the enable bit for UART_RS485_PARITY_ERR_INT_ST
register. (R/W)
UART_RS485_CLASH_INT_ENA This is the enable bit for UART_RS485_CLASH_INT_ST register.
(R/W)
RY
UART_AT_CMD_CHAR_DET_INT_ENA This is the enable bit for
UART_AT_CMD_CHAR_DET_INT_ST register. (R/W)
UART_WAKEUP_INT_ENA This is the enable bit for UART_WAKEUP_INT_ST register. (R/W)
A
IN
IM
EL
PR
Espressif Systems 367 ESP32-C3 TRM (Pre-release v0.4)
Submit Documentation Feedback
22 UART Controller (UART)
Register 22.6. UART_INT_CLR_REG (0x0010)
R X N IT _ LR LR
RT XF ON NT _C LR LR
R
CL
UA T_T _DO AR ERR _C _C
UA T_R _X F_I INT _C _C
UA T_G _BR _ID _C R_I LR
R L K LE LR NT_
R X _P _ NT INT
R W F _ T T
T_ LR
R X K NT R _C
R X H INT LR R
R
UA _B IF _IN _C LR
I
IN _C
UL _I LR
UA T_R R_C G_ _C CL
_R IFO RR _C LR
UA T_T _BR E_I Y_E INT
UA T_T 485 RM H_I T_
UA T_S _X DE E_I E_
CL
R A ER F_ LR
R R O_ IN LR
L_ NT
_F TY C
XF _E _I LR
RT XF Y_E INT _C
R S _ F S DE
R R O _ T LR
R S H NT T_
R W H_ N N
R S _C HA R
R T E UT R
N
O P _
UA T_S ITC _DO _DO
UA T_P M_ OV T_C
UA T_R 485 _C _CL
UA T_C K_D TO _CL
UA T_D S_C T_I _IN
UA T_F FIF G_ _C
IF M NT
UA T_T RIT R_ INT
UA T_R 485 LA R_
R S D T
T
UA _R CM _IN
RT T_ UP
O
UA T_A KE
R A
d)
UA T_W
ve
er
R
s
UA
(re
31 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
UART_RXFIFO_FULL_INT_CLR Set this bit to clear UART_THE RXFIFO_FULL_INT_RAW interrupt.
(WT)
UART_TXFIFO_EMPTY_INT_CLR Set this bit to clear UART_TXFIFO_EMPTY_INT_RAW interrupt.
(WT)
UART_PARITY_ERR_INT_CLR Set this bit to clear UART_PARITY_ERR_INT_RAW interrupt. (WT)
A
UART_FRM_ERR_INT_CLR Set this bit to clear UART_FRM_ERR_INT_RAW interrupt. (WT)
UART_RXFIFO_OVF_INT_CLR Set this bit to clear UART_UART_RXFIFO_OVF_INT_RAW interrupt.
(WT)
IN
UART_DSR_CHG_INT_CLR Set this bit to clear UART_DSR_CHG_INT_RAW interrupt. (WT)
UART_CTS_CHG_INT_CLR Set this bit to clear UART_CTS_CHG_INT_RAW interrupt. (WT)
IM
UART_BRK_DET_INT_CLR Set this bit to clear UART_BRK_DET_INT_RAW interrupt. (WT)
UART_RXFIFO_TOUT_INT_CLR Set this bit to clear UART_RXFIFO_TOUT_INT_RAW interrupt. (WT)
EL
UART_SW_XON_INT_CLR Set this bit to clear UART_SW_XON_INT_RAW interrupt. (WT)
UART_SW_XOFF_INT_CLR Set this bit to clear UART_SW_XOFF_INT_RAW interrupt. (WT)
UART_GLITCH_DET_INT_CLR Set this bit to clear UART_GLITCH_DET_INT_RAW interrupt. (WT)
UART_TX_BRK_DONE_INT_CLR Set this bit to clear UART_TX_BRK_DONE_INT_RAW interrupt.
PR
(WT)
UART_TX_BRK_IDLE_DONE_INT_CLR Set this bit to clear UART_TX_BRK_IDLE_DONE_INT_RAW
interrupt. (WT)
UART_TX_DONE_INT_CLR Set this bit to clear UART_TX_DONE_INT_RAW interrupt. (WT)
UART_RS485_PARITY_ERR_INT_CLR Set this bit to clear UART_RS485_PARITY_ERR_INT_RAW
interrupt. (WT)
Continued on the next page...
Espressif Systems 368 ESP32-C3 TRM (Pre-release v0.4)
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22 UART Controller (UART)
Register 22.6. UART_INT_CLR_REG (0x0010)
Continued from the previous page...
UART_RS485_FRM_ERR_INT_CLR Set this bit to clear UART_RS485_FRM_ERR_INT_RAW inter-
rupt. (WT)
UART_RS485_CLASH_INT_CLR Set this bit to clear UART_RS485_CLASH_INT_RAW interrupt.
(WT)
UART_AT_CMD_CHAR_DET_INT_CLR Set this bit to clear UART_AT_CMD_CHAR_DET_INT_RAW
interrupt. (WT)
RY
UART_WAKEUP_INT_CLR Set this bit to clear UART_WAKEUP_INT_RAW interrupt. (WT)
Register 22.7. UART_CLKDIV_REG (0x0014)
A
A G
FR
V_
IV
DI
D
LK
LK
d)
)
ed
_C
_C
ve
rv
RT
RT
r
IN
se
se
UA
UA
(re
(re
31 24 23 20 19 12 11 0
0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0 0 0x2b6 Reset
UART_CLKDIV The integral part of the frequency divisor. (R/W)
IM
UART_CLKDIV_FRAG The decimal part of the frequency divisor. (R/W)
Register 22.8. UART_RX_FILT_REG (0x0018)
EL
N
_E
LT
ILT
FI
F
H_
H_
TC
TC
LI
LI
d)
_G
_G
e
rv
RT
RT
se
UA
UA
(re
PR
31 9 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x8 Reset
UART_GLITCH_FILT When input pulse width is lower than this value, the pulse is ignored. (R/W)
UART_GLITCH_FILT_EN Set this bit to enable RX signal filter. (R/W)
Espressif Systems 369 ESP32-C3 TRM (Pre-release v0.4)
Submit Documentation Feedback
22 UART Controller (UART)
Register 22.9. UART_CONF0_REG (0x0020)
M
UA T_D K_E _M N
R T N AS
R R BA EN
NU
R L R _E
R RD BA N
R RD TX V
R RD W V
R X EN T
UA T_T A_ _EN
R RD O_ T
UA T_I OP _E
UA T_I A_ CTL
UA T_I A_ _IN
UA T_I A_ CK
UA T_C R_W UD
UA T_I A_ _IN
UA _E O K_
UA T_S D_B LX
UA T_T A_ RS
IT EN
T_
UA T_I FIF RS
R O OW
RT W RK
M
R X DP
RT UT CL
R T NV
R X NV
BI
R RD RX
UA SW TR
R T NV
R X NV
_S TS
R X NV
R S NV
R RD TX
AR _
R X _
NU
_P I TY
Y
UA T_R FIFO
P_
UA T_A M_
_ _D
UA T_C R_I
UA T_L _FL
RT _R
UA T_T D_I
UA T_R R_I
UA T_R S_I
UA T_T S_I
UA T_D D_I
_
TO
RT AR
IT
R E
)d
UA _M
_B
UA _P
ve
RT
RT
RT
ser
UA
UA
UA
(re
31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 Reset
UART_PARITY This register is used to configure the parity check mode. (R/W)
UART_PARITY_EN Set this bit to enable UART parity check. (R/W)
RY
UART_BIT_NUM This register is used to set the length of data. (R/W)
UART_STOP_BIT_NUM This register is used to set the length of stop bit. (R/W)
UART_SW_RTS This register is used to configure the software RTS signal which is used in software
flow control. (R/W)
A
UART_SW_DTR This register is used to configure the software DTR signal which is used in software
flow control. (R/W) IN
UART_TXD_BRK Set this bit to enbale transmitter to send NULL when the process of sending data
is done. (R/W)
UART_IRDA_DPLX Set this bit to enable IrDA loopback mode. (R/W)
IM
UART_IRDA_TX_EN This is the start enable bit for IrDA transmitter. (R/W)
UART_IRDA_WCTL 1’h1: The IrDA transmitter’s 11th bit is the same as 10th bit. 1’h0: Set IrDA
transmitter’s 11th bit to 0. (R/W)
UART_IRDA_TX_INV Set this bit to invert the level of IrDA transmitter. (R/W)
EL
UART_IRDA_RX_INV Set this bit to invert the level of IrDA receiver. (R/W)
UART_LOOPBACK Set this bit to enable UART loopback test mode. (R/W)
UART_TX_FLOW_EN Set this bit to enable flow control function for transmitter. (R/W)
PR
UART_IRDA_EN Set this bit to enable IrDA protocol. (R/W)
UART_RXFIFO_RST Set this bit to reset the UART RX FIFO. (R/W)
UART_TXFIFO_RST Set this bit to reset the UART TX FIFO. (R/W)
UART_RXD_INV Set this bit to inverse the level value of UART RXD signal. (R/W)
UART_CTS_INV Set this bit to inverse the level value of UART CTS signal. (R/W)
UART_DSR_INV Set this bit to inverse the level value of UART DSR signal. (R/W)
Continued on the next page...
Espressif Systems 370 ESP32-C3 TRM (Pre-release v0.4)
Submit Documentation Feedback
22 UART Controller (UART)
Register 22.9. UART_CONF0_REG (0x0020)
Continued from the previous page...
UART_TXD_INV Set this bit to inverse the level value of UART TXD signal. (R/W)
UART_RTS_INV Set this bit to inverse the level value of UART RTS signal. (R/W)
UART_DTR_INV Set this bit to inverse the level value of UART DTR signal. (R/W)
UART_CLK_EN 1’h1: Force clock on for register. 1’h0: Support clock only when application writes
registers. (R/W)
RY
UART_ERR_WR_MASK 1’h1: Receiver stops storing data into FIFO when data is wrong. 1’h0:
Receiver stores the data even if the received data is wrong. (R/W)
UART_AUTOBAUD_EN This is the enable bit for detecting baud rate. (R/W)
UART_MEM_CLK_EN UART memory clock gate enable signal. (R/W)
A
Register 22.10. UART_CONF1_REG (0x0024)
IN RH
D
D
O IS
RH
T_ _D
TH
VF
TH
DA OW
Y_
L_
PT
IS UT N
RT X_ OW N
X_ FL
_D TO _E
UL
UA _R FL _E
M
_R _
_F
RT X_ UT
_E
O
O
UA T_R _TO
IF
IF
XF
XF
IM R X
d)
UA T_R
_R
_T
e
rv
RT
RT
se
R
UA
UA
UA
(re
31 22 21 20 19 18 17 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x60 0x60 Reset
UART_RXFIFO_FULL_THRHD It will produce UART_RXFIFO_FULL_INT interrupt when receiver re-
EL
ceives more data than this register value. (R/W)
UART_TXFIFO_EMPTY_THRHD It will produce UART_TXFIFO_EMPTY_INT interrupt when the data
amount in TX FIFO is less than this register value. (R/W)
UART_DIS_RX_DAT_OVF Disable UART RX data overflow detection. (R/W)
PR
UART_RX_TOUT_FLOW_DIS Set this bit to stop accumulating idle_cnt when hardware flow control
works. (R/W)
UART_RX_FLOW_EN This is the flow enable bit for UART receiver. (R/W)
UART_RX_TOUT_EN This is the enable bit for UART receiver’s timeout function. (R/W)
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Register 22.11. UART_FLOW_CONF_REG (0x0034)
EN
N_
O
LO EL
RT ON E_X FF
_C
_S O ON
R O _X F
UA T_F RC ON
UA T_X RC XO
_F _D
UA T_F ND OF
W
W FF
R O E_
R E _X
UA T_S ND
R E
)
ed
UA T_S
rv
se
R
UA
(re
31 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_SW_FLOW_CON_EN Set this bit to enable software flow control. It is used with register
SW_XON or SW_XOFF. (R/W)
RY
UART_XONOFF_DEL Set this bit to remove flow control char from the received data. (R/W)
UART_FORCE_XON Set this bit to enable the transmitter to go on sending data. (R/W)
UART_FORCE_XOFF Set this bit to stop the transmitter from sending data. (R/W)
UART_SEND_XON Set this bit to send XON character. It is cleared by hardware automatically.
A
(R/W/SS/SC)
UART_SEND_XOFF Set this bit to send XOFF character. It is cleared by hardware automatically.
(R/W/SS/SC)
IN
Register 22.12. UART_SLEEP_CONF_REG (0x0038)
IM
LD
HO
ES
HR
_T
VE
TI
AC
d)
EL ve
T_
r
se
R
UA
(re
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xf0 Reset
UART_ACTIVE_THRESHOLD The UART is activated from light-sleep mode when the input RXD edge
PR
changes more times than this register value. (R/W)
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Register 22.13. UART_SWFC_CONF0_REG (0x003C)
LD
HO
ES
R
HA
HR
_C
_T
FF
FF
O
XO
)
ed
_X
T_
rv
RT
se
R
UA
UA
(re
31 17 16 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x13 0xe0 Reset
UART_XOFF_THRESHOLD When the data amount in RX FIFO is more than this register value with
UART_SW_FLOW_CON_EN set to 1, it will send a XOFF character. (R/W)
RY
UART_XOFF_CHAR This register stores the XOFF flow control character. (R/W)
Register 22.14. UART_SWFC_CONF1_REG (0x0040)
A
LD
O
SH
AR
RE
CH
TH
N_
N_
O
O
IN
d )
_X
_X
ve
RT
RT
r
se
UA
UA
(re
31 17 16 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x11 0x0 Reset
IM
UART_XON_THRESHOLD When the data amount in RX FIFO is less than this register value with
UART_SW_FLOW_CON_EN set to 1, it will send a XON character. (R/W)
UART_XON_CHAR This register stores the XON flow control character. (R/W)
EL
Register 22.15. UART_TXBRK_CONF_REG (0x0044)
M
NU
K_
BR
X_
PR
)
ed
_T
rv
RT
se
UA
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xa Reset
UART_TX_BRK_NUM This register is used to configure the number of 0 to be sent after the process
of sending data is done. It is active when txd_brk is set to 1. (R/W)
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Register 22.16. UART_IDLE_CONF_REG (0x0048)
HD
UM
HR
_N
_T
E
E
DL
DL
_I
_I
RX
)
TX
ed
T_
T_
rv
se
R
UA
UA
(re
31 20 19 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0x100 0x100 Reset
UART_RX_IDLE_THRHD It will produce frame end signal when receiver takes more time to receive
one byte data than this register value, in the unit of bit time (the time it takes to transfer one bit).
(R/W)
RY
UART_TX_IDLE_NUM This register is used to configure the duration time between transfers, in the
unit of bit time (the time it takes to transfer one bit). (R/W)
A
Register 22.17. UART_RS485_CONF_REG (0x004C)
UA T_D 1_E _R TX_ M
M
RT L0 N X_ EN
R L TX _ NU
NU
EN
UA T_D 485 XBY Y_
Y_
IN
R S R DL
DL
UA _R 85 X_
X_
N
RT S4 _R
_E
_T
S4 N
85
UA _R 85
85
_R _E
S4
RT S4
d)
_R
UA _R
ve
RT
RT
r
se
UA
UA
(re
31 10 9 6 5 4 3 2 1 0
IM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RS485_EN Set this bit to choose the RS485 mode. (R/W)
UART_DL0_EN Set this bit to delay the stop bit by 1 bit. (R/W)
EL
UART_DL1_EN Set this bit to delay the stop bit by 1 bit. (R/W)
UART_RS485TX_RX_EN Set this bit to enable receiver could receive data when the transmitter is
transmitting data in RS485 mode. (R/W)
UART_RS485RXBY_TX_EN 1’h1: enable RS485 transmitter to send data when RS485 receiver line
PR
is busy. (R/W)
UART_RS485_RX_DLY_NUM This register is used to delay the receiver’s internal data signal. (R/W)
UART_RS485_TX_DLY_NUM This register is used to delay the transmitter’s internal data signal.
(R/W)
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Register 22.18. UART_CLK_CONF_REG (0x0078)
UM
RT ST LK N
UA SC CO N
_N
_B
A
UA T_R _SC K_E
_ _ _E
RT LK_ RE
V_
L
IV
V
CL N
SE
DI
DI
_D
R X L
E
UA _T SC
K_
K_
K_
LK
CL
CL
RT X_
SC
)
ed
UA T_R
_S
_S
_S
T_
rv
RT
RT
se
R
UA
UA
UA
UA
(re
31 26 25 24 23 22 21 20 19 12 11 6 5 0
0 0 0 0 0 0 1 1 0 1 3 0x1 0x0 0x0 Reset
UART_SCLK_DIV_B The denominator of the frequency divisor. (R/W)
UART_SCLK_DIV_A The numerator of the frequency divisor. (R/W)
RY
UART_SCLK_DIV_NUM The integral part of the frequency divisor. (R/W)
UART_SCLK_SEL UART clock source select. 1: APB_CLK; 2: FOSC_CLK; 3: XTAL_CLK. (R/W)
UART_SCLK_EN Set this bit to enable UART TX/RX clock. (R/W)
UART_RST_CORE Write 1 and then write 0 to this bit, to reset UART TX/RX. (R/W)
A
UART_TX_SCLK_EN Set this bit to enable UART TX clock. (R/W)
UART_RX_SCLK_EN Set this bit to enable UART RX clock. (R/W)
IN
Register 22.19. UART_STATUS_REG (0x001C)
IM
T
NT
N
_C
_C
O
FO
N
N
_D N
_D N
IF
SR
RT XD
TR
FI
RT TS
RT TS
UA T_R D
XF
)
)
R X
X
ed
ed
UA _C
UA T_R
_R
UA T_T
_T
rv
rv
RT
RT
se
se
R
R
UA
UA
UA
UA
(re
(re
31 30 29 28 26 25 16 15 14 13 12 10 9 0
EL
1 1 1 0 0 0 0 1 1 0 0 0 0 0 Reset
UART_RXFIFO_CNT Stores the byte number of valid data in RX FIFO. (RO)
UART_DSRN The register represent the level value of the internal UART DSR signal. (RO)
PR
UART_CTSN This register represent the level value of the internal UART CTS signal. (RO)
UART_RXD This register represent the level value of the internal UART RXD signal. (RO)
UART_TXFIFO_CNT Stores the byte number of data in TX FIFO. (RO)
UART_DTRN This bit represents the level of the internal UART DTR signal. (RO)
UART_RTSN This bit represents the level of the internal UART RTS signal. (RO)
UART_TXD This bit represents the level of the internal UART TXD signal. (RO)
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Register 22.20. UART_MEM_TX_STATUS_REG (0x0064)
DR
AD
R
W
DD
T X_
RA
B_
X_
AP
d)
)
ed
_T
ve
T_
rv
RT
er
se
R
s
UA
UA
(re
(re
31 21 20 11 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0x0 0 0x0 Reset
UART_APB_TX_WADDR This register stores the offset address in TX FIFO when software writes TX
FIFO via APB. (RO)
RY
UART_TX_RADDR This register stores the offset address in TX FIFO when TX FSM reads data via
Tx_FIFO_Ctrl. (RO)
Register 22.21. UART_MEM_RX_STATUS_REG (0x0068)
A
R
DD
RA
DR
X_
AD
_R
W
IN
PB
X_
d)
)
ed
_R
_A
ve
rv
RT
RT
r
se
se
UA
UA
(re
(re
31 21 20 11 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0x100 0 0x100 Reset
IM
UART_APB_RX_RADDR This register stores the offset address in RX FIFO when software reads data
from RX FIFO via APB. UART0 is 10’h100. UART1 is 10’h180. (RO)
UART_RX_WADDR This register stores the offset address in RX FIFO when Rx_FIFO_Ctrl writes RX
FIFO. (RO)
EL
Register 22.22. UART_FSM_STATUS_REG (0x006C)
UT
UT
_O
_O
PR
RX
U TX
_U
T_
)
ST
ed
_S
T_
rv
RT
se
R
UA
UA
(re
31 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_ST_URX_OUT This is the status register of receiver. (RO)
UART_ST_UTX_OUT This is the status register of transmitter. (RO)
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Register 22.23. UART_LOWPULSE_REG (0x0028)
NT
_C
IN
M
E_
LS
PU
W
LO
d)
ve
T_
er
R
s
UA
(re
31 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xfff Reset
UART_LOWPULSE_MIN_CNT This register stores the value of the minimum duration time of the low
level pulse, in the unit of APB_CLK cycles. It is used in baud rate detection. (RO)
RY
Register 22.24. UART_HIGHPULSE_REG (0x002C)
T
N
_C
A
IN
_M
SE
UL
HP
IG
)
ed
_H
IN
rv
RT
se
UA
(re
31 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xfff Reset
IM
UART_HIGHPULSE_MIN_CNT This register stores the value of the maximum duration time for the
high level pulse, in the unit of APB_CLK cycles. It is used in baud rate detection. (RO)
Register 22.25. UART_RXD_CNT_REG (0x0030)
EL
T
CN
E_
G
ED
D_
RX
)
ed
T_
rv
se
R
UA
(re
PR
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
UART_RXD_EDGE_CNT This register stores the count of RXD edge change. It is used in baud rate
detection. (RO)
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Register 22.26. UART_POSPULSE_REG (0x0070)
NT
_C
IN
M
E_
DG
SE
PO
d)
ve
T_
er
R
s
UA
(re
31 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xfff Reset
UART_POSEDGE_MIN_CNT This register stores the minimal input clock count between two positive
edges. It is used in baud rate detection. (RO)
RY
Register 22.27. UART_NEGPULSE_REG (0x0074)
T
_CN
IN
A
M
E_
G
ED
GE
d)
_N
ve
RT
r
se
IN
UA
(re
31 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xfff Reset
UART_NEGEDGE_MIN_CNT This register stores the minimal input clock count between two negative
IM
edges. It is used in baud rate detection. (RO)
Register 22.28. UART_AT_CMD_PRECNT_REG (0x0050)
EL
UM
_N
LE
ID
E_
R
)
ed
_P
rv
RT
se
UA
(re
31 16 15 0
PR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x901 Reset
UART_PRE_IDLE_NUM This register is used to configure the idle duration time before the first
AT_CMD is received by receiver, in the unit of bit time (the time it takes to transfer one bit). (R/W)
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Register 22.29. UART_AT_CMD_POSTCNT_REG (0x0054)
UM
E _N
DL
_I
ST
O
d)
_P
ve
RT
er
s
UA
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x901 Reset
UART_POST_IDLE_NUM This register is used to configure the duration time between the last
AT_CMD and the next data, in the unit of bit time (the time it takes to transfer one bit). (R/W)
RY
Register 22.30. UART_AT_CMD_GAPTOUT_REG (0x0058)
UT
O
_T
AP
A _G
X
)
d
_R
ve
RT
er
s
UA
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN
0 11 Reset
UART_RX_GAP_TOUT This register is used to configure the duration time between the AT_CMD
chars, in the unit of bit time (the time it takes to transfer one bit). (R/W)
IM
Register 22.31. UART_AT_CMD_CHAR_REG (0x005C)
AR
CH
M
EL
NU
D_
R_
CM
HA
T_
)
ed
_C
_A
rv
RT
RT
se
UA
UA
(re
31 16 15 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3 0x2b Reset
PR
UART_AT_CMD_CHAR This register is used to configure the content of AT_CMD character. (R/W)
UART_CHAR_NUM This register is used to configure the number of continuous AT_CMD chars re-
ceived by receiver. (R/W)
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Register 22.32. UART_DATE_REG (0x007C)
E
AT
_D
RT
UA
31 0
0x2008270 Reset
UART_DATE This is the version control register. (R/W)
Register 22.33. UART_ID_REG (0x0080)
RY
RL
E_ E
AT AT
CT
PD PD
_U _U
RT EG
D
UA T_R
_I
RT
R
UA
UA
31 30 29 0
A
0 1 0x000500 Reset
UART_ID This register is used to configure the UART_ID. (R/W)
IN
UART_UPDATE_CTRL This bit used to control register synchronization mode. This register must be
cleared before write 1 to UART_REG_UPDATE to synchronize configure value to UART core clock.
(R/W)
UART_REG_UPDATE Software write 1 would synchronize registers into UART Core clock domain
IM
and would be cleared by hardware after synchronization is done. (R/W/SC)
EL
PR
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Register 22.34. UHCI_CONF0_REG (0x0000)
EN
F_
se EP EN N EN
O
C R ID N N
(re I_S D_ C_E F_
_E
UH _C T_ _E _E
C EA E EO
CI NC N RK
CI AR OF C R
UH I_H C_R LE_
UH I_E _E _B
UH I_U _E _C
UH I_R T0 E
_T RS E
C AR _C
CI X_ _C
C LK RX
C d) _E
C EN E
X_ T
T
UH _L OD
UH rve ER
UH _U T1
UH I_C T_
RS
C AR
CI AR
d)
UH I_U
UH I_U
ve
er
C
s
UH
(re
31 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 Reset
UHCI_TX_RST Write 1, then write 0 to this bit to reset decode state machine. (R/W)
RY
UHCI_RX_RST Write 1, then write 0 to this bit to reset encode state machine. (R/W)
UHCI_UART0_CE Set this bit to link up HCI and UART0. (R/W)
UHCI_UART1_CE Set this bit to link up HCI and UART1. (R/W)
UHCI_SEPER_EN Set this bit to separate the data frame using a special char. (R/W)
A
UHCI_HEAD_EN Set this bit to encode the data packet with a formatting header. (R/W)
UHCI_CRC_REC_EN Set this bit to enable UHCI to receive the 16 bit CRC. (R/W)
IN
UHCI_UART_IDLE_EOF_EN If this bit is set to 1, UHCI will end the payload receiving process when
UART has been in idle state. (R/W)
UHCI_LEN_EOF_EN If this bit is set to 1, UHCI decoder receiving payload data is end when the
IM
receiving byte count has reached the specified value. The value is payload length indicated by UHCI
packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN
is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. (R/W)
EL
UHCI_ENCODE_CRC_EN Set this bit to enable data integrity checking by appending a 16 bit CCITT-
CRC to end of the payload. (R/W)
UHCI_CLK_EN 1’b1: Force clock on for register. 1’b0: Support clock only when application writes
registers. (R/W)
UHCI_UART_RX_BRK_EOF_EN If this bit is set to 1, UHCI will end payload receive process when
PR
NULL frame is received by UART. (R/W)
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Register 22.35. UHCI_CONF1_REG (0x0014)
E
_R
UH I_C E_ K_ _RE
RT
N
UH I_C C_D AD M
UM N
_E
_S _E
C R HE SU
TA
HE K_ LE
C AV EC M
CK EQ
UH I_S CH NU
_S
_C C B
UH rve IT_ RT
CI HE ISA
S
C d) SW
C _ _
se A A
K
(re _W ST
UH _T C
CI X_A
CI W_
d)
X
UH I_S
ve
UH I_T
er
C
s
UH
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 Reset
UHCI_CHECK_SUM_EN This is the enable bit to check header checksum when UHCI receives a
data packet. (R/W)
RY
UHCI_CHECK_SEQ_EN This is the enable bit to check sequence number when UHCI receives a data
packet. (R/W)
UHCI_CRC_DISABLE Set this bit to support CRC calculation. Data Integrity Check Present bit in
UHCI packet frame should be 1. (R/W)
A
UHCI_SAVE_HEAD Set this bit to save the packet header when HCI receives a data packet. (R/W)
UHCI_TX_CHECK_SUM_RE Set this bit to encode the data packet with a checksum. (R/W)
IN
UHCI_TX_ACK_NUM_RE Set this bit to encode the data packet with an acknowledgment when a
reliable packet is to be transmit. (R/W)
UHCI_WAIT_SW_START The uhci-encoder will jump to ST_SW_WAIT status if this register is set to
1. (R/W)
IM
UHCI_SW_START If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data
packet out when this bit is set to 1. (R/W/SC)
EL
PR
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Register 22.36. UHCI_ESCAPE_CONF_REG (0x0020)
UH I_T 13_ SC N
UH I_T 11_ SC_ N
SC N
N
UH I_R DB SC N
UH I_T C0 SC N
CI X_D ES EN
C0 SC N
C X_ _E _E
C X_ E _E
_E _E
_E
C X_ _E _E
C X_ _E _E
X_ _E _E
UH I_R 11 SC
_T B C
C X_ _E
UH I_R 13
C X_
d)
UH I_R
ve
er
C
s
UH
(re
31 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 Reset
UHCI_TX_C0_ESC_EN Set this bit to enable decoding char 0xc0 when DMA receives data. (R/W)
UHCI_TX_DB_ESC_EN Set this bit to enable decoding char 0xdb when DMA receives data. (R/W)
RY
UHCI_TX_11_ESC_EN Set this bit to enable decoding flow control char 0x11 when DMA receives
data. (R/W)
UHCI_TX_13_ESC_EN Set this bit to enable decoding flow control char 0x13 when DMA receives
data. (R/W)
A
UHCI_RX_C0_ESC_EN Set this bit to enable replacing 0xc0 by special char when DMA sends data.
(R/W)
UHCI_RX_DB_ESC_EN Set this bit to enable replacing 0xdb by special char when DMA sends data.
(R/W)
IN
UHCI_RX_11_ESC_EN Set this bit to enable replacing flow control char 0x11 by special char when
DMA sends data. (R/W)
IM
UHCI_RX_13_ESC_EN Set this bit to enable replacing flow control char 0x13 by special char when
DMA sends data. (R/W)
EL
PR
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22 UART Controller (UART)
Register 22.37. UHCI_HUNG_CONF_REG (0x0024)
FT
FT
NA
NA
HI
HI
_S
_E
_S
_E
UT
UT
UT
UT
UT
UT
EO
EO
EO
EO
EO
EO
IM
IM
IM
IM
IM
IM
_T
_T
_T
_T
_T
_T
FO
FO
FO
O
IF
IF
IF
FI
FI
FI
XF
XF
XF
)
RX
RX
X
ed
_R
_T
_T
_T
rv
_
CI
CI
CI
CI
CI
CI
se
UH
UH
UH
UH
UH
UH
(re
31 24 23 22 20 19 12 11 10 8 7 0
0 0 0 0 0 0 0 0 1 0 0x10 1 0 0x10 Reset
UHCI_TXFIFO_TIMEOUT This register stores the timeout value. It will produce the
RY
UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. (R/W)
UHCI_TXFIFO_TIMEOUT_SHIFT This register is used to configure the tick count maximum value.
(R/W)
UHCI_TXFIFO_TIMEOUT_ENA This is the enable bit for Tx-FIFO receive-data timeout. (R/W)
UHCI_RXFIFO_TIMEOUT This register stores the timeout value. It will produce the
A
UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. (R/W)
IN
UHCI_RXFIFO_TIMEOUT_SHIFT This register is used to configure the tick count maximum value.
(R/W)
UHCI_RXFIFO_TIMEOUT_ENA This is the enable bit for DMA send-data timeout. (R/W)
IM
Register 22.38. UHCI_ACK_NUM_REG (0x0028)
AD
O
EL
_L
UM
UM
_N
_N
CK
CK
d)
_A
_A
ve
r
CI
CI
se
UH
UH
(re
31 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x0 Reset
PR
UHCI_ACK_NUM This ACK number used in software flow control. (R/W)
UHCI_ACK_NUM_LOAD Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded.
(WT)
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Register 22.39. UHCI_QUICK_SENT_REG (0x0030)
UM
M
N
NU
N
_N
_E
_E
D_
ND
ND
D
EN
EN
SE
SE
_S
_S
S_
S_
LE
LE
AY
AY
G
LW
LW
IN
IN
)
ed
_A
_A
_S
_S
rv
CI
CI
CI
CI
se
UH
UH
UH
UH
(re
31 8 7 6 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0x0 Reset
UHCI_SINGLE_SEND_NUM This register is used to specify the single_send register. (R/W)
RY
UHCI_SINGLE_SEND_EN Set this bit to enable single_send mode to send short packet. (R/W/SC)
UHCI_ALWAYS_SEND_NUM This register is used to specify the always_send register. (R/W)
UHCI_ALWAYS_SEND_EN Set this bit to enable always_send mode to send short packet. (R/W)
A
Register 22.40. UHCI_REG_Q0_WORD0_REG (0x0034)
0
RD
IN _S
END
0_
_Q
W
O
CI
UH
IM
31 0
0x000000 Reset
UHCI_SEND_Q0_WORD0 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
EL
Register 22.41. UHCI_REG_Q0_WORD1_REG (0x0038)
1
RD
O
W
PR
0_
Q
D_
EN
_S
CI
UH
31 0
0x000000 Reset
UHCI_SEND_Q0_WORD1 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
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Register 22.42. UHCI_REG_Q1_WORD0_REG (0x003C)
0
RD
O
W
1_
_Q
END
_S
CI
UH
31 0
0x000000 Reset
UHCI_SEND_Q1_WORD0 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
RY
Register 22.43. UHCI_REG_Q1_WORD1_REG (0x0040)
1
RD
O
W
1_
A
_Q
END
_S
CI
UH
31
IN
0x000000
0
Reset
UHCI_SEND_Q1_WORD1 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
IM
Register 22.44. UHCI_REG_Q2_WORD0_REG (0x0044)
EL
0
RD
O
W
2_
_Q
END
_S
CI
UH
31 0
PR
0x000000 Reset
UHCI_SEND_Q2_WORD0 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
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Register 22.45. UHCI_REG_Q2_WORD1_REG (0x0048)
1
RD
O
W
2_
_Q
END
_S
CI
UH
31 0
0x000000 Reset
UHCI_SEND_Q2_WORD1 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
RY
Register 22.46. UHCI_REG_Q3_WORD0_REG (0x004C)
0
RD
O
W
3_
A
_Q
END
_S
CI
UH
31
IN
0x000000
0
Reset
UHCI_SEND_Q3_WORD0 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
IM
Register 22.47. UHCI_REG_Q3_WORD1_REG (0x0050)
EL
1
RD
O
W
3_
_Q
END
_S
CI
UH
31 0
PR
0x000000 Reset
UHCI_SEND_Q3_WORD1 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
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Register 22.48. UHCI_REG_Q4_WORD0_REG (0x0054)
0
RD
O
W
4_
_Q
END
_S
CI
UH
31 0
0x000000 Reset
UHCI_SEND_Q4_WORD0 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
RY
Register 22.49. UHCI_REG_Q4_WORD1_REG (0x0058)
1
RD
O
W
4_
A
_Q
END
_S
CI
UH
31
IN
0x000000
0
Reset
UHCI_SEND_Q4_WORD1 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
IM
Register 22.50. UHCI_REG_Q5_WORD0_REG (0x005C)
EL
0
RD
O
W
5_
_Q
END
_S
CI
UH
31 0
PR
0x000000 Reset
UHCI_SEND_Q5_WORD0 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
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Register 22.51. UHCI_REG_Q5_WORD1_REG (0x0060)
1
RD
O
W
5_
_Q
END
_S
CI
UH
31 0
0x000000 Reset
UHCI_SEND_Q5_WORD1 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
RY
Register 22.52. UHCI_REG_Q6_WORD0_REG (0x0064)
0
RD
O
W
6_
A
_Q
END
_S
CI
UH
31
IN
0x000000
0
Reset
UHCI_SEND_Q6_WORD0 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
IM
Register 22.53. UHCI_REG_Q6_WORD1_REG (0x0068)
EL
1
RD
O
W
6_
_Q
END
_S
CI
UH
31 0
PR
0x000000 Reset
UHCI_SEND_Q6_WORD1 This register is used as a quick_sent register when specified by
UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. (R/W)
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Register 22.54. UHCI_ESC_CONF0_REG (0x006C)
R0
AR
A
H
CH
_C
R
C_
HA
SC
ES
_C
_E
R_
ER
ER
PE
EP
EP
)
E
ed
_S
_S
_S
rv
CI
CI
CI
se
UH
UH
UH
(re
31 24 23 16 15 8 7 0
0 0 0 0 0 0 0 0 0xdc 0xdb 0xc0 Reset
UHCI_SEPER_CHAR This register is used to define the separate char that need to be encoded,
default is 0xc0. (R/W)
RY
UHCI_SEPER_ESC_CHAR0 This register is used to define the first char of slip escape sequence
when encoding the separate char, default is 0xdb. (R/W)
UHCI_SEPER_ESC_CHAR1 This register is used to define the second char of slip escape sequence
when encoding the separate char, default is 0xdc. (R/W)
A
Register 22.55. UHCI_ESC_CONF1_REG (0x0070)
IN
R1
0
AR
HA
CH
C
0_
0_
0
Q
EQ
E
SE
_S
_S
C_
SC
SC
d)
S
ve
_E
_E
_E
IM
r
CI
CI
CI
se
UH
UH
UH
(re
31 24 23 16 15 8 7 0
0 0 0 0 0 0 0 0 0xdd 0xdb 0xdb Reset
UHCI_ESC_SEQ0 This register is used to define a char that need to be encoded, default is 0xdb that
EL
used as the first char of slip escape sequence. (R/W)
UHCI_ESC_SEQ0_CHAR0 This register is used to define the first char of slip escape sequence when
encoding the UHCI_ESC_SEQ0, default is 0xdb. (R/W)
UHCI_ESC_SEQ0_CHAR1 This register is used to define the second char of slip escape sequence
PR
when encoding the UHCI_ESC_SEQ0, default is 0xdd. (R/W)
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Register 22.56. UHCI_ESC_CONF2_REG (0x0074)
R1
R0
HA
A
CH
C
1_
1_
1
Q
EQ
E
SE
_S
_S
C_
SC
SC
)
ES
ed
_E
_E
rv
_
CI
CI
CI
se
UH
UH
UH
(re
31 24 23 16 15 8 7 0
0 0 0 0 0 0 0 0 0xde 0xdb 0x11 Reset
UHCI_ESC_SEQ1 This register is used to define a char that need to be encoded, default is 0x11 that
used as flow control char. (R/W)
RY
UHCI_ESC_SEQ1_CHAR0 This register is used to define the first char of slip escape sequence when
encoding the UHCI_ESC_SEQ1, default is 0xdb. (R/W)
UHCI_ESC_SEQ1_CHAR1 This register is used to define the second char of slip escape sequence
when encoding the UHCI_ESC_SEQ1, default is 0xde. (R/W)
A
Register 22.57. UHCI_ESC_CONF3_REG (0x0078)
IN
1
0
AR
AR
CH
CH
2_
2_
2
EQ
EQ
EQ
_S
_S
_S
SC
SC
SC
ed)
_E
_E
_E
rv
IM CI
CI
CI
se
UH
UH
UH
(re
31 24 23 16 15 8 7 0
0 0 0 0 0 0 0 0 0xdf 0xdb 0x13 Reset
UHCI_ESC_SEQ2 This register is used to define a char that need to be decoded, default is 0x13 that
EL
used as flow control char. (R/W)
UHCI_ESC_SEQ2_CHAR0 This register is used to define the first char of slip escape sequence when
encoding the UHCI_ESC_SEQ2, default is 0xdb. (R/W)
UHCI_ESC_SEQ2_CHAR1 This register is used to define the second char of slip escape sequence
PR
when encoding the UHCI_ESC_SEQ2, default is 0xdf. (R/W)
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Register 22.58. UHCI_PKT_THRES_REG (0x007C)
S
HR
_T
KT
)
ed
_P
v
er
CI
s
UH
(re
31 13 12 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80 Reset
UHCI_PKT_THRS This register is used to configure the maximum value of the packet length when
UHCI_HEAD_EN is 0. (R/W)
RY
Register 22.59. UHCI_INT_RAW_REG (0x0004)
CI X_S NG NT_ INT AW
W
X_ AR INT AW RA
UH I_T HU _I _Q_ T_R
UH I_S D_ F_IN T_ W
UH I_T D_ RE _RA W
_R T _ R _
W
T_ W
AR IN AW
C EN O _IN RA
C EN A_ T RA
C X_ S_ G W
C X_ NG G IN
RA
IN A
UH I_R HU RE _Q_
UH I_S T_E L0 T_
T_ _R
ST T_ _R
C U TR _IN
T
UH I_O _C L1
A C PP TR
UH I_A _C
C PP
)
ed
UH I_A
rv
se
C
UH
(re
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN
0 0 0 0 0 0 0
9
0
8
0 0
7 6
0
5
0
4
0
3
0
2
0
1
0
0
0 Reset
UHCI_RX_START_INT_RAW This is the interrupt raw bit. Triggered when a separator char has been
sent. (R/WTC/SS)
IM
UHCI_TX_START_INT_RAW This is the interrupt raw bit. Triggered when UHCI detects a separator
char. (R/WTC/SS)
UHCI_RX_HUNG_INT_RAW This is the interrupt raw bit. Triggered when UHCI takes more time to
EL
receive data than configure value. (R/WTC/SS)
UHCI_TX_HUNG_INT_RAW This is the interrupt raw bit. Triggered when UHCI takes more time to
read data from RAM than the configured value. (R/WTC/SS)
UHCI_SEND_S_REG_Q_INT_RAW This is the interrupt raw bit. Triggered when UHCI has sent out
a short packet using single_send registers. (R/WTC/SS)
PR
UHCI_SEND_A_REG_Q_INT_RAW This is the interrupt raw bit. Triggered when UHCI has sent out
a short packet using always_send registers. (R/WTC/SS)
UHCI_OUT_EOF_INT_RAW This is the interrupt raw bit. Triggered when there are some errors in
EOF in the transmit data. (R/WTC/SS)
UHCI_APP_CTRL0_INT_RAW This is the interrupt raw bit. Triggered when set this bit to 1. Clear it
when write 0 to this bit. (R/W)
UHCI_APP_CTRL1_INT_RAW This is the interrupt raw bit. Triggered when set this bit to 1. Clear it
when write 0 to this bit. (R/W)
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Register 22.60. UHCI_INT_ST_REG (0x0008)
UH I_T HU _I _Q_ T_S ST
C X_ NG G IN T_
CI X_S NG NT_ INT T
X_ AR INT T ST
UH I_R HU RE _Q_ _IN
_R T _ S _
C EN K _IN ST
C EN A_ OF ST
C X_ S_ G R
ST
IN T
AR IN T
UH I_T D_ RE _ER
UH I_S TLIN L0 T_
UH I_S D_ _E T_
T_ T_S
ST T_ _S
T_
C U TR _IN
UH I_O _C L1
C PP TR
UH I_A _C
C PP
d)
UH I_A
ve
er
C
s
UH
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_RX_START_INT_ST This is the masked interrupt bit for UHCI_RX_START_INT interrupt when
RY
UHCI_RX_START_INT_ENA is set to 1. (RO)
UHCI_TX_START_INT_ST This is the masked interrupt bit for UHCI_TX_START_INT interrupt when
UHCI_TX_START_INT_ENA is set to 1. (RO)
UHCI_RX_HUNG_INT_ST This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when
UHCI_RX_HUNG_INT_ENA is set to 1. (RO)
A
UHCI_TX_HUNG_INT_ST This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when
UHCI_TX_HUNG_INT_ENA is set to 1. (RO)
IN
UHCI_SEND_S_REG_Q_INT_ST This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT in-
terrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1. (RO)
UHCI_SEND_A_REG_Q_INT_ST This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT in-
IM
terrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1. (RO)
UHCI_OUTLINK_EOF_ERR_INT_ST This is the masked interrupt bit for
UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set
to 1. (RO)
EL
UHCI_APP_CTRL0_INT_ST This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt
when UHCI_APP_CTRL0_INT_ENA is set to 1. (RO)
UHCI_APP_CTRL1_INT_ST This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt
when UHCI_APP_CTRL1_INT_ENA is set to 1. (RO)
PR
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Register 22.61. UHCI_INT_ENA_REG (0x000C)
CI X_S NG NT_ INT NA A
UH I_T HU _I _Q_ T_E EN
A
C X_ NG G IN T_
X_ AR INT NA EN
UH I_R HU RE _Q_ _IN
_R T _ E _
UH I_S D_ _E T_ A
UH I_T D_ RE _ER A
C EN K _IN EN
C EN A_ OF EN
A
T_ A
AR IN NA
C X_ S_ G R
EN
IN N
UH I_S TLIN L0 T_
T_ _E
ST T_ _E
C U TR _IN
T
UH I_O _C L1
C PP TR
UH I_A _C
C PP
d)
UH I_A
ve
er
C
s
UH
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_RX_START_INT_ENA This is the interrupt enable bit for UHCI_RX_START_INT interrupt. (R/W)
RY
UHCI_TX_START_INT_ENA This is the interrupt enable bit for UHCI_TX_START_INT interrupt. (R/W)
UHCI_RX_HUNG_INT_ENA This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. (R/W)
A
UHCI_TX_HUNG_INT_ENA This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. (R/W)
IN
UHCI_SEND_S_REG_Q_INT_ENA This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT
interrupt. (R/W)
UHCI_SEND_A_REG_Q_INT_ENA This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT
interrupt. (R/W)
IM
UHCI_OUTLINK_EOF_ERR_INT_ENA This is the interrupt enable bit for
UHCI_OUTLINK_EOF_ERR_INT interrupt. (R/W)
UHCI_APP_CTRL0_INT_ENA This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt.
(R/W)
EL
UHCI_APP_CTRL1_INT_ENA This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt.
(R/W)
PR
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Register 22.62. UHCI_INT_CLR_REG (0x0010)
CI X_S NG NT_ INT LR R
UH I_T HU _I _Q_ T_C CL
R
C X_ NG G IN T_
X_ AR INT LR CL
UH I_R HU RE _Q_ _IN
_R T _ C _
UH I_S D_ _E T_ R
UH I_T D_ RE _ER R
C EN K _IN CL
C EN A_ OF CL
R
IN LR
AR IN LR
C X_ S_ G R
CL
UH I_S TLIN L0 T_
T_ _C
ST T_ _C
T_
C U TR _IN
T
UH I_O _C L1
C PP TR
UH _A _C
CI PP
d)
UH I_A
ve
er
C
s
UH
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_RX_START_INT_CLR Set this bit to clear UHCI_RX_START_INT interrupt. (WT)
RY
UHCI_TX_START_INT_CLR Set this bit to clear UHCI_TX_START_INT interrupt. (WT)
UHCI_RX_HUNG_INT_CLR Set this bit to clear UHCI_RX_HUNG_INT interrupt. (WT)
UHCI_TX_HUNG_INT_CLR Set this bit to clear UHCI_TX_HUNG_INT interrupt. (WT)
A
UHCI_SEND_S_REG_Q_INT_CLR Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt. (WT)
UHCI_SEND_A_REG_Q_INT_CLR Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt. (WT)
IN
UHCI_OUTLINK_EOF_ERR_INT_CLR Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt.
(WT)
UHCI_APP_CTRL0_INT_CLR Set this bit to clear UHCI_APP_CTRL0_INT interrupt. (WT)
IM
UHCI_APP_CTRL1_INT_CLR Set this bit to clear UHCI_APP_CTRL1_INT interrupt. (WT)
Register 22.63. UHCI_STATE0_REG (0x0018)
EL
E
TE
US
TA
A
_S
_C
DE
RR
O
_E
EC
)
X
ed
_D
_R
rv
CI
CI
se
UH
UH
(re
31 6 5 3 2 0
PR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_RX_ERR_CAUSE This register indicates the error type when DMA has received a packet with
error. 3’b001: Checksum error in HCI packet; 3’b010: Sequence number error in HCI packet;
3’b011: CRC bit error in HCI packet; 3’b100: 0xc0 is found but received HCI packet is not end;
3’b101: 0xc0 is not found when receiving HCI packet is end; 3’b110: CRC check error. (RO)
UHCI_DECODE_STATE UHCI decoder status. (RO)
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Register 22.64. UHCI_STATE1_REG (0x001C)
TE
TA
_S
DE
O
NC
d)
ve
_E
er
CI
s
UH
(re
31 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_ENCODE_STATE UHCI encoder status. (RO)
RY
Register 22.65. UHCI_RX_HEAD_REG (0x002C)
AD
HE
X_
_R
CI
UH
A
31 0
0x000000 Reset
UHCI_RX_HEAD This register stores the header of the current received packet. (RO)
IN
Register 22.66. UHCI_DATE_REG (0x0080)
IM UH
CI
_D
AT
E
31 0
0x2007170 Reset
EL
UHCI_DATE This is the version control register. (R/W)
PR
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23 I2C Controller (I2C)
23 I2C Controller (I2C)
The I2C (Inter-Integrated Circuit) bus allows ESP32-C3 to communicate with multiple external devices. These
external devices can share one bus.
23.1 Overview
The I2C bus has two lines, namely a serial data line (SDA) and a serial clock line (SCL). Both SDA and SCL lines
are open-drain. The I2C bus can be connected to a single or multiple master devices and a single or multiple
slave devices. However, only one master device can access a slave at a time via the bus.
The master initiates communication by generating a START condition: pulling the SDA line low while SCL is high,
RY
and sending nine clock pulses via SCL. The first eight pulses are used to transmit a 7-bit address followed by a
read/write (R/W ) bit. If the address of an I2C slave matches the 7-bit address transmitted, this matching slave
can respond by pulling SDA low on the ninth clock pulse. The master and the slave can send or receive data
according to the R/W bit. Whether to terminate the data transfer or not is determined by the logic level of the
acknowledge (ACK) bit. During data transfer, SDA changes only when SCL is low. Once finishing
A
communication, the master sends a STOP condition: pulling SDA up while SCL is high. If a master both reads
and writes data in one transfer, then it should send a RSTART condition, a slave address and a R/W bit before
changing its operation. The RSTART condition is used to change the transfer direction and the mode of the
devices (master mode or slave mode).
IN
23.2 Features
The I2C controller has the following features:
IM
• Master mode and slave mode
• Communication between multiple slaves
• Standard mode (100 Kbit/s)
EL
• Fast mode (400 Kbit/s)
• 7-bit addressing and 10-bit addressing
• Continuous data transfer achieved by pulling SCL low
• Programmable digital noise filtering
PR
• Double addressing mode, which uses slave address and slave memory or register address
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23.3 I2C Architecture
A RY
IN
Figure 231. I2C Master Architecture
IM
EL
PR
Figure 232. I2C Slave Architecture
The I2C controller runs either in master mode or slave mode, which is determined by I2C_MS_MODE. Figure
23-1 shows the architecture of a master, while Figure 23-2 shows that of a slave. The I2C controller has the
following main parts:
• transmit and receive memory (TX/RX RAM)
• command controller (CMD_Controller)
• SCL clock controller (SCL_FSM)
• SDA data controller (SCL_MAIN_FSM)
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• serial/parallel data converter (DATA_Shifter)
• filter for SCL (SCL_Filter)
• filter for SDA (SDA_Filter)
Besides, the I2C controller also has a clock module which generates I2C clocks, and a synchronization module
which synchronizes the APB bus and the I2C controller.
The clock module is used to select clock sources, turn on and off clocks, and divide clocks. SCL_Filter and
SDA_Filter remove noises on SCL input signals and SDA input signals respectively. The synchronization module
synchronizes signal transfer between different clock domains.
Figure 23-3 and Figure 23-4 are the timing diagram and corresponding parameters of the I2C protocol.
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SCL_FSM generates the timing sequence conforming to the I2C protocol.
SCL_MAIN_FSM controls the execution of I2C commands and the sequence of the SDA line. CMD_Controller is
used for an I2C master to generate (R)START, STOP, WRITE, READ and END commands. TX RAM and RX RAM
store data to be transmitted and data received respectively. DATA_Shifter shifts data between serial and parallel
form.
A
IN
IM
EL
Figure 233. I2C Protocol Timing (Cited from Fig.31 in The I2Cbus specification Version 2.1)
PR
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A RY
Figure 234. I2C Timing Parameters (Cited from Table 5 in The I2Cbus specification Version 2.1)
23.4 Functional Description
IN
Note that operations may differ between the I2C controller in ESP32-C3 and other masters or slaves on the bus.
Please refer to datasheets of individual I2C devices for specific information.
IM
23.4.1 Clock Configuration
Registers, TX RAM, and RX RAM are configured and accessed in the APB_CLK clock domain, whose frequency
is 1 ∼ 80 MHz. The main logic of the I2C controller, including SCL_FSM, SCL_MAIN_FSM, SCL_FILTER,
SDA_FILTER, and DATA_SHIFTER, are in the I2C_SCLK clock domain.
EL
You can choose the clock source for I2C_SCLK from XTAL_CLK or FOSC_CLK via I2C_SCLK_SEL. When
I2C_SCLK_SEL is cleared, the clock source is XTAL_CLK. When I2C_SCLK_SEL is set, the clock source is
FOSC_CLK. The clock source is enabled by configuring I2C_SCLK_ACTIVE as high level, and then passes
through a fractional divider to generate I2C_SCLK according to the following equation:
PR
I2C_SCLK_DIV _A
Divisor = I2C_SCLK_DIV _N U M + 1 +
I2C_SCLK_DIV _B
The frequency of XTAL_CLK is 40 MHz, while the frequency of FOSC_CLK is 17.5 MHz. Limited by timing
parameters, the derived clock I2C_SCLK should operate at a frequency 20 timers larger than SCL’s
frequency.
23.4.2 SCL and SDA Noise Filtering
SCL_Filter and SDA_Filter modules are identical and are used to filter signal noises on SCL and SDA, respectively.
These filters can be enabled or disabled by configuring I2C_SCL_FILTER_EN and I2C_SDA_FILTER_EN.
Take SCL_Filter as an example. When enabled, SCL_Filter samples input signals on the SCL line continuously.
These input signals are valid only if they remain unchanged for consecutive I2C_SCL_FILTER_THRES I2C_SCLK
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clock cycles. Given that only valid input signals can pass through the filter, SCL_Filter can remove glitches whose
pulse width is shorter than I2C_SCL_FILTER_THRES I2C_SCLK clock cycles, while SDA_Filter can remove
glitches whose pulse width is shorter than I2C_SDA_FILTER_THRES I2C_SCLK clock cycles.
23.4.3 SCL Clock Stretching
The I2C controller in slave mode (i.e. slave) can hold the SCL line low in exchange for more time to process data.
This function called clock stretching is enabled by setting the I2C_SLAVE_SCL_STRETCH_EN bit. The time
period to release the SCL line from stretching is configured by setting the I2C_STRETCH_PROTECT_NUM field,
in order to avoid timing sequence errors. The slave will hold the SCL line low when one of the following four
events occurs:
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1. Address match: The address of the slave matches the address sent by the master via the SDA line, and the
R/W bit is 1.
2. RAM being full: RX RAM of the slave is full. Note that when the slave receives less than 32 bytes, it is not
necessary to enable clock stretching; when the slave receives 32 bytes or more, you may interrupt data
transmission to wrapped around RAM via the FIFO threshold, or enable clock stretching for more time to
process data. When clock stretching is enabled, I2C_RX_FULL_ACK_LEVEL must be cleared, otherwise
A
there will be unpredictable consequences.
3. RAM being empty: The slave is sending data, but its TX RAM is empty.
IN
4. Sending an ACK: If I2C_SLAVE_BYTE_ACK_CTL_EN is set, the slave pulls SCL low when sending an ACK
bit. At this stage, software validates data and configures I2C_SLAVE_BYTE_ACK_LVL to control the level of
the ACK bit. Note that when RX RAM of the slave is full, the level of the ACK bit to be sent is determined by
I2C_RX_FULL_ACK_LEVEL, instead of I2C_SLAVE_BYTE_ACK_LVL. In this case,
IM
I2C_RX_FULL_ACK_LEVEL should also be cleared to ensure proper functioning of clock stretching.
After SCL has been stretched low, the cause of stretching can be read from the I2C_STRETCH_CAUSE bit.
Clock stretching is disabled by setting the I2C_SLAVE_SCL_STRETCH_CLR bit.
EL
23.4.4 Generating SCL Pulses in Idle State
Usually when the I2C bus is idle, the SCL line is held high. The I2C controller in ESP32-C3 can be programmed
to generate SCL pulses in idle state. This function only works when the I2C controller is configured as master. If
the I2C_SCL_RST_SLV_EN bit is set, hardware will send I2C_SCL_RST_SLV_NUM SCL pulses. When software
reads 0 in I2C_SCL_RST_SLV_EN, set I2C_CONF_UPGATE to stop this function.
PR
23.4.5 Synchronization
I2C registers are configured in APB_CLK domain, whereas the I2C controller is configured in asynchronous
I2C_SCLK domain. Therefore, before being used by the I2C controller, register values should be synchronized by
first writing configuration registers and then writing 1 to I2C_CONF_UPGATE. Registers that need
synchronization are listed in Table 23-1.
Table 231. I2C Synchronous Registers
Register Parameter Address
I2C_CTR_REG I2C_SLV_TX_AUTO_START_EN 0x0004
I2C_ADDR_10BIT_RW_CHECK_EN
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I2C_ADDR_BROADCASTING_EN
I2C_SDA_FORCE_OUT
I2C_SCL_FORCE_OUT
I2C_SAMPLE_SCL_LEVEL
I2C_RX_FULL_ACK_LEVEL
I2C_MS_MODE
I2C_TX_LSB_FIRST
I2C_RX_LSB_FIRST
I2C_ARBITRATION_EN
I2C_TO_REG I2C_TIME_OUT_EN 0x000C
I2C_TIME_OUT_VALUE
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I2C_SLAVE_ADDR_REG I2C_ADDR_10BIT_EN 0x0010
I2C_SLAVE_ADDR
I2C_FIFO_CONF_REG I2C_FIFO_ADDR_CFG_EN 0x0018
I2C_SCL_SP_CONF_REG I2C_SDA_PD_EN 0x0080
I2C_SCL_PD_EN
I2C_SCL_RST_SLV_NUM
A
I2C_SCL_RST_SLV_EN
I2C_SCL_STRETCH_CONF_REG I2C_SLAVE_BYTE_ACK_CTL_EN 0x0084
I2C_SLAVE_BYTE_ACK_LVL
IN
I2C_SLAVE_SCL_STRETCH_EN
I2C_STRETCH_PROTECT_NUM
I2C_SCL_LOW_PERIOD_REG I2C_SCL_LOW_PERIOD 0x0000
I2C_SCL_HIGH_PERIOD_REG I2C_WAIT_HIGH_PERIOD 0x0038
IM
I2C_HIGH_PERIOD
I2C_SDA_HOLD_REG I2C_SDA_HOLD_TIME 0x0030
I2C_SDA_SAMPLE_REG I2C_SDA_SAMPLE_TIME 0x0034
I2C_SCL_START_HOLD_REG I2C_SCL_START_HOLD_TIME 0x0040
EL
I2C_SCL_RSTART_SETUP_REG I2C_SCL_RSTART_SETUP_TIME 0x0044
I2C_SCL_STOP_HOLD_REG I2C_SCL_STOP_HOLD_TIME 0x0048
I2C_SCL_STOP_SETUP_REG I2C_SCL_STOP_SETUP_TIME 0x004C
I2C_SCL_ST_TIME_OUT_REG I2C_SCL_ST_TO_I2C 0x0078
I2C_SCL_MAIN_ST_TIME_OUT_REG I2C_SCL_MAIN_ST_TO_I2C 0x007C
PR
I2C_FILTER_CFG_REG I2C_SCL_FILTER_EN 0x0050
I2C_SCL_FILTER_THRES
I2C_SDA_FILTER_EN
I2C_SDA_FILTER_THRES
23.4.6 OpenDrain Output
SCL and SDA output drivers must be configured as open drain. There are two ways to achieve this:
1. Set I2C_SCL_FORCE_OUT and I2C_SDA_FORCE_OUT, and configure GPIO_PINn_PAD_DRIVER for
corresponding SCL and SDA pads as open-drain.
2. Clear I2C_SCL_FORCE_OUT and I2C_SDA_FORCE_OUT.
Because these lines are configured as open-drain, the low-to-high transition time of each line is longer,
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determined together by the pull-up resistor and the line capacitance. The output duty cycle of I2C is limited by
the SDA and SCL line’s pull-up speed, mainly SCL’s speed.
In addition, when I2C_SCL_FORCE_OUT and I2C_SCL_PD_EN are set to 1, SCL can be forced low; when
I2C_SDA_FORCE_OUT and I2C_SDA_PD_EN are set to 1, SDA can be forced low.
23.4.7 Timing Parameter Configuration
A RY
Figure 235. I2C Timing Diagram
IN
Figure 23-5 shows the timing diagram of an I2C master. This figure also specifies registers used to configure the
START bit, STOP bit, data hold time, data sample time, waiting time on the rising SCL edge, etc. Timing
parameters are calculated as follows in I2C_SCLK clock cycles:
IM
1. tLOW = (I2C_SCL_LOW _P ERIOD + 1) · TI2C_SCLK
2. tHIGH = (I2C_SCL_HIGH_P ERIOD + 1) · TI2C_SCLK
3. tSU :ST A = (I2C_SCL_RST ART _SET U P _T IM E + 1) · TI2C_SCLK
EL
4. tHD:ST A = (I2C_SCL_ST ART _HOLD_T IM E + 1) · TI2C_SCLK
5. tr = (I2C_SCL_W AIT _HIGH_P ERIOD + 1) · TI2C_SCLK
6. tSU :ST O = (I2C_SCL_ST OP _SET U P _T IM E + 1) · TI2C_SCLK
7. tBU F = (I2C_SCL_ST OP _HOLD_T IM E + 1) · TI2C_SCLK
PR
8. tHD:DAT = (I2C_SDA_HOLD_T IM E + 1) · TI2C_SCLK
9. tSU :DAT = (I2C_SCL_LOW _P ERIOD − I2C_SDA_HOLD_T IM E) · TI2C_SCLK
Timing registers below are divided into two groups, depending on the mode in which these registers are
active:
• Master mode only:
1. I2C_SCL_START_HOLD_TIME: Specifies the interval between pulling SDA low and pulling SCL low
when the master generates a START condition. This interval is (I2C_SCL_START_HOLD_TIME +1) in
I2C_SCLK cycles. This register is active only when the I2C controller works in master mode.
2. I2C_SCL_LOW_PERIOD: Specifies the low period of SCL. This period lasts (I2C_SCL_LOW_PERIOD
+ 1) in I2C_SCLK cycles. However, it could be extended when SCL is pulled low by peripheral devices
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or by an END command executed by the I2C controller, or when the clock is stretched. This register is
active only when the I2C controller works in master mode.
3. I2C_SCL_WAIT_HIGH_PERIOD: Specifies time for SCL to go high in I2C_SCLK cycles. Please make
sure that SCL could be pulled high within this time period. Otherwise, the high period of SCL may be
incorrect. This register is active only when the I2C controller works in master mode.
4. I2C_SCL_HIGH_PERIOD: Specifies the high period of SCL in I2C_SCLK cycles. This register is active
only when the I2C controller works in master mode. When SCL goes high within
(I2C_SCL_WAIT_HIGH_PERIOD + 1) in I2C_SCLK cycles, its frequency is:
fI2C_SCLK
fscl =
I2C_SCL_LOW_PERIOD+I2C_SCL_HIGH_PERIOD+I2C_SCL_WAIT_HIGH_PERIOD+3
RY
• Master mode and slave mode:
1. I2C_SDA_SAMPLE_TIME: Specifies the interval between the rising edge of SCL and the level
sampling time of SDA. It is advised to set a value in the middle of SCL’s high period, so as to correctly
sample the level of SCL. This register is active both in master mode and slave mode.
2. I2C_SDA_HOLD_TIME: Specifies the interval between changing the SDA output level and the falling
A
edge of SCL. This register is active both in master mode and slave mode.
Timing parameters limits corresponding register configuration.
1. fI2C_SCLK
fSCL > 20
IN
2. 3 × fI2C_SCLK ≤ (I2C_SDA_HOLD_T IM E − 4) × fAP B_CLK
3. I2C_SDA_HOLD_TIME + I2C_SCL_START_HOLD_TIME > SDA_FILTER_THRES + 3
IM
4. I2C_SCL_WAIT_HIGH_PERIOD < I2C_SDA_SAMPLE_TIME < I2C_SCL_HIGH_PERIOD
5. I2C_SDA_SAMPLE_TIME < I2C_SCL_WAIT_HIGH_PERIOD + I2C_SCL_START_HOLD_TIME +
I2C_SCL_RSTART_SETUP_TIME
6. I2C_STRETCH_PROTECT_NUM + I2C_SDA_HOLD_TIME > I2C_SCL_LOW_PERIOD
EL
23.4.8 Timeout Control
The I2C controller has three types of timeout control, namely timeout control for SCL_FSM, for SCL_MAIN_FSM,
and for the SCL line. The first two are always enabled, while the third is configurable.
PR
When SCL_FSM remains unchanged for more than 2I2C_SCL_ST _T O_I2C clock cycles, an I2C_SCL_ST_TO_INT
interrupt is triggered, and then SCL_FSM goes to idle state. The value of I2C_SCL_ST_TO_I2C should be less
than or equal to 22, which means SCL_FSM could remain unchanged for 222 I2C_SCLK clock cycles at most
before the interrupt is generated.
When SCL_MAIN_FSM remains unchanged for more than 2I2C_SCL_M AIN _ST _T O_I2C clock cycles, an
I2C_SCL_MAIN_ST_TO_INT interrupt is triggered, and then SCL_MAIN_FSM goes to idle state. The value of
I2C_SCL_MAIN_ST_TO_I2C should be less than or equal to 22, which means SCL_MAIN_FSM could remain
unchanged for 222 I2C_SCLK clock cycles at most before the interrupt is generated.
Timeout control for SCL is enabled by setting I2C_TIME_OUT_EN. When the level of SCL remains unchanged for
more than I2C_TIME_OUT_VALUE clock cycles, an I2C_TIME_OUT_INT interrupt is triggered, and then the I2C
bus goes to idle state.
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23.4.9 Command Configuration
When the I2C controller works in master mode, CMD_Controller reads commands from 8 sequential command
registers and controls SCL_FSM and SCL_MAIN_FSM accordingly.
RY
Figure 236. Structure of I2C Command Registers
Command registers, whose structure is illustrated in Figure 23-6, are active only when the I2C controller works in
master mode. Fields of command registers are:
A
1. CMD_DONE: Indicates that a command has been executed. After each command has been executed, the
CMD_DONE bit in the corresponding command register is set to 1 by hardware. By reading this bit,
software can tell if the command has been executed. When writing new commands, this bit must be
cleared by software.
IN
2. op_code: Indicates the command. The I2C controller supports five commands:
• RSTART: op_code = 6. The I2C controller sends a START bit or a RSTART bit defined by the I2C
IM
protocol.
• WRITE: op_code = 1. The I2C controller sends a slave address, a register address (only in double
addressing mode) and data to the slave.
• READ: op_code = 3. The I2C controller reads data from the slave.
EL
• STOP: op_code = 2. The I2C controller sends a STOP bit defined by the I2C protocol. This code also
indicates that the command sequence has been executed, and the CMD_Controller stops reading
commands. After restarted by software, the CMD_Controller resumes reading commands from
command register 0.
• END: op_code = 4. The I2C controller pulls the SCL line down and suspends I2C communication.
PR
This code also indicates that the command sequence has completed, and the CMD_Controller stops
executing commands. Once software refreshes data in command registers and the RAM, the
CMD_Controller can be restarted to execute commands from command register 0 again.
3. ack_value: Used to configure the level of the ACK bit sent by the I2C controller during a read operation.
This bit is ignored in RSTART, STOP, END and WRITE conditions.
4. ack_exp: Used to configure the level of the ACK bit expected by the I2C controller during a write operation.
This bit is ignored during RSTART, STOP, END and READ conditions.
5. ack_check_en: Used to enable the I2C controller during a write operation to check whether the ACK level
sent by the slave matches ack_exp in the command. If this bit is set and the level received does not match
ack_exp in the WRITE command, the master will generate an I2C_NACK_INT interrupt and a STOP
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condition for data transfer. If this bit is cleared, the controller will not check the ACK level sent by the slave.
This bit is ignored during RSTART, STOP, END and READ conditions.
6. byte_num: Specifies the length of data (in bytes) to be read or written. Can range from 1 to 255 bytes. This
bit is ignored during RSTART, STOP and END conditions.
Each command sequence is executed starting from command register 0 and terminated by a STOP or an END.
Therefore, there must be a STOP or an END command in one command sequence.
A complete data transfer on the I2C bus should be initiated by a START and terminated by a STOP. The transfer
process may be completed using multiple sequences, separated by END commands. Each sequence may differ
in the direction of data transfer, clock frequency, slave addresses, data length, etc. This allows efficient use of
available peripheral RAM and also achieves more flexible I2C communication.
RY
23.4.10 TX/RX RAM Data Storage
Both TX RAM and RX RAM are 32 × 8 bits, and can be accessed in FIFO or non-FIFO mode. If
I2C_NONFIFO_EN bit is cleared, both RAMs are accessed in FIFO mode; if I2C_NONFIFO_EN bit is set, both
RAMs are accessed in non-FIFO mode.
A
TX RAM stores data that the I2C controller needs to send. During communication, when the I2C controller needs
to send data (except acknowledgement bits), it reads data from TX RAM and sends them sequentially via SDA.
When the I2C controller works in master mode, all data must be stored in TX RAM in the order they will be sent to
IN
slaves. The data stored in TX RAM include slave addresses, read/write bits, register addresses (only in double
addressing mode) and data to be sent. When the I2C controller works in slave mode, TX RAM only stores data to
be sent.
IM
TX RAM can be read and written by the CPU. The CPU writes to TX RAM either in FIFO mode or in non-FIFO
mode (direct address). In FIFO mode, the CPU writes to TX RAM via the fixed address I2C_DATA_REG, with
addresses for writing in TX RAM incremented automatically by hardware. In non-FIFO mode, the CPU accesses
TX RAM directly via address fields (I2C Base Address + 0x100) ~(I2C Base Address + 0x17C). Each byte in TX
RAM occupies an entire word in the address space. Therefore, the address of the first byte is I2C Base Address
EL
+ 0x100, the second byte is I2C Base Address + 0x104, the third byte is I2C Base Address + 0x108, and so on.
The CPU can only read TX RAM via direct addresses. Addresses for reading TX RAM are the same with
addresses for writing TX RAM.
RX RAM stores data the I2C controller receives during communication. When the I2C controller works in slave
mode, neither slave addresses sent by the master nor register addresses (only in double addressing mode) will
PR
be stored into RX RAM. Values of RX RAM can be read by software after I2C communication completes.
RX RAM can only be read by the CPU. The CPU reads RX RAM either in FIFO mode or in non-FIFO mode (direct
address). In FIFO mode, the CPU reads RX RAM via the fixed address I2C_DATA_REG, with addresses for
reading RX RAM incremented automatically by hardware. In non-FIFO mode, the CPU accesses TX RAM directly
via address fields (I2C Base Address + 0x180) ~(I2C Base Address + 0x1FC). Each byte in RX RAM occupies an
entire word in the address space. Therefore, the address of the first byte is I2C Base Address + 0x180, the
second byte is I2C Base Address + 0x184, the third byte is I2C Base Address + 0x188 and so on.
In FIFO mode, TX RAM of a master may wrap around to send data larger than 32 bytes. Set I2C_FIFO_PRT_EN.
If the size of data to be sent is smaller than I2C_TXFIFO_WM_THRHD (master), an I2C_TXFIFO_WM_INT (master)
interrupt is generated. After receiving the interrupt, software continues writing to I2C_DATA_REG (master).
Please ensure that software writes to or refreshes TX RAM before the master sends data, otherwise it may result
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in unpredictable consequences.
In FIFO mode, RX RAM of a slave may also wrap around to receive data larger than 32 bytes. Set
I2C_FIFO_PRT_EN and clear I2C_RX_FULL_ACK_LEVEL. If data already received (to be overwritten) is larger
than I2C_RXFIFO_WM_THRHD (slave), an I2C_RXFIFO_WM_INT (slave) interrupt is generated. After receiving the
interrupt, software continues reading from I2C_DATA_REG (slave).
23.4.11 Data Conversion
DATA_Shifter is used for serial/parallel conversion, converting byte data in TX RAM to an outgoing serial bitstream
or an incoming serial bitstream to byte data in RX RAM. I2C_RX_LSB_FIRST and I2C_TX_LSB_FIRST can be
used to select LSB- or MSB-first storage and transmission of data.
RY
23.4.12 Addressing Mode
Besides 7-bit addressing, the ESP32-C3 I2C controller also supports 10-bit addressing and double addressing.
10-bit addressing can be mixed with 7-bit addressing.
Define the slave address as SLV_ADDR. In 7-bit addressing mode, the slave address is SLV_ADDR[6:0]; in 10-bit
A
addressing mode, the slave address is SLV_ADDR[9:0].
In 7-bit addressing mode, the master only needs to send one byte of address, which comprises SLV_ADDR[6:0]
and a R/W bit. In 7-bit addressing mode, there is a special case called general call addressing (broadcast). It is
IN
enabled by setting I2C_ADDR_BROADCASTING_EN in a slave. When the slave receives the general call address
(0x00) from the master and the R/W bit followed is 0, it responds to the master regardless of its own
address.
IM
In 10-bit addressing mode, the master needs to send two bytes of address. The first byte is
slave_addr_first_7bits followed by a R/W bit, and slave_addr_first_7bits should be configured as (0x78 |
SLV_ADDR[9:8]). The second byte is slave_addr_second_byte, which should be configured as SLV_ADDR[7:0].
The slave can enable 10-bit addressing by configuring I2C_ADDR_10BIT_EN. I2C_SLAVE_ADDR is used to
configure I2C slave address. Specifically, I2C_SLAVE_ADDR[14:7] should be configured as SLV_ADDR[7:0], and
EL
I2C_SLAVE_ADDR[6:0] should be configured as (0x78 | SLV_ADDR[9:8]). Since a 10-bit slave address has one
more byte than a 7-bit address, byte_num of the WRITE command and the number of bytes in the RAM increase
by one.
When working in slave mode, the I2C controller supports double addressing, where the first address is the
address of an I2C slave, and the second one is the slave’s memory address. When using double addressing,
PR
RAM must be accessed in non-FIFO mode. Double addressing is enabled by setting
I2C_FIFO_ADDR_CFG_EN.
23.4.13 R/W Bit Check in 10bit Addressing Mode
In 10-bit addressing mode, when I2C_ADDR_10BIT_RW_CHECK_EN is set to 1, the I2C controller performs a
check on the first byte, which consists of slave_addr_first_7bits and a R/W bit. When the R/W bit does not
indicate a WRITE operation, i.e. not in line with the I2C protocol, the data transfer ends. If the check feature is
not enabled, when the R/W bit does not indicate a WRITE, the data transfer still continues, but transfer failure
may occur.
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23.4.14 To Start the I2C Controller
To start the I2C controller in master mode, after configuring the controller to master mode and command
registers, write 1 to I2C_TRANS_START in order that the master starts to parse and execute command
sequences. The master always executes a command sequence starting from command register 0 to a STOP or
an END at the end. To execute another command sequence starting from command register 0, refresh
commands by writing 1 again to I2C_TRANS_START.
To start the I2C controller in slave mode, there are two ways:
• Set I2C_SLV_TX_AUTO_START_EN, and the slave starts automatic transfer upon an address match;
• Clear I2C_SLV_TX_AUTO_START_EN, and always set I2C_TRANS_START before transfer.
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23.5 Programming Example
This sections provides programming examples for typical communication scenarios. ESP32-C3 has one I2C
controller. For the convenience of description, I2C masters and slaves in all subsequent figures are ESP32-C3
I2C controllers. I2C master is referred to as I2Cmaster , and I2C slave is referred to as I2Cslave .
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23.5.1 I2Cmaster Writes to I2Cslave with a 7bit Address in One Command Sequence
23.5.1.1 Introduction
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Figure 237. I2Cmaster Writing to I2Cslave with a 7bit Address
Figure 23-7 shows how I2Cmaster writes N bytes of data to I2Cslave ’s RAM using 7-bit addressing. As shown in
figure 23-7 , the first byte in the RAM of I2Cmaster is a 7-bit I2Cslave address followed by a R/W bit. When the
R/W bit is 0, it indicates a WRITE operation. The remaining bytes are used to store data ready for transfer. The
cmd box contains related command sequences.
After the command sequence is configured and data in RAM is ready, I2Cmaster enables the controller and initiates
data transfer by setting the I2C_TRANS_START bit. The controller has four steps to take:
1. Wait for SCL to go high, to avoid SCL being used by other masters or slaves.
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2. Execute a RSTART command and send a START bit.
3. Execute a WRITE command by taking N+1 bytes from the RAM in order and send them to I2Cslave in the
same order. The first byte is the address of I2Cslave .
4. Send a STOP. Once the I2Cmaster transfers a STOP bit, an I2C_TRANS_COMPLETE_INT interrupt is
generated.
23.5.1.2 Configuration Example
1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0.
2. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
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3. Configure command registers of I2Cmaster .
Command register op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) RSTART — — — —
I2C_COMMAND1 (master) WRITE ack_value ack_exp 1 N+1
I2C_COMMAND2 (master) STOP — — — —
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4. Write I2Cslave address and data to be sent to TX RAM of I2Cmaster in either FIFO mode or non-FIFO mode
according to Section 23.4.10.
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5. Write address of I2Cslave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register.
6. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
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7. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start transfer.
8. I2Cslave compares the slave address sent by I2Cmaster with its own address in I2C_SLAVE_ADDR (slave).
When ack_check_en (master) in I2Cmaster ’s WRITE command is 1, I2Cmaster checks ACK value each time it
sends a byte. When ack_check_en (master) is 0, I2Cmaster does not check ACK value and take I2Cslave as a
matching slave by default.
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• Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2Cmaster
continues data transfer.
• Not match: If the received ACK value does not match ack_exp, I2Cmaster generates an I2C_NACK_INT
(master) interrupt and stops data transfer.
PR
9. I2Cmaster sends data, and checks ACK value or not according to ack_check_en (master).
10. If data to be sent (N) is larger than 32 bytes, TX RAM of I2Cmaster may wrap around in FIFO mode. For
details, please refer to Section 23.4.10.
11. If data to be received (N) is larger than 32 bytes, RX RAM of I2Cslave may wrap around in FIFO mode. For
details, please refer to Section 23.4.10.
If data to be received (N) is larger than 32 bytes, the other way is to enable clock stretching by setting the
I2C_SLAVE_SCL_STRETCH_EN (slave), and clearing I2C_RX_FULL_ACK_LEVEL. When RX RAM is full, an
I2C_SLAVE_STRETCH_INT (slave) interrupt is generated. In this way, I2Cslave can hold SCL low, in
exchange for more time to read data. After software has finished reading, you can set
I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR
(slave) to release the SCL line.
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12. After data transfer completes, I2Cmaster executes the STOP command, and generates an
I2C_TRANS_COMPLETE_INT (master) interrupt.
23.5.2 I2Cmaster Writes to I2Cslave with a 10bit Address in One Command Sequence
23.5.2.1 Introduction
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Figure 238. I2Cmaster Writing to a Slave with a 10bit Address
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Figure 23-8 shows how I2Cmaster writes N bytes of data using 10-bit addressing to an I2C slave. The
configuration and transfer process is similar to what is described in 23.5.1, except that a 10-bit I2Cslave address is
formed from two bytes. Since a 10-bit I2Cslave address has one more byte than a 7-bit I2Cslave address,
byte_num and length of data in TX RAM increase by 1 accordingly.
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23.5.2.2 Configuration Example
1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0.
2. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
3. Configure command registers of I2Cmaster .
PR
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) RSTART — — — —
I2C_COMMAND1 (master) WRITE ack_value ack_exp 1 N+2
I2C_COMMAND2 (master) STOP — — — —
4. Configure I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) as I2Cslave ’s 10-bit address, and set
I2C_ADDR_10BIT_EN (slave) to 1 to enable 10-bit addressing.
5. Write I2Cslave address and data to be sent to TX RAM of I2Cmaster . The first byte of I2Cslave address
comprises ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a R/W bit. The second byte of I2Cslave address is
I2C_SLAVE_ADDR[7:0]. These two bytes are followed by data to be sent in FIFO or non-FIFO mode.
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6. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
7. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start transfer.
8. I2Cslave compares the slave address sent by I2Cmaster with its own address in I2C_SLAVE_ADDR (slave).
When ack_check_en (master) in I2Cmaster ’s WRITE command is 1, I2Cmaster checks ACK value each time it
sends a byte. When ack_check_en (master) is 0, I2Cmaster does not check ACK value and take I2Cslave as
matching slave by default.
• Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2Cmaster
continues data transfer.
• Not match: If the received ACK value does not match ack_exp, I2Cmaster generates an I2C_NACK_INT
(master) interrupt and stops data transfer.
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9. I2Cmaster sends data, and checks ACK value or not according to ack_check_en (master).
10. If data to be sent is larger than 32 bytes, TX RAM of I2Cmaster may wrap around in FIFO mode. For details,
please refer to Section 23.4.10.
11. If data to be received is larger than 32 bytes, RX RAM of I2Cslave may wrap around in FIFO mode. For
A
details, please refer to Section 23.4.10.
If data to be received is larger than 32 bytes, the other way is to enable clock stretching by setting
I2C_SLAVE_SCL_STRETCH_EN (slave), and clearing I2C_RX_FULL_ACK_LEVEL to 0. When RX RAM is
IN
full, an I2C_SLAVE_STRETCH_INT (slave) interrupt is generated. In this way, I2Cslave can hold SCL low, in
exchange for more time to read data. After software has finished reading, you can set
I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR
(slave) to release the SCL line.
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12. After data transfer completes, I2Cmaster executes the STOP command, and generates an
I2C_TRANS_COMPLETE_INT (master) interrupt.
EL
PR
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23.5.3 I2Cmaster Writes to I2Cslave with Two 7bit Addresses in One Command Sequence
23.5.3.1 Introduction
A RY
Figure 239. I2Cmaster Writing to I2Cslave with Two 7bit Addresses
IN
Figure 23-9 shows how I2Cmaster writes N bytes of data to I2Cslave ’s RAM using 7-bit double addressing. The
configuration and transfer process is similar to what is described in Section 23.5.1, except that in 7-bit double
addressing mode I2Cmaster sends two 7-bit addresses. The first address is the address of an I2C slave, and the
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second one is I2Cslave ’s memory address (i.e. addrM in Figure 23-9). When using double addressing, RAM must
be accessed in non-FIFO mode. The I2C slave put received byte0 ~ byte(N-1) into its RAM in an order staring
from addrM. The RAM is overwritten every 32 bytes.
23.5.3.2 Configuration Example
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1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0.
2. Set I2C_FIFO_ADDR_CFG_EN (slave) to 1 to enable double addressing mode.
3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
PR
4. Configure command registers of I2Cmaster .
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) RSTART — — — —
I2C_COMMAND1 (master) WRITE ack_value ack_exp 1 N+2
I2C_COMMAND2 (master) STOP — — — —
5. Write I2Cslave address and data to be sent to TX RAM of I2Cmaster in FIFO or non-FIFO mode.
6. Write address of I2Cslave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register.
7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
8. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start transfer.
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9. I2Cslave compares the slave address sent by I2Cmaster with its own address in I2C_SLAVE_ADDR (slave).
When ack_check_en (master) in I2Cmaster ’s WRITE command is 1, I2Cmaster checks ACK value each time it
sends a byte. When ack_check_en (master) is 0, I2Cmaster does not check ACK value and take I2Cslave as
matching slave by default.
• Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2Cmaster
continues data transfer.
• Not match: If the received ACK value does not match ack_exp, I2Cmaster generates an I2C_NACK_INT
(master) interrupt and stops data transfer.
10. I2Cslave receives the RX RAM address sent by I2Cmaster and adds the offset.
11. I2Cmaster sends data, and checks ACK value or not according to ack_check_en (master).
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12. If data to be sent is larger than 32 bytes, TX RAM of I2Cmaster may wrap around in FIFO mode. For details,
please refer to Section 23.4.10.
13. If data to be received is larger than 32 bytes, you may enable clock stretching by setting
I2C_SLAVE_SCL_STRETCH_EN (slave), and clearing I2C_RX_FULL_ACK_LEVEL to 0. When RX RAM is
full, an I2C_SLAVE_STRETCH_INT (slave) interrupt is generated. In this way, I2Cslave can hold SCL low, in
A
exchange for more time to read data. After software has finished reading, you can set
I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR
(slave) to release the SCL line.
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14. After data transfer completes, I2Cmaster executes the STOP command, and generates an
I2C_TRANS_COMPLETE_INT (master) interrupt.
IM
EL
PR
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23.5.4 I2Cmaster Writes to I2Cslave with a 7bit Address in Multiple Command Sequences
23.5.4.1 Introduction
A RY
IN
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Figure 2310. I2Cmaster Writing to I2Cslave with a 7bit Address in Multiple Sequences
Given that the I2C Controller RAM holds only 32 bytes, when data are too large to be processed even by the
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wrapped RAM, it is advised to transmit them in multiple command sequences. At the end of every command
sequence is an END command. When the controller executes this END command to pull SCL low, software
refreshes command sequence registers and the RAM for next the transfer.
Figure 23-10 shows how I2Cmaster writes to an I2C slave in two or three segments as an example. For the first
segment, the CMD_Controller registers are configured as shown in Segment0. Once data in I2Cmaster ’s RAM is
ready and I2C_TRANS_START is set, I2Cmaster initiates data transfer. After executing the END command,
I2Cmaster turns off the SCL clock and pulls SCL low to reserve the bus. Meanwhile, the controller generates an
I2C_END_DETECT_INT interrupt.
For the second segment, after detecting the I2C_END_DETECT_INT interrupt, software refreshes the
CMD_Controller registers, reloads the RAM and clears this interrupt, as shown in Segment1. If cmd1 in the
second segment is a STOP, then data is transmitted to I2Cslave in two segments. I2Cmaster resumes data transfer
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after I2C_TRANS_START is set, and terminates the transfer by sending a STOP bit.
For the third segment, after the second data transfer finishes and an I2C_END_DETECT_INT is detected, the
CMD_Controller registers of I2Cmaster are configured as shown in Segment2. Once I2C_TRANS_START is set,
I2Cmaster generates a STOP bit and terminates the transfer.
Note that other I2Cmaster s will not transact on the bus between two segments. The bus is only released after a
STOP signal is sent. The I2C controller can be reset by setting I2C_FSM_RST field at any time. This field will later
be cleared automatically by hardware.
23.5.4.2 Configuration Example
1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0.
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2. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
3. Configure command registers of I2Cmaster .
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) RSTART — — — —
A
I2C_COMMAND1 (master) WRITE ack_value ack_exp 1 N+1
I2C_COMMAND2 (master) END — IN — — —
4. Write I2Cslave address and data to be sent to TX RAM of I2Cmaster in either FIFO mode or non-FIFO mode
according to Section 23.4.10.
5. Write address of I2Cslave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register
IM
6. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
7. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start transfer.
8. I2Cslave compares the slave address sent by I2Cmaster with its own address in I2C_SLAVE_ADDR (slave).
When ack_check_en (master) in I2Cmaster ’s WRITE command is 1, I2Cmaster checks ACK value each time it
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sends a byte. When ack_check_en (master) is 0, I2Cmaster does not check ACK value and take I2Cslave as
matching slave by default.
• Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2Cmaster
continues data transfer.
PR
• Not match: If the received ACK value does not match ack_exp, I2Cmaster generates an I2C_NACK_INT
(master) interrupt and stops data transfer.
9. I2Cmaster sends data, and checks ACK value or not according to ack_check_en (master).
10. After the I2C_END_DETECT_INT (master) interrupt is generated, set I2C_END_DETECT_INT_CLR (master)
to 1 to clear this interrupt.
11. Update I2Cmaster ’s command registers.
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) WRITE ack_value ack_exp 1 M
I2C_COMMAND1 (master) END/STOP — — — —
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12. Write M bytes of data to be sent to TX RAM of I2Cmaster in FIFO or non-FIFO mode.
13. Write 1 to I2C_TRANS_START (master) bit to start transfer and repeat step 9.
14. If the command is a STOP, I2C stops transfer and generates an I2C_TRANS_COMPLETE_INT (master)
interrupt.
15. If the command is an END, repeat step 10.
16. Update I2Cmaster ’s command registers.
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND1 (master) STOP — — — —
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17. Write 1 to I2C_TRANS_START (master) bit to start transfer.
18. I2Cmaster executes the STOP command and generates an I2C_TRANS_COMPLETE_INT (master) interrupt.
23.5.5 I2Cmaster Reads I2Cslave with a 7bit Address in One Command Sequence
23.5.5.1 Introduction
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IN
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Figure 2311. I2Cmaster Reading I2Cslave with a 7bit Address
Figure 23-11 shows how I2Cmaster reads N bytes of data from an I2C slave using 7-bit addressing. cmd1 is a
WRITE command, and when this command is executed I2Cmaster sends I2Cslave address. The byte sent
comprises a 7-bit I2Cslave address and a R/W bit. When the R/W bit is 1, it indicates a READ operation. If the
address of an I2C slave matches the sent address, this matching slave starts sending data to I2Cmaster . I2Cmaster
generates acknowledgements according to ack_value defined in the READ command upon receiving a
byte.
As illustrated in Figure 23-11, I2Cmaster executes two READ commands: it generates ACKs for (N-1) bytes of data
in cmd2, and a NACK for the last byte of data in cmd 3. This configuration may be changed as required.
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I2Cmaster writes received data into the controller RAM from addr0, whose original content (a I2Cslave address and
a R/W bit) is overwritten by byte0 marked red in Figure 23-11.
23.5.5.2 Configuration Example
1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0.
2. We recommend setting I2C_SLAVE_SCL_STRETCH_EN (slave) to 1, so that SCL can be held low for more
processing time when I2Cslave needs to send data. If this bit is not set, software should write data to be
sent to I2Cslave ’s TX RAM before I2Cmaster initiates transfer. Configuration below is applicable to scenario
where I2C_SLAVE_SCL_STRETCH_EN (slave) is 1.
3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
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4. Configure command registers of I2Cmaster .
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) RSTART — — — —
I2C_COMMAND1 (master) WRITE 0 0 1 1
A
I2C_COMMAND2 (master) READ 0 0 1 N-1
I2C_COMMAND3 (master) READ 1 0 1 1
I2C_COMMAND4 (master) STOP — — — —
IN
5. Write I2Cslave address to TX RAM of I2Cmaster in either FIFO mode or non-FIFO mode according to Section
23.4.10.
6. Write address of I2Cslave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register.
IM
7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
8. Write 1 to I2C_TRANS_START (master) bit to start I2Cmaster ’s transfer.
9. Start I2Cslave ’s transfer according to Section 23.4.14.
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10. I2Cslave compares the slave address sent by I2Cmaster with its own address in I2C_SLAVE_ADDR (slave).
When ack_check_en (master) in I2Cmaster ’s WRITE command is 1, I2Cmaster checks ACK value each time it
sends a byte. When ack_check_en (master) is 0, I2Cmaster does not check ACK value and take I2Cslave as
matching slave by default.
PR
• Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2Cmaster
continues data transfer.
• Not match: If the received ACK value does not match ack_exp, I2Cmaster generates an I2C_NACK_INT
(master) interrupt and stops data transfer.
11. After I2C_SLAVE_STRETCH_INT (slave) is generated, the I2C_STRETCH_CAUSE bit is 0. The I2Cslave
address matches the address sent over SDA, and I2Cslave needs to send data.
12. Write data to be sent to TX RAM of I2Cslave according to Section 23.4.10.
13. Set I2C_SLAVE_SCL_STRETCH_CLR (slave) to 1 to release SCL.
14. I2Cslave sends data, and I2Cmaster checks ACK value or not according to ack_check_en (master) in the
READ command.
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15. If data to be read by I2Cmaster is larger than 32 bytes, an I2C_SLAVE_STRETCH_INT (slave) interrupt will be
generated when TX RAM of I2Cslave becomes empty. In this way, I2Cslave can hold SCL low, so that
software has more time to pad data in TX RAM of I2Cslave and read data in RX RAM of I2Cmaster . After
software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt,
and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line.
16. After I2Cmaster has received the last byte of data, set ack_value (master) to 1. I2Cslave will stop transfer once
receiving the I2C_NACK_INT interrupt.
17. After data transfer completes, I2Cmaster executes the STOP command, and generates an
I2C_TRANS_COMPLETE_INT (master) interrupt.
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23.5.6 I2Cmaster Reads I2Cslave with a 10bit Address in One Command Sequence
23.5.6.1 Introduction
A
IN
IM
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Figure 2312. I2Cmaster Reading I2Cslave with a 10bit Address
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Figure 23-12 shows how I2Cmaster reads data from an I2C slave using 10-bit addressing. Unlike 7-bit addressing,
in 10-bit addressing the WRITE command of the I2Cmaster is formed from two bytes, and correspondingly TX
RAM of this master stores a 10-bit address of two bytes. The R/W bit in the first byte is 0, which indicates a
WRITE operation. After a RSTART condition, I2Cmaster sends the first byte of address again to read data from
I2Cslave , but the R/W bit is 1, which indicates a READ operation. The two address bytes can be configured as
described in Section 23.5.2.
23.5.6.2 Configuration Example
1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0.
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2. We recommend setting I2C_SLAVE_SCL_STRETCH_EN (slave) to 1, so that SCL can be held low for more
processing time when I2Cslave needs to send data. If this bit is not set, software should write data to be
sent to I2Cslave ’s TX RAM before I2Cmaster initiates transfer. Configuration below is applicable to scenario
where I2C_SLAVE_SCL_STRETCH_EN (slave) is 1.
3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
4. Configure command registers of I2Cmaster .
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) RSTART — — — —
I2C_COMMAND1 (master) WRITE 0 0 1 2
I2C_COMMAND2 (master) RSTART — — — —
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I2C_COMMAND3 (master) WRITE 0 0 1 1
I2C_COMMAND4 (master) READ 0 0 1 N-1
I2C_COMMAND5 (master) READ 1 0 1 1
I2C_COMMAND6 (master) STOP — — — —
A
5. Configure I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) as I2Cslave ’s 10-bit address, and set
I2C_ADDR_10BIT_EN (slave) to 1 to enable 10-bit addressing.
IN
6. Write I2Cslave address and data to be sent to TX RAM of I2Cmaster in either FIFO or non-FIFO mode. The first
byte of address comprises ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a R/W bit, which is 1 and indicates a
WRITE operation. The second byte of address is I2C_SLAVE_ADDR[7:0]. The third byte is ((0x78 |
I2C_SLAVE_ADDR[9:8])«1) and a R/W bit, which is 1 and indicates a READ operation.
IM
7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
8. Write 1 to I2C_TRANS_START (master) to start I2Cmaster ’s transfer.
9. Start I2Cslave ’s transfer according to Section 23.4.14.
10. I2Cslave compares the slave address sent by I2Cmaster with its own address in I2C_SLAVE_ADDR (slave).
EL
When ack_check_en (master) in I2Cmaster ’s WRITE command is 1, I2Cmaster checks ACK value each time it
sends a byte. When ack_check_en (master) is 0, I2Cmaster does not check ACK value and take I2Cslave as
matching slave by default.
• Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2Cmaster
continues data transfer.
PR
• Not match: If the received ACK value does not match ack_exp, I2Cmaster generates an I2C_NACK_INT
(master) interrupt and stops data transfer.
11. I2Cmaster sends a RSTART and the third byte in TX RAM, which is ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a
R/W bit that indicates READ.
12. I2Cslave repeats step 10. If its address matches the address sent by I2Cmaster , I2Cslave proceed on to the
next steps.
13. After I2C_SLAVE_STRETCH_INT (slave) is generated, the I2C_STRETCH_CAUSE bit is 0. The I2Cslave
address matches the address sent over SDA, and I2Cslave needs to send data.
14. Write data to be sent to TX RAM of I2Cslave in either FIFO mode or non-FIFO mode according to Section
23.4.10.
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15. Set I2C_SLAVE_SCL_STRETCH_CLR (slave) to 1 to release SCL.
16. I2Cslave sends data, and I2Cmaster checks ACK value or not according to ack_check_en (master) in the
READ command.
17. If data to be read by I2Cmaster is larger than 32 bytes, an I2C_SLAVE_STRETCH_INT (slave) interrupt will be
generated when TX RAM of I2Cslave becomes empty. In this way, I2Cslave can hold SCL low, so that
software has more time to pad data in TX RAM of I2Cslave and read data in RX RAM of I2Cmaster . After
software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt,
and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line.
18. After I2Cmaster has received the last byte of data, set ack_value (master) to 1. I2Cslave will stop transfer once
receiving the I2C_NACK_INT interrupt.
RY
19. After data transfer completes, I2Cmaster executes the STOP command, and generates an
I2C_TRANS_COMPLETE_INT (master) interrupt.
23.5.7 I2Cmaster Reads I2Cslave with Two 7bit Addresses in One Command Sequence
23.5.7.1 Introduction
A
IN
IM
EL
PR
Figure 2313. I2Cmaster Reading N Bytes of Data from addrM of I2Cslave with a 7bit Address
Figure 23-13 shows how I2Cmaster reads data from specified addresses in an I2C slave. I2Cmaster sends two bytes
of addresses: the first byte is a 7-bit I2Cslave address followed by a R/W bit, which is 0 and indicates a WRITE;
the second byte is I2Cslave ’s memory address. After a RSTART condition, I2Cmaster sends the first byte of address
again, but the R/W bit is 1 which indicates a READ. Then, I2Cmaster reads data starting from addrM.
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23.5.7.2 Configuration Example
1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0.
2. We recommend setting I2C_SLAVE_SCL_STRETCH_EN (slave) to 1, so that SCL can be held low for more
processing time when I2Cslave needs to send data. If this bit is not set, software should write data to be
sent to I2Cslave ’s TX RAM before I2Cmaster initiates transfer. Configuration below is applicable to scenario
where I2C_SLAVE_SCL_STRETCH_EN (slave) is 1.
3. Set I2C_FIFO_ADDR_CFG_EN (slave) to 1 to enable double addressing mode.
4. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
5. Configure command registers of I2Cmaster .
RY
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) RSTART — — — —
I2C_COMMAND1 (master) WRITE 0 0 1 2
I2C_COMMAND2 (master) RSTART — — — —
I2C_COMMAND3 (master) WRITE 0 0 1 1
A
I2C_COMMAND4 (master) READ 0 0 1 N-1
I2C_COMMAND5 (master) READ 1 0 1 1
I2C_COMMAND6 (master) STOP — — — —
IN
6. Configure I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register as I2Cslave ’s 7-bit address,
and set I2C_ADDR_10BIT_EN (slave) to 0 to enable 7-bit addressing.
IM
7. Write I2Cslave address and data to be sent to TX RAM of I2Cmaster in either FIFO or non-FIFO mode
according to Section 23.4.10. The first byte of address comprises ( I2C_SLAVE_ADDR[6:0])«1) and a R/W
bit, which is 0 and indicates a WRITE. The second byte of address is memory address M of I2Cslave . The
third byte is ( I2C_SLAVE_ADDR[6:0])«1) and a R/W bit, which is 1 and indicates a READ.
EL
8. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
9. Write 1 to I2C_TRANS_START (master) and I2C_TRANS_START (slave) to start I2Cmaster ’s transfer.
10. Start I2Cslave ’s transfer according to Section 23.4.14.
11. I2Cslave compares the slave address sent by I2Cmaster with its own address in I2C_SLAVE_ADDR (slave).
PR
When ack_check_en (master) in I2Cmaster ’s WRITE command is 1, I2Cmaster checks ACK value each time it
sends a byte. When ack_check_en (master) is 0, I2Cmaster does not check ACK value and take I2Cslave as
matching slave by default.
• Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2Cmaster
continues data transfer.
• Not match: If the received ACK value does not match ack_exp, I2Cmaster generates an I2C_NACK_INT
(master) interrupt and stops data transfer.
12. I2Cslave receives memory address sent by I2Cmaster and adds the offset.
13. I2Cmaster sends a RSTART and the third byte in TX RAM, which is ((0x78 | I2C_SLAVE_ADDR[9:8])«1) and a
R bit.
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14. I2Cslave repeats step 11. If its address matches the address sent by I2Cmaster , I2Cslave proceed on to the
next steps.
15. After I2C_SLAVE_STRETCH_INT (slave) is generated, the I2C_STRETCH_CAUSE bit is 0. The I2Cslave
address matches the address sent over SDA, and I2Cslave needs to send data.
16. Write data to be sent to TX RAM of I2Cslave in either FIFO mode or non-FIFO mode according to Section
23.4.10.
17. Set I2C_SLAVE_SCL_STRETCH_CLR (slave) to 1 to release SCL.
18. I2Cslave sends data, and I2Cmaster checks ACK value or not according to ack_check_en (master) in the
READ command.
RY
19. If data to be read by I2Cmaster is larger than 32 bytes, an I2C_SLAVE_STRETCH_INT (slave) interrupt will be
generated when TX RAM of I2Cslave becomes empty. In this way, I2Cslave can hold SCL low, so that
software has more time to pad data in TX RAM of I2Cslave and read data in RX RAM of I2Cmaster . After
software has finished reading, you can set I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt,
and set I2C_SLAVE_SCL_STRETCH_CLR (slave) to release the SCL line.
20. After I2Cmaster has received the last byte of data, set ack_value (master) to 1. I2Cslave will stop transfer once
A
receiving the I2C_NACK_INT interrupt.
21. After data transfer completes, I2Cmaster executes the STOP command, and generates an
I2C_TRANS_COMPLETE_INT (master) interrupt.
IN
IM
EL
PR
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23.5.8 I2Cmaster Reads I2Cslave with a 7bit Address in Multiple Command Sequences
23.5.8.1 Introduction
A RY
IN
IM
EL
PR
Figure 2314. I2Cmaster Reading I2Cslave with a 7bit Address in Segments
Figure 23-14 shows how I2Cmaster reads (N+M) bytes of data from an I2C slave in two/three segments separated
by END commands. Configuration procedures are described as follows:
1. The procedures for Segment0 is similar to 23-11, except that the last command is an END.
2. Prepare data in the TX RAM of I2Cslave , and set I2C_TRANS_START to start data transfer. After executing
the END command, I2Cmaster refreshes command registers and the RAM as shown in Segment1, and
clears the corresponding I2C_END_DETECT_INT interrupt. If cmd2 in Segment1 is a STOP, then data is
read from I2Cslave in two segments. I2Cmaster resumes data transfer by setting I2C_TRANS_START and
terminates the transfer by sending a STOP bit.
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3. If cmd2 in Segment1 is an END, then data is read from I2Cslave in three segments. After the second data
transfer finishes and an I2C_END_DETECT_INT interrupt is detected, the cmd box is configured as shown
in Segment2. Once I2C_TRANS_START is set, I2Cmaster terminates the transfer by sending a STOP bit.
23.5.8.2 Configuration Example
1. Set I2C_MS_MODE (master) to 1, and I2C_MS_MODE (slave) to 0.
2. We recommend setting I2C_SLAVE_SCL_STRETCH_EN (slave) to 1, so that SCL can be held low for more
processing time when I2Cslave needs to send data. If this bit is not set, software should write data to be
sent to I2Cslave ’s TX RAM before I2Cmaster initiates transfer. Configuration below is applicable to scenario
where I2C_SLAVE_SCL_STRETCH_EN (slave) is 1.
RY
3. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
4. Configure command registers of I2Cmaster .
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) RSTART — — — —
A
I2C_COMMAND1 (master) WRITE 0 0 1 1
I2C_COMMAND2 (master) READ 0 0 1 N
I2C_COMMAND4 (master) END — — — —
IN
5. Write I2Cslave address to TX RAM of I2Cmaster in FIFO or non-FIFO mode.
6. Write address of I2Cslave to I2C_SLAVE_ADDR (slave) in I2C_SLAVE_ADDR_REG (slave) register.
IM
7. Write 1 to I2C_CONF_UPGATE (master) and I2C_CONF_UPGATE (slave) to synchronize registers.
8. Write 1 to I2C_TRANS_START (master) to start I2Cmaster ’s transfer.
9. Start I2Cslave ’s transfer according to Section 23.4.14.
10. I2Cslave compares the slave address sent by I2Cmaster with its own address in I2C_SLAVE_ADDR (slave).
EL
When ack_check_en (master) in I2Cmaster ’s WRITE command is 1, I2Cmaster checks ACK value each time it
sends a byte. When ack_check_en (master) is 0, I2Cmaster does not check ACK value and take I2Cslave as
matching slave by default.
• Match: If the received ACK value matches ack_exp (master) (the expected ACK value), I2Cmaster
PR
continues data transfer.
• Not match: If the received ACK value does not match ack_exp, I2Cmaster generates an I2C_NACK_INT
(master) interrupt and stops data transfer.
11. After I2C_SLAVE_STRETCH_INT (slave) is generated, the I2C_STRETCH_CAUSE bit is 0. The I2Cslave
address matches the address sent over SDA, and I2Cslave needs to send data.
12. Write data to be sent to TX RAM of I2Cslave in either FIFO mode or non-FIFO mode according to Section
23.4.10.
13. Set I2C_SLAVE_SCL_STRETCH_CLR (slave) to 1 to release SCL.
14. I2Cslave sends data, and I2Cmaster checks ACK value or not according to ack_check_en (master) in the
READ command.
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15. If data to be read by I2Cmaster in one READ command (N or M) is larger than 32 bytes, an
I2C_SLAVE_STRETCH_INT (slave) interrupt will be generated when TX RAM of I2Cslave becomes empty. In
this way, I2Cslave can hold SCL low, so that software has more time to pad data in TX RAM of I2Cslave and
read data in RX RAM of I2Cmaster . After software has finished reading, you can set
I2C_SLAVE_STRETCH_INT_CLR (slave) to 1 to clear interrupt, and set I2C_SLAVE_SCL_STRETCH_CLR
(slave) to release the SCL line.
16. Once finishing reading data in the first READ command, I2Cmaster executes the END command and triggers
an I2C_END_DETECT_INT (master) interrupt, which is cleared by setting I2C_END_DETECT_INT_CLR
(master) to 1.
17. Update I2Cmaster ’s command registers using one of the following two methods:
RY
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) READ ack_value ack_exp 1 M
I2C_COMMAND1 (master) END — — — —
Or
A
Command registers op_code ack_value ack_exp ack_check_en byte_num
I2C_COMMAND0 (master) READ 0 0 1 M-1
I2C_COMMAND0 (master)
I2C_COMMAND1 (master)
READ
STOP
1
—
IN 0
—
1
—
1
—
18. Write M bytes of data to be sent to TX RAM of I2Cslave . If M is larger than 32, then repeat step 14 in FIFO or
IM
non-FIFO mode.
19. Write 1 to I2C_TRANS_START (master) bit to start transfer and repeat step 14.
20. If the last command is a STOP, then set ack_value (master) to 1 after I2Cmaster has received the last byte of
data. I2Cslave stops transfer upon the I2C_NACK_INT interrupt. I2Cmaster executes the STOP command to
EL
stop transfer and generates an I2C_TRANS_COMPLETE_INT (master) interrupt.
21. If the last command is an END, then repeat step 16 and proceed on to the next steps.
22. Update I2Cmaster ’s command registers.
Command registers op_code ack_value ack_exp ack_check_en byte_num
PR
I2C_COMMAND1 (master) STOP — — — —
23. Write 1 to I2C_TRANS_START (master) bit to start transfer.
24. I2Cmaster executes the STOP command to stop transfer, and generates an I2C_TRANS_COMPLETE_INT
(master) interrupt.
23.6 Interrupts
• I2C_SLAVE_STRETCH_INT: Generated when one of the four stretching events occurs in slave mode.
• I2C_DET_START_INT: Triggered when the master or the slave detects a START bit.
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• I2C_SCL_MAIN_ST_TO_INT: Triggered when the main state machine SCL_MAIN_FSM remains unchanged
for over I2C_SCL_MAIN_ST_TO_I2C[23:0] clock cycles.
• I2C_SCL_ST_TO_INT: Triggered when the state machine SCL_FSM remains unchanged for over
I2C_SCL_ST_TO_I2C[23:0] clock cycles.
• I2C_RXFIFO_UDF_INT: Triggered when the I2C controller reads RX FIFO via the APB bus, but RX FIFO is
empty.
• I2C_TXFIFO_OVF_INT: Triggered when the I2C controller writes TX FIFO via the APB bus, but TX FIFO is full.
• I2C_NACK_INT: Triggered when the ACK value received by the master is not as expected, or when the
ACK value received by the slave is 1.
RY
• I2C_TRANS_START_INT: Triggered when the I2C controller sends a START bit.
• I2C_TIME_OUT_INT: Triggered when SCL stays high or low for more than I2C_TIME_OUT_VALUE clock
cycles during data transfer.
• I2C_TRANS_COMPLETE_INT: Triggered when the I2C controller detects a STOP bit.
• I2C_MST_TXFIFO_UDF_INT: Triggered when TX FIFO of the master underflows.
A
• I2C_ARBITRATION_LOST_INT: Triggered when the SDA’s output value does not match its input value while
the master’s SCL is high.
IN
• I2C_BYTE_TRANS_DONE_INT: Triggered when the I2C controller sends or receives a byte.
• I2C_END_DETECT_INT: Triggered when op_code of the master indicates an END command and an END
condition is detected.
IM
• I2C_RXFIFO_OVF_INT: Triggered when RX FIFO of the I2C controller overflows.
• I2C_TXFIFO_WM_INT: I2C TX FIFO watermark interrupt. Triggered when I2C_FIFO_PRT_EN is 1 and the
pointers of TX FIFO are less than I2C_TXFIFO_WM_THRHD[4:0].
• I2C_RXFIFO_WM_INT: I2C RX FIFO watermark interrupt. Triggered when I2C_FIFO_PRT_EN is 1 and the
EL
pointers of RX FIFO are greater than I2C_RXFIFO_WM_THRHD[4:0].
PR
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23.7 Register Summary
The addresses in this section are relative to I2C Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
Name Description Address Access
Timing registers
I2C_SCL_LOW_PERIOD_REG Configures the low level width of SCL 0x0000 R/W
Configures the hold time after a negative SCL
I2C_SDA_HOLD_REG 0x0030 R/W
edge
Configures the sample time after a positive SCL
I2C_SDA_SAMPLE_REG 0x0034 R/W
edge
RY
I2C_SCL_HIGH_PERIOD_REG Configures the high level width of SCL 0x0038 R/W
Configures the delay between the SDA and
I2C_SCL_START_HOLD_REG 0x0040 R/W
SCL negative edge for a START condition
Configures the delay between the positive edge
I2C_SCL_RSTART_SETUP_REG 0x0044 R/W
of SCL and the negative edge of SDA
A
Configures the delay after the SCL clock edge
I2C_SCL_STOP_HOLD_REG 0x0048 R/W
for a STOP condition
Configures the delay between the SDA and
I2C_SCL_STOP_SETUP_REG 0x004C R/W
I2C_SCL_ST_TIME_OUT_REG
IN
SCL positive edge for a STOP condition
SCL status timeout register 0x0078 R/W
I2C_SCL_MAIN_ST_TIME_OUT_REG SCL main status timeout register 0x007C R/W
Configuration registers
IM
I2C_CTR_REG Transmission configuration register 0x0004 varies
I2C_TO_REG Timeout control register 0x000C R/W
I2C_SLAVE_ADDR_REG Slave address configuration register 0x0010 R/W
I2C_FIFO_CONF_REG FIFO configuration register 0x0018 R/W
I2C_FILTER_CFG_REG SCL and SDA filter configuration register 0x0050 R/W
EL
I2C_CLK_CONF_REG I2C clock configuration register 0x0054 R/W
I2C_SCL_SP_CONF_REG Power configuration register 0x0080 varies
I2C_SCL_STRETCH_CONF_REG Configures SCL clock stretching 0x0084 varies
Status registers
I2C_SR_REG Describes I2C work status 0x0008 RO
PR
I2C_FIFO_ST_REG FIFO status register 0x0014 RO
I2C_DATA_REG Stores value of RX FIFO data 0x001C RO
Interrupt registers
I2C_INT_RAW_REG Raw interrupt status 0x0020 R/SS/WTC
I2C_INT_CLR_REG Interrupt clear bits 0x0024 WT
I2C_INT_ENA_REG Interrupt enable bits 0x0028 R/W
I2C_INT_STATUS_REG Status of captured I2C communication events 0x002C RO
Command registers
I2C_COMD0_REG I2C command register 0 0x0058 varies
I2C_COMD1_REG I2C command register 1 0x005C varies
I2C_COMD2_REG I2C command register 2 0x0060 varies
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Name Description Address Access
I2C_COMD3_REG I2C command register 3 0x0064 varies
I2C_COMD4_REG I2C command register 4 0x0068 varies
I2C_COMD5_REG I2C command register 5 0x006C varies
I2C_COMD6_REG I2C command register 6 0x0070 varies
I2C_COMD7_REG I2C command register 7 0x0074 varies
Version register
I2C_DATE_REG Version control register 0x00F8 R/W
A RY
IN
IM
EL
PR
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23.8 Registers
The addresses in this section are relative to I2C Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 23.1. I2C_SCL_LOW_PERIOD_REG (0x0000)
D
IO
ER
_P
W
LO
_
d)
CL
ve
_S
ser
C
(re
I2
31 9 8 0
RY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SCL_LOW_PERIOD This field is used to configure how long SCL remains low in master mode,
in I2C module clock cycles. (R/W)
A
Register 23.2. I2C_SDA_HOLD_REG (0x0030)
E
IN
IM
_T
LD
O
_H
d)
DA
ve
_S
r
se
C
(re
I2
31 9 8 0
IM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SDA_HOLD_TIME This field is used to configure the time to hold the data after the falling edge
of SCL, in I2C module clock cycles. (R/W)
EL
Register 23.3. I2C_SDA_SAMPLE_REG (0x0034)
E
M
TI
E_
PL
PR
M
SA
A_
d)
ve
SD
r
se
C_
(re
I2
31 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SDA_SAMPLE_TIME This field is used to configure how long SDA is sampled, in I2C module
clock cycles. (R/W)
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Register 23.4. I2C_SCL_HIGH_PERIOD_REG (0x0038)
D
IO
ER
D
P
IO
H_
ER
G
HI
P
H_
T_
AI
G
HI
W
L_
_
d)
CL
ve
SC
_S
er
C_
s
C
(re
I2
I2
31 16 15 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SCL_HIGH_PERIOD This field is used to configure how long SCL remains high in master mode,
RY
in I2C module clock cycles. (R/W)
I2C_SCL_WAIT_HIGH_PERIOD This field is used to configure the SCL_FSM’s waiting period for SCL
high level in master mode, in I2C module clock cycles. (R/W)
A
Register 23.5. I2C_SCL_START_HOLD_REG (0x0040)
E
M
TI
_
IN
LD
HO
T_
AR
ST
L_
)
ed
C
rv
_S
se
C
(re
I2
IM
31 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 Reset
I2C_SCL_START_HOLD_TIME This field is used to configure the time between the falling edge of
SDA and the falling edge of SCL for a START condition, in I2C module clock cycles. (R/W)
EL
Register 23.6. I2C_SCL_RSTART_SETUP_REG (0x0044)
E
M
TI
P_
PR
TU
SE
R T_
TA
RS
L_
)
ed
SC
rv
se
C_
(re
I2
31 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 Reset
I2C_SCL_RSTART_SETUP_TIME This field is used to configure the time between the rising edge of
SCL and the falling edge of SDA for a RSTART condition, in I2C module clock cycles. (R/W)
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Register 23.7. I2C_SCL_STOP_HOLD_REG (0x0048)
E
IM
_T
LD
HO
P_
O
_ST
d)
CL
ve
_S
ser
C
(re
I2
31 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 Reset
I2C_SCL_STOP_HOLD_TIME This field is used to configure the delay after the STOP condition, in
I2C module clock cycles. (R/W)
RY
Register 23.8. I2C_SCL_STOP_SETUP_REG (0x004C)
E
M
TI
P_
A
TU
SE
P_
O
ST
L_
)
ed
C
IN
rv
_S
se
C
(re
I2
31 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 Reset
I2C_SCL_STOP_SETUP_TIME This field is used to configure the time between the rising edge of
IM
SCL and the rising edge of SDA, in I2C module clock cycles. (R/W)
Register 23.9. I2C_SCL_ST_TIME_OUT_REG (0x0078)
EL
C2
_I
O
_T
ST
L_
d)
e
SC
rv
se
C_
(re
I2
PR
31 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 Reset
I2C_SCL_ST_TO_I2C The maximum time that SCL_FSM remains unchanged. It should be no more
than 23. (R/W)
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23 I2C Controller (I2C)
Register 23.10. I2C_SCL_MAIN_ST_TIME_OUT_REG (0x007C)
2C
_I
TO
ST_
N_
AI
_M
d)
CL
ve
S
er
C_
s
(re
I2
31 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 Reset
I2C_SCL_MAIN_ST_TO_I2C The maximum time that SCL_MAIN_FSM remains unchanged. It
should be no more than 23. (R/W)
A RY
IN
IM
EL
PR
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23 I2C Controller (I2C)
Register 23.11. I2C_CTR_REG (0x0004)
_E EN
N
_
C_ M P _ H E
N
C_ B T E R K
I2 FS _U TO _C G_
I2 AR RS AT TA EC
F U W N
FO E EV L
RC _OU EL
A_ RC L_L VE
C_ N A R TI
I2 O X_ IT_ AS
UT
SD FO C LE
E_ T
N
_ G S
_E
C_ _ 0B C
C_ L_ _S _
O
C_ AN _F ST
C_ _F E T
C_ _ ST T
I2 SLV _1 AD
I2 SC LE CK
I2 X N N
I2 RX OD AR
I2 MS S_ RS
SB IR
IO
O
P A
I
C_ L F
C_ M _
C_ K_ T
C_ D R
I2 TX_ SB_
I2 CL RA
I2 SA ULL
I2 AD _B
M
T
T
R
R
C_ _L
d)
I
C_ D
ve
I2 AD
I2 R
C
T
r
se
C_
(re
I2
31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 Reset
I2C_SDA_FORCE_OUT 0: direct output; 1: open-drain output. (R/W)
RY
I2C_SCL_FORCE_OUT 0: direct output; 1: open-drain output. (R/W)
I2C_SAMPLE_SCL_LEVEL This bit is used to select the sampling mode. 0: samples SDA data on
the SCL high level; 1: samples SDA data on the SCL low level. (R/W)
I2C_RX_FULL_ACK_LEVEL This bit is used to configure the ACK value that need to be sent by
A
master when I2C_RXFIFO_CNT has reached the threshold. (R/W)
I2C_MS_MODE Set this bit to configure the I2C controller as an I2C Master. Clear this bit to configure
the I2C controller as a slave. (R/W)
IN
I2C_TRANS_START Set this bit to start sending the data in TX FIFO. (WT)
I2C_TX_LSB_FIRST This bit is used to control the order to send data. 0: sends data from the most
significant bit; 1: sends data from the least significant bit. (R/W)
IM
I2C_RX_LSB_FIRST This bit is used to control the order to receive data. 0: receives data from the
most significant bit; 1: receives data from the least significant bit. (R/W)
I2C_CLK_EN This field controls APB_CLK clock gating. 0: APB_CLK is gated to save power; 1:
EL
APB_CLK is always on. (R/W)
I2C_ARBITRATION_EN This is the enable bit for I2C bus arbitration function. (R/W)
I2C_FSM_RST This bit is used to reset the SCL_FSM. (WT)
I2C_CONF_UPGATE Synchronization bit. (WT)
PR
I2C_SLV_TX_AUTO_START_EN This is the enable bit for slave to send data automatically. (R/W)
I2C_ADDR_10BIT_RW_CHECK_EN This is the enable bit to check if the R/W bit of 10-bit addressing
is consistent with the I2C protocol. (R/W)
I2C_ADDR_BROADCASTING_EN This is the enable bit for 7-bit general call addressing. (R/W)
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23 I2C Controller (I2C)
Register 23.12. I2C_TO_REG (0x000C)
UE
L
N
VA
_E
_
UT
UT
O
O
E_
E_
d)
IM
IM
ve
T
er
C_
C_
s
(re
I2
I2
31 6 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 Reset
I2C_TIME_OUT_VALUE This field is used to configure the timeout for receiving a data bit in APB clock
cycles. (R/W)
RY
I2C_TIME_OUT_EN This is the enable bit for timeout control. (R/W)
Register 23.13. I2C_SLAVE_ADDR_REG (0x0010)
N
_E
A R
IT
DD
0B
_A
_1
E
DR
AV
)d
ve
AD
SL
er
C_
C_
s
(re
IN
I2
I2
31 30 15 14 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SLAVE_ADDR When the I2C controller is in slave mode, this field is used to configure the slave
IM
address. (R/W)
I2C_ADDR_10BIT_EN This field is used to enable the 10-bit addressing mode in master mode. (R/W)
EL
PR
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23 I2C Controller (I2C)
Register 23.14. I2C_FIFO_CONF_REG (0x0018)
HD
HD
N _E
HR
HR
_E FG
_T
_T
IF _C
I2 RX FO EN
T
I2 FIF IFO ST
NO _A S
M
M
NF DDR
C_ O _R
I _
C_ _F _R
_W
_W
C_ F T
O
I2 TX_ PR
FO
FO
_
d)
C_ O
FI
FI
ve
I2 FIF
RX
TX
er
C_
C_
C_
s
(re
I2
I2
I2
31 15 14 13 12 11 10 9 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0x4 0xb Reset
I2C_RXFIFO_WM_THRHD The watermark threshold of RX FIFO in non-FIFO mode. When
I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0],
RY
I2C_RXFIFO_WM_INT_RAW bit is valid. (R/W)
I2C_TXFIFO_WM_THRHD The watermark threshold of TX FIFO in non-FIFO mode. When
I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD[4:0],
I2C_TXFIFO_WM_INT_RAW bit is valid. (R/W)
I2C_NONFIFO_EN Set this bit to enable APB non-FIFO mode. (R/W)
A
I2C_FIFO_ADDR_CFG_EN When this bit is set to 1, the byte received after the I2C address byte
represents the offset address in the I2C Slave RAM. (R/W)
I2C_RX_FIFO_RST Set this bit to reset RX FIFO. (R/W)
IN
I2C_TX_FIFO_RST Set this bit to reset TX FIFO. (R/W)
I2C_FIFO_PRT_EN The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the
IM
valid bits and TX/RX FIFO overflow, underflow, full and empty interrupts. (R/W)
Register 23.15. I2C_FILTER_CFG_REG (0x0050)
EL
ES
ES
HR
HR
ER N
N
LT E
_T
_E
_T
FI R_
ER
ER
L_ LTE
LT
LT
SC _FI
FI
FI
A_
L_
)
ed
C_ A
SC
I2 SD
SD
rv
se
C_
C_
C_
(re
I2
I2
I2
PR
31 10 9 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Reset
I2C_SCL_FILTER_THRES When a pulse on the SCL input has smaller width than the value of this
field in I2C module clock cycles, the I2C controller ignores that pulse. (R/W)
I2C_SDA_FILTER_THRES When a pulse on the SDA input has smaller width than the value of this
field in I2C module clock cycles, the I2C controller ignores that pulse. (R/W)
I2C_SCL_FILTER_EN This is the filter enable bit for SCL. (R/W)
I2C_SDA_FILTER_EN This is the filter enable bit for SDA. (R/W)
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23 I2C Controller (I2C)
Register 23.16. I2C_CLK_CONF_REG (0x0054)
M
NU
EL E
_S IV
_A
V_
V_
LK CT
V
DI
DI
DI
SC _A
K_
K_
K_
C_ LK
d)
CL
CL
CL
ve
I2 SC
S
er
C_
C_
C_
s
C
(re
I2
I2
I2
I2
31 22 21 20 19 14 13 8 7 0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset
I2C_SCLK_DIV_NUM The integral part of the divisor. (R/W)
I2C_SCLK_DIV_A The numerator of the divisor’s fractional part. (R/W)
RY
I2C_SCLK_DIV_B The denominator of the divisor’s fractional part. (R/W)
I2C_SCLK_SEL The clock selection bit for the I2C controller. 0: XTAL_CLK; 1: FOSC_CLK. (R/W)
I2C_SCLK_ACTIVE The clock switch bit for the I2C controller. (R/W)
A
Register 23.17. I2C_SCL_SP_CONF_REG (0x0080)
IN
M
NU
EN
V_
V_
SL
SL
PD N
N
L_ _E
_E
T_
T_
SC _PD
RS
RS
L_
L_
d)
C_ A
ve
SC
SC
I2 SD
r
se
C_
C_
C_
(re
I2
I2
I2
IM
31 8 7 6 5 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SCL_RST_SLV_EN When the master is idle, set this bit to send out SCL pulses. The number of
pulses equals to I2C_SCL_RST_SLV_NUM[4:0]. (R/W/SC)
EL
I2C_SCL_RST_SLV_NUM Configures the pulses of SCL generated in master mode. Valid when
I2C_SCL_RST_SLV_EN is 1. (R/W)
I2C_SCL_PD_EN The power down enable bit for the I2C output SCL line. 0: Not power down; 1:
Power down. Set I2C_SCL_FORCE_OUT and I2C_SCL_PD_EN to 1 to stretch SCL low. (R/W)
PR
I2C_SDA_PD_EN The power down enable bit for the I2C output SDA line. 0: Not power down; 1:
Power down. Set I2C_SDA_FORCE_OUT and I2C_SDA_PD_EN to 1 to stretch SDA low. (R/W)
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23 I2C Controller (I2C)
Register 23.18. I2C_SCL_STRETCH_CONF_REG (0x0084)
H_ LR
RE H N
UM
EN
ST TC _E
TC _C
L_ RE TL
_N
E_ L_ CK VL
SC ST _C
AV SC _A _L
CT
SL E_ TE CK
TE
C_ AV Y A
O
I2 SL E_B TE_
PR
H_
C_ AV Y
I2 SL E_B
TC
RE
C_ AV
)
ed
ST
I2 SL
rv
se
C_
C_
(re
I2
I2
31 14 13 12 11 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_STRETCH_PROTECT_NUM Configures the time period to release the SCL line from stretching
RY
to avoid timing violation. Usually it should be larger than the SDA steup time. (R/W)
I2C_SLAVE_SCL_STRETCH_EN The enable bit for SCL clock stretching. 0: Disable; 1: Enable. The
SCL output line will be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and one of the
four stretching events occurs. The cause of stretching can be seen in I2C_STRETCH_CAUSE.
(R/W)
A
I2C_SLAVE_SCL_STRETCH_CLR Set this bit to clear SCL clock stretching. (WT)
I2C_SLAVE_BYTE_ACK_CTL_EN The enable bit for slave to control the level of the ACK bit. (R/W)
IN
I2C_SLAVE_BYTE_ACK_LVL Set the level of the ACK bit when I2C_SLAVE_BYTE_ACK_CTL_EN is
set. (R/W)
IM
EL
PR
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23 I2C Controller (I2C)
Register 23.19. I2C_SR_REG (0x0008)
T
AS
D
_L
SE
SE
E
T
AS
AT
se B_ SY ES
AU
ST
_L
(re AR BU DR
NT
NT
_C
N_
TE
SP RW
EC
T
C_ S D
_C
CH
_C
C_ d S
TA
I2 BU E_A
AI
I2 rve LO
_R
RE E_
O
_M
O
_S
ET
IF
_
F
C_ AV
C_ AV
)
d)
C_ )
)
ed
ed
ed
FI
CL
CL
TR
XF
ve
I2 SL
I2 SL
TX
rv
rv
R
_S
S
er
er
se
se
C_
C_
C_
C_
s
s
C
(re
(re
(re
(re
I2
I2
I2
I2
I2
I2
31 30 28 27 26 24 23 18 17 16 15 14 13 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0x3 0 0 0 0 0 0 0 0 0 Reset
I2C_RESP_REC The received ACK value in master mode or slave mode. 0: ACK; 1: NACK. (RO)
RY
I2C_SLAVE_RW When in slave mode, 0: master writes to slave; 1: master reads from slave. (RO)
I2C_ARB_LOST When the I2C controller loses control of the SCL line, this bit changes to 1. (RO)
I2C_BUS_BUSY 0: the I2C bus is in idle state; 1: the I2C bus is busy transferring data. (RO)
I2C_SLAVE_ADDRESSED When the I2C controller is in slave mode, and the address sent by the
A
master matches the address of the slave, this bit is at high level. (RO)
I2C_RXFIFO_CNT This field represents the number of data bytes to be sent. (RO) IN
I2C_STRETCH_CAUSE The cause of SCL clock stretching in slave mode. 0: stretching SCL low
when the master starts to read data; 1: stretching SCL low when TX FIFO is empty in slave mode;
2: stretching SCL low when RX FIFO is full in slave mode. (RO)
I2C_TXFIFO_CNT This field stores the number of data bytes received in RAM. (RO)
IM
I2C_SCL_MAIN_STATE_LAST This field indicates the status of the state machine. 0: idle; 1: address
shift; 2: ACK address; 3: receive data; 4: transmit data; 5: send ACK; 6: wait for ACK. (RO)
I2C_SCL_STATE_LAST This field indicates the status of the state machine used to produce SCL. 0:
idle; 1: start; 2: falling edge; 3: low; 4: rising edge; 5: high; 6: stop. (RO)
EL
PR
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23 I2C Controller (I2C)
Register 23.20. I2C_FIFO_ST_REG (0x0014)
T
IN
DR
DR
DR
DR
O
_P
AD
AD
AD
AD
W
_W
_W
_R
_R
_R
FO
O
O
E
IF
IF
IF
AV
d)
)
ed
I
XF
XF
XF
XF
ve
SL
rv
R
_T
T
er
se
C_
C_
C_
C_
s
C
(re
(re
I2
I2
I2
I2
I2
31 30 29 22 21 20 19 15 14 10 9 5 4 0
0 0 0 0 0 0 0 0 0 Reset
I2C_RXFIFO_RADDR This is the offset address of the APB reading from RX FIFO. (RO)
I2C_RXFIFO_WADDR This is the offset address of the I2C controller receiving data and writing to RX
RY
FIFO. (RO)
I2C_TXFIFO_RADDR This is the offset address of the I2C controller reading from TX FIFO. (RO)
I2C_TXFIFO_WADDR This is the offset address of APB bus writing to TX FIFO. (RO)
I2C_SLAVE_RW_POINT The received data in I2C slave mode. (RO)
A
Register 23.21. I2C_DATA_REG (0x001C)
IN
TA
DA
_R
d)
O
ve
F
FI
r
se
C_
(re
I2
IM
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_FIFO_RDATA Data read from RX FIFO. (RO)
EL
PR
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23 I2C Controller (I2C)
Register 23.22. I2C_INT_RAW_REG (0x0020)
AW
FI _W _IN _R T_ W
I2 RX DE NS OS T_R AW
RX O VF NT _IN A
W
W
C_ FI T _ AW AW
FO M T AW R
C_ IF O _I E _R
C_ L_ IN NT N W
C_ C O IN AW A
_L IN R
C_ FI TE _D T_ A
I2 NA O_ F_ _R T_R
I2 EN _TR ON F_ NT_
I2 AR TX MP RA AW
I2 SC MA _I H_I RA
I2 TXF O_ CT ON INT
I2 RX ST_ _ST _R _R
M T_ W
W
AW
NT W
_
T
C_ T C T_ _R
C_ IF U NT IN
I D I
C_ AN T IN A
_W _IN _RA
C_ TE T U _
W
C_ L_ R C T
C_ E ST W A
_I RA
I2 BY TRA O_ ETE
I2 TR _IN F_ T_R
I2 SC STA RET _IN
I2 TXF O_ O_I O_
I2 TIM S_ RA _R
_R
I2 MS S_ IN NT
T
T
I
L
C_ AN T T_
F L
C_ T_ T L
I2 DE E_S CA
I2 TR _OU AR
T
_
_
D
_ O
K V
_
A
C_ AV L
C_ B FI
I2 SL RA
E
F
_
d)
I
C_ N
C_ D
ve
I2 GE
er
_
s
C
(re
I2
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
I2C_RXFIFO_WM_INT_RAW The raw interrupt bit for the I2C_RXFIFO_WM_INT interrupt.
RY
(R/SS/WTC)
I2C_TXFIFO_WM_INT_RAW The raw interrupt bit for the I2C_TXFIFO_WM_INT interrupt.
(R/SS/WTC)
I2C_RXFIFO_OVF_INT_RAW The raw interrupt bit for the I2C_RXFIFO_OVF_INT interrupt.
A
(R/SS/WTC)
I2C_END_DETECT_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
(R/SS/WTC)
IN
I2C_BYTE_TRANS_DONE_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
(R/SS/WTC)
I2C_ARBITRATION_LOST_INT_RAW The raw interrupt bit for the I2C_ARBITRATION_LOST_INT in-
IM
terrupt. (R/SS/WTC)
I2C_MST_TXFIFO_UDF_INT_RAW The raw interrupt bit for the I2C_TRANS_COMPLETE_INT inter-
rupt. (R/SS/WTC)
I2C_TRANS_COMPLETE_INT_RAW The raw interrupt bit for the I2C_TRANS_COMPLETE_INT in-
EL
terrupt. (R/SS/WTC)
I2C_TIME_OUT_INT_RAW The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. (R/SS/WTC)
I2C_TRANS_START_INT_RAW The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
(R/SS/WTC)
PR
I2C_NACK_INT_RAW The raw interrupt bit for the I2C_SLAVE_STRETCH_INT interrupt. (R/SS/WTC)
I2C_TXFIFO_OVF_INT_RAW The raw interrupt bit for the I2C_TXFIFO_OVF_INT interrupt.
(R/SS/WTC)
I2C_RXFIFO_UDF_INT_RAW The raw interrupt bit for the I2C_RXFIFO_UDF_INT interrupt.
(R/SS/WTC)
Continued on the next page...
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23 I2C Controller (I2C)
Register 23.22. I2C_INT_RAW_REG (0x0020)
Continued from the previous page...
I2C_SCL_ST_TO_INT_RAW The raw interrupt bit for the I2C_SCL_ST_TO_INT interrupt.
(R/SS/WTC)
I2C_SCL_MAIN_ST_TO_INT_RAW The raw interrupt bit for the I2C_SCL_MAIN_ST_TO_INT inter-
rupt. (R/SS/WTC)
I2C_DET_START_INT_RAW The raw interrupt bit for the I2C_DET_START_INT interrupt.
(R/SS/WTC)
RY
I2C_SLAVE_STRETCH_INT_RAW The raw interrupt bit for the I2C_SLAVE_STRETCH_INT interrupt.
(R/SS/WTC)
I2C_GENERAL_CALL_INT_RAW The raw interrupt bit for the I2C_GENARAL_CALL_INT interrupt.
(R/SS/WTC)
A
IN
IM
EL
PR
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23 I2C Controller (I2C)
Register 23.23. I2C_INT_CLR_REG (0x0024)
LR
FI _W _IN _C T_ R
I2 RX DE NS OS T_C LR
RX O VF NT _IN L
R
FO M T LR C
R
C_ IF O _I E _C
C_ FI T _ LR LR
_L IN C
C_ C O IN LR L
C_ FI TE _D T_ L
C_ L_ IN NT N R
I2 NA O_ F_ _C T_C
I2 EN _TR ON F_ NT_
I2 TXF O_ CT ON INT
I2 SC MA _I H_I CL
I2 AR TX MP CLR LR
I2 RX ST_ _ST _C _C
M T_ R
R
LR
_
C_ T C T_ _C
T
NT R
C_ IF U NT IN
I D I
C_ AN T IN L
C_ TE T U _
_W _IN _CL
C_ L_ R C T
C_ E ST R L
_I CL
I2 BY TRA O_ ETE
I2 TR _IN F_ T_C
I2 SC STA RET _IN
I2 TXF O_ O_I O_
I2 TIM S_ CL _C
_C
I2 MS S_ IN NT
T
T
I
L
C_ AN T T_
F L
C_ T_ T L
I2 DE E_S CA
I2 TR _OU AR
T
_
_
D
_ O
K V
_
A
C_ AV L
C_ B FI
I2 SL RA
E
F
_
d)
I
C_ N
C_ D
ve
I2 GE
er
_
s
C
(re
I2
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RXFIFO_WM_INT_CLR Set this bit to clear the I2C_RXFIFO_WM_INT interrupt. (WT)
RY
I2C_TXFIFO_WM_INT_CLR Set this bit to clear the I2C_TXFIFO_WM_INT interrupt. (WT)
I2C_RXFIFO_OVF_INT_CLR Set this bit to clear the I2C_RXFIFO_OVF_INT interrupt. (WT)
I2C_END_DETECT_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. (WT)
A
I2C_BYTE_TRANS_DONE_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. (WT)
I2C_ARBITRATION_LOST_INT_CLR Set this bit to clear the I2C_ARBITRATION_LOST_INT inter-
rupt. (WT)
IN
I2C_MST_TXFIFO_UDF_INT_CLR Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
(WT)
IM
I2C_TRANS_COMPLETE_INT_CLR Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
(WT)
I2C_TIME_OUT_INT_CLR Set this bit to clear the I2C_TIME_OUT_INT interrupt. (WT)
I2C_TRANS_START_INT_CLR Set this bit to clear the I2C_TRANS_START_INT interrupt. (WT)
EL
I2C_NACK_INT_CLR Set this bit to clear the I2C_SLAVE_STRETCH_INT interrupt. (WT)
I2C_TXFIFO_OVF_INT_CLR Set this bit to clear the I2C_TXFIFO_OVF_INT interrupt. (WT)
I2C_RXFIFO_UDF_INT_CLR Set this bit to clear the I2C_RXFIFO_UDF_INT interrupt. (WT)
PR
I2C_SCL_ST_TO_INT_CLR Set this bit to clear the I2C_SCL_ST_TO_INT interrupt. (WT)
I2C_SCL_MAIN_ST_TO_INT_CLR Set this bit to clear the I2C_SCL_MAIN_ST_TO_INT interrupt.
(WT)
I2C_DET_START_INT_CLR Set this bit to clear the I2C_DET_START_INT interrupt. (WT)
I2C_SLAVE_STRETCH_INT_CLR Set this bit to clear the I2C_SLAVE_STRETCH_INT interrupt. (WT)
I2C_GENERAL_CALL_INT_CLR Set this bit for the I2C_GENARAL_CALL_INT interrupt. (WT)
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Register 23.24. I2C_INT_ENA_REG (0x0028)
A
FI _W _IN _E T_ A
I2 RX DE NS OS T_E NA
FO M T NA EN
RX O VF NT _IN N
A
A
T A A
C_ IF O _I E _E
C_ C O IN A N
_L IN E
C_ FI TE _D T_ N
C_ L_ IN NT N A
N
I2 EN _TR ON F_ NT_
I2 NA O_ F_ _EN T_E
I2 SC MA _I H_I EN
I2 TXF O_ CT ON INT
I2 AR TX MP EN NA
I2 RX ST_ _ST _EN _E
M T_ A
A
NA
_
T
NT A
C_ T C T_ _E
C_ IF U NT IN
I D I
C_ AN T IN N
_W _IN _EN
C_ TE T U _
C_ L_ R C T
C_ E ST A N
_I EN
A
I2 BY TRA O_ ETE
I2 SC STA RET _IN
I2 TR _IN F_ T_E
I2 TXF O_ O_I O_
I2 MS S_ IN NT
I2 TIM S_ EN _E
_E
T
I
L
C_ AN T T_
F L
C_ FI T _
C_ T_ T L
I2 DE E_S CA
I2 TR _OU AR
T
_
_
D
_ O
K V
_
A
C_ AV L
C_ B FI
I2 SL RA
E
F
_
d)
I
C_ N
C_ D
ve
I2 GE
er
_
s
C
(re
I2
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RXFIFO_WM_INT_ENA The interrupt enable bit for the I2C_RXFIFO_WM_INT interrupt. (R/W)
RY
I2C_TXFIFO_WM_INT_ENA The interrupt enable bit for the I2C_TXFIFO_WM_INT interrupt. (R/W)
I2C_RXFIFO_OVF_INT_ENA The interrupt enable bit for the I2C_RXFIFO_OVF_INT interrupt. (R/W)
I2C_END_DETECT_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. (R/W)
A
I2C_BYTE_TRANS_DONE_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT inter-
rupt. (R/W)
IN
I2C_ARBITRATION_LOST_INT_ENA The interrupt enable bit for the I2C_ARBITRATION_LOST_INT
interrupt. (R/W)
I2C_MST_TXFIFO_UDF_INT_ENA The interrupt enable bit for the I2C_TRANS_COMPLETE_INT in-
IM
terrupt. (R/W)
I2C_TRANS_COMPLETE_INT_ENA The interrupt enable bit for the I2C_TRANS_COMPLETE_INT
interrupt. (R/W)
I2C_TIME_OUT_INT_ENA The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. (R/W)
EL
I2C_TRANS_START_INT_ENA The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
(R/W)
I2C_NACK_INT_ENA The interrupt enable bit for the I2C_SLAVE_STRETCH_INT interrupt. (R/W)
I2C_TXFIFO_OVF_INT_ENA The interrupt enable bit for the I2C_TXFIFO_OVF_INT interrupt. (R/W)
PR
I2C_RXFIFO_UDF_INT_ENA The interrupt enable bit for the I2C_RXFIFO_UDF_INT interrupt. (R/W)
I2C_SCL_ST_TO_INT_ENA The interrupt enable bit for the I2C_SCL_ST_TO_INT interrupt. (R/W)
I2C_SCL_MAIN_ST_TO_INT_ENA The interrupt enable bit for the I2C_SCL_MAIN_ST_TO_INT in-
terrupt. (R/W)
I2C_DET_START_INT_ENA The interrupt enable bit for the I2C_DET_START_INT interrupt. (R/W)
I2C_SLAVE_STRETCH_INT_ENA The interrupt enable bit for the I2C_SLAVE_STRETCH_INT inter-
rupt. (R/W)
I2C_GENERAL_CALL_INT_ENA The interrupt enable bit for the I2C_GENARAL_CALL_INT interrupt.
(R/W)
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Register 23.25. I2C_INT_STATUS_REG (0x002C)
T
RX O VF NT _IN T
I2 RX DE NS OS T_S T
FO M T T S
C_ IF O _I E _S
_L IN S
T
FI _W _IN _S T_
C_ FI TE _D T_ T
T
I2 NA O_ F_ _S T_S
I2 EN _TR ON F_ NT_
I2 TXF O_ CT ON INT
I2 SC MA _I H_I ST
I2 RX ST_ _ST _ST _S
I2 AR TX MP ST T
_
T
C_ T C T_ _S
C_ IF U NT IN
I D I
C_ TE T U _
C_ L_ R C T
C_ AN T IN T
_W _IN _ST
C_ L_ IN NT N
T
_I ST
C_ C O IN T
I2 BY TRA O_ ETE
I2 SC STA RET _IN
I2 TR _IN F_ T_S
I2 TXF O_ O_I O_
I2 TIM S_ _ST _S
I2 MS S_ _IN INT
_S
M T_
T
T
NT
L
C_ AN T T_
F L
C_ FI T _
C_ T_ T L
I2 DE E_S CA
I2 TR _OU AR
T
_ O
K V
_
C_ E ST
A
C_ AV L
C_ B FI
I2 SL RA
E
F
_
d)
I
C_ N
C_ D
ve
I2 GE
er
_
s
C
(re
I2
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RXFIFO_WM_INT_ST The masked interrupt status bit for the I2C_RXFIFO_WM_INT interrupt.
RY
(RO)
I2C_TXFIFO_WM_INT_ST The masked interrupt status bit for the I2C_TXFIFO_WM_INT interrupt.
(RO)
I2C_RXFIFO_OVF_INT_ST The masked interrupt status bit for the I2C_RXFIFO_OVF_INT interrupt.
(RO)
A
I2C_END_DETECT_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
(RO)
IN
I2C_BYTE_TRANS_DONE_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT
interrupt. (RO)
I2C_ARBITRATION_LOST_INT_ST The masked interrupt status bit for the
IM
I2C_ARBITRATION_LOST_INT interrupt. (RO)
I2C_MST_TXFIFO_UDF_INT_ST The masked interrupt status bit for the
I2C_TRANS_COMPLETE_INT interrupt. (RO)
I2C_TRANS_COMPLETE_INT_ST The masked interrupt status bit for the
EL
I2C_TRANS_COMPLETE_INT interrupt. (RO)
I2C_TIME_OUT_INT_ST The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. (RO)
I2C_TRANS_START_INT_ST The masked interrupt status bit for the I2C_TRANS_START_INT inter-
rupt. (RO)
PR
I2C_NACK_INT_ST The masked interrupt status bit for the I2C_SLAVE_STRETCH_INT interrupt.
(RO)
I2C_TXFIFO_OVF_INT_ST The masked interrupt status bit for the I2C_TXFIFO_OVF_INT interrupt.
(RO)
I2C_RXFIFO_UDF_INT_ST The masked interrupt status bit for the I2C_RXFIFO_UDF_INT interrupt.
(RO)
Continued on the next page...
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Register 23.25. I2C_INT_STATUS_REG (0x002C)
Continued from the previous page...
I2C_SCL_ST_TO_INT_ST The masked interrupt status bit for the I2C_SCL_ST_TO_INT interrupt.
(RO)
I2C_SCL_MAIN_ST_TO_INT_ST The masked interrupt status bit for the I2C_SCL_MAIN_ST_TO_INT
interrupt. (RO)
I2C_DET_START_INT_ST The masked interrupt status bit for the I2C_DET_START_INT interrupt.
(RO)
RY
I2C_SLAVE_STRETCH_INT_ST The masked interrupt status bit for the I2C_SLAVE_STRETCH_INT
interrupt. (RO)
I2C_GENERAL_CALL_INT_ST The masked interrupt status bit for the I2C_GENARAL_CALL_INT in-
terrupt. (RO)
A
Register 23.26. I2C_COMD0_REG (0x0058)
IN
NE
O
_D
D0
D0
AN
AN
M
M
M
M
)
ed
CO
CO
rv
se
C_
C_
IM
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_COMMAND0 This is the content of command register 0. It consists of three parts:
EL
• op_code is the command. 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
• Byte_num represents the number of bytes that need to be sent or received.
• ack_check_en, ack_exp and ack are used to control the ACK bit. For more information, see
Section 23.4.9.
PR
(R/W)
I2C_COMMAND0_DONE When command 0 has been executed in master mode, this bit changes
to high level. (R/W/SS)
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Register 23.27. I2C_COMD1_REG (0x005C)
NE
O
_D
D1
D1
AN
AN
M
M
M
M
d)
CO
CO
ve
er
C_
C_
s
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_COMMAND1 This is the content of command register 1. It is the same as that of
I2C_COMMAND0. (R/W)
RY
I2C_COMMAND1_DONE When command 1 has been executed in master mode, this bit changes
to high level. (R/W/SS)
Register 23.28. I2C_COMD2_REG (0x0060)
A
NE
O
_D
D2
D2
AN
AN
IN
M
M
M
M
d)
O
CO
ve
_C
r
se
C_
C
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IM
I2C_COMMAND2 This is the content of command register 2. It is the same as that of
I2C_COMMAND0. (R/W)
I2C_COMMAND2_DONE When command 2 has been executed in master mode, this bit changes
to high Level. (R/W/SS)
EL
Register 23.29. I2C_COMD3_REG (0x0064)
NE
PR _D
D3
O
D3
AN
AN
M
M
M
M
d )
CO
CO
r ve
se
C_
C_
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_COMMAND3 This is the content of command register 3. It is the same as that of
I2C_COMMAND0. (R/W)
I2C_COMMAND3_DONE When command 3 has been executed in master mode, this bit changes
to high level. (R/W/SS)
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Register 23.30. I2C_COMD4_REG (0x0068)
NE
O
_D
D4
D4
AN
AN
M
M
M
M
d)
CO
CO
ve
er
C_
C_
s
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_COMMAND4 This is the content of command register 4. It is the same as that of
I2C_COMMAND0. (R/W)
RY
I2C_COMMAND4_DONE When command 4 has been executed in master mode, this bit changes
to high level. (R/W/SS)
Register 23.31. I2C_COMD5_REG (0x006C)
A
NE
O
_D
D5
D5
AN
AN
IN
M
M
M
M
d)
O
CO
ve
_C
r
se
C_
C
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IM
I2C_COMMAND5 This is the content of command register 5. It is the same as that of
I2C_COMMAND0. (R/W)
I2C_COMMAND5_DONE When command 5 has been executed in master mode, this bit changes
to high level. (R/W/SS)
EL
Register 23.32. I2C_COMD6_REG (0x0070)
NE
PR _D
D6
O
D6
AN
AN
M
M
M
M
d )
CO
CO
r ve
se
C_
C_
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_COMMAND6 This is the content of command register 6. It is the same as that of
I2C_COMMAND0. (R/W)
I2C_COMMAND6_DONE When command 6 has been executed in master mode, this bit changes
to high level. (R/W/SS)
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Register 23.33. I2C_COMD7_REG (0x0074)
NE
O
_D
D7
D7
AN
AN
M
M
M
M
d)
CO
CO
ve
er
C_
C_
s
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_COMMAND7 This is the content of command register 7. It is the same as that of
I2C_COMMAND0. (R/W)
RY
I2C_COMMAND7_DONE When command 7 has been executed in master mode, this bit changes
to high level. (R/W/SS)
Register 23.34. I2C_DATE_REG (0x00F8)
A
E
AT
C_D
I2
31
IN
0x20070201
0
Reset
I2C_DATE This is the version control register. (R/W)
IM
EL
PR
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
The ESP32-C3 contains an USB Serial/JTAG Controller. This unit can be used to program the SoC’s flash, read
program output, as well as attach a debugger to the running program. All of these are possible for any computer
with a USB host (’host’ in the rest of this text) without any active external components.
24.1 Overview
The workflow of developing on previous versions of Espressif chips generally use two methods of communication
with the SoC: one is a serial port and the other is the JTAG debugging port. The serial port is a two-wire interface
traditionally used to push new firmware-under-development to the chip (’programming’). As most modern
RY
computers do not have a compatible serial port anymore, interfacing to this serial port requires an USB-to-serial
converter IC or board. After programming is finished, the port is used to monitor any debugging output from the
program, in order to keep an eye on the general state of program execution. When program execution is not
what the developer expects (i.e. the program crashes), the JTAG debugging port is then used to inspect the
state of the program and its variables and set break- and watchpoints. This requires interfacing with the JTAG
debug port, which generally requires an external JTAG adapter.
A
All these external interfaces take up six pins in total, which cannot be used for other purposes while debugging.
Especially on devices with small packages, like the ESP32-C3, not being able to use these pins can be limiting to
a design.
IN
In order to alleviate this issue, as well as to negate the need for external devices, the ESP32-C3 contains an USB
Serial/JTAG Controller, which integrates the functionality of both an USB-to-serial converter as well as those of an
USB-to-JTAG adapter. As this device directly interfaces to an external USB host using only the two data lines
IM
required by USB1.1, debugging the ESP32-C3 only requires two pins to be dedicated to this functionality.
24.2 Features
• USB Full-speed device.
EL
• Fixed function device, hardwired for CDC-ACM (Communication Device Class - Abstract Control Model)
and JTAG adapter functionality.
• 2 OUT Endpoints, 3 IN Endpoints in addition to Control Endpoint 0; Up to 64-byte data payload size.
• Internal PHY, so no or very few external components needed to connect to a host computer.
PR
• CDC-ACM adherent serial port emulation is plug-and-play on most modern OSes.
• JTAG interface allows fast communication with CPU debug core using a compact representation of JTAG
instructions.
• CDC-ACM supports host controllable chip reset and entry into download mode.
As shown in Figure 24-1, the USB Serial/JTAG Controller consists of an USB PHY, a USB device interface, a
JTAG command processor and a response capture unit, as well as the CDC-ACM registers. The PHY and part of
the device interface are clocked from a 48 MHz clock derived from the main PLL, the rest of the logic is clocked
from APB_CLK. The JTAG command processor is connected to the JTAG debug unit of the main processor; the
CDC-ACM registers are connected to the APB bus and as such can be read from and written to by software
running on the main CPU.
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RY
Figure 241. USB Serial/JTAG High Level Diagram
Note that while the USB Serial/JTAG device is a USB 2.0 device, it only supports Full-speed (12 Mbps) and not
the High-speed (480 Mbps) mode the USB2.0 standard introduced.
A
Figure 24-2 shows the internal details of the USB Serial/JTAG controller on the USB side. The USB Serial/JTAG
Controller consists of an USB 2.0 Full Speed device. It contains a control endpoint, a dummy interrupt endpoint,
two bulk input endpoints as well as two bulk output endpoints. Together, these form an USB Composite device,
IN
which consists of an CDC-ACM USB class device as well as a vendor-specific device implementing the JTAG
interface. On the SoC side, the JTAG interface is directly connected to the RISC-V CPU’s debugging interface,
allowing debugging of programs running on that core. Meanwhile, the CDC-ACM device is exposed as a set of
registers, allowing a program on the CPU to read and write from this. Additionally, the ROM startup code of the
IM
SoC contains code allowing the user to reprogram attached flash memory using this interface.
EL
PR
Figure 242. USB Serial/JTAG Block Diagram
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
24.3 Functional Description
The USB Serial/JTAG Controller interfaces with an USB host processor on one side, and the CPU debug
hardware as well as the software running on the USB port on the other side.
24.3.1 CDCACM USB Interface Functional Description
The CDC-ACM interface adheres to the standard USB CDC-ACM class for serial port emulation. It contains a
dummy interrupt endpoint (which will never send any events, as they are not implemented nor needed) and a Bulk
IN as well as a Bulk OUT endpoint for the host’s received and sent serial data respectively. These endpoints can
handle 64-byte packets at a time, allowing for high throughput. As CDC-ACM is a standard USB device class, a
host generally does not need any special installation procedures for it to function: when the USB debugging
RY
device is properly connected to a host, the operating system should show a new serial port moments later.
The CDC-ACM interface accepts the following standard CDC-ACM control requests:
Table 241. Standard CDCACM Control Requests
Command Action
A
SEND_BREAK Accepted but ignored (dummy)
SET_LINE_CODING Accepted but ignored (dummy)
GET_LINE_CODING Always returns 9600 baud, no parity, 8 databits, 1 stopbit
SET_CONTROL_LINE_STATE
IN
Set the state of the RTS/DTR lines, see Table 24-2
Aside from general-purpose communication, the CDC-ACM interface also can be used to reset the ESP32-C3
IM
and optionally make it go into download mode in order to flash new firmware. This is done by setting the RTS
and DTR lines on the virtual serial port.
Table 242. CDCACM Settings with RTS and DTR
RTS DTR Action
EL
0 0 Clear download mode flag
0 1 Set download mode flag
1 0 Reset ESP32-C3
1 1 No action
PR
Note that if the download mode flag is set when the ESP32-C3 is reset, the ESP32-C3 will reboot into download
mode. When this flag is cleared and the chip is reset, the ESP32-C3 will boot from flash. For specific sequences,
please refer to Section 24.4. All these functions can also be disabled by programming various eFuses, please
refer to Chapter 4 eFuse Controller (EFUSE) for more details.
24.3.2 CDCACM Firmware Interface Functional Description
As the USB Serial/JTAG Controller is connected to the internal APB bus of the ESP32-C3, the CPU can interact
with it. This is mainly used to read and write data from and to the virtual serial port on the attached host.
USB CDC-ACM serial data is sent to and received from the host in packets of 0 to 64 bytes in size. When
enough CDC-ACM data has accumulated in the host, the host will send a packet to the CDC-ACM receive
endpoint, and when the USB Serial/JTAG Controller has a free buffer, it will accept this packet. Conversely, the
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
host will check periodically if the USB Serial/JTAG Controller has a packet ready to be sent to the host, and if so,
receive this packet.
Firmware can get notified of new data from the host in one of two ways. First of all, the
USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL bit will remain set to one as long as there still is unread host
data in the buffer. Secondly, the availability of data will trigger the
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt as well.
When data is available, it can be read by firmware by repeatedly reading bytes from
USB_SERIAL_JTAG_EP1_REG. The amount of bytes to read can be determined by checking the
USB_REG_SERIAL_OUT_EP_DATA_AVAIL bit after reading each byte to see if there is more data to read. After all
data is read, the USB debug device is automatically readied to receive a new data packet from the host.
RY
When the firmware has data to send, it can do so by putting it in the send buffer and triggering a flush, allowing
the host to receive the data in a USB packet. In order to do so, there needs to be space available in the send
buffer. Firmware can check this by reading USB_REG_SERIAL_IN_EP_DATA_FREE; a one in this register field
indicates there is still free room in the buffer. While this is the case, firmware can fill the buffer by writing bytes to
the USB_SERIAL_JTAG_EP1_REG register.
A
Writing the buffer doesn’t immediately trigger sending data to the host. This does not happen until the buffer is
flushed; a flush causes the entire buffer to be readied for reception by the USB host at once. A flush can be
triggered in two ways: after the 64th byte is written to the buffer, the USB hardware will automatically flush the
IN
buffer to the host. Alternatively, firmware can trigger a flush by writing a one to
USB_REG_SERIAL_WR_DONE.
Regardless of how a flush is triggered, the send buffer will be unavailable for firmware to write into until it has
been fully read by the host. As soon as this happens, the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt
IM
will be triggered, indicating the send buffer can receive another 64 bytes.
24.3.3 USBtoJTAG Interface
The USB-to-JTAG interface uses a vendor-specific class for its implementation. It consists of two endpoints, one
EL
to receive commands and one to send responses. Additionally, some less time-sensitive commands can be
given as control requests.
24.3.4 JTAG Command Processor
Commands from the host to the JTAG interface are interpreted by the JTAG command processor. Internally, the
PR
JTAG command processor implements a full four-wire JTAG bus, consisting of the TCK, TMS and TDI output
lines to the RISC-V CPU, as well as the TDO line signalling back from the CPU to the JTAG response capture
unit. These signals adhere to the IEEE 1149.1 JTAG standards. Additionally, there is a SRST line to reset the
SoC.
The JTAG command processor parses each received nibble (4-bit value) as a command. As USB data is
received in 8-bit bytes, this means each byte contains two commands. The USB command processor will
execute high-nibble first and low-nibble second. The commands are used to control the TCK, TMS, TDI, and
SRST lines of the internal JTAG bus, as well as signal the JTAG response capture unit that the state of the TDO
line (which is driven by the CPU debug logic) needs to be captured.
Of this internal JTAG bus, TCK, TMS, TDI and TDO are connected directly to the JTAG debugging logic of the
RISC-V CPU. SRST is connected to the reset logic of the digital circuitry in the SoC and a high level on this line
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will cause a digital system reset. Note that the USB Serial/JTAG Controller itself is not affected by SRST.
A nibble can contain the following commands:
Table 243. Commands of a Nibble
bit 3 2 1 0
CMD_CLK 0 cap tms tdi
CMD_RST 1 0 0 srst
CMD_FLUSH 1 0 1 0
CMD_RSV 1 0 1 1
CMD_REP 1 1 R1 R0
RY
• CMD_CLK will set the TDI and TMS to the indicated values and emit one clock pulse on TCK. If the CAP bit
is 1, it will also instruct the JTAG response capture unit to capture the state of the TDO line. This instruction
forms the basis of JTAG communication.
• CMD_RST will set the state of the SRST line to the indicated value. This can be used to reset the
ESP32-C3.
A
• CMD_FLUSH will instruct the JTAG response capture unit to flush the buffer of all bits it collected so the
host is able to read them. Note that in some cases, a JTAG transaction will end in an odd number of
IN
commands and as such an odd number of nibbles. In this case, it is allowable to repeat the CMD_FLUSH
to get an even number of nibbles fitting an integer number of bytes.
• CMD_RSV is reserved in the current implementation. The ESP32-C3 will ignore this command when it
receives it.
IM
• CMD_REP repeats the last (non-CMD_REP) command a certain number of times. It’s intended goal is to
compress command streams which repeat the same CMD_CLK instruction multiple times. A command like
CMD_CLK can be followed by multiple CMD_REP commands. The number of repetitions done by one
CMD_REP can be expressed as no_repetitions = (R1 × 2 + R0) × (4cmd_rep_count ), where
EL
cmd_rep_count is how many CMD_REP instructions went directly before it. Note that the CMD_REP is
only intended to repeat a CMD_CLK command. Specifically, using it on a CMD_FLUSH command may
lead to an unresponsive USB device, needing an USB reset to recover.
24.3.5 USBtoJTAG Interface: CMD_REP usage example
PR
Here is a list of commands as an illustration of the use of CMD_REP. Note each command is a nibble; in this
example the bytewise command stream would be 0x0D 0x5E 0xCF.
1. 0x0 (CMD_CLK: cap=0, tdi=0, tms=0)
2. 0xD (CMD_REP: R1=0, R0=1)
3. 0x5 (CMD_CLK: cap=1, tdi=0, tms=1)
4. 0xE (CMD_REP: R1=1, R0=0)
5. 0xC (CMD_REP: R1=0, R0=0)
6. 0xF (CMD_REP: R1=1, R0=1)
This is what happens at every step:
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1. TCK is clocked with the TDI and TMS lines set to 0. No data is captured.
2. TCK is clocked another (0 × 2 + 1) × (42 ) = 1 time with the same settings as step 1.
3. TCK is clocked with the TDI and TMS lines set to 0. Data on the TDO line is captured.
4. TCK is clocked another (1 × 2 + 0) × (40 ) = 2 times with the same settings as step 3.
5. Nothing happens: (0 × 2 + 0) × (41 ) = 0. Note that this does increase cmd_rep_count for the next step.
6. TCK is clocked another (1 × 2 + 1) × (42 ) = 48 times with the same settings as step 3.
In other words: This example stream has the same net effect as command 1 twice, then repeating command 3
for 51 times.
RY
24.3.6 USBtoJTAG Interface: Response Capture Unit
The response capture unit reads the TDO line of the internal JTAG bus and captures its value when the command
parser executes a CMD_CLK with cap=1. It puts this bit into an internal shift register, and writes a byte into the
USB buffer when 8 bits have been collected. Of these 8 bits, the least significant one is the one that is read from
TDO the earliest.
A
As soon as either 64 bytes (512 bits) have been collected or a CMD_FLUSH command is executed, the response
capture unit will make the buffer available for the host to receive. Note that the interface to the USB logic is
double-buffered. This way, as long as USB throughput is sufficient, the response capture unit can always receive
IN
more data: while one of the buffers is waiting to be sent to the host, the other one can receive more data. When
the host has received data from its buffer and the response capture unit flushes its buffer, the two buffers change
position.
IM
This also means that a command stream can cause at most 128 bytes of capture data to be generated (less if
there are flush commands in the stream) without the host acting to receive the generated data. If more data is
generated anyway, the command stream is paused and the device will not accept more commands before the
generated capture data is read out.
Note that in general, the logic of the response capture unit tries not to send zero-byte responses: for instance,
EL
sending a series of CMD_FLUSH commands will not cause a series of zero-byte USB responses to be sent.
However, in the current implementation, some zero-byte responses may be generated in extraordinary
circumstances. It’s recommended to ignore these responses.
24.3.7 USBtoJTAG Interface: Control Transfer Requests
PR
Aside from the command processor and the response capture unit, the USB-to-JTAG interface also understands
some control requests, as documented in the table below:
Table 244. USBtoJTAG Control Requests
bmRequestType bRequest wValue wIndex wLength Data
01000000b 0 (VEND_JTAG_SETDIV) [divider] interface 0 None
01000000b 1 (VEND_JTAG_SETIO) [iobits] interface 0 None
11000000b 2 (VEND_JTAG_GETTDO) 0 interface 1 [iostate]
10000000b 6 (GET_DESCRIPTOR) 0x2000 0 256 [jtag cap desc]
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• VEND_JTAG_SETDIV sets the divider used. This directly affects the duration of a TCK clock pulse. The
TCK clock pulses are derived from APB_CLK, which is divided down using an internal divider. This control
request allows the host to set this divider. Note that on startup, the divider is set to 2, meaning the TCK
clock rate will generally be 40 MHz.
• VEND_JTAG_SETIO can bypass the JTAG command processor to set the internal TDI, TDO, TMS and
SRST lines to given values. These values are encoded in the wValue field in the format of 11’b0, srst, trst,
tck, tms, tdi.
• VEND_JTAG_GETTDO can bypass the JTAG response capture unit to read the internal TDO signal directly.
This request returns one byte of data, of which the least significant bit represents the status of the TDO line.
• GET_DESCRIPTOR is a standard USB request, however it can also be used with a vendor-specific wValue
RY
of 0x2000 to get the JTAG capabilities descriptor. This returns a certain amount of bytes representing the
following fixed structure, which describes the capabilities of the USB-to-JTAG adapter. This structure
allows host software to automatically support future revisions of the hardware without needing an update.
The JTAG capabilities descriptor of the ESP32-C3 is as follows. Note that all 16-bit values are little-endian.
Table 245. JTAG Capabilities Descriptor
A
Byte Value Description
0 1 JTAG protocol capabilities structure version
1
2
10
1
IN
Total length of JTAG protocol capabilities
Type of this struct: 1 for speed capabilities struct
3 8 Length of this speed capabilities struct
4~5 8000 APB_CLK speed in 10 kHz increments. Note that the maximal TCK speed is half of this
IM
6~7 1 Minimum divisor
8~9 255 Maximum divisor
24.4 Recommended Operation
EL
There is very little setup needed in order to use the USB Serial/JTAG Device. The USB-to-JTAG hardware itself
does not need any setup aside from the standard USB initialization the host operating system already does. The
CDC-ACM emulation, on the host side, also is plug-and-play.
On the firmware side, very little initialization should be needed either: the USB hardware is self-initializing and after
PR
boot-up, if a host is connected and listening on the CDC-ACM interface, data can be exchanged as described
above without any specific setup aside from the firmware optionally setting up an interrupt service handler.
One thing to note is that there may be situations where the host is either not attached or the CDC-ACM virtual
port is not opened. In this case, the packets that are flushed to the host will never be picked up and the transmit
buffer will never be empty. It is important to detect this and time out, as this is the only way to reliably detect that
the port on the host side is closed.
Another thing to note is that the USB device is dependent on both the PLL for the 48 MHz USB PHY clock, as
well as APB_CLK. Specifically, an APB_CLK of 40 MHz or more is required for proper USB compliant operation,
although the USB device will still function with most hosts with an APB_CLK as low as 10 MHz. Behaviour
shown when this happens is dependent on the host USB hardware and drivers, and can include the device being
unresponsive and it disappearing when first accessed.
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More specifically, the APB_CLK will be affected by clock gating the USB Serial/JTAG Controller, which may
happen in Light Sleep. Additionally, the USB serial/JTAG Controller (as well as the attached RISC-V CPU) will be
entirely powered down in Deep Sleep mode. If a device needs to be debugged in either of these two modes, it
may be preferable to use an external JTAG debugger and serial interface instead.
The CDC-ACM interface can also be used to reset the SoC and take it into or out of download mode. Generating
the correct sequence of handshake signals can be a bit complicated: Most operating systems only allow setting
or resetting DTR and RTS separately, and not in tandem. Additionally, some drivers (e.g. the standard CDC-ACM
driver on Windows) do not set DTR until RTS is set and the user needs to explicitly set RTS in order to
’propagate’ the DTR value. These are the recommended procedures:
To reset the SoC into download mode:
RY
Table 246. Reset SoC into Download Mode
Action Internal state Note
Clear DTR RTS=?, DTR=0 Initialize to known values
Clear RTS RTS=0, DTR=0 -
Set DTR RTS=0, DTR=1 Set download mode flag
A
Clear RTS RTS=0, DTR=1 Propagate DTR
Set RTS RTS=1, DTR=1 -
Clear DTR RTS=1, DTR=0 Reset SoC
Set RTS
IN
RTS=1, DTR=0 Propagate DTR
Clear RTS RTS=0, DTR=0 Clear download flag
IM
To reset the SoC into booting from flash:
Table 247. Reset SoC into Booting
Action Internal state Note
Clear DTR RTS=?, DTR=0 -
EL
Clear RTS RTS=0, DTR=0 Clear download flag
Set RTS RTS=1, DTR=0 Reset SoC
Clear RTS RTS=0, DTR=0 Exit reset
PR
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24.5 Register Summary
The addresses in this section are relative to USB Serial/JTAG Controller base address provided in Table 3-4 in
Chapter 3 System and Memory.
Name Description Address Access
Configuration Registers
USB_SERIAL_JTAG_EP1_REG FIFO access for the CDC-ACM data IN and OUT 0x0000 R/W
endpoints
USB_SERIAL_JTAG_CONF0_REG PHY hardware configuration 0x0018 R/W
USB_SERIAL_JTAG_TEST_REG Registers used for debugging the PHY 0x001C R/W
USB_SERIAL_JTAG_MISC_CONF_REG Clock enable control 0x0044 R/W
RY
USB_SERIAL_JTAG_MEM_CONF_REG Memory power control 0x0048 R/W
Status Registers
USB_SERIAL_JTAG_EP1_CONF_REG Configuration and control registers for the CDC- 0x0004 varies
ACM FIFOs
USB_SERIAL_JTAG_JFIFO_ST_REG JTAG FIFO status and control registers 0x0020 varies
A
USB_SERIAL_JTAG_FRAM_NUM_REG Last received SOF frame index register 0x0024 RO
USB_SERIAL_JTAG_IN_EP0_ST_REG Control IN endpoint status information 0x0028 RO
USB_SERIAL_JTAG_IN_EP1_ST_REG CDC-ACM IN endpoint status information 0x002C RO
USB_SERIAL_JTAG_IN_EP2_ST_REG
tion
IN
CDC-ACM interrupt IN endpoint status informa- 0x0030 RO
USB_SERIAL_JTAG_IN_EP3_ST_REG JTAG IN endpoint status information 0x0034 RO
USB_SERIAL_JTAG_OUT_EP0_ST_REG Control OUT endpoint status information 0x0038 RO
IM
USB_SERIAL_JTAG_OUT_EP1_ST_REG CDC-ACM OUT endpoint status information 0x003C RO
USB_SERIAL_JTAG_OUT_EP2_ST_REG JTAG OUT endpoint status information 0x0040 RO
Interrupt Registers
USB_SERIAL_JTAG_INT_RAW_REG Interrupt raw status register 0x0008 R/WTC/SS
USB_SERIAL_JTAG_INT_ST_REG Interrupt status register 0x000C RO
EL
USB_SERIAL_JTAG_INT_ENA_REG Interrupt enable status register 0x0010 R/W
USB_SERIAL_JTAG_INT_CLR_REG Interrupt clear status register 0x0014 WT
Version Registers
USB_SERIAL_JTAG_DATE_REG Version register 0x0080 R/W
PR
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24.6 Registers
The addresses in this section are relative to USB Serial/JTAG Controller base address provided in Table 3-4 in
Chapter 3 System and Memory.
Register 24.1. USB_SERIAL_JTAG_EP1_REG (0x0000)
TE
BY
R_
DW
_R
G
TA
_J
AL
RI
d)
E
ve
_S
RY
er
B
s
US
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
USB_SERIAL_JTAG_RDWR_BYTE Write and read byte data to/from UART Tx/Rx
FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is
A
set then user can write data (up to 64 bytes) into UART Tx FIFO. When
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check
USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR
IN
to know how many data is received, then read that amount of data from UART Rx FIFO. (R/W)
IM
EL
PR
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Register 24.2. USB_SERIAL_JTAG_CONF0_REG (0x0018)
IDE
E
RR
RR RID
E
VE
BL
R
IDE
DP ULLU N
_O
UL OWN
G_ _PU ALUE
_O OVE
IAL AG_ LLUP ENA
S
Y_ PINS
DO
JTA EXC _PIN
L_
LD
LU
D_
VE
_V
L
UL
L
L
_
G_ B_PA
UL
SE
G
HG
H
_P
L
P
RIA TAG CH
P
_P
EF
EF
EF
M_
AD
_
DM
PH
US
PU
SE L_JT _DP
VR
VR
VR
EX
D
_P
G_
G_
G_
G_
G_
G_
_
G_
G
AG
US SERI JTA
US SERI JTA
US SERI JTA
JTA
US SERI JTA
JTA
JTA
JTA
US SERI JTA
JT
_J
_
_
_
_
_
_
L_
L_
L_
L_
AL
AL
AL
AL
IAL
AL
AL
A
RIA
RIA
RIA
US SERI
US SERI
ER
ER
SE
SE
SE
)
S
ed
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
rv
se
US
US
US
US
US
US
(re
RY
31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 Reset
USB_SERIAL_JTAG_PHY_SEL Select internal/external PHY. 1’b0: internal PHY, 1’b1: external PHY.
(R/W)
A
USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE Enable software control USB D+ D- exchange.
(R/W)
USB_SERIAL_JTAG_EXCHG_PINS USB D+ D- exchange (R/W)
IN
USB_SERIAL_JTAG_VREFL Control single-end input high threshold. 1.76 V to 2 V, step 80 mV.
(R/W)
USB_SERIAL_JTAG_VREFH Control single-end input low threshold. 0.8 V to 1.04 V, step 80 mV.
IM
(R/W)
USB_SERIAL_JTAG_VREF_OVERRIDE Enable software control input threshold. (R/W)
USB_SERIAL_JTAG_PAD_PULL_OVERRIDE Enable software control USB D+ D- pull-up pull-
down. (R/W)
EL
USB_SERIAL_JTAG_DP_PULLUP Control USB D+ pull-up. (R/W)
USB_SERIAL_JTAG_DP_PULLDOWN Control USB D+ pull-down. (R/W)
USB_SERIAL_JTAG_DM_PULLUP Control USB D- pull-up. (R/W)
PR
USB_SERIAL_JTAG_DM_PULLDOWN Control USB D- pull-down. (R/W)
USB_SERIAL_JTAG_PULLUP_VALUE Control pull-up value. (R/W)
USB_SERIAL_JTAG_USB_PAD_ENABLE Enable USB pad function. (R/W)
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Register 24.3. USB_SERIAL_JTAG_TEST_REG (0x001C)
AB E
LE
EN O
TA TE _T M
ES US P
T_ B_
_J G_ ST _D
_T _ D
G ST X_
AL A E TX
RI _JT _T T_
SE AL AG ES
B_ RI _JT _T
US _SE IAL TAG
B R _J
US SE AL
B_ RI
)
ed
US _SE
rv
se
B
US
(re
31 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
USB_SERIAL_JTAG_TEST_ENABLE Enable test of the USB pad. (R/W)
RY
USB_SERIAL_JTAG_TEST_USB_OE USB pad output enable in test. (R/W)
USB_SERIAL_JTAG_TEST_TX_DP USB D+ tx value in test. (R/W)
USB_SERIAL_JTAG_TEST_TX_DM USB D- tx value in test. (R/W)
A
Register 24.4. USB_SERIAL_JTAG_MISC_CONF_REG (0x0044)
IN
EN
_
LK
_C
G
TA
_J
AL
RI
d )
IM
SE
ve
B_
ser
US
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
USB_SERIAL_JTAG_CLK_EN 1’h1: Force clock on for register. 1’h0: Support clock only when
EL
application writes registers. (R/W)
PR
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Register 24.5. USB_SERIAL_JTAG_MEM_CONF_REG (0x0048)
D N
_P K_E
EM CL
_M M _
SB E
_ U _M
G B
TA US
_J G_
AL A
RI _JT
SE AL
B_ RI
)
ed
US _SE
v
er
B
s
US
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
RY
USB_SERIAL_JTAG_USB_MEM_PD Set to power down USB memory. (R/W)
USB_SERIAL_JTAG_USB_MEM_CLK_EN Set to force clock-on for USB memory. (R/W)
Register 24.6. USB_SERIAL_JTAG_EP1_CONF_REG (0x0004)
A
A_ VAIL
EE
A
FR
ON P_D ATA_
IN
AT
D
WR _IN EP_
T_
_E
OU
E
L_
G_ RIAL
_D
RIA JTAG ERIA
E
IM
S
_S
G_
US SERI JTA
JTA
_
_
L_
AL
AL
US SERI
)
ed
SE
rv
B_
B_
B_
se
US
(re
EL
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
USB_SERIAL_JTAG_WR_DONE Set this bit to indicate writing byte data to UART Tx FIFO is done.
This bit then stays 0 until data in UART Tx FIFO is read by the USB Host. (WT)
PR
USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE 1’b1: Indicate UART Tx FIFO is not full and data
can be written into in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the data
is sent to the USB Host. (RO)
USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL 1’b1: Indicate there is data in UART Rx FIFO.
(RO)
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Register 24.7. USB_SERIAL_JTAG_JFIFO_ST_REG (0x0020)
Y
U IF SE T
PT
_O _F E E
_ L
_C Y
AG T_ O_ T
T
G T _R ES
FO L
FO PT
B_ IAL AG T_F EM
AL G_ _FIF _CN
N_ _EM L
FI FU
NT
FO L
TA OU O R
FI _FU
_ J _ FIF _
B_ IAL AG N_ IFO
O
IF
N_ O
US ER _JT G_I T_F
FI
S AL A U
US ER _JT OU
A N
B_ RI _JT _O
SE _JT _I
_I
_
US SE AL AG
G
TA
B_ RI _JT
JT
_J
L_
US _SE IAL
S AL
I A
B_ RI
RI
B R
US ER
d)
US _SE
US SE
ve
S
B_
er
B
s
US
(re
31 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Reset
RY
USB_SERIAL_JTAG_IN_FIFO_CNT JTAG in FIFO counter. (RO)
USB_SERIAL_JTAG_IN_FIFO_EMPTY Set to indicate JTAG in FIFO is empty. (RO)
USB_SERIAL_JTAG_IN_FIFO_FULL Set to indicate JTAG in FIFO is full. (RO)
USB_SERIAL_JTAG_OUT_FIFO_CNT JTAT out FIFO counter. (RO)
A
USB_SERIAL_JTAG_OUT_FIFO_EMPTY Set to indicate JTAG out FIFO is empty. (RO)
USB_SERIAL_JTAG_OUT_FIFO_FULL Set to indicate JTAG out FIFO is full. (RO)
IN
USB_SERIAL_JTAG_IN_FIFO_RESET Write 1 to reset JTAG in FIFO. (R/W)
USB_SERIAL_JTAG_OUT_FIFO_RESET Write 1 to reset JTAG out FIFO. (R/W)
IM
Register 24.8. USB_SERIAL_JTAG_FRAM_NUM_REG (0x0024)
X
DE
IN
E_
M
EL
A
FR
F_
O
_S
G
TA
_J
AL
RI
)
ed
SE
rv
B_
se
US
(re
PR
31 11 10 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
USB_SERIAL_JTAG_SOF_FRAME_INDEX Frame index of received SOF frame. (RO)
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Register 24.9. USB_SERIAL_JTAG_IN_EP0_ST_REG (0x0028)
R
DR
DD
AD
E
A
AT
R_
D_
ST
_W
_R
0_
P0
P0
EP
E
E
N_
N_
N_
_I
_I
_I
G
G
TA
TA
TA
_J
_J
_J
AL
AL
IA
RI
RI
ER
d)
SE
E
ve
_S
_S
B_
er
B
s
US
US
US
(re
31 16 15 9 8 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
RY
USB_SERIAL_JTAG_IN_EP0_STATE State of IN Endpoint 0. (RO)
USB_SERIAL_JTAG_IN_EP0_WR_ADDR Write data address of IN endpoint 0. (RO)
USB_SERIAL_JTAG_IN_EP0_RD_ADDR Read data address of IN endpoint 0. (RO)
A
Register 24.10. USB_SERIAL_JTAG_IN_EP1_ST_REG (0x002C)
IN
DR
DR
AD
D
E
_A
AT
R_
D
ST
_W
_R
1_
P1
P1
EP
_E
_E
N_
N
N
_I
_I
_I
G
G
TA
TA
TA
_J
_J
_J
IM
AL
AL
AL
RI
RI
RI
d)
SE
SE
SE
ve
B_
B_
B_
r
se
US
US
US
(re
31 16 15 9 8 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
EL
USB_SERIAL_JTAG_IN_EP1_STATE State of IN Endpoint 1. (RO)
USB_SERIAL_JTAG_IN_EP1_WR_ADDR Write data address of IN endpoint 1. (RO)
USB_SERIAL_JTAG_IN_EP1_RD_ADDR Read data address of IN endpoint 1. (RO)
PR
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
Register 24.11. USB_SERIAL_JTAG_IN_EP2_ST_REG (0x0030)
R
DR
DD
AD
E
A
AT
R_
D_
ST
_W
_R
2_
P2
P2
EP
E
E
N_
N_
N_
_I
_I
_I
G
G
TA
TA
TA
_J
_J
_J
AL
AL
IA
RI
RI
ER
d)
SE
E
ve
_S
_S
B_
er
B
s
US
US
US
(re
31 16 15 9 8 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
RY
USB_SERIAL_JTAG_IN_EP2_STATE State of IN Endpoint 2. (RO)
USB_SERIAL_JTAG_IN_EP2_WR_ADDR Write data address of IN endpoint 2. (RO)
USB_SERIAL_JTAG_IN_EP2_RD_ADDR Read data address of IN endpoint 2. (RO)
A
Register 24.12. USB_SERIAL_JTAG_IN_EP3_ST_REG (0x0034)
IN
DR
DR
AD
D
E
_A
AT
R_
D
ST
_W
_R
3_
P3
P3
EP
_E
_E
N_
N
N
_I
_I
_I
G
G
TA
TA
TA
_J
_J
_J
IM
AL
AL
AL
RI
RI
RI
d)
SE
SE
SE
ve
B_
B_
B_
r
se
US
US
US
(re
31 16 15 9 8 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
EL
USB_SERIAL_JTAG_IN_EP3_STATE State of IN Endpoint 3. (RO)
USB_SERIAL_JTAG_IN_EP3_WR_ADDR Write data address of IN endpoint 3. (RO)
USB_SERIAL_JTAG_IN_EP3_RD_ADDR Read data address of IN endpoint 3. (RO)
PR
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
Register 24.13. USB_SERIAL_JTAG_OUT_EP0_ST_REG (0x0038)
DR
R
DD
AD
E
_A
AT
R_
RD
ST
W
0_
0_
0_
EP
EP
_E
_
_
UT
UT
UT
_O
_O
_O
G
G
TA
TA
TA
J
_J
_J
L_
AL
AL
IA
RI
RI
ER
d)
SE
E
ve
_S
_S
B_
er
B
s
US
US
US
(re
31 16 15 9 8 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
USB_SERIAL_JTAG_OUT_EP0_STATE State of OUT Endpoint 0. (RO)
USB_SERIAL_JTAG_OUT_EP0_WR_ADDR Write data address of OUT Endpoint 0.
When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected, there are
USB_SERIAL_JTAG_OUT_EP0_WR_ADDR - 2 bytes of data in OUT EP0. (RO)
A
USB_SERIAL_JTAG_OUT_EP0_RD_ADDR Read data address of OUT endpoint 0. (RO)
IN
Register 24.14. USB_SERIAL_JTAG_OUT_EP1_ST_REG (0x003C)
TA
_C
T
N
DR
DR
DA
AD
AD
TE
C_
IM
R_
D_
TA
RE
W
_R
_S
1_
1_
P1
P1
P
P
_E
_E
_E
_E
UT
UT
UT
UT
_O
_O
_O
_O
G
G
TA
TA
TA
TA
_J
_J
_J
_J
AL
AL
AL
AL
RI
RI
RI
RI
)
ed
SE
SE
SE
E
EL
_S
rv
B_
B_
B_
se
B
US
US
US
US
(re
31 23 22 16 15 9 8 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
USB_SERIAL_JTAG_OUT_EP1_STATE State of OUT Endpoint 1. (RO)
PR
USB_SERIAL_JTAG_OUT_EP1_WR_ADDR Write data address of OUT Endpoint 1.
When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected, there are
USB_SERIAL_JTAG_OUT_EP1_WR_ADDR - 2 bytes of data in OUT EP1. (RO)
USB_SERIAL_JTAG_OUT_EP1_RD_ADDR Read data address of OUT endpoint 1. (RO)
USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT Data count in OUT Endpoint 1 when one packet
is received. (RO)
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
Register 24.15. USB_SERIAL_JTAG_OUT_EP2_ST_REG (0x0040)
DR
R
DD
AD
E
_A
AT
R_
RD
ST
W
2_
2_
2_
EP
EP
_E
_
_
UT
UT
UT
_O
_O
_O
G
G
TA
TA
TA
J
_J
_J
L_
AL
AL
IA
RI
RI
ER
d)
SE
E
ve
_S
_S
B_
er
B
s
US
US
US
(re
31 16 15 9 8 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
USB_SERIAL_JTAG_OUT_EP2_STATE State of OUT Endpoint 2. (RO)
USB_SERIAL_JTAG_OUT_EP2_WR_ADDR Write data address of OUT endpoint 2.
When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected, there are
USB_SERIAL_JTAG_OUT_EP2_WR_ADDR - 2 bytes of data in OUT EP2. (RO)
A
USB_SERIAL_JTAG_OUT_EP2_RD_ADDR Read data address of OUT endpoint 2. (RO)
IN
IM
EL
PR
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
Register 24.16. USB_SERIAL_JTAG_INT_RAW_REG (0x0008)
W
W
UF N_R T_IN AD_ _RA
A
W
W
_R
RA
RA
INT
INT
T_
T_
AW V_P AW
W
US SERI JTA N_TO S_R _PAY AD_
_ IN
RC _ERR T_RA 1_IN
AW
_IN _RA
JTA T_R REC T_R
KT
LO
LO
_R
_IN RAW
P
W
T
IN
_R W
E
AY
INT
_
JTA SOF _OU PTY_
A
AW
_P
_R
PID _ERR INT_
H_
E
G_ T_EP ZERO
EC
T
ES
IN
US
EM
IAL AG_ B_B ZER
T_
_
NT
C1 RR_
FL
_
_
_
SE L_JT _SER L_IN
_I
IN_
L_ G_O _EP2
E
E
R
U
F_
K
_IN
G_ _ER
IAL
6
G_
AG RIA
5
ER _JTA OUT
U
CR
S
E
ST
_C
U
S
I
G_
G_
G_
G_
_
G_
G
AG
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
T
T
J
J
_
_
_
_
_
L_
_
_
L_
RY
AL
AL
AL
AL
AL
AL
AL
A
RIA
RIA
US SERI
ER
)
ed
E
S
S
rv
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
se
US
US
US
US
(re
31 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset
USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW The raw interrupt bit turns to high level when a
A
flush command is received for IN endpoint 2 of JTAG. (R/WTC/SS)
USB_SERIAL_JTAG_SOF_INT_RAW The raw interrupt bit turns to high level when a SOF frame is
received. (R/WTC/SS)
IN
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt bit turns to high level
when the Serial Port OUT Endpoint received one packet. (R/WTC/SS)
IM
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW The raw interrupt bit turns to high level when
the Serial Port IN Endpoint is empty. (R/WTC/SS)
USB_SERIAL_JTAG_PID_ERR_INT_RAW The raw interrupt bit turns to high level when a PID error
is detected. (R/WTC/SS)
EL
USB_SERIAL_JTAG_CRC5_ERR_INT_RAW The raw interrupt bit turns to high level when a CRC5
error is detected. (R/WTC/SS)
USB_SERIAL_JTAG_CRC16_ERR_INT_RAW The raw interrupt bit turns to high level when a CRC16
error is detected. (R/WTC/SS)
PR
USB_SERIAL_JTAG_STUFF_ERR_INT_RAW The raw interrupt bit turns to high level when a bit
stuffing error is detected. (R/WTC/SS)
USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt bit turns to high level
when an IN token for IN endpoint 1 is received. (R/WTC/SS)
USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW The raw interrupt bit turns to high level when a
USB bus reset is detected. (R/WTC/SS)
USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high
level when OUT endpoint 1 received packet with zero payload. (R/WTC/SS)
USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high
level when OUT endpoint 2 received packet with zero payload. (R/WTC/SS)
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
Register 24.17. USB_SERIAL_JTAG_INT_ST_REG (0x000C)
UF N_R T_IN AD_ _ST
T
_S
T
T
_S
INT
INT
_S
INT
INT
US SERI JTA N_TO S_R _PAY AD_
T
_IN _ST
T_
JTA NT_S REC T_S
_
T
LO
LO
P1
PK
_S
T
IN
E
AY
INT
V_
INT T
_
ST
JTA SOF _OU PTY_
ID ERR_ T_S
_IN _ST
_P
H_
_
ST
E
INT
G_ T_EP ZERO
EC
_IN
ES
US
EM
IAL AG_ B_B ZER
T_
T_
C1 RR_
R
T
FL
_
R
_
_
SE L_JT _SER L_IN
IN_
E
L_ G_O _EP2
E
E
R
U
6_
F_
K
G_ _ER
IAL
_
G_
G RIA
C5
_I
ER _JTA OUT
U
CR
R
S
E
ST
_C
U
_P
S
I
G_
G_
G_
_
G_
G
RIA TAG
AG
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
J T
J
_
_
_
_
_
L_
L_
_
L_
AL
AL
AL
AL
AL
AL
A
A
RIA
RY
US SERI
ER
)
ed
E
S
S
rv
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
se
US
US
US
US
(re
31 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST The raw interrupt status bit for the
A
USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. (RO)
USB_SERIAL_JTAG_SOF_INT_ST The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT
interrupt. (RO)
IN
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. (RO)
IM
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. (RO)
USB_SERIAL_JTAG_PID_ERR_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_PID_ERR_INT interrupt. (RO)
EL
USB_SERIAL_JTAG_CRC5_ERR_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. (RO)
USB_SERIAL_JTAG_CRC16_ERR_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. (RO)
PR
USB_SERIAL_JTAG_STUFF_ERR_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. (RO)
USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. (RO)
USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. (RO)
USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. (RO)
USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the
USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. (RO)
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
Register 24.18. USB_SERIAL_JTAG_INT_ENA_REG (0x0010)
A
A
UF N_R T_IN AD_ _EN
N
NA
A
_E
EN
_E
INT
INT
T_
INT
PK A
US SERI JTA N_TO S_R _PAY AD_
A
RC _ERR T_EN 1_IN
NA
_IN _EN
T_
JTA T_E REC T_E
LO
LO
_E
P
_IN ENA
T
IN
A
E
AY
NA
INT
V_
_
JTA SOF _OU PTY_
_P
NA
_E
PID _ERR INT_
H_
E
G_ T_EP ZERO
EC
T
_E
ES
IN
US
EM
IAL AG_ B_B ZER
NA
T_
_
NT
C1 RR_
FL
_
_
_
SE L_JT _SER L_IN
_ I
IN_
L_ G_O _EP2
E
E
R
U
F_
K
_IN
G_ _ER
IAL
6
G_
AG RIA
5
ER _JTA OUT
U
CR
S
E
ST
_C
U
S
I
G_
G_
G_
G_
_
G_
G
AG
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
T
T
J
J
_
_
_
_
_
L_
_
_
L_
AL
AL
AL
AL
AL
AL
AL
RY
A
RIA
RIA
US SERI
ER
d)
E
rve
S
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
se
US
US
US
US
(re
31 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA The interrupt enable bit for the
A
USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. (R/W)
USB_SERIAL_JTAG_SOF_INT_ENA The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT
interrupt. (R/W)
IN
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. (R/W)
IM
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. (R/W)
USB_SERIAL_JTAG_PID_ERR_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_PID_ERR_INT interrupt. (R/W)
EL
USB_SERIAL_JTAG_CRC5_ERR_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. (R/W)
USB_SERIAL_JTAG_CRC16_ERR_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. (R/W)
PR
USB_SERIAL_JTAG_STUFF_ERR_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. (R/W)
USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. (R/W)
USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. (R/W)
USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. (R/W)
USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the
USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. (R/W)
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
Register 24.19. USB_SERIAL_JTAG_INT_CLR_REG (0x0014)
UF N_R T_IN AD_ _CLR
LR
LR
_C
LR
_C
INT
INT
_C
INT
INT
PK R
US SERI JTA N_TO S_R _PAY AD_
LR
_IN _CL
T_
JTA T_C REC T_C
_
LO
LO
P1
_C
LR
T
IN
R
E
AY
INT
V_
CL
_
JTA SOF _OU PTY_
ID ERR_ T_C
_IN _CL
_P
H_
_
CL
E
INT
G_ T_EP ZERO
EC
_IN
INT
ES
US
EM
IAL AG_ B_B ZER
T_
LR
T_
C1 RR_
R
FL
_
R
_
_
SE L_JT _SER L_IN
IN_
E
L_ G_O _EP2
E
E
R
U
6_
F_
K
_IN
G_ _ER
IAL
_
G_
G RIA
C5
ER _JTA OUT
U
CR
R
S
E
ST
_C
U
_P
S
I
G_
G_
G_
_
G_
G
RIA TAG
AG
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
US SERI JTA
J T
J
_
_
_
_
_
L_
L_
_
L_
AL
AL
AL
AL
AL
AL
RY
A
A
RIA
US SERI
ER
d)
E
rve
S
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
B_
se
US
US
US
US
(re
31 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR Set this bit to clear the
A
USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. (WT)
USB_SERIAL_JTAG_SOF_INT_CLR Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT
interrupt. (WT)
IN
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. (WT)
IM
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. (WT)
USB_SERIAL_JTAG_PID_ERR_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_PID_ERR_INT interrupt. (WT)
EL
USB_SERIAL_JTAG_CRC5_ERR_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. (WT)
USB_SERIAL_JTAG_CRC16_ERR_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. (WT)
PR
USB_SERIAL_JTAG_STUFF_ERR_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. (WT)
USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. (WT)
USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. (WT)
USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. (WT)
USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR Set this bit to clear the
USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. (WT)
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24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
Register 24.20. USB_SERIAL_JTAG_DATE_REG (0x0080)
E
AT
_D
G
TA
_J
AL
RI
SE
B_
US
31 0
0x2007300 Reset
USB_SERIAL_JTAG_DATE Version control register. (R/W)
A RY
IN
IM
EL
PR
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25 Two-wire Automotive Interface (TWAI)
25 Twowire Automotive Interface (TWAI)
The Two-wire Automotive Interface (TWAI® ) is a multi-master, multi-cast communication protocol with functions
such as error detection and signaling and inbuilt message priorities and arbitration. The TWAI protocol is suited
for automotive and industrial applications (see Section 25.2 for more details).
ESP32-C3 contains a TWAI controller that can be connected to the TWAI bus via an external transceiver. The
TWAI controller contains numerous advanced features, and can be utilized in a wide range of use cases such as
automotive products, industrial automation controls, building automation, etc.
25.1 Features
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The TWAI controller on ESP32-C3 supports the following features:
• Compatible with ISO 11898-1 protocol (CAN Specification 2.0)
• Supports Standard Frame Format (11-bit ID) and Extended Frame Format (29-bit ID)
• Bit rates from 1 Kbit/s to 1 Mbit/s
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• Multiple modes of operation
– Normal
– Listen-only (no influence on bus)
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– Self-test (no acknowledgment required during data transmission)
• 64-byte Receive FIFO
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• Special transmissions
– Single-shot transmissions (does not automatically re-transmit upon error)
– Self Reception (the TWAI controller transmits and receives messages simultaneously)
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• Acceptance Filter (supports single and dual filter modes)
• Error detection and handling
– Error Counters
– Configurable Error Warning Limit
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– Error Code Capture
– Arbitration Lost Capture
25.2 Functional Protocol
25.2.1 TWAI Properties
The TWAI protocol connects two or more nodes in a bus network, and allows nodes to exchange messages in a
latency bounded manner. A TWAI bus has the following properties.
Single Channel and NonReturntoZero: The bus consists of a single channel to carry bits, and thus
communication is half-duplex. Synchronization is also implemented in this channel, so extra channels (e.g., clock
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or enable) are not required. The bit stream of a TWAI message is encoded using the Non-Return-to-Zero (NRZ)
method.
Bit Values: The single channel can either be in a dominant or recessive state, representing a logical 0 and a
logical 1 respectively. A node transmitting data in a dominant state always overrides the other node transmitting
data in a recessive state. The physical implementation on the bus is left to the application level to decide (e.g.,
differential pair or a single wire).
Bit Stuffing: Certain fields of TWAI messages are bit-stuffed. A transmitter that transmits five consecutive bits of
the same value (e.g., dominant value or recessive value) should automatically insert a complementary bit.
Likewise, a receiver that receives five consecutive bits should treat the next bit as a stuffed bit. Bit stuffing is
applied to the following fields: SOF, arbitration field, control field, data field, and CRC sequence (see Section
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25.2.2 for more details).
Multicast: All nodes receive the same bits as they are connected to the same bus. Data is consistent across all
nodes unless there is a bus error (see Section 25.2.3 for more details).
Multimaster: Any node can initiate a transmission. If a transmission is already ongoing, a node will wait until the
current transmission is over before initiating a new transmission.
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Message Priority and Arbitration: If two or more nodes simultaneously initiate a transmission, the TWAI
protocol ensures that one node will win arbitration of the bus. The arbitration field of the message transmitted by
each node is used to determine which node will win arbitration.
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Error Detection and Signaling: Each node actively monitors the bus for errors, and signals the detected errors
by transmitting an error frame.
Fault Confinement: Each node maintains a set of error counters that are incremented/decremented according
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to a set of rules. When the error counters surpass a certain threshold, the node will automatically eliminate itself
from the network by switching itself off.
Configurable Bit Rate: The bit rate for a single TWAI bus is configurable. However, all nodes on the same bus
must operate at the same bit rate.
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Transmitters and Receivers: At any point in time, a TWAI node can either be a transmitter or a receiver.
• A node generating a message is a transmitter. The node remains a transmitter until the bus is idle or until
the node loses arbitration. Please note that nodes that have not lost arbitration can all be transmitters.
• All nodes that are not transmitters are receivers.
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25.2.2 TWAI Messages
TWAI nodes use messages to transmit data, and signal errors to other nodes when detecting errors on the bus.
Messages are split into various frame types, and some frame types will have different frame formats.
The TWAI protocol has of the following frame types:
• Data frame
• Remote frame
• Error frame
• Overload frame
• Interframe space
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The TWAI protocol has the following frame formats:
• Standard Frame Format (SFF) that uses a 11-bit identifier
• Extended Frame Format (EFF) that uses a 29-bit identifier
25.2.2.1 Data Frames and Remote Frames
Data frames are used by nodes to send data to other nodes, and can have a payload of 0 to 8 data bytes.
Remote frames are used for nodes to request a data frame with the same identifier from other nodes, and thus
they do not contain any data bytes. However, data frames and remote frames share many fields. Figure 25-1
illustrates the fields and sub-fields of different frames and formats.
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Figure 251. Bit Fields in Data Frames and Remote Frames
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Arbitration Field
When two or more nodes transmits a data or remote frame simultaneously, the arbitration field is used to
determine which node will win arbitration of the bus. In the arbitration field, if a node transmits a recessive bit
while detects a dominant bit, this indicates that another node has overridden its recessive bit. Therefore, the node
transmitting the recessive bit has lost arbitration of the bus and should immediately switch to be a receiver.
The arbitration field primarily consists of a frame identifier that is transmitted from the most significant bit first.
Given that a dominant bit represents a logical 0, and a recessive bit represents a logical 1:
• A frame with the smallest ID value always wins arbitration.
• Given the same ID and format, data frames always prevail over remote frames due to their RTR bits being
dominant.
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• Given the same first 11 bits of ID, a Standard Format Data Frame always prevails over an Extended Format
Data Frame due to its SRR bits being recessive.
Control Field
The control field primarily consists of the DLC (Data Length Code) which indicates the number of payload data
bytes for a data frame, or the number of requested data bytes for a remote frame. The DLC is transmitted from
the most significant bit first.
Data Field
The data field contains the actual payload data bytes of a data frame. Remote frames do not contain any data
field.
CRC Field
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The CRC field primarily consists of a CRC sequence. The CRC sequence is a 15-bit cyclic redundancy code
calculated form the de-stuffed contents (everything from the SOF to the end of the data field) of a data or remote
frame.
ACK Field
The ACK field primarily consists of an ACK Slot and an ACK Delim. The ACK field indicates that the receiver has
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received an effective message from the transmitter.
Table 251. Data Frames and Remote Frames in SFF and EFF
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Data/Remote Frames Description
SOF The SOF (Start of Frame) is a single dominant bit used to synchronize nodes on
the bus.
Base ID The Base ID (ID.28 to ID.18) is the 11-bit identifier for SFF, or the first 11 bits of
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the 29-bit identifier for EFF.
RTR The RTR (Remote Transmission Request) bit indicates whether the message is a
data frame (dominant) or a remote frame (recessive). This means that a remote
frame will always lose arbitration to a data frame if they have the same ID.
SRR The SRR (Substitute Remote Request) bit is transmitted in EFF to substitute for
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the RTR bit at the same position in SFF.
IDE The IDE (Identifier Extension) bit indicates whether the message is SFF (dominant)
or EFF (recessive). This means that a SFF frame will always win arbitration over
an EFF frame if they have the same Base ID.
Extd ID The Extended ID (ID.17 to ID.0) is the remaining 18 bits of the 29-bit identifier for
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EFF.
r1 The r1 bit (reserved bit 1) is always dominant.
r0 The r0 bit (reserved bit 0) is always dominant.
DLC The DLC (Data Length Code) is 4-bit long and should contain any value from 0
to 8. Data frames use the DLC to indicate the number of data bytes in the data
frame. Remote frames used the DLC to indicate the number of data bytes to
request from another node.
Data Bytes The data payload of data frames. The number of bytes should match the value
of DLC. Data byte 0 is transmitted first, and each data byte is transmitted from
the most significant bit first.
CRC Sequence The CRC sequence is a 15-bit cyclic redundancy code.
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Data/Remote Frames Description
CRC Delim The CRC Delim (CRC Delimiter) is a single recessive bit that follows the CRC
sequence.
ACK Slot The ACK Slot (Acknowledgment Slot) is intended for receiver nodes to indicate
that the data or remote frame was received without any issue. The transmitter
node will send a recessive bit in the ACK Slot and receiver nodes should override
the ACK Slot with a dominant bit if the frame was received without errors.
ACK Delim The ACK Delim (Acknowledgment Delimiter) is a single recessive bit.
EOF The EOF (End of Frame) marks the end of a data or remote frame, and consists
of seven recessive bits.
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25.2.2.2 Error and Overload Frames
Error Frames
Error frames are transmitted when a node detects a bus error. Error frames notably consist of an Error Flag which
is made up of six consecutive bits of the same value, thus violating the bit-stuffing rule. Therefore, when a
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particular node detects a bus error and transmits an error frame, all other nodes will then detect a stuff error and
transmit their own error frames in response. This has the effect of propagating the detection of a bus error across
all nodes on the bus.
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When a node detects a bus error, it will transmit an error frame starting from the next bit. However, if the type of
bus error was a CRC error, then the error frame will start at the bit following the ACK Delim (see Section 25.2.3
for more details). The following Figure 25-2 shows different fields of an error frame:
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Figure 252. Fields of an Error Frame
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Table 252. Error Frame
Error Frame Description
Error Flag The Error Flag has two forms, the Active Error Flag consisting of 6 domi-
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nant bits and the Passive Error Flag consisting of 6 recessive bits (unless
overridden by dominant bits of other nodes). Active Error Flags are sent
by error active nodes, whilst Passive Error Flags are sent by error passive
nodes.
Error Flag Superposition The Error Flag Superposition field meant to allow for other nodes on the
bus to transmit their respective Active Error Flags. The superposition field
can range from 0 to 6 bits, and ends when the first recessive bit is detected
(i.e., the first it of the Delimiter).
Error Delimeter The Delimiter field marks the end of the error/overload frame, and consists
of 8 recessive bits.
Overload Frames
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An overload frame has the same bit fields as an error frame containing an Active Error Flag. The key difference is
in the cases that can trigger the transmission of an overload frame. Figure 25-3 below shows the bit fields of an
overload frame.
Figure 253. Fields of an Overload Frame
Table 253. Overload Frame
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Overload Flag Description
Overload Flag Consists of 6 dominant bits. Same as an Active Error Flag.
Overload Flag Superposition Allows for the superposition of Overload Flags from other nodes, similar to an
Error Flag Superposition.
Overload Delimiter Consists of 8 recessive bits. Same as an Error Delimiter.
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Overload frames will be transmitted under the following cases:
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1. A receiver requires a delay of the next data or remote frame.
2. A dominant bit is detected at the first and second bit of intermission.
3. A dominant bit is detected at the eighth (last) bit of an Error Delimiter. Note that in this case, TEC and REC
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will not be incremented (see Section 25.2.3 for more details).
Transmitting an overload frame due to one of the above cases must also satisfy the following rules:
• The start of an overload frame due to case 1 is only allowed to be started at the first bit time of an expected
intermission.
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• The start of an overload frame due to case 2 and 3 is only allowed to be started one bit after detecting the
dominant bit.
• A maximum of two overload frames may be generated in order to delay the transmission of the next data or
remote frame.
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25.2.2.3 Interframe Space
The Interframe Space acts as a separator between frames. Data frames and remote frames must be separated
from preceding frames by an Interframe Space, regardless of the preceding frame’s type (data frame, remote
frame, error frame, or overload frame). However, error frames and overload frames do not need to be separated
from preceding frames.
Figure 25-4 shows the fields within an Interframe Space:
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Figure 254. The Fields within an Interframe Space
Table 254. Interframe Space
Interframe Space Description
Intermission The Intermission consists of 3 recessive bits.
Suspend Transmission An Error Passive node that has just transmitted a message must include
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a Suspend Transmission field. This field consists of 8 recessive bits. Error
Active nodes should not include this field.
Bus Idle The Bus Idle field is of arbitrary length. Bus Idle ends when an SOF is
transmitted. If a node has a pending transmission, the SOF should be
transmitted at the first bit following Intermission.
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25.2.3 TWAI Errors IN
25.2.3.1 Error Types
Bus Errors in TWAI are categorized into the following types:
Bit Error
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A Bit Error occurs when a node transmits a bit value (i.e., dominant or recessive) but the opposite bit is detected
(e.g., a dominant bit is transmitted but a recessive is detected). However, if the transmitted bit is recessive and is
located in the Arbitration Field or ACK Slot or Passive Error Flag, then detecting a dominant bit will not be
considered a Bit Error.
Stuff Error
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A stuff error is detected when six consecutive bits of the same value are detected (which violats the bit-stuffing
encoding rules).
CRC Error
A receiver of a data or remote frame will calculate CRC based on the bits it has received. A CRC error occurs
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when the CRC calculated by the receiver does not match the CRC sequence in the received data or remote
Frame.
Format Error
A Format Error is detected when a format-fixed bit field of a message contains an illegal bit. For example, the r1
and r0 fields must be dominant.
ACK Error
An ACK Error occurs when a transmitter does not detect a dominant bit at the ACK Slot.
25.2.3.2 Error States
TWAI nodes implement fault confinement by each maintaining two error counters, where the counter values
determine the error state. The two error counters are known as the Transmit Error Counter (TEC) and Receive
Error Counter (REC). TWAI has the following error states.
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Error Active
An Error Active node is able to participate in bus communication and transmit an Active Error Flag when it
detects an error.
Error Passive
An Error Passive node is able to participate in bus communication, but can only transmit an Passive Error Flag
when it detects an error. Error Passive nodes that have transmitted a data or remote frame must also include the
Suspend Transmission field in the subsequent Interframe Space.
Bus Off
A Bus Off node is not permitted to influence the bus in any way (i.e., is not allowed to transmit data).
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25.2.3.3 Error Counters
The TEC and REC are incremented/decremented according to the following rules. Note that more than one
rule can apply to a given message transfer.
1. When a receiver detects an error, the REC is increased by 1, except when the detected error was a Bit
Error during the transmission of an Active Error Flag or an Overload Flag.
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2. When a receiver detects a dominant bit as the first bit after sending an Error Flag, the REC is increased by 8.
3. When a transmitter sends an Error Flag, the TEC is increased by 8. However, the following scenarios are
exempt from this rule:
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• A transmitter is Error Passive since the transmitter generates an Acknowledgment Error because of
not detecting a dominant bit in the ACK Slot, while detecting a dominant bit when sending a passive
error flag. In this case, the TEC should not be increased.
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• A transmitter transmits an Error Flag due to a Stuff Error during Arbitration. If the stuffed bit should
have been recessive but was monitored as dominant, then the TEC should not be increased.
4. If a transmitter detects a Bit Error whilst sending an Active Error Flag or Overload Flag, the TEC is increased
by 8.
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5. If a receiver detects a Bit Error while sending an Active Error Flag or Overload Flag, the REC is increased by
8.
6. A node can tolerate up to 7 consecutive dominant bits after sending an Active/Passive Error Flag, or
Overload Flag. After detecting the 14th consecutive dominant bit (when sending an Active Error Flag or
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Overload Flag), or the 8th consecutive dominant bit following a Passive Error Flag, a transmitter will
increase its TEC by 8 and a receiver will increase its REC by 8. Every additional 8 consecutive dominant
bits will also increase the TEC (for transmitters) or REC (for receivers) by 8 as well.
7. When a transmitter has transmitted a message (getting ACK and no errors until the EOF is complete), the
TEC is decremented by 1, unless the TEC is already at 0.
8. When a receiver successfully receives a message (no errors before ACK Slot, and successful sending of
ACK), the REC is decremented.
• If the REC is between 1 and 127, the REC will be decremented by 1.
• If the REC is greater than 127, the REC will be set to 127.
• If the REC is 0, the REC will remain 0.
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9. A node becomes Error Passive when its TEC and/or REC is greater than or equal to 128. Though the node
becomes Error Passive, it still sends an Active Error Flag. Note that once the REC has reached to 128, any
further increases to its value are invalid until the REC returns to a value less than 128.
10. A node becomes Bus Off when its TEC is greater than or equal to 256.
11. An Error Passive node becomes Error Active when both the TEC and REC are less than or equal to 127.
12. A Bus Off node can become Error Active (with both its TEC and REC reset to 0) after it monitors 128
occurrences of 11 consecutive recessive bits on the bus.
25.2.4 TWAI Bit Timing
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25.2.4.1 Nominal Bit
The TWAI protocol allows a TWAI bus to operate at a particular bit rate. However, all nodes within a TWAI bus
must operate at the same bit rate.
• The Nominal Bit Rate is defined as the number of bits transmitted per second.
• The Nominal Bit Time is defined as 1/Nominal Bit Rate.
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A single Nominal Bit Time is divided into multiple segments, and each segment is made up of multiple Time
Quanta. A Time Quantum is a minimum unit of time, and is implemented as some form of prescaled clock signal
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in each node. Figure 25-5 illustrates the segments within a single Nominal Bit Time.
TWAI controllers will operate in time steps of one Time Quanta where the state of the TWAI bus is analyzed. If the
bus states in two consecutive Time Quantas are different (i.e., recessive to dominant or vice versa), it means an
edge is generated. The intersection of PBS1 and PBS2 is considered the Sample Point and the sampled bus
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value is considered the value of that bit.
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Figure 255. Layout of a Bit
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Table 255. Segments of a Nominal Bit Time
Segment Description
SS The SS (Synchronization Segment) is 1 Time Quantum long. If all nodes are perfectly
synchronized, the edge of a bit will lie in the SS.
PBS1 PBS1 (Phase Buffer Segment 1) can be 1 to 16 Time Quanta long. PBS1 is meant
to compensate for the physical delay times within the network. PBS1 can also be
lengthened for synchronization purposes.
PBS2 PBS2 (Phase Buffer Segment 2) can be 1 to 8 Time Quanta long. PBS2 is meant to
compensate for the information processing time of nodes. PBS2 can also be shortened
for synchronization purposes.
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25.2.4.2 Hard Synchronization and Resynchronization
Due to clock skew and jitter, the bit timing of nodes on the same bus may become out of phase. Therefore, a bit
edge may come before or after the SS. To ensure that the internal bit timing clocks of each node are kept in
phase, TWAI has various methods of synchronization. The Phase Error “e” is measured in the number of Time
Quanta and relative to the SS.
• A positive Phase Error (e > 0) is when the edge lies after the SS and before the Sample Point (i.e., the edge
is late).
• A negative Phase Error (e < 0) is when the edge lies after the Sample Point of the previous bit and before
SS (i.e., the edge is early).
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To correct for Phase Errors, there are two forms of synchronization, known as Hard Synchronization and
Resynchronization. Hard Synchronization and Resynchronization obey the following rules:
• Only one synchronization may occur in a single bit time.
• Synchronizations only occurs on recessive to dominant edges.
Hard Synchronization
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Hard Synchronization occurs on the recessive to dominant (i.e., the first SOF bit after Bus Idle) edges when the
bus is idle. All nodes will restart their internal bit timings so that the recessive to dominant edge lies within the SS
of the restarted bit timing.
Resynchronization
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Resynchronization occurs on recessive to dominant edges when the bus is not idel. If the edge has a positive
Phase Error (e > 0), PBS1 is lengthened by a certain number of Time Quanta. If the edge has a negative Phase
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Error (e < 0), PBS2 will be shortened by a certain number of Time Quanta.
The number of Time Quanta to lengthen or shorten depends on the magnitude of the Phase Error, and is also
limited by the Synchronization Jump Width (SJW) value which is programmable.
• When the magnitude of the Phase Error (e) is less than or equal to the SJW, PBS1/PBS2 are
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lengthened/shortened by the e number of Time Quanta. This has a same effect as Hard Synchronization.
• When the magnitude of the Phase Error is greater to the SJW, PBS1/PBS2 are lengthened/shortened by
the SJW number of Time Quanta. This means it may take multiple bits of synchronization before the Phase
Error is entirely corrected.
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25.3 Architectural Overview
The major functional blocks of the TWAI controller are shown in Figure 25-6.
25.3.1 Registers Block
The ESP32-C3 CPU accesses peripherals using 32-bit aligned words. However, the majority of registers in the
TWAI controller only contain useful data at the least significant byte (bits [7:0]). Therefore, in these registers, bits
[31:8] are ignored on writes, and return 0 on reads.
Configuration Registers
The configuration registers store various configuration items for the TWAI controller such as bit rates, operation
mode, Acceptance Filter, etc. Configuration registers can only be modified whilst the TWAI controller is in Reset
Mode (See Section 25.4.1).
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Figure 256. TWAI Overview Diagram
Command Registers
The command register is used by the CPU to drive the TWAI controller to initiate certain actions such as
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transmitting a message or clearing the Receive Buffer. The command register can only be modified when the
TWAI controller is in Operation Mode (see section 25.4.1).
Interrupt & Status Registers
The interrupt register indicates what events have occurred in the TWAI controller (each event is represented by a
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separate bit). The status register indicates the current status of the TWAI controller.
Error Management Registers
The error management registers include error counters and capture registers. The error counter registers
represent TEC and REC values. The capture registers will record information about instances where TWAI
controller detects a bus error, or when it loses arbitration.
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Transmit Buffer Registers
The transmit buffer is a 13-byte buffer used to store a TWAI message to be transmitted.
Receive Buffer Registers
The Receive Buffer is a 13-byte buffer which stores a single message. The Receive Buffer acts as a window of
Receive FIFO, whose first message will be mapped into the Receive Buffer.
Note that the Transmit Buffer registers, Receive Buffer registers, and the Acceptance Filter registers share the
same address range (offset 0x0040 to 0x0070). Their access is governed by the following rules:
• When the TWAI controller is in Reset Mode, all reads and writes to the address range maps to the
Acceptance Filter registers.
• When the TWAI controller is in Operation Mode:
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– All reads to the address range maps to the Receive Buffer registers.
– All writes to the address range maps to the Transmit Buffer registers.
25.3.2 Bit Stream Processor
The Bit Stream Processing (BSP) module frames data from the Transmit Buffer (e.g. bit stuffing and additional
CRC fields) and generates a bit stream for the Bit Timing Logic (BTL) module. At the same time, the BSP module
is also responsible for processing the received bit stream (e.g., de-stuffing and verifying CRC) from the BTL
module and placing the message into the Receive FIFO. The BSP will also detect errors on the TWAI bus and
report them to the Error Management Logic (EML).
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25.3.3 Error Management Logic
The Error Management Logic (EML) module updates the TEC and REC, records error information like error types
and positions, and updates the error state of the TWAI controller such that the BSP module generates the correct
Error Flags. Furthermore, this module also records the bit position when the TWAI controller loses
arbitration.
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25.3.4 Bit Timing Logic
The Bit Timing Logic (BTL) module transmits and receives messages at the configured bit rate. The BTL module
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also handles bit timing synchronization so that communication remains stable. A single bit time consists of
multiple programmable segments that allows users to set the length of each segment to account for factors such
as propagation delay and controller processing time, etc.
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25.3.5 Acceptance Filter
The Acceptance Filter is a programmable message filtering unit that allows the TWAI controller to accept or reject
a received message based on the message’s ID field. Only accepted messages will be stored in the Receive
FIFO. The Acceptance Filter’s registers can be programmed to specify a single filter, or two separate filters (dual
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filter mode).
25.3.6 Receive FIFO
The Receive FIFO is a 64-byte buffer (inside the TWAI controller) that stores received messages accepted by the
Acceptance Filter. Messages in the Receive FIFO can vary in size (between 3 to 13-bytes). When the Receive
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FIFO is full (or does not have enough space to store the next received message in its entirety), the Overrun
Interrupt will be triggered, and any subsequent received messages will be lost until adequate space is cleared in
the Receive FIFO. The first message in the Receive FIFO will be mapped to the 13-byte Receive Buffer until that
message is cleared (using the Release Receive Buffer command bit). After being cleared, the Receive Buffer will
map to the next message in the Receive FIFO, and the space occupied by the previous message in the Receive
FIFO can be used to receive new messages.
25.4 Functional Description
25.4.1 Modes
The ESP32-C3 TWAI controller has two working modes: Reset Mode and Operation Mode. Reset Mode and
Operation Mode are entered by setting or clearing the TWAI_RESET_MODE bit.
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25.4.1.1 Reset Mode
Entering Reset Mode is required in order to modify the various configuration registers of the TWAI controller.
When entering Reset Mode, the TWAI controller is essentially disconnected from the TWAI bus. When in Reset
Mode, the TWAI controller will not be able to transmit any messages (including error signals). Any transmission in
progress is immediately terminated. Likewise, the TWAI controller will not be able to receive any messages
either.
25.4.1.2 Operation Mode
In operation mode, the TWAI controller connects to the bus and write-protect all configuration registers to ensure
consistency during operation. When in Operation Mode, the TWAI controller can transmit and receive messages
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(including error signaling) depending on which operation sub-mode the TWAI controller was configured with. The
TWAI controller supports the following operation sub-modes:
• Normal Mode: The TWAI controller can transmit and receive messages including error signals (such as
error and overload Frames).
• Selftest Mode: Self-test mode is similar to normal Mode, but the TWAI controller will consider the
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transmission of a data or RTR frame successful and do not generate an ACK error even if it was not
acknowledged. This is commonly used when the TWAI controller does self-test.
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• Listenonly Mode: The TWAI controller will be able to receive messages, but will remain completely
passive on the TWAI bus. Thus, the TWAI controller will not be able to transmit any messages,
acknowledgments, or error signals. The error counters will remain frozen. This mode is useful for TWAI bus
monitoring.
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Note that when exiting Reset Mode (i.e., entering Operation Mode), the TWAI controller must wait for 11
consecutive recessive bits to occur before being able to fully connect the TWAI bus (i.e., be able to transmit or
receive).
25.4.2 Bit Timing
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The operating bit rate of the TWAI controller must be configured whilst the TWAI controller is in Reset Mode. The
bit rate is configured using TWAI_BUS_TIMING_0_REG and TWAI_BUS_TIMING_1_REG, and the two registers
contain the following fields:
The following Table 25-6 illustrates the bit fields of TWAI_BUS_TIMING_0_REG.
PR
Table 256. Bit Information of TWAI_BUS_TIMING_0_REG (0x18)
Bit 31-16 Bit 15 Bit 14 Bit 13 Bit 12 ...... Bit 1 Bit 0
Reserved SJW.1 SJW.0 Reserved BRP.12 ...... BRP.1 BRP.0
Notes:
• BRP: The TWAI Time Quanta clock is derived from the APB clock that is usually 80 MHz. The Baud Rate
Prescaler (BRP) field is used to define the prescaler according to the equation below, where tT q is the Time
Quanta clock cycle and tCLK is APB clock cycle:
tT q = 2 × tCLK × (212 × BRP.12 + 211 × BRP.11 + ... + 21 × BRP.1 + 20 × BRP.0 + 1)
• SJW: Synchronization Jump Width (SJW) is configured in SJW.0 and SJW.1 where SJW = (2 x SJW.1 +
SJW.0 + 1)�
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The following Table 25-7 illustrates the bit fields of TWAI_BUS_TIMING_1_REG.
Table 257. Bit Information of TWAI_BUS_TIMING_1_REG (0x1c)
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved SAM PBS2.2 PBS2.1 PBS2.0 PBS1.3 PBS1.2 PBS1.1 PBS1.0
Notes:
• PBS1: The number of Time Quanta in Phase Buffer Segment 1 is defined according to the following
equation: (8 x PBS1.3 + 4 x PBS1.2 + 2 x PBS1.1 + PBS1.0 + 1)�
• PBS2: The number of Time Quanta in Phase Buffer Segment 2 is defined according to the following
equation: (4 x PBS2.2 + 2 x PBS2.1 + PBS2.0 + 1)�
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• SAM: Enables triple sampling if set to 1. This is useful for low/medium speed buses to filter spikes on the
bus line.
25.4.3 Interrupt Management
The ESP32-C3 TWAI controller provides eight interrupts, each represented by a single bit in the
A
TWAI_INT_RAW_REG. For a particular interrupt to be triggered, the corresponding enable bit in TWAI_INT
ENA_REG must be set.
IN
The TWAI controller provides the following interrupts:
• Receive Interrupt
• Transmit Interrupt
IM
• Error Warning Interrupt
• Data Overrun Interrupt
• Error Passive Interrupt
• Arbitration Lost Interrupt
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• Bus Error Interrupt
• Bus Status Interrupt
The TWAI controller’s interrupt signal to the interrupt matrix will be asserted whenever one or more interrupt bits
are set in the TWAI_INT_RAW_REG, and deasserted when all bits in TWAI_INT_RAW_REG are cleared. The
PR
majority of interrupt bits in TWAI_INT_RAW_REG are automatically cleared when the register is read, except for
the Receive Interrupt which can only be cleared when all the messages are released by setting the
TWAI_RELEASE_BUF bit.
25.4.3.1 Receive Interrupt (RXI)
The Receive Interrupt (RXI) is asserted whenever the TWAI controller has received messages that are pending to
be read from the Receive Buffer (i.e., when TWAI_RX_MESSAGE_CNT_REG > 0). Pending received messages
includes valid messages in the Receive FIFO and also overrun messages. The RXI will not be deasserted until all
pending received messages are cleared using the TWAI_RELEASE_BUF command bit.
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25.4.3.2 Transmit Interrupt (TXI)
The Transmit Interrupt (TXI) is triggered whenever Transmit Buffer becomes free, indicating another message can
be loaded into the Transmit Buffer to be transmitted. The Transmit Buffer becomes free under the following
scenarios:
• A message transmission has completed successfully, i.e., acknowledged without any errors. (Any failed
messages will automatically be resent.)
• A single shot transmission has completed (successfully or unsuccessfully, indicated by the
TWAI_TX_COMPLETE bit).
• A message transmission was aborted using the TWAI_ABORT_TX command bit.
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25.4.3.3 Error Warning Interrupt (EWI)
The Error Warning Interrupt (EWI) is triggered whenever there is a change to the TWAI_ERR_ST and
TWAI_BUS_OFF_ST bits of the TWAI_STATUS_REG (i.e., transition from 0 to 1 or vice versa). Thus, an EWI
could indicate one of the following events, depending on the values TWAI_ERR_ST and TWAI_BUS_OFF_ST at
A
the moment when the EWI is triggered.
• If TWAI_ERR_ST = 0 and TWAI_BUS_OFF_ST = 0: IN
– If the TWAI controller was in the Error Active state, it indicates both the TEC and REC have returned
below the threshold value set by TWAI_ERR_WARNING_LIMIT_REG.
– If the TWAI controller was previously in the Bus Off Recovery state, it indicates that Bus Recovery has
completed successfully.
IM
• If TWAI_ERR_ST = 1 and TWAI_BUS_OFF_ST = 0: The TEC or REC error counters have exceeded the
threshold value set by TWAI_ERR_WARNING_LIMIT_REG.
• If TWAI_ERR_ST = 1 and TWAI_BUS_OFF_ST = 1: The TWAI controller has entered the BUS_OFF state
(due to the TEC >= 256).
EL
• If TWAI_ERR_ST = 0 and TWAI_BUS_OFF_ST = 1: The TWAI controller’s TEC has dropped below the
threshold value set by TWAI_ERR_WARNING_LIMIT_REG during BUS_OFF recovery.
25.4.3.4 Data Overrun Interrupt (DOI)
PR
The Data Overrun Interrupt (DOI) is triggered whenever the Receive FIFO has overrun. The DOI indicates that the
Receive FIFO is full and should be cleared immediately to prevent any further overrun messages.
The DOI is only triggered by the first message that causes the Receive FIFO to overrun (i.e., the transition from
the Receive FIFO not being full to the Receive FIFO overrunning). Any subsequent overrun messages will not
trigger the DOI again. The DOI could be triggered again when all received messages (valid or overrun) have been
cleared.
25.4.3.5 Error Passive Interrupt (TXI)
The Error Passive Interrupt (EPI) is triggered whenever the TWAI controller switches from Error Active to Error
Passive, or vice versa.
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25.4.3.6 Arbitration Lost Interrupt (ALI)
The Arbitration Lost Interrupt (ALI) is triggered whenever the TWAI controller is attempting to transmit a message
and loses arbitration. The bit position where the TWAI controller lost arbitration is automatically recorded in
Arbitration Lost Capture register (TWAI_ARB LOST CAP_REG). When the ALI occurs again, the Arbitration Lost
Capture register will no longer record new bit location until it is cleared (via CPU reading this register).
25.4.3.7 Bus Error Interrupt (BEI)
The Bus Error Interrupt (BEI) is triggered whenever TWAI controller detects an error on the TWAI bus. When a
bus error occurs, the Bus Error type and its bit position are automatically recorded in the Error Code Capture
register (TWAI_ERR_CODE_CAP_REG). When the BEI occurs again, the Error Code Capture register will no
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longer record new error information until it is cleared (via a read from the CPU).
25.4.3.8 Bus Status Interrupt (BSI)
The Bus Status Interrupt (BSI) is triggered whenever TWAI controller is switching between receive/transmit status
and idle status. When a BSI occurs, the current status of TWAI controller can be measured by reading
A
TWAI_RX_ST and TWAI_TX_ST in TWAI_STATUS_REG register.
25.4.4 Transmit and Receive Buffers
25.4.4.1 Overview of Buffers
IN
Table 258. Buffer Layout for Standard Frame Format and Extended Frame Format
IM
Standard Frame Format (SFF) Extended Frame Format (EFF)
TWAI Address Content TWAI Address Content
0x40 TX/RX frame information 0x40 TX/RX frame information
0x44 TX/RX identifier 1 0x44 TX/RX identifier 1
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0x48 TX/RX identifier 2 0x48 TX/RX identifier 2
0x4c TX/RX data byte 1 0x4c TX/RX identifier 3
0x50 TX/RX data byte 2 0x50 TX/RX identifier 4
0x54 TX/RX data byte 3 0x54 TX/RX data byte 1
0x58 TX/RX data byte 4 0x58 TX/RX data byte 2
PR
0x5c TX/RX data byte 5 0x5c TX/RX data byte 3
0x60 TX/RX data byte 6 0x60 TX/RX data byte 4
0x64 TX/RX data byte 7 0x64 TX/RX data byte 5
0x68 TX/RX data byte 8 0x68 TX/RX data byte 6
0x6c reserved 0x6c TX/RX data byte 7
0x70 reserved 0x70 TX/RX data byte 8
Table 25-8 illustrates the layout of the Transmit Buffer and Receive Buffer registers. Both the Transmit and
Receive Buffer registers share the same address space and are only accessible when the TWAI controller is in
Operation Mode. The CPU accesses Transmit Buffer registers for write operations, and Receive Buffer registers
for read operations . Both buffers share the exact same register layout and fields to represent a message
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(received or to be transmitted). The Transmit Buffer registers are used to configure a TWAI message to be
transmitted. The CPU would write to the Transmit Buffer registers specifying the message’s frame type, frame
format, frame ID, and frame data (payload). Once the Transmit Buffer is configured, the CPU would then initiate
the transmission by setting the TWAI_TX_REQ bit in TWAI_CMD_REG.
• For a self-reception request, set the TWAI_SELF_RX_REQ bit instead.
• For a single-shot transmission, set both the TWAI_TX_REQ and the TWAI_ABORT_TX simultaneously.
The Receive Buffer registers map the first message in the Receive FIFO. The CPU would read the Receive Buffer
registers to obtain the first message’s frame type, frame format, frame ID, and frame data (payload). Once the
message has been read from the Receive Buffer registers, the CPU can set the TWAI_RELEASE_BUF bit in
TWAI_CMD_REG to clear the Receive Buffer registers. If there are still messages in the Receive FIFO, the
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Receive Buffer registers will map the first message again.
25.4.4.2 Frame Information
The frame information is one byte long and specifies a message’s frame type, frame format, and length of data.
The frame information fields are shown in Table 25-9.
A
Table 259. TX/RX Frame Information (SFF/EFF)�TWAI Address 0x40
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved FF 1
RTR 2
X3
IN
X 3
DLC.3 4
DLC.2 4
DLC.1 4
DLC.04
Notes:
1. FF: The Frame Format (FF) bit specifies whether the message is Extended Frame Format (EFF) or Standard
IM
Frame Format (SFF). The message is EFF when FF bit is 1, and SFF when FF bit is 0.
2. RTR: The Remote Transmission Request (RTR) bit specifies whether the message is a data frame or a
remote frame. The message is a remote frame when the RTR bit is 1, and a data frame when the RTR bit is
0.
EL
3. X: Don’t care, can be any value.
4. DLC: The Data Length Code (DLC) field specifies the number of data bytes for a data frame, or the number
of data bytes to request in a remote frame. TWAI data frames are limited to a maximum payload of 8 data
bytes, and thus the DLC should range anywhere from 0 to 8.
PR
25.4.4.3 Frame Identifier
The Frame Identifier fields is two-byte (11-bit) long if the message is SFF, and four-byte (29-bit) long if the
message is EFF.
The Frame Identifier fields for an SFF (11-bit) message is shown in Table 25-10 ~ 25-11.
Table 2510. TX/RX Identifier 1 (SFF); TWAI Address 0x44
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3
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Table 2511. TX/RX Identifier 2 (SFF); TWAI Address 0x48
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 2 2 2
Reserved ID.2 ID.1 ID.0 X X X X X2
Notes:
1. Don’t care. Recommended to be compatible with receive buffer (i.e., set to RTR ) in case of using the self
reception functionality (or together with self-test functionality).
2. Don’t care. Recommended to be compatible with receive buffer (i.e., set to 0 ) in case of using the self
reception functionality (or together with self-test functionality).
The Frame Identifier fields for an EFF (29-bits) message is shown in Table 25-12 ~ 25-15.
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Table 2512. TX/RX Identifier 1 (EFF); TWAI Address 0x44
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21
A
Table 2513. TX/RX Identifier 2 (EFF); TWAI Address 0x48
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved ID.20 ID.19 ID.18
IN
ID.17 ID.16 ID.15 ID.14 ID.13
Table 2514. TX/RX Identifier 3 (EFF); TWAI Address 0x4c
IM
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved ID.12 ID.11 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5
Table 2515. TX/RX Identifier 4 (EFF); TWAI Address 0x50
EL
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 2
Reserved ID.4 ID.3 ID.2 ID.1 ID.0 X X X2
Notes:
1. Don’t care. Recommended to be compatible with receive buffer (i.e., set to RTR ) in case of using the self
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reception functionality (or together with self-test functionality).
2. Don’t care. Recommended to be compatible with receive buffer (i.e., set to 0 ) in case of using the self
reception functionality (or together with self-test functionality).
25.4.4.4 Frame Data
The Frame Data field contains the payloads of transmitted or received data frame, and can range from 0 to eight
bytes. The number of valid bytes should be equal to the DLC. However, if the DLC is larger than eight bytes, the
number of valid bytes would still be limited to eight. Remote frames do not have data payloads, so their Frame
Data fields will be unused.
For example, when transmitting a data frame with five bytes, the CPU should write five to the DLC field, and then
write data to the corresponding register of the first to the fifth data field. Likewise, when the CPU receives a data
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frame with a DLC of five data bytes, only the first to the fifth data byte will contain valid payload data for the CPU
to read.
25.4.5 Receive FIFO and Data Overruns
The Receive FIFO is a 64-byte internal buffer used to store received messages in First In First Out order. A single
received message can occupy between 3 to 13 bytes of space in the Receive FIFO, and their endianness is
identical to the register layout of the Receive Buffer registers. The Receive Buffer registers are mapped to the
bytes of the first message in the Receive FIFO.
When the TWAI controller receives a message, it will increment the value of TWAI_RX_MESSAGE_COUNTER up
to a maximum of 64. If there is adequate space in the Receive FIFO, the message contents will be written into
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the Receive FIFO. Once a message has been read from the Receive Buffer, the TWAI_RELEASE_BUF bit should
be set. This will decrement TWAI_RX_MESSAGE_COUNTER and free the space occupied by the first message
in the Receive FIFO. The Receive Buffer will then map to the next message in the Receive FIFO.
A data overrun occurs when the TWAI controller receives a message, but the Receive FIFO lacks the adequate
free space to store the received message in its entirety (either due to the message contents being larger than the
free space in the Receive FIFO, or the Receive FIFO being completely full).
A
When a data overrun occurs:
• The free space left in the Receive FIFO is filled with the partial contents of the overrun message. If the
IN
Receive FIFO is already full, then none of the overrun message’s contents will be stored.
• When data in the Receive FIFO overruns for the first time, a Data Overrun Interrupt will be triggered.
• Each overrun message will still increment the TWAI_RX_MESSAGE_COUNTER up to a maximum of 64.
IM
• The Receive FIFO will internally mark overrun messages as invalid. The TWAI_MISS_ST bit can be used to
determine whether the message currently mapped to by the Receive Buffer is valid or overrun.
To clear an overrun Receive FIFO, the TWAI_RELEASE_BUF must be called repeatedly until
TWAI_RX_MESSAGE_COUNTER is 0. This has the effect of reading all valid messages in the Receive FIFO and
EL
clearing all overrun messages.
25.4.6 Acceptance Filter
The Acceptance Filter allows the TWAI controller to filter out received messages based on their ID (and optionally
their first data byte and frame type). Only accepted messages are passed on to the Receive FIFO. The use of
PR
Acceptance Filters allows a more lightweight operation of the TWAI controller (e.g., less use of Receive FIFO,
fewer Receive Interrupts) since the TWAI Controller only need to handle a subset of messages.
The Acceptance Filter configuration registers can only be accessed whilst the TWAI controller is in Reset Mode,
since they share the same address spaces with the Transmit Buffer and Receive Buffer registers.
The configuration registers consist of a 32-bit Acceptance Code Value and a 32-bit Acceptance Mask Value. The
Acceptance Code value specifies a bit pattern which each filtered bit of the message must match in order for the
message to be accepted. The Acceptance Mask Value is able to mask out certain bits of the Code value (i.e., set
as “Don’t Care” bits). Each filtered bit of the message must either match the acceptance code or be masked in
order for the message to be accepted, as demonstrated in Figure 25-7.
The TWAI controller Acceptance Filter allows the 32-bit Acceptance Code and Mask Values to either define a
single filter (i.e., Single Filter Mode), or two filters (i.e., Dual Filter Mode). How the Acceptance Filter interprets the
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Figure 257. Acceptance Filter
32-bit code and mask values is dependent on filter mode and the format of received messages (i.e., SFF or
EFF).
25.4.6.1 Single Filter Mode
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Single Filter Mode is enabled by setting the TWAI_RX_FILTER_MODE bit to 1. This will cause the 32-bit code and
mask values to define a single filter. The single filter can filter the following bits of a data or remote frame:
• SFF
– The entire 11-bit ID
A
– RTR bit
– Data byte 1 and Data byte 2 IN
• EFF
– The entire 29-bit ID
– RTR bit
IM
The following Figure 25-8 illustrates how the 32-bit code and mask values will be interpreted under Single Filter
Mode.
EL
PR
Figure 258. Single Filter Mode
25.4.6.2 Dual Filter Mode
Dual Filter Mode is enabled by clearing the TWAI_RX_FILTER_MODE bit to 0. This will cause the 32-bit code and
mask values to define a two separate filters referred to as filter 1 or filter 2. Under Dual Filter Mode, a message
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will be accepted if it is accepted by one of the two filters.
The two filters can filter the following bits of a data or remote frame:
• SFF
– The entire 11-bit ID
– RTR bit
– Data byte 1 (for filter 1 only)
• EFF
– The first 16 bits of the 29-bit ID
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The following Figure 25-9 illustrates how the 32-bit code and mask values will be interpreted in Dual Filter
Mode.
A
IN
IM
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PR
Figure 259. Dual Filter Mode
25.4.7 Error Management
The TWAI protocol requires that each TWAI node maintains the Transmit Error Counter (TEC) and Receive Error
Counter (REC). The value of both error counters determines the current error state of the TWAI controller (i.e.,
Error Active, Error Passive, Bus-Off). The TWAI controller stores the TEC and REC values in
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TWAI_TX_ERR_CNT_REG and TWAI_RX_ERR_CNT_REG respectively, and they can be read by the CPU
anytime. In addition to the error states, the TWAI controller also offers an Error Warning Limit (EWL) feature that
can warn users of the occurrence of severe bus errors before the TWAI controller enters the Error Passive
state.
The current error state of the TWAI controller is indicated via a combination of the following values and status bits:
TEC, REC, TWAI_ERR_ST, and TWAI_BUS_OFF_ST. Certain changes to these values and bits will also trigger
interrupts, thus allowing the users to be notified of error state transitions (see section 25.4.3). The following figure
25-10 shows the relation between the error states, values and bits, and error state related interrupts.
A RY
IN
Figure 2510. Error State Transition
IM
25.4.7.1 Error Warning Limit
The Error Warning Limit (EWL) is a configurable threshold value for the TEC and REC, which will trigger an
interrupt when exceeded. The EWL is intended to serve as a warning about severe TWAI bus errors, and is
triggered before the TWAI controller enters the Error Passive state. The EWL is configured in
EL
TWAI_ERR_WARNING_LIMIT_REG and can only be configured whilst the TWAI controller is in Reset Mode. The
TWAI_ERR_WARNING_LIMIT_REG has a default value of 96. When the values of TEC and/or REC are larger than
or equal to the EWL value, the TWAI_ERR_ST bit is immediately set to 1. Likewise, when the values of both the
TEC and REC are smaller than the EWL value, the TWAI_ERR_ST bit is immediately reset to 0. The Error Warning
Interrupt is triggered whenever the value of the TWAI_ERR_ST bit (or the TWAI_BUS_OFF_ST) changes.
PR
25.4.7.2 Error Passive
The TWAI controller is in the Error Passive state when the TEC or REC value exceeds 127. Likewise, when both
the TEC and REC are less than or equal to 127, the TWAI controller enters the Error Active state. The Error
Passive Interrupt is triggered whenever the TWAI controller transitions from the Error Active state to the Error
Passive state or vice versa.
25.4.7.3 BusOff and BusOff Recovery
The TWAI controller enters the Bus-Off state when the TEC value exceeds 255. On entering the Bus-Off state,
the TWAI controller will automatically do the following:
• Set REC to 0
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• Set TEC to 127
• Set the TWAI_BUS_OFF_ST bit to 1
• Enter Reset Mode
The Error Warning Interrupt is triggered whenever the value of the TWAI_BUS_OFF_ST bit (or the TWAI_ERR_ST
bit) changes.
To return to the Error Active state, the TWAI controller must undergo Bus-Off Recovery. Bus-Off Recovery
requires the TWAI controller to observe 128 occurrences of 11 consecutive recessive bits on the bus. To initiate
Bus-Off Recovery (after entering the Bus-Off state), the TWAI controller should enter Operation Mode by setting
the TWAI_RESET_MODE bit to 0. The TEC tracks the progress of Bus-Off Recovery by decrementing the TEC
each time when the TWAI controller observes 11 consecutive recessive bits. When Bus-Off Recovery has
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completed (i.e., TEC has decremented from 127 to 0), the TWAI_BUS_OFF_ST bit will automatically be reset to
0, thus triggering the Error Warning Interrupt.
25.4.8 Error Code Capture
The Error Code Capture (ECC) feature allows the TWAI controller to record the error type and bit position of a
A
TWAI bus error in the form of an error code. Upon detecting a TWAI bus error, the Bus Error Interrupt is triggered
and the error code is recorded in TWAI_ERR_CODE_CAP_REG. Subsequent bus errors will trigger the Bus Error
Interrupt, but their error codes will not be recorded until the current error code is read from the
TWAI_ERR_CODE_CAP_REG.
IN
The following Table 25-16 shows the fields of the TWAI_ERR_CODE_CAP_REG:
Table 2516. Bit Information of TWAI_ERR_CODE_CAP_REG (0x30)
IM
Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 1 2 3 3 3 3
Reserved ERRC.1 ERRC.0 DIR SEG.4 SEG.3 SEG.2 SEG.1 SEG.03
Notes:
EL
• ERRC: The Error Code (ERRC) indicates the type of bus error: 00 for bit error, 01 for format error, 10 for
stuff error, and 11 for other types of error.
• DIR: The Direction (DIR) indicates whether the TWAI controller was transmitting or receiving when the bus
error occurred: 0 for transmitter, 1 for receiver.
PR
• SEG: The Error Segment (SEG) indicates which segment of the TWAI message (i.e., bit position) the bus
error occurred at.
The following Table 25-17 shows how to interpret the SEG.0 to SEG.4 bits.
Table 2517. Bit Information of Bits SEG.4 SEG.0
Bit SEG.4 Bit SEG.3 Bit SEG.2 Bit SEG.1 Bit SEG.0 Description
0 0 0 1 1 start of frame
0 0 0 1 0 ID.28 ~ ID.21
0 0 1 1 0 ID.20 ~ ID.18
0 0 1 0 0 bit SRTR
0 0 1 0 1 bit IDE
0 0 1 1 1 ID.17 ~ ID.13
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Bit SEG.4 Bit SEG.3 Bit SEG.2 Bit SEG.1 Bit SEG.0 Description
0 1 1 1 1 ID.12 ~ ID.5
0 1 1 1 0 ID.4 ~ ID.0
0 1 1 0 0 bit RTR
0 1 1 0 1 reserved bit 1
0 1 0 0 1 reserved bit 0
0 1 0 1 1 data length code
0 1 0 1 0 data field
0 1 0 0 0 CRC sequence
1 1 0 0 0 CRC delimiter
1 1 0 0 1 ACK slot
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1 1 0 1 1 ACK delimiter
1 1 0 1 0 end of frame
1 0 0 1 0 intermission
1 0 0 0 1 active error flag
1 0 1 1 0 passive error flag
A
1 0 0 1 1 tolerate dominant bits
1 0 1 1 1 error delimiter
1 1 1 0 0 overload flag
Notes:
IN
• Bit SRTR: under Standard Frame Format.
• Bit IDE: Identifier Extension Bit, 0 for Standard Frame Format.
IM
25.4.9 Arbitration Lost Capture
The Arbitration Lost Capture (ALC) feature allows the TWAI controller to record the bit position where it loses
arbitration. When the TWAI controller loses arbitration, the bit position is recorded in TWAI_ARB LOST CAP_REG
EL
and the Arbitration Lost Interrupt is triggered.
Subsequent losses in arbitration will trigger the Arbitration Lost Interrupt, but will not be recorded in TWAI_ARB
LOST CAP_REG until the current Arbitration Lost Capture is read from the TWAI_ERR_CODE_CAP_REG.
Table 25-18 illustrates bits and fields of TWAI_ERR_CODE_CAP_REG whilst Figure 25-11 illustrates the bit
positions of a TWAI message.
PR
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Table 2518. Bit Information of TWAI_ARB LOST CAP_REG (0x2c)
Bit 31-5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 1 1 1
Reserved BITNO.4 BITNO.3 BITNO.2 BITNO.1 BITNO.01
Notes:
• BITNO: Bit Number (BITNO) indicates the nth bit of a TWAI message where arbitration was lost.
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Figure 2511. Positions of Arbitration Lost Bits
A
IN
IM
EL
PR
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25.5 Register Summary
’|’ here means separate line to distinguish between TWAI working modes discussed in Section 25.4.1 Modes.
The left describes the access in Operation Mode. The right belongs to Reset Mode and is marked in red. The
addresses in this section are relative to Two-wire Automotive Interface base address provided in Table 3-4 in
Chapter 3 System and Memory.
Name Description Address Access
Configuration Registers
TWAI_MODE_REG Mode Register 0x0000 R/W
TWAI_BUS_TIMING_0_REG Bus Timing Register 0 0x0018 RO | R/W
TWAI_BUS_TIMING_1_REG Bus Timing Register 1 0x001C RO | R/W
RY
TWAI_ERR_WARNING_LIMIT_REG Error Warning Limit Register 0x0034 RO | R/W
TWAI_DATA_0_REG Data Register 0 0x0040 WO | R/W
TWAI_DATA_1_REG Data Register 1 0x0044 WO | R/W
TWAI_DATA_2_REG Data Register 2 0x0048 WO | R/W
TWAI_DATA_3_REG Data Register 3 0x004C WO | R/W
A
TWAI_DATA_4_REG Data Register 4 0x0050 WO | R/W
TWAI_DATA_5_REG Data Register 5 0x0054 WO | R/W
TWAI_DATA_6_REG Data Register 6 0x0058 WO | R/W
TWAI_DATA_7_REG
TWAI_DATA_8_REG
IN
Data Register 7
Data Register 8
0x005C
0x0060
WO | R/W
WO | RO
TWAI_DATA_9_REG Data Register 9 0x0064 WO | RO
TWAI_DATA_10_REG Data Register 10 0x0068 WO | RO
IM
TWAI_DATA_11_REG Data Register 11 0x006C WO | RO
TWAI_DATA_12_REG Data Register 12 0x0070 WO | RO
TWAI_CLOCK_DIVIDER_REG Clock Divider Register 0x007C varies
Contro Registers
TWAI_CMD_REG Command Register 0x0004 WO
EL
Status Register
TWAI_STATUS_REG Status Register 0x0008 RO
TWAI_ARB LOST CAP_REG Arbitration Lost Capture Register 0x002C RO
TWAI_ERR_CODE_CAP_REG Error Code Capture Register 0x0030 RO
TWAI_RX_ERR_CNT_REG Receive Error Counter Register 0x0038 RO | R/W
PR
TWAI_TX_ERR_CNT_REG Transmit Error Counter Register 0x003C RO | R/W
TWAI_RX_MESSAGE_CNT_REG Receive Message Counter Register 0x0074 RO
Interrupt Registers
TWAI_INT_RAW_REG Interrupt Register 0x000C RO
TWAI_INT ENA_REG Interrupt Enable Register 0x0010 R/W
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25.6 Registers
’|’ here means separate line. The left describes the access in Operation Mode. The right belongs to Reset Mode
with red color. The addresses in this section are relative to Two-wire Automotive Interface base address provided
in Table 3-4 in Chapter 3 System and Memory.
Register 25.1. TWAI_MODE_REG (0x0000)
DE
_M LY E
DE O
ES _O _M E
ET N OD
O _M
_R EN T D
AI IST ES MO
TW I_L F_ R_
A EL TE
T
TW I_S FIL
A X_
d)
TW I_R
ve
RY
er
A
s
TW
(re
31 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
TWAI_RESET_MODE This bit is used to configure the operation mode of the TWAI Controller. 1:
Reset mode; 0: Operation mode (R/W)
A
TWAI_LISTEN_ONLY_MODE 1: Listen only mode. In this mode the nodes will only receive messages
from the bus, without generating the acknowledge signal nor updating the RX error counter. (R/W)
IN
TWAI_SELF_TEST_MODE 1: Self test mode. In this mode the TX nodes can perform a successful
transmission without receiving the acknowledge signal. This mode is often used to test a single
node with the self reception request command. (R/W)
IM
TWAI_RX_FILTER_MODE This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single
filter mode (R/W)
EL
Register 25.2. TWAI_BUS_TIMING_0_REG (0x0018)
TH
ID
_W
SC
P
ed JUM
RE
_P
_
UD
se NC
d)
BA
Y
PR
_S
e
rv
rv
_
AI
AI
se
TW
TW
(re
(re
31 16 15 14 13 12 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0x00 Reset
TWAI_BAUD_PRESC Baud Rate Prescaler value, determines the frequency dividing ratio. (RO | R/W)
TWAI_SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 ~ 14 Tq wide. (RO | R/W)
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Register 25.3. TWAI_BUS_TIMING_1_REG (0x001C)
1
M
G
SA
SE
SE
E_
E_
E_
M
IM
IM
)
ed
I
_T
_T
_T
rv
AI
AI
AI
se
TW
TW
TW
(re
31 8 7 6 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Reset
TWAI_TIME_SEG1 The width of PBS1. (RO | R/W)
TWAI_TIME_SEG2 The width of PBS2. (RO | R/W)
RY
TWAI_TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled
three times (RO | R/W)
Register 25.4. TWAI_ERR_WARNING_LIMIT_REG (0x0034)
A
IT
IM
_L
NG
NI
AR
IN
W
R_
d)
R
ve
_E
r
AI
se
TW
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x60 Reset
IM
TWAI_ERR_WARNING_LIMIT Error warning threshold. In the case when any of an error counter
value exceeds the threshold, or all the error counter values are below the threshold, an error warning
interrupt will be triggered (given the enable signal is valid). (RO | R/W)
EL
PR
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Register 25.5. TWAI_DATA_0_REG (0x0040)
_0
DE
O
E_C
NC
TA
EP
CC
_A
AI
W
|T
0
E_
YT
_B
)
ed
X
_T
rv
AI
se
TW
(re
31 8 7 0
RY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_0 Stored the 0th byte information of the data to be transmitted in operation mode.
(WO)
TWAI_ACCEPTANCE_CODE_0 Stored the 0th byte of the filter code in reset mode. (R/W)
A
Register 25.6. TWAI_DATA_1_REG (0x0044)
IN
_1
DE
O
_C
CE
N
TA
EP
IM
CC
_A
AI
W
|T
1
E_
YT
_B
d)
X
ve
_T
r
AI
se
TW
(re
EL
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_1 Stored the 1st byte information of the data to be transmitted in operation mode.
(WO)
PR
TWAI_ACCEPTANCE_CODE_1 Stored the 1st byte of the filter code in reset mode. (R/W)
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Register 25.7. TWAI_DATA_2_REG (0x0048)
_2
DE
O
E_C
NC
TA
EP
CC
_A
AI
W
|T
2
E_
YT
_B
)
ed
X
_T
rv
AI
se
TW
(re
31 8 7 0
RY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_2 Stored the 2nd byte information of the data to be transmitted in operation mode.
(WO)
TWAI_ACCEPTANCE_CODE_2 Stored the 2nd byte of the filter code in reset mode. (R/W)
A
Register 25.8. TWAI_DATA_3_REG (0x004C)
IN
_3
DE
O
_C
CE
N
TA
EP
IM
CC
_A
AI
W
|T
3
E_
YT
_B
d)
X
ve
_T
r
AI
se
TW
(re
EL
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_3 Stored the 3rd byte information of the data to be transmitted in operation mode.
(WO)
PR
TWAI_ACCEPTANCE_CODE_3 Stored the 3rd byte of the filter code in reset mode. (R/W)
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Register 25.9. TWAI_DATA_4_REG (0x0050)
0
K_
AS
E_M
NC
TA
EP
CC
_A
AI
W
|T
4
E_
YT
_B
d)
X
ve
_T
er
AI
s
TW
(re
31 8 7 0
RY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_4 Stored the 4th byte information of the data to be transmitted in operation mode.
(WO)
TWAI_ACCEPTANCE_MASK_0 Stored the 0th byte of the filter code in reset mode. (R/W)
A
Register 25.10. TWAI_DATA_5_REG (0x0054)
IN
1
K_
AS
_M
CE
N
TA
EP
IM
CC
_A
AI
W
|T
5
E_
YT
_B
d)
X
ve
_T
r
AI
se
TW
(re
EL
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_5 Stored the 5th byte information of the data to be transmitted in operation mode.
(WO)
PR
TWAI_ACCEPTANCE_MASK_1 Stored the 1st byte of the filter code in reset mode. (R/W)
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Register 25.11. TWAI_DATA_6_REG (0x0058)
2
K_
AS
E_M
NC
TA
EP
CC
_A
AI
W
|T
6
E_
YT
_B
d)
X
ve
_T
er
AI
s
TW
(re
31 8 7 0
RY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_6 Stored the 6th byte information of the data to be transmitted in operation mode.
(WO)
TWAI_ACCEPTANCE_MASK_2 Stored the 2nd byte of the filter code in reset mode. (R/W)
A
Register 25.12. TWAI_DATA_7_REG (0x005C)
IN
3
K_
AS
_M
CE
N
TA
EP
IM
CC
_A
AI
W
|T
7
E_
YT
_B
d)
X
ve
_T
r
AI
se
TW
(re
EL
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_7 Stored the 7th byte information of the data to be transmitted in operation mode.
(WO)
PR
TWAI_ACCEPTANCE_MASK_3 Stored the 3rd byte of the filter code in reset mode. (R/W)
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Register 25.13. TWAI_DATA_8_REG (0x0060)
8
E_
YT
_B
d)
X
ve
_T
r
AI
se
TW
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_8 Stored the 8th byte information of the data to be transmitted in operation mode.
(WO)
RY
Register 25.14. TWAI_DATA_9_REG (0x0064)
9
E_
YT
_B
d)
X
ve
_T
er
AI
s
TW
(re
A
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_9 Stored the 9th byte information of the data to be transmitted in operation mode.
(WO)
IM
Register 25.15. TWAI_DATA_10_REG (0x0068)
10
E_
YT
_B
d)
X
ve
_T
r
AI
se
EL
TW
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_10 Stored the 10th byte information of the data to be transmitted in operation mode.
(WO)
PR
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Register 25.16. TWAI_DATA_11_REG (0x006C)
11
E_
YT
_B
)
ed
X
_T
rv
AI
se
TW
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_BYTE_11 Stored the 11th byte information of the data to be transmitted in operation mode.
(WO)
RY
Register 25.17. TWAI_DATA_12_REG (0x0070)
12
E_
YT
_B
d)
X
e
_T
rv
AI
se
A TW
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
IN
TWAI_TX_BYTE_12 Stored the 12th byte information of the data to be transmitted in operation mode.
(WO)
IM
Register 25.18. TWAI_CLOCK_DIVIDER_REG (0x007C)
FF
_O
CK
O
d)
D
L
_C
_C
ve
EL r
AI
AI
se
TW
TW
(re
31 9 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_CD These bits are used to configure the divisor of the external CLKOUT pin. (R/W)
PR
TWAI_CLOCK_OFF This bit can be configured in reset mode. 1: Disable the external CLKOUT pin;
0: Enable the external CLKOUT pin (RO | R/W)
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Register 25.19. TWAI_CMD_REG (0x0004)
AI BO SE UN
X_ T_ UF
A L VE Q
E
TW I_A EA RR
_T R _B
TW I_R _O _R
RE TX
A LR X
Q
R
TW _C _
AI ELF
)
E
ed
TW I_S
rv
se
A
TW
(re
31 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TWAI_TX_REQ Set the bit to 1 to drive nodes to start transmission. (WO)
TWAI_ABORT_TX Set the bit to 1 to cancel a pending transmission request. (WO)
RY
TWAI_RELEASE_BUF Set the bit to 1 to release the RX buffer. (WO)
TWAI_CLR_OVERRUN Set the bit to 1 to clear the data overrun status bit. (WO)
TWAI_SELF_RX_REQ Self reception request command. Set the bit to 1 to allow a message be
transmitted and received simultaneously. (WO)
A
Register 25.20. TWAI_STATUS_REG (0x0008)
IN
AI VE F_S TE
F_ ST
A X_ T T
TW I_O BU PLE
TW I_T _S _S
ST
_R RR T
BU N_
A RR FF
A US ST
X_ U
A X_ M
TW I_E _O
TW I_T CO
TW I_T ST
TW I_R ST
TW _B _
AI ISS
A X_
A X_
)
ed
TW I_M
rv
se
A
IM
TW
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Reset
TWAI_RX_BUF_ST 1: The data in the RX buffer is not empty, with at least one received data packet.
(RO)
EL
TWAI_OVERRUN_ST 1: The RX FIFO is full and data overrun has occurred. (RO)
TWAI_TX_BUF_ST 1: The TX buffer is empty, the CPU may write a message into it. (RO)
TWAI_TX_COMPLETE 1: The TWAI controller has successfully received a packet from the bus. (RO)
PR
TWAI_RX_ST 1: The TWAI Controller is receiving a message from the bus. (RO)
TWAI_TX_ST 1: The TWAI Controller is transmitting a message to the bus. (RO)
TWAI_ERR_ST 1: At least one of the RX/TX error counter has reached or exceeded the value set in
register TWAI_ERR_WARNING_LIMIT_REG. (RO)
TWAI_BUS_OFF_ST 1: In bus-off status, the TWAI Controller is no longer involved in bus activities.
(RO)
TWAI_MISS_ST This bit reflects whether the data packet in the RX FIFO is complete. 1: The current
packet is missing; 0: The current packet is complete (RO)
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Register 25.21. TWAI_ARB LOST CAP_REG (0x002C)
AP
_C
ST
O
_L
RB
)
ed
_A
rv
AI
se
TW
(re
31 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_ARB_LOST_CAP This register contains information about the bit position of lost arbitration.
(RO)
RY
Register 25.22. TWAI_ERR_CODE_CAP_REG (0x0030)
T
O
EN
TI
EC
M
E
EG
_E TYP
IR
_D
_S
A TW CC
CC
_
CC
d)
ve
_E
_E
r
AI
AI
AI
se
TW
TW
(re
31 8 7 6 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN0 0 0 0 0 0 0 0 0 0x0 0 0x0 Reset
TWAI_ECC_SEGMENT This register contains information about the location of errors, see Table 25-
16 for details. (RO)
IM
TWAI_ECC_DIRECTION This register contains information about transmission direction of the node
when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting
a message (RO)
TWAI_ECC_TYPE This register contains information about error types: 00: bit error; 01: form error;
EL
10: stuff error; 11: other type of error (RO)
Register 25.23. TWAI_RX_ERR_CNT_REG (0x0038)
PR
T
CN
R_
ER
X_
d)
_R
ve
r
AI
se
TW
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_RX_ERR_CNT The RX error counter register, reflects value changes in reception status. (RO |
R/W)
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Register 25.24. TWAI_TX_ERR_CNT_REG (0x003C)
NT
_C
RR
_E
d)
X
ve
_T
er
AI
s
TW
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
TWAI_TX_ERR_CNT The TX error counter register, reflects value changes in transmission status. (RO
| R/W)
RY
Register 25.25. TWAI_RX_MESSAGE_CNT_REG (0x0074)
R
TE
UN
CO
E_
G
A
SA
ES
M
X_
d)
_R
e
rv
AI
se
TW
(re
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IN
0 0 0 0 0 0 0 0 0
7
0
6
0x0
0
Reset
TWAI_RX_MESSAGE_COUNTER This register reflects the number of messages available within the
RX FIFO. (RO)
IM
EL
PR
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Register 25.26. TWAI_INT_RAW_REG (0x000C)
T
_S
ST
se RR OS T ST
VE ST
X_ _S _IN T
NT
TW rve _P T_ _ST
IN T T_
(re I_E _L _IN T_
_R T N S
SI _
AI X_I AR NT_
_I
A d) AS INT
A RB RR _IN
TW _T _W _I
TW I_A _E TE
ST
AI RR UN
A US TA
T_
TW _E RR
TW _B _S
N
AI US
AI VE
d)
TW I_O
TW I_B
ve
er
A
s
TW
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TWAI_RX_INT_ST Receive interrupt. If this bit is set to 1, it indicates there are messages to be
handled in the RX FIFO. (RO)
RY
TWAI_TX_INT_ST Transmit interrupt. If this bit is set to 1, it indicates the message transmission is
finished and a new transmission is able to start. (RO)
TWAI_ERR_WARN_INT_ST Error warning interrupt. If this bit is set to 1, it indicates the error status
signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or
A
from 1 to 0). (RO)
TWAI_OVERRUN_INT_ST Data overrun interrupt. If this bit is set to 1, it indicates a data overrun
interrupt is generated in the RX FIFO. (RO)
IN
TWAI_ERR_PASSIVE_INT_ST Error passive interrupt. If this bit is set to 1, it indicates the TWAI
Controller is switched between error active status and error passive status due to the change of
error counters. (RO)
IM
TWAI_ARB_LOST_INT_ST Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration
lost interrupt is generated. (RO)
TWAI_BUS_ERR_INT_ST Error interrupt. If this bit is set to 1, it indicates an error is detected on the
bus. (RO)
EL
TWAI_BUS_STATE_INT_ST Bus state interrupt. If this bit is set to 1, it indicates the status of TWAI
controller has changed. (RO)
PR
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Register 25.27. TWAI_INT ENA_REG (0x0010)
NA
A
TW rve _P T_ _EN A
_E
_I A
EN
se RR OS T EN
X_ _E _IN NA
A d) AS INT A
VE EN
NT
IN N T_
(re I_E _L _IN T_
_R T N E
SI _
AI X_I AR NT_
A RB RR _IN
A
T_ A
TW _T _W _I
TW I_A _E TE
EN
AI RR UN
A US TA
TW _E RR
TW _B _S
N
AI US
AI VE
d)
TW I_O
TW I_B
ve
er
A
s
TW
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TWAI_RX_INT_ENA Set this bit to 1 to enable receive interrupt. (R/W)
RY
TWAI_TX_INT_ENA Set this bit to 1 to enable transmit interrupt. (R/W)
TWAI_ERR_WARN_INT_ENA Set this bit to 1 to enable error warning interrupt. (R/W)
TWAI_OVERRUN_INT_ENA Set this bit to 1 to enable data overrun interrupt. (R/W)
TWAI_ERR_PASSIVE_INT_ENA Set this bit to 1 to enable error passive interrupt. (R/W)
A
TWAI_ARB_LOST_INT_ENA Set this bit to 1 to enable arbitration lost interrupt. (R/W)
TWAI_BUS_ERR_INT_ENA Set this bit to 1 to enable bus error interrupt. (R/W)
IN
TWAI_BUS_STATE_INT_ENA Set this bit to 1 to enable bus state interrupt. (R/W)
IM
EL
PR
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26 LED PWM Controller (LEDC)
26 LED PWM Controller (LEDC)
26.1 Overview
The LED PWM Controller is a peripheral designed to generate PWM signals for LED control. It has specialized
features such as automatic duty cycle fading. However, the LED PWM Controller can also be used to generate
PWM signals for other purposes.
26.2 Features
The LED PWM Controller has the following features:
RY
• Six independent PWM generators (i.e. six channels)
• Four independent timers that support division by fractions
• Automatic duty cycle fading (i.e. gradual increase/decrease of a PWM’s duty cycle without interference
from the processor) with interrupt generation on fade completion
A
• Adjustable phase of PWM signal output
• PWM signal output in low-power mode (Light-sleep mode)
IN
• Maximum PWM resolution: 14 bits
Note that the four timers are identical regarding their features and operation. The following sections refer to the
timers collectively as Timerx (where x ranges from 0 to 3). Likewise, the six PWM generators are also identical in
features and operation, and thus are collectively referred to as PWMn (where n ranges from 0 to 5).
IM
EL
PR
Figure 261. LED PWM Architecture
26.3 Functional Description
26.3.1 Architecture
Figure 26-1 shows the architecture of the LED PWM Controller.
The four timers can be independently configured (i.e. configurable clock divider, and counter overflow value) and
each internally maintains a timebase counter (i.e. a counter that counts on cycles of a reference clock). Each
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PWM generator selects one of the timers and uses the timer’s counter value as a reference to generate its PWM
signal.
Figure 26-2 illustrates the main functional blocks of the timer and the PWM generator.
A RY
Figure 262. LED PWM Generator Diagram
IN
26.3.2 Timers
Each timer in LED PWM Controller internally maintains a timebase counter. Referring to Figure 26-2, this clock
IM
signal used by the timebase counter is named ref_pulsex. All timers use the same clock source LEDC_CLKx,
which is then passed through a clock divider to generate ref_pulsex for the counter.
26.3.2.1 Clock Source
EL
Software configuring registers for LED PWM is clocked by APB_CLK. For more information about APB_CLK, see
Chapter 6 Reset and Clock. To use the LED PWM pheripheral, the APB_CLK signal to the LED PWM has to be
enabled. The APB_CLK signal to LED PWM can be enabled by setting the SYSTEM_LEDC_CLK_EN field in the
register SYSTEM_PERIP_CLK_EN0_REG and be reset via software by setting the SYSTEM_LEDC_RST field in
the register SYSTEM_PERIP_RST_EN0_REG. For more information, please refer to Table 13-1 in Chapter 13
PR
System Registers (SYSREG).
Timers in the LED PWM Controller choose their common clock source from one of the following clock signals:
APB_CLK, FOSC_CLK and XTAL_CLK (see Chapter 6 Reset and Clock for more details about each clock signal).
The procedure for selecting a clock source signal for LEDC_CLKx is described below:
• APB_CLK: Set LEDC_APB_CLK_SEL[1:0] to 1
• FOSC_CLK: Set LEDC_APB_CLK_SEL[1:0] to 2
• XTAL_CLK: Set LEDC_APB_CLK_SEL[1:0] to 3
The LEDC_CLKx signal will then be passed through the clock divider.
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26.3.2.2 Clock Divider Configuration
The LEDC_CLKx signal is passed through a clock divider to generate the ref_pulsex signal for the counter. The
frequency of ref_pulsex is equal to the frequency of LEDC_CLKx divided by the LEDC_CLK_DIV_TIMERx divider
value (see Figure 26-2).
The LEDC_CLK_DIV_TIMERx divider value is a fractional clock divider. Thus, it supports non-integer divider
values. LEDC_CLK_DIV_TIMERx is configured via the LEDC_CLK_DIV_TIMERx field according to the following
equation.
B
LEDC_CLK_DIV _T IM ERx = A + 256
• A corresponds to the most significant 10 bits of LEDC_CLK_DIV_TIMERx (i.e.
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LEDC_TIMERx_CONF_REG[21:12])
• The fractional part B corresponds to the least significant 8 bits of LEDC_CLK_DIV_TIMERx
(i.e. LEDC_TIMERx_CONF_REG[11:4])
When the fractional part B is zero, LEDC_CLK_DIV_TIMERx is equivalent to an integer divider value (i.e. an
integer prescaler). In other words, a ref_pulsex clock pulse is generated after every A number of LEDC_CLKx
A
clock pulses.
However, when B is nonzero, LEDC_CLK_DIV_TIMERx becomes a non-integer divider value. The clock divider
implements non-integer frequency division by alternating between A and (A+1) LEDC_CLKx clock pulses per
IN
ref_pulsex clock pulse. This will result in the average frequency of ref_pulsex clock pulse being the desired
frequency (i.e. the non-integer divided frequency). For every 256 ref_pulsex clock pulses:
• A number of B ref_pulsex clock pulses will consist of (A+1) LEDC_CLKx clock pulses
IM
• A number of (256-B) ref_pulsex clock pulses will consist of A LEDC_CLKx clock pulses
• The ref_pulsex clock pulses consisting of (A+1) pulses are evenly distributed amongst those consisting of A
pulses
Figure 26-3 illustrates the relation between LEDC_CLKx clock pulses and ref_pulsex clock pulses when dividing
EL
by a non-integer LEDC_CLK_DIV_TIMERx.
PR
Figure 263. Frequency Division When LEDC_CLK_DIV_TIMERx is a NonInteger Value
To change the timer’s clock divider value at runtime, first set the LEDC_CLK_DIV_TIMERx field, and then set the
LEDC_TIMERx_PARA_UP field to apply the new configuration. This will cause the newly configured values to
take effect upon the next overflow of the counter. The LEDC_TIMERx_PARA_UP field will be automatically
cleared by hardware.
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26.3.2.3 14bit Counter
Each timer contains a 14-bit timebase counter that uses ref_pulsex as its reference clock (see Figure 26-2). The
LEDC_TIMERx_DUTY_RES field configures the overflow value of this 14-bit counter. Hence, the maximum
resolution of the PWM signal is 14 bits. The counter counts up to 2LEDC_T IM ERx_DU T Y _RES − 1, overflows and
begins counting from 0 again. The counter’s value can be read, reset, and suspended by software.
The counter can trigger LEDC_TIMERx_OVF_INT interrupt (generated automatically by hardware without
configuration) every time the counter overflows. It can also be configured to trigger LEDC_OVF_CNT_CHn_INT
interrupt after the counter overflows LEDC_OV F _N U M _CHn + 1 times. To configure
LEDC_OVF_CNT_CHn_INT interrupt, please:
1. Configure LEDC_TIMER_SEL_CHn as the counter for the PWM generator
RY
2. Enable the counter by setting LEDC_OVF_CNT_EN_CHn
3. Set LEDC_OVF_NUM_CHn to the number of counter overflows to generate an interrupt, minus 1
4. Enable the overflow interrupt by setting LEDC_OVF_CNT_CHn_INT_ENA
5. Set LEDC_TIMERx_DUTY_RES to enable the timer and wait for a LEDC_OVF_CNT_CHn_INT interrupt
A
Referring to Figure 26-2, the frequency of a PWM generator output signal (sig_outn) is dependent on the
frequency of the timer’s clock source (LEDC_CLKx), the clock divider value (LEDC_CLK_DIV_TIMERx), and the
range of the counter (LEDC_TIMERx_DUTY_RES):
IN
fLEDC_CLKx
fPWM =
LEDC_CLK_DIVx · 2LEDC_TIMERx_DUTY_RES
IM
To change the overflow value at runtime, first set the LEDC_TIMERx_DUTY_RES field, and then set the
LEDC_TIMERx_PARA_UP field. This will cause the newly configured values to take effect upon the next overflow
of the counter. If LEDC_OVF_CNT_EN_CHn field is reconfigured, LEDC_TIMERx_PARA_UP should also be set to
apply the new configuration. In summary, these configuration values need to be updated by setting
LEDC_TIMERx_PARA_UP. LEDC_TIMERx_PARA_UP field will be automatically cleared by hardware.
EL
26.3.3 PWM Generators
To generate a PWM signal, a PWM generator (PWMn) selects a timer (Timerx). Each PWM generator can be
configured separately by setting LEDC_TIMER_SEL_CHn to use one of four timers to generate the PWM
output.
PR
As shown in Figure 26-2, each PWM generator has a comparator and two multiplexers. A PWM generator
compares the timer’s 14-bit counter value (Timerx_cnt) to two trigger values Hpointn and Lpointn. When the
timer’s counter value is equal to Hpointn or Lpointn, the PWM signal is high or low, respectively, as described
below:
• If Timerx_cnt == Hpointn, sig_outn is 1.
• If Timerx_cnt == Lpointn, sig_outn is 0.
Figure 26-4 illustrates how Hpointn or Lpointn are used to generate a fixed duty cycle PWM output signal.
For a particular PWM generator (PWMn), its Hpointn is sampled from the LEDC_HPOINT_CHn field each time the
selected timer’s counter overflows. Likewise, Lpointn is also sampled on every counter overflow and is calculated
from the sum of the LEDC_DUTY_CHn[18:4] and LEDC_HPOINT_CHn fields. By setting Hpointn and Lpointn via
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Figure 264. LED_PWM Output Signal Diagram
RY
the LEDC_HPOINT_CHn and LEDC_DUTY_CHn[18:4] fields, the relative phase and duty cycle of the PWM
output can be set.
The PWM output signal (sig_outn) is enabled by setting LEDC_SIG_OUT_EN_CHn. When
LEDC_SIG_OUT_EN_CHn is cleared, PWM signal output is disabled, and the output signal (sig_outn) will output
A
a constant level as specified by LEDC_IDLE_LV_CHn.
The bits LEDC_DUTY_CHn[3:0] are used to dither the duty cycles of the PWM output signal (sig_outn) by
IN
periodically altering the duty cycle of sig_outn. When LEDC_DUTY_CHn[3:0] is set to a non-zero value, then for
every 16 cycles of sig_outn, LEDC_DUTY_CHn[3:0] of those cycles will have PWM pulses that are one timer tick
longer than the other (16- LEDC_DUTY_CHn[3:0]) cycles. For instance, if LEDC_DUTY_CHn[18:4] is set to 10
and LEDC_DUTY_CHn[3:0] is set to 5, then 5 of 16 cycles will have a PWM pulse with a duty value of 11 and the
rest of the 16 cycles will have a PWM pulse with a duty value of 10. The average duty cycle after 16 cycles is
IM
10.3125.
If fields LEDC_TIMER_SEL_CHn, LEDC_HPOINT_CHn, LEDC_DUTY_CHn[18:4] and LEDC_SIG_OUT_EN_CHn
are reconfigured, LEDC_PARA_UP_CHn must be set to apply the new configuration. This will cause the newly
configured values to take effect upon the next overflow of the counter. LEDC_PARA_UP_CHn field will be
EL
automatically cleared by hardware.
26.3.4 Duty Cycle Fading
The PWM generators can fade the duty cycle of a PWM output signal (i.e. gradually change the duty cycle from
one value to another). If Duty Cycle Fading is enabled, the value of Lpointn will be incremented/decremented
PR
after a fixed number of counter overflows has occured. Figure 26-5 illustrates Duty Cycle Fading.
Duty Cycle Fading is configured using the following register fields:
• LEDC_DUTY_CHn is used to set the initial value of Lpointn
• LEDC_DUTY_START_CHn will enable/disable duty cycle fading when set/cleared
• LEDC_DUTY_CYCLE_CHn sets the number of counter overflow cycles for every Lpointn
increment/decrement. In other words, Lpointn will be incremented/decremented after
LEDC_DUTY_CYCLE_CHn counter overflows.
• LEDC_DUTY_INC_CHn configures whether Lpointn is incremented/decremented if set/cleared
• LEDC_DUTY_SCALE_CHn sets the amount that Lpointn is incremented/decremented
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Figure 265. Output Signal Diagram of Fading Duty Cycle
RY
• LEDC_DUTY_NUM_CHn sets the maximum number of increments/decrements before duty cycle fading
stops.
If the fields LEDC_DUTY_CHn, LEDC_DUTY_START_CHn, LEDC_DUTY_CYCLE_CHn, LEDC_DUTY_INC_CHn,
LEDC_DUTY_SCALE_CHn, and LEDC_DUTY_NUM_CHn are reconfigured, LEDC_PARA_UP_CHn must be set
A
to apply the new configuration. After this field is set, the values for duty cycle fading will take effect at once.
LEDC_PARA_UP_CHn field will be automatically cleared by hardware.
IN
26.3.5 Interrupts
• LEDC_OVF_CNT_CHn_INT: Triggered when the timer counter overflows for (LEDC_OVF_NUM_CHn + 1)
times and the register LEDC_OVF_CNT_EN_CHn is set to 1.
IM
• LEDC_DUTY_CHNG_END_CHn_INT: Triggered when a fade on an LED PWM generator has finished.
• LEDC_TIMERx_OVF_INT: Triggered when an LED PWM timer has reached its maximum counter value.
EL
PR
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26.4 Register Summary
The addresses in this section are relative to the LED PWM Controller base address provided in Table 3-4 in
Chapter 3 System and Memory.
Name Description Address Access
Configuration Register
LEDC_CH0_CONF0_REG Configuration register 0 for channel 0 0x0000 varies
LEDC_CH0_CONF1_REG Configuration register 1 for channel 0 0x000C varies
LEDC_CH1_CONF0_REG Configuration register 0 for channel 1 0x0014 varies
LEDC_CH1_CONF1_REG Configuration register 1 for channel 1 0x0020 varies
LEDC_CH2_CONF0_REG Configuration register 0 for channel 2 0x0028 varies
RY
LEDC_CH2_CONF1_REG Configuration register 1 for channel 2 0x0034 varies
LEDC_CH3_CONF0_REG Configuration register 0 for channel 3 0x003C varies
LEDC_CH3_CONF1_REG Configuration register 1 for channel 3 0x0048 varies
LEDC_CH4_CONF0_REG Configuration register 0 for channel 4 0x0050 varies
LEDC_CH4_CONF1_REG Configuration register 1 for channel 4 0x005C varies
A
LEDC_CH5_CONF0_REG Configuration register 0 for channel 5 0x0064 varies
LEDC_CH5_CONF1_REG Configuration register 1 for channel 5 0x0070 varies
LEDC_CONF_REG Global ledc configuration register 0x00D0 R/W
Hpoint Register
LEDC_CH0_HPOINT_REG
IN
High point register for channel 0 0x0004 R/W
LEDC_CH1_HPOINT_REG High point register for channel 1 0x0018 R/W
LEDC_CH2_HPOINT_REG High point register for channel 2 0x002C R/W
IM
LEDC_CH3_HPOINT_REG High point register for channel 3 0x0040 R/W
LEDC_CH4_HPOINT_REG High point register for channel 4 0x0054 R/W
LEDC_CH5_HPOINT_REG High point register for channel 5 0x0068 R/W
Duty Cycle Register
LEDC_CH0_DUTY_REG Initial duty cycle for channel 0 0x0008 R/W
EL
LEDC_CH0_DUTY_R_REG Current duty cycle for channel 0 0x0010 RO
LEDC_CH1_DUTY_REG Initial duty cycle for channel 1 0x001C R/W
LEDC_CH1_DUTY_R_REG Current duty cycle for channel 1 0x0024 RO
LEDC_CH2_DUTY_REG Initial duty cycle for channel 2 0x0030 R/W
LEDC_CH2_DUTY_R_REG Current duty cycle for channel 2 0x0038 RO
PR
LEDC_CH3_DUTY_REG Initial duty cycle for channel 3 0x0044 R/W
LEDC_CH3_DUTY_R_REG Current duty cycle for channel 3 0x004C RO
LEDC_CH4_DUTY_REG Initial duty cycle for channel 4 0x0058 R/W
LEDC_CH4_DUTY_R_REG Current duty cycle for channel 4 0x0060 RO
LEDC_CH5_DUTY_REG Initial duty cycle for channel 5 0x006C R/W
LEDC_CH5_DUTY_R_REG Current duty cycle for channel 5 0x0074 RO
Timer Register
LEDC_TIMER0_CONF_REG Timer 0 configuration 0x00A0 varies
LEDC_TIMER0_VALUE_REG Timer 0 current counter value 0x00A4 RO
LEDC_TIMER1_CONF_REG Timer 1 configuration 0x00A8 varies
LEDC_TIMER1_VALUE_REG Timer 1 current counter value 0x00AC RO
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Name Description Address Access
LEDC_TIMER2_CONF_REG Timer 2 configuration 0x00B0 varies
LEDC_TIMER2_VALUE_REG Timer 2 current counter value 0x00B4 RO
LEDC_TIMER3_CONF_REG Timer 3 configuration 0x00B8 varies
LEDC_TIMER3_VALUE_REG Timer 3 current counter value 0x00BC RO
Interrupt Register
LEDC_INT_RAW_REG Raw interrupt status 0x00C0 R/WTC/SS
LEDC_INT_ST_REG Masked interrupt status 0x00C4 RO
LEDC_INT_ENA_REG Interrupt enable bits 0x00C8 R/W
LEDC_INT_CLR_REG Interrupt clear bits 0x00CC WT
Version Register
RY
LEDC_DATE_REG Version control register 0x00FC R/W
A
IN
IM
EL
PR
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26.5 Registers
The addresses in this section are relative to LED PWM Controller base address provided in Table 3-4 in Chapter 3
System and Memory.
Register 26.1. LEDC_CHn_CONF0_REG (n: 05) (0x0000+20*n)
n n
CH H
N_ _C
n
_E ET
_S _CH
Hn
Hn
NT ES
DC _O CH n
_C
LE SIG LV_ CH
U n
N
_C
_C _R
IM T_E
EL
_ E_ _
UM
VF NT
DC DL UP
_O F_C
_N
LE C_I RA_
ER
VF
DC V
d)
D A
LE C_O
_O
LE C_P
_T
ve
DC
r
se
D
LE
LE
LE
(re
RY
31 17 16 15 14 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LEDC_TIMER_SEL_CHn This field is used to select one of the timers for channel n.
0: select Timer0; 1: select Timer1; 2: select Timer2; 3: select Timer3 (R/W)
A
LEDC_SIG_OUT_EN_CHn Set this bit to enable signal output on channel n. (R/W)
LEDC_IDLE_LV_CHn This bit is used to control the output value when channel n is inactive (when
LEDC_SIG_OUT_EN_CHn is 0). (R/W)
IN
LEDC_PARA_UP_CHn This bit is used to update the listed fields below for channel n, and will be
automatically cleared by hardware. (WT)
IM
• LEDC_HPOINT_CHn
• LEDC_DUTY_START_CHn
• LEDC_SIG_OUT_EN_CHn
• LEDC_TIMER_SEL_CHn
EL
• LEDC_DUTY_NUM_CHn
• LEDC_DUTY_CYCLE_CHn
• LEDC_DUTY_SCALE_CHn
PR
• LEDC_DUTY_INC_CHn
• LEDC_OVF_CNT_EN_CHn
LEDC_OVF_NUM_CHn This field is used to configure the maximum times of overflow minus 1.
The LEDC_OVF_CNT_CHn_INT interrupt will be triggered when channel n overflows for
(LEDC_OVF_NUM_CHn + 1) times. (R/W)
LEDC_OVF_CNT_EN_CHn This bit is used to count the number of times when the timer selected by
channel n overflows. (R/W)
LEDC_OVF_CNT_RESET_CHn Set this bit to reset the timer-overflow counter of channel n. (WT)
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Register 26.2. LEDC_CHn_CONF1_REG (n: 05) (0x000C+20*n)
Hn
n
CH Hn
CH
Hn
_C
C_ C
n
_
IN T_
_C
LE
CL
Y_ AR
UM
CA
CY
UT ST
_N
_S
_D TY_
Y_
TY
Y
UT
UT
DC U
DU
LE C_D
_D
_D
_
DC
DC
DC
D
LE
LE
LE
LE
31 30 29 20 19 10 9 0
0 1 0x0 0x0 0x0 Reset
LEDC_DUTY_SCALE_CHn This field configures the step size of the duty cycle change during fading.
(R/W)
RY
LEDC_DUTY_CYCLE_CHn The duty will change every LEDC_DUTY_CYCLE_CHn cycle on channel
n. (R/W)
LEDC_DUTY_NUM_CHn This field controls the number of times the duty cycle will be changed. (R/W)
A
LEDC_DUTY_INC_CHn This bit determines whether the duty cycle of the output signal on channel n
increases or decreases. 1: Increase; 0: Decrease. (R/W)
LEDC_DUTY_START_CHn If this bit is set to 1, other configured fields in LEDC_CHn_CONF1_REG
will take effect upon the next timer overflow. (R/W/SC)
IN
IM
Register 26.3. LEDC_CONF_REG (0x00D0)
L
SE
_
LK
N
_C
_E
PB
LK
d )
_C
_A
ve
DC
DC
ser
EL
LE
LE
(re
31 30 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LEDC_APB_CLK_SEL This field is used to select the common clock source for all the 4 timers.
1: APB_CLK; 2: FOSC_CLK; 3: XTAL_CLK. (R/W)
PR
LEDC_CLK_EN This bit is used to control the clock.
1: Force clock on for register. 0: Support clock only when application writes registers. (R/W)
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Register 26.4. LEDC_CHn_HPOINT_REG (n: 05) (0x0004+20*n)
n
CH
T_
IN
PO
)
ed
_H
rv
DC
se
LE
(re
31 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00 Reset
LEDC_HPOINT_CHn The output value changes to high when the selected timer for this channel has
reached the value specified by this field. (R/W)
RY
Register 26.5. LEDC_CHn_DUTY_REG (n: 05) (0x0008+20*n)
Hn
_C
U TY
d)
_D
e
rv
DC
se
A LE
(re
31 19 18 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0x000 Reset
IN
LEDC_DUTY_CHn This field is used to change the output duty by controlling the Lpoint. The output
value turns to low when the selected timer for this channel has reached the Lpoint. (R/W)
IM
Register 26.6. LEDC_CHn_DUTY_R_REG (n: 05) (0x0010+20*n)
n
CH
R_
Y_
UT
d)
EL
_D
e
rv
DC
se
LE
(re
31 19 18 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0x000 Reset
LEDC_DUTY_R_CHn This field stores the current duty cycle of the output signal on channel n. (RO)
PR
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Register 26.7. LEDC_TIMERx_CONF_REG (x: 03) (0x00A0+8*x)
ES
P
_R
_U
ER
E
TY
US
RA
IM
x_ T
DU
ER S
PA
PA
_T
R
IV
D d) x_
IM x_
x_
_D
LE rve ER
_T ER
ER
LK
se IM
DC IM
IM
)
ed
_C
(re C_T
LE C_T
T
C_
rv
DC
se
D
LE
LE
LE
(re
31 26 25 24 23 22 21 4 3 0
0 0 0 0 0 0 0 0 1 0 0x000 0x0 Reset
LEDC_TIMERx_DUTY_RES This field is used to control the range of the counter in timer x. (R/W)
LEDC_CLK_DIV_TIMERx This field is used to configure the divisor for the divider in timer x. The least
RY
significant eight bits represent the fractional part. (R/W)
LEDC_TIMERx_PAUSE This bit is used to suspend the counter in timer x. (R/W)
LEDC_TIMERx_RST This bit is used to reset timer x. The counter will show 0 after reset. (R/W)
LEDC_TIMERx_PARA_UP Set this bit to update LEDC_CLK_DIV_TIMERx and
A
LEDC_TIMERx_DUTY_RES. (WT)
IN
Register 26.8. LEDC_TIMERx_VALUE_REG (x: 03) (0x00A4+8*x)
T
CN
x_
ER
IM
IM
d)
_T
e
rv
DC
se
LE
(re
31 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EL
LEDC_TIMERx_CNT This field stores the current counter value of timer x. (RO)
PR
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0
0
31
31
0
0
0
0
0
0
0
0
Espressif Systems
0
0
(R/WTC/SS)
set to 1. (RO)
0
0
PR
0
0
(re (re
s
0
0
se
rve
er
ve
26 LED PWM Controller (LEDC)
0
0
d) d)
0
0
0
0
0
0
LEDC_OVF_CNT_CHn_INT_ST This
EL
0
0
is
0
0
0
16
0
16
ual change of duty has finished. (R/WTC/SS)
the
0
0
15
15
LE LE
D D
523
IM
0
0
14
14
LE C_O LE C_O
DC V DC V
0
0
13
13
LE _O F_C LE _O F_C
D V N D V N
0
0
12
12
LE C_O F_C T_C LE C_O F_C T_C
masked
D V N H D V N H
0
0
11
11
LE C_O F_C T_C 5_I LE C_O F_C T_C 5_I
D V N H NT DC V N H NT
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0
0
interrupt when LEDC_TIMERx_OVF_INT_ENA is set to 1. (RO)
10
10
LE C_O F_C T_C 4_I _S LE _O F_C T_C 4_I _R
D V N H NT T D V N H NT AW
9
9
0
0
LE C_O F_C T_C 3_I _S
D V N H NT T
IN reached the value specified by LEDC_OVF_NUM_CHn. (R/WTC/SS)
LE C_O F_C T_C 3_I _R
D V N H NT AW
8
8
0
0
interrupt
LE C_D F_C T_C 2_I _S LE C_D F_C T_C 2_I _R
D U N H NT T D U N H NT AW
Register 26.10. LEDC_INT_ST_REG (0x00C4)
Register 26.9. LEDC_INT_RAW_REG (0x00C0)
7
7
0
0
LE C_D TY_ T_C 1_I _S LE C_D TY_ T_C 1_I _R
D U C H NT T D U C H NT AW
6
6
0
0
LE C_D TY_ HN 0_I _S LE C_D TY_ HN 0_I _R
D U C G_ NT T D U C G_ NT AW
A
5
5
0
0
status
LE C_D TY_ HN EN _S LE C_D TY_ HN EN _R
D U C G_ D_ T D U C G_ D_ AW
4
4
0
0
LE C_D TY_ HN EN CH LE C_D TY_ HN EN CH
D U C G_ D_ 5_ D U C G _ D _ 5_
3
3
bit
0
0
LE C_D TY_ HN EN CH IN LE C_D TY_ HN EN CH IN
D U C G_ D_ 4_ T_ D U C G_ D_ 4_ T_
2
2
0
0
LE C_T TY_ HN EN CH IN ST LE C_T TY_ HN EN CH IN RAW
D IM C G_ D_ 3_ T_ D IM C G_ D_ 3_ T_
for
1
1
0
0
LE C_T ER HN EN CH IN ST LE C_T ER HN EN CH IN RAW
LEDC_OVF_CNT_CHn_INT interrupt when LEDC_OVF_CNT_CHn_INT_ENA is set to 1. (RO)
D IM 3_ G_ D_ 2_ T_ D IM 3_ G_ D_ 2_ T_
0
0
LE C_T ER OV EN CH IN ST LE C_T ER OV EN CH IN RAW
DC IM 2_ F_ D_ 1_ T_S DC IM 2_ F_ D_ 1_ T_R
the
LEDC_DUTY_CHNG_END_CHn_INT interrupt when LEDC_DUTY_CHNG_END_CHn_INT_ENA is
LEDC_DUTY_CHNG_END_CHn_INT_ST This is the masked interrupt status bit for the
LEDC_TIMERx_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMERx_OVF_INT
LEDC_OVF_CNT_CHn_INT_RAW Interrupt raw bit for channel n. Triggered when the ovf_cnt has
LEDC_DUTY_CHNG_END_CHn_INT_RAW Interrupt raw bit for channel n. Triggered when the grad-
LEDC_TIMERx_OVF_INT_RAW Triggered when the timerx has reached its maximum counter value.
_T ER OV INT CH INT T _T ER OV INT CH INT AW
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IM 1_ F_ _S 0_ _S IM 1_ F_ _R 0_ _R
0 Reset
0 Reset
ER OV IN T IN T ER OV IN AW IN A
0_ F_ T_S T_ 0_ F_ T_R T_ W
ESP32-C3 TRM (Pre-release v0.4)
O IN T ST O IN A RA
VF T_ VF T_ W W
_I ST _I R
NT NT AW
_S _R
T AW
0
0
31
31
0
0
0
0
0
0
(R/W)
0
0
Espressif Systems
0
0
rupt. (R/W)
0
0
PR
0
0
(re (re
0
0
se se
rve rv
ed
26 LED PWM Controller (LEDC)
0
0
d) )
0
0
0
0
0
0
EL
0
0
0
0
0
16
0
16
LEDC_DUTY_CHNG_END_CHn_INT_CLR Set
LEDC_DUTY_CHNG_END_CHn_INT_ENA The
0
0
15
15
LE LE
D D
524
IM
0
0
14
14
LE C_O LE C_O
DC V DC V
LEDC_DUTY_CHNG_END_CHn_INT interrupt. (WT)
0
0
13
13
LEDC_DUTY_CHNG_END_CHn_INT interrupt. (R/W)
LE _O F_C LE _O F_C
D V N D V N
0
0
this
12
12
LE C_O F_C T_C LE C_O F_C T_C
D V N H D V N H
0
0
11
11
interrupt
LE C_O F_C T_C 5_I LE C_O F_C T_C 5_I
DC V N H NT DC V N H NT
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0
0
10
10
LE _O F_C T_C 4_I _C LE _O F_C T_C 4_I _E
D V N H NT LR D V N H NT NA
9
9
0
0
bit
LE C_O F_C T_C 3_I _C
D V N H NT LR
IN LE C_O F_C T_C 3_I _E
D V N H NT NA
8
8
0
0
LE C_D F_C T_C 2_I _C LE C_D F_C T_C 2_I _E
D U N H NT LR D U N H NT NA
Register 26.11. LEDC_INT_ENA_REG (0x00C8)
7
7
Register 26.12. LEDC_INT_CLR_REG (0x00CC)
0
0
enable
LE C_D TY_ T_C 1_I _C LE C_D TY_ T_C 1_I _E
D U C H NT LR D U C H NT NA
to
6
6
0
0
LE C_D TY_ HN 0_I _C LE C_D TY_ HN 0_I _E
DC U C G_ NT LR D U C G_ NT NA
A
5
5
0
0
LE _D TY_ HN EN _C LE C_D TY_ HN EN _E
bit
D U C G_ D_ LR D U C G_ D_ NA
4
4
0
0
LE C_D TY_ HN EN CH LE C_D TY_ HN EN CH
D U C G_ D_ 5_ D U C G _ D _ 5_
3
3
0
0
LE C_D TY_ HN EN CH IN LE C_D TY_ HN EN CH IN
D U C G_ D_ 4_ T_ D U C G_ D_ 4_ T_
clear
2
2
0
0
for
LE C_T TY_ HN EN CH IN CLR LE C_T TY_ HN EN CH IN ENA
D IM C G_ D_ 3_ T_ D IM C G_ D_ 3_ T_
1
1
0
0
LE C_T ER HN EN CH IN CLR LE C_T ER HN EN CH IN ENA
LEDC_TIMERx_OVF_INT_CLR Set this bit to clear the LEDC_TIMERx_OVF_INT interrupt. (WT)
D IM 3_ G_ D_ 2_ T_ D IM 3_ G_ D_ 2_ T_
0
0
LE C_T ER OV EN CH IN CLR LE C_T ER OV EN CH IN ENA
DC IM 2_ F_ D_ 1_ T_C DC IM 2_ F_ D_ 1_ T_E
LEDC_OVF_CNT_CHn_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CHn_INT interrupt. (WT)
the
the
LEDC_OVF_CNT_CHn_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CHn_INT inter-
LEDC_TIMERx_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMERx_OVF_INT interrupt.
_T ER OV INT CH INT LR _T ER OV INT CH INT NA
RY
IM 1_ F_ _C 0_ _C IM 1_ F_ _E 0_ _E
0 Reset
0 Reset
ER OV IN LR IN L ER OV IN NA IN N
0_ F_ T_C T_ R 0_ F_ T_E T_ A
ESP32-C3 TRM (Pre-release v0.4)
O IN L CL O IN N EN
VF T_ R R VF T_ A A
_I C _I EN
NT LR NT A
_C _E
LR NA
26 LED PWM Controller (LEDC)
Register 26.13. LEDC_DATE_REG (0x00FC)
E
AT
_D
DC
LE
C_
D
LE
31 0
0x19061700 Reset
LEDC_LEDC_DATE This is the version control register. (R/W)
A RY
IN
IM
EL
PR
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27 Remote Control Peripheral (RMT)
27 Remote Control Peripheral (RMT)
27.1 Overview
The RMT (Remote Control) module is designed to send and receive infrared remote control signals. A variety of
remote control protocols are supported. The RMT module converts pulse codes stored in the module’s built-in
RAM into output signals, or converts input signals into pulse codes and stores them back in RAM. Optionally, the
RMT module modulates its output signals with a carrier wave, or demodulates and filters its input signals.
The RMT module has four channels, numbered from zero to three. Channels 0 ~ 1 (TX channels) are dedicated to
transmit signals, and channels 2 ~ 3 (RX channels) to receive signals. Each TX/RX channel has the same
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functionality controlled by a dedicated set of registers and is able to independently either transmit or receive data.
TX channels are indicated by n which is used as a placeholder for the channel number, and by m for RX
channels.
27.2 Features
A
• Two TX channels
• Two RX channels IN
• Support multiple channels (programmable) transmitting data simultaneously
• Four channels share a 192 x 32-bit RAM
• Support modulation on TX pulses
IM
• Support filtering and demodulation on RX pulses
• Wrap TX mode
• Wrap RX mode
• Continuous TX mode
EL
27.3 Functional Description
PR
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27.3.1 RMT Architecture
A RY
IN
IM
Figure 271. RMT Architecture
The RMT module has four independent channels, two of which are TX channels and the other two are RX
EL
channels. Each TX channel has its own clock-divider counter, state machine, and transmitter. Each RX channel
also has its own clock-divider counter, state machine, and receiver. The four channels share a 192 x 32-bit
RAM.
27.3.2 RMT RAM
PR
Figure 272. Format of Pulse Code in RAM
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Figure 27-2 shows the format of pulse code in RAM. Each pulse code contains a 16-bit entry with two fields,
level and period.
• Level (0 or 1): indicates a low-/high-level value was received or is going to be sent.
• Period: points out how many clk_div clock cycles the level lasts for, see Figure 27-1.
A zero (0) period is interpreted as a transmission end-marker. If the period is not an end-marker, its value is
limited by APB clock and RMT clock:
3 × Tapb_clk + 5 × Trmt_sclk < period × Tclk_div (1)
The RAM is divided into four 48 x 32-bit blocks. By default, each channel uses one block, block zero for channel
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zero, block one for channel one, and so on.
If the data size of one single transfer is larger than this block size of TX channel n or RX channel m, users can
configure the channel
• to enable wrap mode by setting RMT_MEM_TX_WRAP_EN_CHn/m.
A
• or to use more blocks by configuring RMT_MEM_SIZE_CHn/m.
Setting RMT_MEM_SIZE_CHn/m > 1 allows channel n/m to use the memory of subsequent channels, block
(n/m) ~ block (n/m + RMT_MEM_SIZE_CHn/m -1). If so, the subsequent channels n/m + 1 ~ n/m +
IN
RMT_MEM_SIZE_CHn/m - 1 can not be used once their RAM blocks are occupied.
Note that the RAM used by each channel is mapped from low address to high address. In such mode, channel 0
is able to use the RAM blocks for channels 1, 2 and 3 by setting RMT_MEM_SIZE_CH0, but channel 3 can not
use the blocks for channels 0, 1, or 2. Therefore, the maximum value of RMT_MEM_SIZE_CHn should not
IM
exceed (4 - n) and the maximum value of RMT_MEM_SIZE_CHm should not exceed (2 - m).
The RMT RAM can be accessed via APB bus, or read by the transmitter and written by the receiver. To avoid any
possible access conflict between the receiver and the APB bus, RMT can be configured to designate the RAM
block’s owner, be it the receiver or the APB bus, by configuring RMT_MEM_OWNER_CHm. If this ownership is
EL
violated, a flag signal RMT_CHm_OWNER_ERR will be generated.
APB bus is able to access RAM in FIFO mode and in Direct Address (NONFIFO) mode, depending on the
configuration of RMT_FIFO_MASK:
• 1: use NONFIFO mode;
PR
• 0: use FIFO mode.
In FIFO mode, the APB reads data from or writes data to RAM via a fixed address stored in
RMT_CHn/mDATA_REG. In NONFIFO mode, the APB writes data to or reads data from a continuous address
range. The write-starting address of TX channel n is: RMT base address + 0x800 + (n - 1) x 48. The access
address for the second data and the following data are RMT base address + 0x800 + (n - 1) x 48 + 0x4, and so
on, incremented by 0x4. The read-starting address of RX channel m is: RMT base address + 0x860 + (m - 1) x
48. The access address for the second data and the following data are RMT base address + 0x860 + (m - 1) x
48 + 0x4, and so on, incremented by 0x4.
When the RMT module is inactive, the RAM can be put into low-power mode by setting
RMT_MEM_FORCE_PD.
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27.3.3 Clock
The clock source of RMT can be APB_CLK, FOSC_CLK or XTAL_CLK, depending on the configuration of
RMT_SCLK_SEL. RMT clock can be enabled by setting RMT_SCLK_ACTIVE. RMT working clock (rmt_sclk) is
obtained by dividing the selected clock source with a fractional divider, see Figure 27-1. The divider is:
RM T _SCLK_DIV _N U M + 1 + RM T _SCLK_DIV _A/RM T _SCLK_DIV _B
For more information, please check Chapter 6 Reset and Clock.
RMT_DIV_CNT_CHn/m is used to configure the divider coefficient of internal clock divider for RMT channels. The
coefficient is normally equal to the value of RMT_DIV_CNT_CHn/m, except value 0 that represents coefficient
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256. The clock divider can be reset by clearing RMT_REF_CNT_RST_CHn/m. The clock generated from the
divider can be used by the counter (see Figure 27-1).
27.3.4 Transmitter
27.3.4.1 Normal TX Mode
A
When RMT_TX_START_CHn is set, the transmitter of channel n starts reading and sending pulse codes from the
starting address of its RAM block. The codes are sent starting from low-address entry.
IN
When an end-marker (a zero period) is encountered, the transmitter stops the transmission, returns to idle state
and generates an RMT_CHn_TX_END_INT interrupt. Setting RMT_TX_STOP_CHn to 1 also stops the
transmission and immediately sets the transmitter back to idle.
The output level of a transmitter in idle state is determined by the “level” field of the end-marker or by the content
IM
of RMT_IDLE_OUT_LV_CHn, depending on the configuration of RMT_IDLE_OUT_EN_CHn.
To implement the above-mentioned configurations, please set RMT_CONF_UPDATE_CHn first. For more
information, see Section 27.3.6.
EL
27.3.4.2 Wrap TX Mode
To transmit more pulse codes than can be fitted in the channel’s RAM, users can enable wrap TX mode by
setting RMT_MEM_TX_WRAP_EN_CHn. In this mode, the transmitter sends the data from RAM in loops till an
end-marker is encountered.
PR
For example, if RMT_MEM_SIZE_CHn = 1, the transmitter starts sending data from the address 48 * n, and then
the data from higher RAM address. Once the transmitter finishes sending the data from (48 * (n + 1) - 1), it
continues sending data from 48 * n again till an end-marker is encountered. Wrap mode is also applicable for
RMT_MEM_SIZE_CHn > 1.
When the size of transmitted pulse codes is larger than or equal to the value set by RMT_TX_LIM_CHn, an
RMT_CHn_TX_THR_EVENT_INT interrupt is triggered. In wrap mode, RMT_TX_LIM_CHn can be set to a half or
a fraction of the size of the channel’s RAM block. When an RMT_CHn_TX_THR_EVENT_INT interrupt is detected
by software, the already used RAM region can be updated with new pulse codes. In this way the transmitter can
seamlessly send unlimited pulse codes in wrap mode.
To update the configuration of RMT_MEM_TX_WRAP_EN_CHn, RMT_MEM_SIZE_CHn, and RMT_TX_LIM_CHn,
please set RMT_CONF_UPDATE_CHn first. For more information, see Section 27.3.6.
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27.3.4.3 TX Modulation
Transmitter output can be modulated with a carrier wave by setting RMT_CARRIER_EN_CHn. The carrier
waveform is configurable.
In a carrier cycle, high level lasts for (RMT_CARRIER_HIGH_CHn + 1) rmt_sclk cycles, while low level lasts for
(RMT_CARRIER_LOW_CHn + 1) rmt_sclk cycles. When RMT_CARRIER_OUT_LV_CHn is set, carrier wave is
added on the high-level of output signals; while RMT_CARRIER_OUT_LV_CHn is cleared, carrier wave is added
on the low-level of output signals.
Carrier wave can be added on all output signals during modulation, or just added on valid pulse codes (the data
stored in RAM), depending on the configuration of RMT_CARRIER_EFF_EN_CHn:
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• 0: add carrier wave on all output signals;
• 1: add carrier wave only on valid signals.
To implement the modulation configuration, please set RMT_CONF_UPDATE_CHn first. For more information,
see Section 27.3.6.
A
27.3.4.4 Continuous TX Mode
This continuous TX mode can be enabled by setting RMT_TX_CONTI_MODE_CHn. In this mode, the transmitter
sends the pulse codes from RAM in loops.
IN
• If an end-marker is encountered, the transmitter starts transmitting the first data again.
• If no end-marker is encountered, the transmitter starts transmitting the first data again after the last data is
transmitted.
IM
If RMT_TX_LOOP_CNT_EN_CHn is set, the loop counting is incremented by 1 each time an end-marker is
encountered. If the counting reaches the value set in RMT_TX _LOOP_NUM_CHn, an RMT_CHn_TX_LOOP_INT
is generated.
In an end-marker, if its period[14:0] is 0, then the period of the previous data must satisfy the following
EL
requirement:
6 × Tapb_clk + 12 × Trmt_sclk < period × Tclk_div (2)
The period of the other data only need to satisfy relation (1).
To implement the above-mentioned configuration, please set RMT_CONF_UPDATE_CHn first. For more
PR
information, see Section 27.3.6.
27.3.4.5 Simultaneous TX Mode
RMT module supports multiple channels transmitting data simultaneously. To use this function, follow the steps
below.
1. Configure RMT_TX_SIM_CHn to choose which multiple channels are used to transmit data simultaneously.
2. Set RMT_TX_SIM_EN to enable this transmission mode.
3. Set RMT_TX_START_CHn for each selected channel, to start data transmitting.
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Once the last channel is configured, these channels start transmitting data simultaneously. Due to hardware
limitations, there is no guarantee that two channels can start sending data exactly at the same time. The interval
between two channels starting transmitting data is within 3 x Tclk_div .
To configure RMT_TX_SIM_EN, please set RMT_CONF_UPDATE_CHn first. For more information, see Section
27.3.6.
27.3.5 Receiver
27.3.5.1 Normal RX Mode
The receiver of channel m is controlled by RMT_RX_EN_CHm:
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• RMT_RX_EN_CHm = 1, the receiver starts working.
• RMT_RX_EN_CHm = 0, the receiver stops receiving data.
When the receiver becomes active, it starts counting from the first edge of the signal, detecting signal levels and
counting clock cycles the level lasts for. Each cycle count is then written back to RAM.
When the receiver detects no change in a signal level for a number of clock cycles more than the value set by
A
RMT_IDLE_THRES_CHm, the receiver will stop receiving data, return to idle state, and generate an
RMT_CHm_RX_END_INT interrupt. IN
Please note that RMT_IDLE_THRES_CHm should be configured to a maximum value according to your
application, otherwise a valid received level may be mistaken as a level in idle state.
If RAM block of this RX channel is used up by the received data, the receiver will stop receiving data, and
generate an RMT_CHn_ERR_INT interrupt triggered by RAM FULL event.
IM
To implement configuration above, please set RMT_CONF_UPDATE_CHm first. For more information, see
Section 27.3.6.
27.3.5.2 Wrap RX Mode
EL
To receive more pulse codes than can be fitted in the channel’s RAM, users can enable wrap RX mode for
channel m by configuring RMT_MEM_RX_WRAP_EN_CHm. In wrap mode, the receiver stores the received data
to RAM block of this channel in loops.
Receiving ends, when the receiver detects no change in a signal level for a number of clock cycles more than the
PR
value set by RMT_IDLE_THRES_CHm. The receiver then returns to idle state and generates an
RMT_CHm_RX_END_INT interrupt.
For example, if RMT_MEM_SIZE_CHm is set to 1, the receiver starts receiving data and stores the data to
address 48 * m, and then to higher RAM address. When the receiver finishes storing the received data to
address (48 * (m + 1) - 1), the receiver continues receiving data and storing data to the address 48 * m again, till
no change is detected on a signal level for more than RMT_IDLE_THRES_CHm clock cycles. Wrap mode is also
applicable for RMT_MEM_SIZE_CHm > 1.
An RMT_CHm_RX_THR_EVENT_INT is generated when the size of received pulse codes is larger than or equal to
the value set by RMT_RX_LIM_CHm. In wrap mode, RMT_RX_LIM_CHM can be set to a half or a fraction of the
size of the channel’s RAM block. When an RMT_CHm_RX_THR_EVENT_INT interrupt is detected by software,
the system will be notified to copy out data stored in already used RMT RAM region, and then the region can be
updated by subsequent data. In this way an arbitrary amount of data can be seamlessly received.
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To implement the configuration above, please set RMT_CONF_UPDATE_CHm first. For more information, see
Section 27.3.6.
27.3.5.3 RX Filtering
Users can enable the receiver to filter input signals by setting RMT_RX_FILTER_EN_CHm for each channel. The
filter samples input signals continuously, and detects the signals which remain unchanged for a continuous
RMT_RX_FILTER_THRES_CHm rmt_sclk cycles as valid, otherwise, the signals are rejected. Only the valid
signals can pass through this filter. The filter removes pulses with a length of less than
RMT_RX_FILTER_THRES_CHn rmt_sclk cycles.
To implement the configuration above, please set RMT_CONF_UPDATE_CHm first. For more information, see
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Section 27.3.6.
27.3.5.4 RX Demodulation
Users can enable demodulation function on input signals or on filtered output signals by setting
RMT_CARRIER_EN_CHm. RX demodulation can be applied to high-level carrier wave or low-level carrier wave,
A
depending on the configuration of RMT_CARRIER_OUT_LV_CHm:
• 1: demodulate high-level carrier wave IN
• 0: demodulate low-level carrier wave
Users can configure RMT_CARRIER_HIGH_THRES_CHm and RMT_CARRIER_LOW_THRES_CHm to set the
thresholds to demodulate high-level carrier wave or low-level carrier wave.
If the high-level of a signal lasts for less than RMT_CARRIER_HIGH_THRES_CHm clk_div cycles, or the low-level
IM
lasts for less than RMT_CARRIER_LOW_THRES_CHm clk_div cycles, such level is detected as a carrier wave
and then is filtered out.
To implement the configuration above, please set RMT_CONF_UPDATE_CHm first. For more information, see
Section 27.3.6.
EL
27.3.6 Configuration Update
To update RMT registers configuration, please set RMT_CONF_UPDATE_CHn/m for each channel first.
All the bits/fields listed in the second column of Table 27-1 should follow this rule.
PR
Table 271. Configuration Update
Register Bit/Field Configuration Update
TX Channels
RMT_CARRIER_OUT_LV_CHn
RMT_CARRIER_EN_CHn
RMT_CARRIER_EFF_EN_CHn
RMT_DIV_CNT_CHn
RMT_CHnCONF0_REG
RMT_TX_STOP_CHn
RMT_IDLE_OUT_EN_CHn
RMT_IDLE_OUT_LV_CHn
RMT_TX_CONTI_MODE_CHn
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Register Bit/Field Configuration Update
RMT_CARRIER_HIGH_CHn
RMT_CHnCARRIER_DUTY_REG
RMT_CARRIER_LOW_CHn
RMT_TX_LOOP_CNT_EN_CHn
RMT_CHn_TX_LIM_REG RMT_TX_LOOP_NUM_CHn
RMT_TX_LIM_CHn
RMT_CHn_TX_SIM_REG RMT_TX_SIM_EN
RX Channels
RMT_CARRIER_OUT_LV_CHm
RMT_CARRIER_EN_CHm
RMT_CHmCONF0_REG
RMT_IDLE_THRES_CHm
RY
RMT_DIV_CNT_CHm
RMT_RX_FILTER_THRES_CHm
RMT_CHmCONF1_REG
RMT_RX_EN_CHm
RMT_CARRIER_HIGH_THRES_CHm
RMT_CHm_RX_CARRIER_RM_REG
RMT_CARRIER_LOW_THRES_CHm
RMT_CHm_RX_LIM_REG RMT_RX_LIM_CHm
A
RMT_REF_CNT_RST_REG RMT_REF_CNT_RST_CHm
27.3.7 Interrupts
IN
• RMT_CHn/m_ERR_INT: triggered when channel n/m does not read or write data correctly. For example, if
the transmitter still tries to read data from RAM when the RAM is empty, or the receiver still tries to write
data into RAM when the RAM is full, this interrupt will be triggered.
IM
• RMT_CHn_TX_THR_EVENT_INT: triggered when the amount of data the transmitter has sent matches the
value of RMT_CHn_TX_LIM_REG.
• RMT_CHm_RX_THR_EVENT_INT: triggered each time when the amount of data received by the receiver
reaches the value set in RMT_CHm_RX_LIM_REG.
EL
• RMT_CHn_TX_END_INT: Triggered when the transmitter has finished transmitting signals.
• RMT_CHm_RX_END_INT: Triggered when the receiver has finished receiving signals.
• RMT_CHn_TX_LOOP_INT: Triggered when the loop counting reaches the value set by
PR
RMT_TX_LOOP_NUM_CHn.
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27.4 Register Summary
The addresses in this section are relative to RMT base address provided in Table 3-4 in Chapter 3 System and
Memory .
Name Description Address Access
FIFO R/W Registers
RMT_CH0DATA_REG The read and write data register for channel 0 by 0x0000 RO
APB FIFO access.
RMT_CH1DATA_REG The read and write data register for channel 1 by 0x0004 RO
APB FIFO access.
RMT_CH2DATA_REG The read and write data register for channel 2 by 0x0008 RO
RY
APB FIFO access.
RMT_CH3DATA_REG The read and write data register for channel 3 by 0x000C RO
APB FIFO access.
Configuration Registers
RMT_CH0CONF0_REG Configuration register 0 for channel 0 0x0010 varies
A
RMT_CH1CONF0_REG Configuration register 0 for channel 1 0x0014 varies
RMT_CH2CONF0_REG Configuration register 0 for channel 2 0x0018 R/W
RMT_CH2CONF1_REG Configuration register 1 for channel 2 0x001C varies
RMT_CH3CONF0_REG
RMT_CH3CONF1_REG
IN
Configuration register 0 for channel 3
Configuration register 1 for channel 3
0x0020
0x0024
R/W
varies
RMT_SYS_CONF_REG Configuration register for RMT APB 0x0068 R/W
RMT_REF_CNT_RST_REG Reset register for RMT clock divider 0x0070 WT
IM
Status Registers
RMT_CH0STATUS_REG Channel 0 status register 0x0028 RO
RMT_CH1STATUS_REG Channel 1 status register 0x002C RO
RMT_CH2STATUS_REG Channel 2 status register 0x0030 RO
RMT_CH3STATUS_REG Channel 3 status register 0x0034 RO
EL
Interrupt Registers
RMT_INT_RAW_REG Raw interrupt status 0x0038 R/WTC/SS
RMT_INT_ST_REG Masked interrupt status 0x003C RO
RMT_INT_ENA_REG Interrupt enable bits 0x0040 R/W
RMT_INT_CLR_REG Interrupt clear bits 0x0044 WT
PR
Carrier Wave Duty Cycle Registers
RMT_CH0CARRIER_DUTY_REG Duty cycle configuration register for channel 0 0x0048 R/W
RMT_CH1CARRIER_DUTY_REG Duty cycle configuration register for channel 1 0x004C R/W
RMT_CH2_RX_CARRIER_RM_REG Carrier remove register for channel 2 0x0050 R/W
RMT_CH3_RX_CARRIER_RM_REG Carrier remove register for channel 3 0x0054 R/W
TX Event Configuration Registers
RMT_CH0_TX_LIM_REG Configuration register for channel 0 TX event 0x0058 varies
RMT_CH1_TX_LIM_REG Configuration register for channel 1 TX event 0x005C varies
RMT_TX_SIM_REG RMT TX synchronous register 0x006C R/W
RX Event Configuration Registers
RMT_CH2_RX_LIM_REG Configuration register for channel 2 RX event 0x0060 R/W
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Name Description Address Access
RMT_CH3_RX_LIM_REG Configuration register for channel 3 RX event 0x0064 R/W
Version Register
RMT_DATE_REG Version control register 0x00CC R/W
27.5 Registers
The addresses in this section are relative to RMT base address provided in Table 3-4 in Chapter 3 System and
Memory.
Register 27.1. RMT_CHnDATA_REG (n = 0, 1) (0x0000, 0x0004)
RY
A
AT
nD
CH
T_
RM
31 0
0x000000 Reset
A
RMT_CHnDATA Read and write data for channel n via APB FIFO. (RO)
IN
Register 27.2. RMT_CHmDATA_REG (m = 2, 3) (0x0008, 0x000C)
m
DA
TA
IM T_
RM
CH
31 0
0x000000 Reset
RMT_CHmDATA Read and write data for channel m via APB FIFO. (RO)
EL
PR
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Register 27.3. RMT_CHnCONF0_REG (n = 0, 1) (0x0010, 0x0014)
_S D_ ST CH n
TX _R _R E_ CH
EF H Hn
Hn
TA RS _C n
T_ EM EM OD N_
_C CH n
) R_ _C C
n
_C
R T T_ H
Hn n
CH
T _ X_ _ n
ed IE N V_
T A n
F_ n
RM _M _M I_M P_E
RM _TX _T _L CH
EN
RM _A CO WR CH
rv R _E _L
E_
T EM UT N_
CH
se AR R T
T LE UT n
n
AT
RM ID O CH
(re C IE OU
V
CH
RM _M _O _E
E_
T d) UPD
T_ LE_ P_
T_ ARR R_
T_
IZ
PB N
RM _ID STO
RM _C RIE
CN
_S
RM rve F_
EM
se ON
T AR
V_
d)
T _
RM _TX
DI
ve
M
(re _C
RM _C
T_
T_
er
T
s
RM
RM
RM
RM
(re
31 25 24 23 22 21 20 19 18 16 15 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 1 1 1 0 0x1 0x2 0 0 0 0 0 0 0 0 Reset
RMT_TX_START_CHn Set this bit to start sending data in channel n. (WT)
RY
RMT_MEM_RD_RST_CHn Set this bit to reset RAM read address accessed by the transmitter for
channel n. (WT)
RMT_APB_MEM_RST_CHn Set this bit to reset RAM W/R address accessed by APB FIFO for chan-
nel n. (WT)
RMT_TX_CONTI_MODE_CHn Set this bit to enable continuous TX mode for channel n. (R/W)
A
In this mode, the transmitter starts its transmission from the first data, and in the following trans-
mission:
IN
• if an end-marker is encountered, the transmitter starts transmitting data from the first data
again;
• if no end-marker is encountered, the transmitter starts transmitting the first data again when
IM
the last data is transmitted.
RMT_MEM_TX_WRAP_EN_CHn Set this bit to enable wrap TX mode for channel n. In this mode, if
the TX data size is larger than the channel’s RAM block size, the transmitter continues transmitting
the first data to the last data in loops. (R/W)
EL
RMT_IDLE_OUT_LV_CHn This bit configures the level of output signal for channel n when the trans-
mitter is in idle state. (R/W)
RMT_IDLE_OUT_EN_CHn This is the output enable-bit for channel n in idle state. (R/W)
RMT_TX_STOP_CHn Set this bit to stop the transmitter of channel n sending data out. (R/W/SC)
PR
Continued on the next page...
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Register 27.3. RMT_CHnCONF0_REG (n = 0, 1) (0x0010, 0x0014)
Continued from the previous page...
RMT_DIV_CNT_CHn This field is used to configure the divider for clock of channel n. (R/W)
RMT_MEM_SIZE_CHn This register is used to configure the maximum number of memory blocks
allocated to channel n. (R/W)
RMT_CARRIER_EFF_EN_CHn 1: Add carrier modulation on the output signal only at data-sending
state for channel n. 0: Add carrier modulation on the output signal at data-sending state and idle
state for channel n. Only valid when RMT_CARRIER_EN_CHn is 1. (R/W)
RY
RMT_CARRIER_EN_CHn This is the carrier modulation enable-bit for channel n. 1: Add carrier mod-
ulation on the output signal. 0: No carrier modulation is added on output signal. (R/W)
RMT_CARRIER_OUT_LV_CHn This bit is used to configure the position of carrier wave for channel
n. (R/W)
A
1’h0: add carrier wave on low level.
1’h1: add carrier wave on high level. IN
RMT_CONF_UPDATE_CHn Synchronization bit for channel n (WT)
IM
EL
PR
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Register 27.4. RMT_CHmCONF0_REG (m = 2, 3) (0x0018, 0x0020)
Hm Hm
_C _C
Hm
EN LV
m
ed R_ T_
_C
CH
m
IE OU
CH
S
E_
RE
R R R_
_
IZ
NT
TH
CA IE
_S
_C
T_ ARR
_
EM
LE
RM d)
V
ID
DI
e
M
RM C
rv
rv
T_
T_
T_
T_
se
se
RM
RM
RM
(re
(re
31 30 29 28 27 26 25 23 22 8 7 0
0 0 1 1 0 0 0x1 0x7fff 0x2 Reset
RMT_DIV_CNT_CHm This field is used to configure the clock divider of channel m. (R/W)
RY
RMT_IDLE_THRES_CHm This field is used to configure RX threshold. When no edge is detected on
the input signal for continuous clock cycles longer than this field value, the receiver stops receiving
data. (R/W)
RMT_MEM_SIZE_CHm This field is used to configure the maximum number of memory blocks allo-
cated to channel m. (R/W)
A
RMT_CARRIER_EN_CHm This is the carrier modulation enable-bit for channel m. 1: Add carrier
modulation on output signal. 0: No carrier modulation is added on output signal. (R/W)
IN
RMT_CARRIER_OUT_LV_CHm This bit is used to configure the position of carrier wave for channel
m. (R/W)
1’h0: add carrier wave on low level.
IM
1’h1: add carrier wave on high level.
EL
PR
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Register 27.5. RMT_CHmCONF1_REG(m = 2, 3) (0x001C, 0x0024)
Hm
Hm
_C
CH ST Hm
_C
m
m
T_ EM EM R_C m
EN
_E R_ ST m
CH
m _CH
RM _M _M NE _CH
ES
RX _W _R H
N_ R _C
P_
E_
HR
RA
T B W N
AT
RM _A _O R_E
_T
W
T_ d) UPD
ER
X_
T EM E
ILT
RM _M FILT
_R
RM rve F_
_F
EM
se ON
T _
)
ed
P
RX
X
M
(re _C
RM _R
rv
T_
se
T
RM
RM
RM
31 (re 16 15 14 13 12 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xf 0 1 0 0 0 Reset
RMT_RX_EN_CHm Set this bit to enable the receiver to start receiving data in channel m. (R/W)
RY
RMT_MEM_WR_RST_CHm Set this bit to reset RAM write address accessed by the receiver for
channel m. (WT)
RMT_APB_MEM_RST_CHm Set this bit to reset RAM W/R address accessed by APB FIFO for chan-
nel m. (WT)
A
RMT_MEM_OWNER_CHm This bit marks the ownership of channel m’s RAM block. (R/W/SC)
1’h1: Receiver is using the RAM. IN
1’h0: APB bus is using the RAM.
RMT_RX_FILTER_EN_CHm Set this bit to enable the receiver’s filter for channel m. (R/W)
RMT_RX_FILTER_THRES_CHm When receiving data, the receiver ignores the input pulse when its
IM
width is shorter than this register value in units of rmt_sclk cycles. (R/W)
RMT_MEM_RX_WRAP_EN_CHm Set this bit to enable wrap RX mode for channel m. In this mode,
if the RX data size is larger than channel m’s RAM block size, the receiver stores the RX data from
the first address to the last address in loops. (R/W)
EL
RMT_CONF_UPDATE_CHm Synchronization bit for channel m. (WT)
PR
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27 Remote Control Peripheral (RMT)
Register 27.6. RMT_SYS_CONF_REG (0x0068)
K N
AS E_O
AP _C CE U
FI _F D
_M RC
UM
T_ EM OR _P
B_ LK _P
FO O
E
RM _M _F RCE
IV
_N
_B
A_
CT
IV
V
SE
T EM O
DI
DI
_D
N
_A
RM _M _F
K_
_
_E
LK
LK
LK
LK
T EM
K
CL
)
ed
SC
SC
SC
SC
CL
RM _M
S
rv
T_
T_
T_
T_
T_
T_
se
T
RM
RM
RM
RM
RM
RM
RM
(re
31 30 27 26 25 24 23 18 17 12 11 4 3 2 1 0
0 0 0 0 0 1 0x1 0x0 0x0 0x1 0 0 0 0 Reset
RMT_APB_FIFO_MASK 1’h1: Access memory directly. 1’h0: Access memory by FIFO. (R/W)
RY
RMT_MEM_CLK_FORCE_ON Set this bit to enable the clock for RMT memory. (R/W)
RMT_MEM_FORCE_PD Set this bit to power down RMT memory. (R/W)
RMT_MEM_FORCE_PU 1: Disable the power-down function of RMT memory in Light-sleep. 0:
Power down RMT memory when RMT is in Light-sleep mode. (R/W)
A
RMT_SCLK_DIV_NUM The integral part of the fractional divider. (R/W)
RMT_SCLK_DIV_A The numerator of the fractional part of the fractional divider. (R/W) IN
RMT_SCLK_DIV_B The denominator of the fractional part of the fractional divider. (R/W)
RMT_SCLK_SEL Choose the clock source of rmt_sclk. 1: APB_CLK; 2: RTC20M_CLK; 3:
XTAL_CLK. (R/W)
IM
RMT_SCLK_ACTIVE rmt_sclk switch. (R/W)
RMT_CLK_EN The enable signal of RMT register clock gate. 1: Power up the drive clock of registers.
0: Power down the drive clock of registers. (R/W)
EL
Register 27.7. RMT_REF_CNT_RST_REG (0x0070) F_ T_ T_ 3
T_ T_ 2
T_ 1
0
RE CN RS CH
CN RS CH
RS CH
CH
T_ EF_ T_ T_
RM _R _CN _RS
T EF T
RM _R _CN
PR
T EF
ed)
RM _R
rv
se
T
RM
(re
31 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_REF_CNT_RST_CH0 This bit is used to reset the clock divider of channel 0. (WT)
RMT_REF_CNT_RST_CH1 This bit is used to reset the clock divider of channel 1. (WT)
RMT_REF_CNT_RST_CH2 This bit is used to reset the clock divider of channel 2. (WT)
RMT_REF_CNT_RST_CH3 This bit is used to reset the clock divider of channel 3. (WT)
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27 Remote Control Peripheral (RMT)
Register 27.8. RMT_CHnSTATUS_REG (n = 0, 1) (0x0028, 0x002C)
D_ n H n
Hn
Hn
CH
_R CH _C
n
_C
C
CH
R_
EM _ R
R_
DR
M TY E R
ER
X_
DD
AD
B_ MP R_
E
R_
A
AP _E _W
_W
_R
DD
n
CH
EM
T_ EM EM
EM
A
_R
E_
M
RM M M
M
B_
T_ B_
B_
EM
AT
AP
AP
ST
M
RM A
T_
T_
T_
T_
T_
RM
RM
RM
RM
RM
31 24 23 22 21 20 12 11 9 8 0
0x0 0 0 0 0 0 0 Reset
RMT_MEM_RADDR_EX_CHn This field records the memory address offset when transmitter of
RY
channel n is using the RAM. (RO)
RMT_STATE_CHn This field records the FSM status of channel n. (RO)
RMT_APB_MEM_WADDR_CHn This field records the memory address offset when writes RAM over
APB bus. (RO)
A
RMT_APB_MEM_RD_ERR_CHn This status bit will be set if the offset address is out of memory size
(overflows) when reads RAM via APB bus. (RO)
RMT_MEM_EMPTY_CHn This status bit will be set when the TX data size is larger than the memory
size and the wrap TX mode is disabled. (RO)
IN
RMT_APB_MEM_WR_ERR_CHn This status bit will be set if the offset address is out of memory size
(overflows) when writes via APB bus. (RO)
IM
RMT_APB_MEM_RADDR_CHn This field records the memory address offset when reads RAM over
APB bus. (RO)
EL
PR
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Register 27.9. RMT_CHmSTATUS_REG (m = 2, 3) (0x0030, 0x0034)
Hm
m
CH
m
H
NE m C
CH
_C
W CH R_
R_
DR
X_
_O LL_ _ER
ER
_E
AD
R_
EM U D
DR
M _F _R
_R
m
AD
CH
T_ EM EM
EM
_W
E_
RM M M
_M
T_ B_
EM
AT
PB
d)
)
ed
ed
P
ST
ve
M
RM _A
A
rv
rv
T_
T_
T_
er
se
se
T
s
RM
RM
RM
RM
(re
(re
(re
31 28 27 26 25 24 22 21 20 12 11 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_MEM_WADDR_EX_CHm This field records the memory address offset when the receiver of
RY
channel m is using the RAM. (RO)
RMT_APB_MEM_RADDR_CHm This field records the memory address offset when reads RAM over
APB bus. (RO)
RMT_STATE_CHm This field records the FSM status of channel m. (RO)
A
RMT_MEM_OWNER_ERR_CHm This status bit will be set when the ownership of memory block is
wrong. (RO)
RMT_MEM_FULL_CHm This status bit will be set if the receiver receives more data than the memory
can fit. (RO)
IN
RMT_APB_MEM_RD_ERR_CHm This status bit will be set if the offset address is out of memory size
(overflows) when reads RAM via APB bus. (RO)
IM
EL
PR
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27 Remote Control Peripheral (RMT)
Register 27.10. RMT_INT_RAW_REG (0x0038)
T 2 R _ N NT AW
T H1 R T_ N T AW
RR T W T W
AW
RM _C _E _IN RA T_IN _RA
RM _C _E THR EVE T_I _R
RM _C _E _IN EVE T_IN _R
_R
T H3 _ _ N NT
T H1 X_ _ T_ W
T H0 _ _ N W
TX ND T W
ND NT AW
NT AW
AW
RM _C _R TH _IN RA
RM _C _T TH EVE RA
RM _C _T THR EVE T_I
0_ _E _IN _RA
_ E _ I _R
T H2 X_ P T_
_ I _R
_R
RR T W
T H2 X_ T_ W
T_ H1_ X_E _IN W
RM _C _R LOO _IN
RM _C _E _IN RA
RM C R IN A
RM _C _R EN RA
CH TX ND T
T_ 3_ _ _R
_
X_ P
D
R
R
RM _C _T LOO
T H0 _
R
R
X
X
X
RM C T
T_ H1_
T 3
T 0
)
ed
H
H
RM _C
rv
se
T
RM
31 (re 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
RMT_CH0_TX_END_INT_RAW The interrupt raw bit of RMT_CH0_TX_END_INT. (R/WTC/SS)
RMT_CH1_TX_END_INT_RAW The interrupt raw bit of RMT_CH1_TX_END_INT. (R/WTC/SS)
RMT_CH2_RX_END_INT_RAW The interrupt raw bit of RMT_CH2_RX_END_INT. (R/WTC/SS)
RMT_CH3_RX_END_INT_RAW The interrupt raw bit of RMT_CH3_RX_END_INT. (R/WTC/SS)
A
RMT_CH0_ERR_INT_RAW The interrupt raw bit of RMT_CH0_ERR_INT. (R/WTC/SS)
RMT_CH1_ERR_INT_RAW The interrupt raw bit of RMT_CH1_ERR_INT. (R/WTC/SS)
IN
RMT_CH2_ERR_INT_RAW The interrupt raw bit of RMT_CH2_ERR_INT. (R/WTC/SS)
RMT_CH3_ERR_INT_RAW The interrupt raw bit of RMT_CH3_ERR_INT. (R/WTC/SS)
RMT_CH0_TX_THR_EVENT_INT_RAW The interrupt raw bit of RMT_CH0_TX_THR_EVENT_INT.
IM
(R/WTC/SS)
RMT_CH1_TX_THR_EVENT_INT_RAW The interrupt raw bit of RMT_CH0_TX_THR_EVENT_INT.
(R/WTC/SS)
RMT_CH2_RX_THR_EVENT_INT_RAW The interrupt raw bit of RMT_CH2_RX_THR_EVENT_INT.
EL
(R/WTC/SS)
RMT_CH3_RX_THR_EVENT_INT_RAW The interrupt raw bit of RMT_CH3_RX_THR_EVENT_INT.
(R/WTC/SS)
RMT_CH0_TX_LOOP_INT_RAW The interrupt raw bit of RMT_CH0_TX_LOOP_INT. (R/WTC/SS)
PR
RMT_CH1_TX_LOOP_INT_RAW The interrupt raw bit of RMT_CH1_TX_LOOP_INT. (R/WTC/SS)
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27 Remote Control Peripheral (RMT)
Register 27.11. RMT_INT_ST_REG (0x003C)
T
T
RM _C _E _IN ST T_IN _ST
ST
RM _C _E THR EVE T_I _S
RM _C _E _IN EVE T_IN _S
T_
T H3 _ _ N NT
T 2 R _ N NT
T H1 R T_ N T
RM _C _R TH _IN ST
RM _C _T TH EVE ST
RM _C _T THR EVE T_I
0_ _E _IN _ST
ND NT T
_I _ST
T
_ E _I _S
T H2 X_ P T_
T H1 X_ _ T_
_S
T H0 _ _ N
RM _C _R LOO _IN
CH TX ND T
TX ND T
RM _C _E _IN ST
RM _C _R _IN ST
RM _C _R EN ST
NT
T_ H1_ X_E _IN
_
_
T H2 X_ T_
T 3 _ P
RR T
RR T
D
R
R
RM _C _T LOO
T H0 _
R
R
X
X
X
X
RM _C _T
T H1
T 0
T 3
)
ed
H
H
RM _C
rv
se
T
RM
(re
31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_CH0_TX_END_INT_ST The masked interrupt status bit for RMT_CH0_TX_END_INT. (RO)
RY
RMT_CH1_TX_END_INT_ST The masked interrupt status bit for RMT_CH1_TX_END_INT. (RO)
RMT_CH2_RX_END_INT_ST The masked interrupt status bit for RMT_CH2_RX_END_INT. (RO)
RMT_CH3_RX_END_INT_ST The masked interrupt status bit for RMT_CH3_RX_END_INT. (RO)
A
RMT_CH0_ERR_INT_ST The masked interrupt status bit for RMT_CH0_ERR_INT. (RO)
RMT_CH1_ERR_INT_ST The masked interrupt status bit for RMT_CH1_ERR_INT. (RO)
IN
RMT_CH2_ERR_INT_ST The masked interrupt status bit for RMT_CH2_ERR_INT. (RO)
RMT_CH3_ERR_INT_ST The masked interrupt status bit for RMT_CH3_ERR_INT. (RO)
RMT_CH0_TX_THR_EVENT_INT_ST The masked interrupt status bit for
IM
RMT_CH0_TX_THR_EVENT_INT. (RO)
RMT_CH1_TX_THR_EVENT_INT_ST The masked interrupt status bit for
RMT_CH1_TX_THR_EVENT_INT. (RO)
RMT_CH2_RX_THR_EVENT_INT_ST The masked interrupt status bit for
EL
RMT_CH2_RX_THR_EVENT_INT. (RO)
RMT_CH3_RX_THR_EVENT_INT_ST The masked interrupt status bit for
RMT_CH3_RX_THR_EVENT_INT. (RO)
RMT_CH0_TX_LOOP_INT_ST The masked interrupt status bit for RMT_CH0_TX_LOOP_INT. (RO)
PR
RMT_CH1_TX_LOOP_INT_ST The masked interrupt status bit for RMT_CH1_TX_LOOP_INT. (RO)
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27 Remote Control Peripheral (RMT)
Register 27.12. RMT_INT_ENA_REG (0x0040)
T 2 R _ N NT A
T H1 R T_ N T A
T_ A
A
N
N
RM _C _E _IN EN T_IN _EN
EN
RM _C _E THR EVE T_I _E
RM _C _E _IN EVE T_IN _E
T H3 _ _ N NT
T H1 X_ _ T_ A
T H0 _ _ N A
TX ND T A
ND NT NA
RM _C _R TH _IN EN
RM _C _T TH EVE EN
NT A
NA
RM _C _T THR EVE T_I
0_ _E _IN _EN
_I _EN
_ E _ I _E
T H2 X_ P T_
_E
RR T A
RR T A
A
T_ H1_ X_E _IN A
RM _C _R LOO _IN
RM _C _E _IN EN
RM _C _R _IN EN
RM _C _R EN EN
CH TX ND T
_
_
_
X_ P
T
D
R
R
RM _C _T LOO
T 2 _
T H0 _
R
R
X
X
X
X
RM C T
T_ H1_
T 3
T 0
T 3
d)
H
H
H
ve
RM _C
er
T
s
RM
31 (re 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
RMT_CH0_TX_END_INT_ENA The interrupt enable bit for RMT_CH0_TX_END_INT. (R/W)
RMT_CH1_TX_END_INT_ENA The interrupt enable bit for RMT_CH1_TX_END_INT. (R/W)
RMT_CH2_RX_END_INT_ENA The interrupt enable bit for RMT_CH2_RX_END_INT. (R/W)
RMT_CH3_RX_END_INT_ENA The interrupt enable bit for RMT_CH3_RX_END_INT. (R/W)
A
RMT_CH0_ERR_INT_ENA The interrupt enable bit for RMT_CH0_ERR_INT. (R/W)
RMT_CH1_ERR_INT_ENA The interrupt enable bit for RMT_CH1_ERR_INT. (R/W)
IN
RMT_CH2_ERR_INT_ENA The interrupt enable bit for RMT_CH2_ERR_INT. (R/W)
RMT_CH3_ERR_INT_ENA The interrupt enable bit for RMT_CH3_ERR_INT. (R/W)
RMT_CH0_TX_THR_EVENT_INT_ENA The interrupt enable bit for
IM
RMT_CH0_TX_THR_EVENT_INT. (R/W)
RMT_CH1_TX_THR_EVENT_INT_ENA The interrupt enable bit for
RMT_CH1_TX_THR_EVENT_INT. (R/W)
RMT_CH2_RX_THR_EVENT_INT_ENA The interrupt enable bit for
EL
RMT_CH2_RX_THR_EVENT_INT. (R/W)
RMT_CH3_RX_THR_EVENT_INT_ENA The interrupt enable bit for
RMT_CH3_RX_THR_EVENT_INT. (R/W)
RMT_CH0_TX_LOOP_INT_ENA The interrupt enable bit for RMT_CH0_TX_LOOP_INT. (R/W)
PR
RMT_CH1_TX_LOOP_INT_ENA The interrupt enable bit for RMT_CH1_TX_LOOP_INT. (R/W)
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Register 27.13. RMT_INT_CLR_REG (0x0044)
T 2 R _ N NT LR
T H1 R T_ N T LR
T_ LR
R
CL
RM _C _E THR EVE T_I _C
RM _C _E _IN EVE T_IN _C
RM _C _E _IN CL T_IN _C
T H3 _ _ N NT
T H1 X_ _ T_ R
T H0 _ _ N R
TX ND T R
ND NT LR
RM _C _R TH _IN CL
RM _C _T TH EVE CL
NT LR
LR
RM _C _T THR EVE T_I
0_ _E _IN _CL
_ E _ I _C
_ I _C
_C
T H2 X_ P T_
RR T R
T H3 R T_ R
R
T_ H1_ X_E _IN R
RM _C _R LOO _IN
CH TX ND T
RM _C _E _IN CL
RM _C _R _IN CL
RM _C _R EN CL
_
_
X_ P
T
D
R
R
RM _C _T LOO
T 2 _
T H0 _
R
R
R
X
X
X
X
RM C T
T_ H1_
T 3
T 0
)
ed
H
RM _C
rv
se
T
RM
31 (re 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
RMT_CH0_TX_END_INT_CLR Set this bit to clear the RMT_CH0_TX_END_INT interrupt. (WT)
RMT_CH1_TX_END_INT_CLR Set this bit to clear the RMT_CH1_TX_END_INT interrupt. (WT)
RMT_CH2_RX_END_INT_CLR Set this bit to clear the RMT_CH2_RX_END_IN interrupt. (WT)
RMT_CH3_RX_END_INT_CLR Set this bit to clear the RMT_CH3_RX_END_IN interrupt. (WT)
A
RMT_CH0_ERR_INT_CLR Set this bit to clear the RMT_CH0_ERR_INT interrupt. (WT)
RMT_CH1_ERR_INT_CLR Set this bit to clear the RMT_CH1_ERR_INT interrupt. (WT)
IN
RMT_CH2_ERR_INT_CLR Set this bit to clear the RMT_CH2_ERR_INT interrupt. (WT)
RMT_CH3_ERR_INT_CLR Set this bit to clear the RMT_CH3_ERR_INT interrupt. (WT)
RMT_CH0_TX_THR_EVENT_INT_CLR Set this bit to clear the RMT_CH0_TX_THR_EVENT_INT in-
IM
terrupt. (WT)
RMT_CH1_TX_THR_EVENT_INT_CLR Set this bit to clear the RMT_CH1_TX_THR_EVENT_INT in-
terrupt. (WT)
RMT_CH2_RX_THR_EVENT_INT_CLR Set this bit to clear the RMT_CH2_RX_THR_EVENT_INT in-
EL
terrupt. (WT)
RMT_CH3_RX_THR_EVENT_INT_CLR Set this bit to clear the RMT_CH3_RX_THR_EVENT_INT in-
terrupt. (WT)
RMT_CH0_TX_LOOP_INT_CLR Set this bit to clear the RMT_CH0_TX_LOOP_INT interrupt. (WT)
PR
RMT_CH1_TX_LOOP_INT_CLR Set this bit to clear the RMT_CH1_TX_LOOP_INT interrupt. (WT)
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Register 27.14. RMT_CHnCARRIER_DUTY_REG (n = 0, 1) (0x0048, 0x004C)
Hn
CH
_C
H_
W
IG
O
H
L
R_
R_
IE
IE
RR
RR
CA
CA
T_
T_
RM
RM
31 16 15 0
0x40 0x40 Reset
RMT_CARRIER_LOW_CHn This field is used to configure carrier wave’s low level clock period for
channel n. (R/W)
RY
RMT_CARRIER_HIGH_CHn This field is used to configure carrier wave’s high level clock period for
channel n. (R/W)
Register 27.15. RMT_CHm_RX_CARRIER_RM_REG (m = 2, 3) (0x0050, 0x0054)
A
m
Hm
CH
_C
S_
ES
RE
IN
HR
TH
_T
H_
W
IG
LO
_H
R_
R
IE
IE
RR
RR
CA
CA
T_
T_
RM
RM
IM
31 16 15 0
0x00 0x00 Reset
RMT_CARRIER_LOW_THRES_CHm The low level period in a carrier modulation mode is
(RMT_CARRIER_LOW_THRES_CHm + 1) for channel m. (R/W)
EL
RMT_CARRIER_HIGH_THRES_CHm The high level period in a carrier modulation mode is
(RMT_CARRIER_HIGH_THRES_CHm + 1) for channel m. (R/W)
PR
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Register 27.16. RMT_CHn_TX_LIM_REG (n = 0, 1) (0x0058, 0x005C)
Hn n
_C CH
EN T_
T_ SE
Hn
CN RE
_C
P_ T_
M
NU
O UN
Hn
P_
_L CO
_C
O
IM
TX _
O
T_ OP
_L
_L
d )
RM _LO
TX
TX
ve
T_
T_
er
T
s
RM
RM
RM
(re
31 21 20 19 18 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80 Reset
RMT_TX_LIM_CHn This field is used to configure the maximum entries that channel n can send out.
RY
(R/W)
RMT_TX_LOOP_NUM_CHn This field is used to configure the maximum loop count when continuous
TX mode is enabled. (R/W)
RMT_TX_LOOP_CNT_EN_CHn This bit is the enable bit for loop counting. (R/W)
A
RMT_LOOP_COUNT_RESET_CHn This bit is used to reset the loop count when continuous TX
mode is enabled. (WT) IN
Register 27.17. RMT_TX_SIM_REG (0x006C)
IM H1
H0
T_ _S _EN
_S _C
_C
IM
RM _TX SIM
TX IM
d)
T _
RM _TX
e
rv
se
T
RM
(re
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EL
RMT_TX_SIM_CH0 Set this bit to enable channel 0 to start sending data synchronously with other
enabled channels. (R/W)
RMT_TX_SIM_CH1 Set this bit to enable channel 1 to start sending data synchronously with other
enabled channels. (R/W)
PR
RMT_TX_SIM_EN This bit is used to enable multiple of channels to start sending data synchronously.
(R/W)
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Register 27.18. RMT_CHm_RX_LIM_REG (m = 2, 3) (0x0060, 0x0064)
EG
_R
M
LI
X_
_R
m
d)
CH
ve
T_
ser
RM
(re
31 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80 Reset
RMT_RX_LIM_CHm This field is used to configure the maximum entries that channel m can receive.
(R/W)
RY
Register 27.19. RMT_DATE_REG (0x00CC)
TE
DA
T_
)
RM
ed
A
rv
T_
se
RM
(re
31 28 27 0
0 0 0 0 0x2006231 Reset
RMT_DATE Version control register. (R/W)
IN
IM
EL
PR
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28 On-Chip Sensor and Analog Signal Processing
28 OnChip Sensor and Analog Signal Processing
28.1 Overview
ESP32-C3 provides the following on-chip sensor and analog signal processing peripherals:
• Two 12-bit Successive Approximation ADCs (SAR ADCs): SAR ADC1 and SAR ADC2, for measuring
analog signals from six channels.
• One temperature sensor for measuring the internal temperature of the ESP32-C3 chip.
28.2 SAR ADCs
RY
28.2.1 Overview
ESP32-C3 integrates two 12-bit SAR ADCs, which are able to measure analog signals from up to six pins. It is
also possible to measure internal signals, such as vdd33. The SAR ADCs are managed by two dedicated
controllers:
A
• DIG ADC controller: drives Digital_Reader0 and Digital_Reader1 to sample channel voltages of SAR ADC1
and SAR ADC2, respectively. This DIG ADC controller supports high-performance multi-channel scanning
and DMA continuous conversion.
IN
• PWDET controller: monitors RF power. Note this controller is only for RF internal use.
28.2.2 Features
IM
• Each SAR ADC has its own ADC Reader module (Digital_Reader0 or Digital_Reader1), which can be
configured and operated separately.
• Support 12-bit sampling resolution
• Support sampling the analog voltages from up to six pins
EL
• DIG ADC controller:
– Provides separate control modules for one-time sampling and multi-channel scanning.
– One-time sampling and multi-channel scanning can be run independently on each ADC.
– Channel scanning sequence in multi-channel scanning mode is user-defined.
PR
– Provides two filters with configurable filter coefficient.
– Supports threshold monitoring. An interrupt will be triggered when the sampled value is greater than
the pre-set high threshold or less than the pre-set low threshold.
– Supports DMA
• PWDET controller: monitors RF power (for internal use only)
28.2.3 Functional Description
The major components of SAR ADCs and their interconnections are shown in Figure 28-1.
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A RY
—: data flow; —: clock signal; —: ADC control signal
IN
Figure 281. SAR ADCs Function Overview
As shown in Figure 28-1, the SAR ADC module consists of the following components:
IM
• SAR ADC1: measures voltages from up to five channels.
• SAR ADC2: measures the voltage from one channel, or measures the internal signals such as vdd33.
• Clock management: selects clock sources and their dividers:
– Clock sources: can be APB_CLK or PLL_240.
EL
– Divided Clocks:
* SAR_CLK: operating clock for SAR ADC1, SAR ADC2, Digital_Reader0, and Digital_Reader1.
Note that the divider (sar_div) of SAR_ADC must be no less than 2.
* ADC_CTRL_CLK: operating clock for DIG ADC FSM.
PR
• Arbiter: this arbiter determines which controller is selected as the ADC2’s working controller, DIG ADC
controller or PWDET controller.
• Digital_Reader0 (driven by DIG ADC FSM): reads data from SAR ADC1.
• Digital_Reader1 (driven by DIG ADC FSM): reads data from SAR ADC2.
• DIG ADC FSM: generates the signals required throughout the ADC sampling process.
• Threshold monitorx: threshold monitor 1 and threshold monitor 2. The monitorx will trigger a interrupt when
the sampled value is greater than the pre-set high threshold or less than the pre-set low threshold.
The following sections describe the individual components in details.
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28.2.3.1 Input Signals
In order to sample an analog signal, an SAR ADC must first select the analog pin or internal signal to measure via
an internal multiplexer. A summary of all the analog signals that may be sent to the SAR ADC module for
processing by either ADC1 or ADC2 are presented in Table 28-1.
Table 281. SAR ADC Input Signals
Signal Channel ADC Selection
GPIO0 0
GPIO1 1
GPIO2 2 SAR ADC1
RY
GPIO3 3
GPIO4 4
GPIO5 0
SAR ADC2
Internal voltage n/a
A
28.2.3.2 ADC Conversion and Attenuation
When the SAR ADCs convert an analog voltage, the resolution (12-bit) of the conversion spans voltage range
IN
from 0 mV to Vref . Vref is the SAR ADC’s internal reference voltage. The output value of the conversion (data) is
mapped to analog voltage Vdata using the following formula:
Vref
Vdata = × data
4095
IM
In order to convert voltages larger than Vref , input signals can be attenuated before being input into the SAR
ADCs. The attenuation can be configured to 0 dB, 2.5 dB, 6 dB, and 12 dB.
28.2.3.3 DIG ADC Controller
EL
The clock of the DIG ADC controller is quite fast, thus the sample rate is high. For more information, see Section
ADC Characteristics in ESP32-C3 Series Datasheet.
This controller supports:
• up to 12-bit sampling resolution
PR
• software-triggered one-time sampling
• timer-triggered multi-channel scanning
The configuration of a one-time sampling triggered by the software is as follows:
• Select SAR ADC1 or SAR ADC2 to perform a one-time sampling:
– if APB_SARADC1_ONETIME_SAMPLE is set, SAR ADC1 is selected.
– if APB_SARADC2_ONETIME_SAMPLE is set, SAR ADC2 is selected.
• Configure APB_SARADC_ONETIME_CHANNEL to select one channel to sample.
• Configure APB_SARADC_ONETIME_ATTEN to set attenuation.
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• Configure APB_SARADC_ONETIME_START to start this one-time sampling.
• On completion of sampling, APB_SARADC_ADCx_DONE_INT_RAW interrupt is generated. Software can
use this interrupt to initiate reading of the sample values from APB_SARADC_ADCx_DATA. x can be 1 or 2.
1: SAR ADC1; 2: SAR ADC2.
If the timer-triggered multi-channel scanning is selected, follow the configuration below. Note that in this mode,
the scan sequence is performed according to the configuration entered into pattern table.
• Configure APB_SARADC_TIMER_TARGET to set the trigger target for DIG ADC timer. When the timer
counting reaches two times of the pre-configured cycle number, a sampling operation is triggered. For the
working clock of the timer, see Section 28.2.3.4.
• Configure APB_SARADC_TIMER_EN to enable the timer.
RY
• When the timer times out, it drives DIG ADC FSM to start sampling according to the pattern table;
• Sampled data is automatically stored in memory via DMA. An interrupt is triggered once the scan is
completed.
Note:
A
Any SAR ADC can not be configured to perform both one-time sampling and multi-channel scanning at the same time.
Therefore, if a pattern table is configured to use any SAR ADC for multi-channel scanning, then this SAR ADC can not be
configured to perform one-time sampling.
IN
28.2.3.4 DIG ADC Clock
IM
Two clocks can be used as the working clock of DIG ADC controller, depending on the configuration of
APB_SARADC_CLK_SEL:
• 1: Select the clock (ADC_CTRL_CLK) divided from PLL_240.
• 2: Select APB_CLK.
EL
If ADC_CTRL_CLK is selected, users can configure the divider by APB_SARADC_CLKM_DIV_NUM. Note that
due to speed limits of SAR ADCs, the operating clock of Digital_Reader0, SAR ADC1, Digital_Reader1, and SAR
ADC2 is SAR_CLK, the frequency of which affects the sampling precision. The lower the frequency, the higher
the precision. SAR_CLK is divided from ADC_CTRL_CLK. The divider coefficient is configured by
APB_SARADC_SAR_CLK_DIV.
PR
The ADC needs 25 SAR_CLK clock cycles per sample, so the maximum sampling rate is limited by the
SAR_CLK frequency.
28.2.3.5 DMA Support
DIG ADC controller supports direct memory access via peripheral DMA, which is triggered by DIG ADC timer.
Users can switch the DMA data path to DIG ADC by configuring APB_SARADC_APB_ADC_TRANS via software.
For specific DMA configuration, please refer to Chapter 2 GDMA Controller (GDMA).
28.2.3.6 DIG ADC FSM
Overview
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Figure 28-2 shows the diagram of DIG ADC FSM.
A RY
Figure 282. Diagram of DIG ADC FSM
Wherein:
IN
• Timer: a dedicated timer for DIG ADC controller, to generate a sample_start signal.
• pr: the pointer to pattern table entries. FSM sends out corresponding signals based on the configuration of
IM
the pattern table entry that the pointer points to.
The execution process is as follows:
• Configure APB_SARADC_TIMER_EN to enable the DIG ADC timer. The timeout event of this timer triggers
an sample_start signal. This signal drives the FSM module to start sampling.
EL
• When the FSM module receives the sample_start signal, it starts the following operations:
– Power up SAR ADC.
– Select SAR ADC1 or SAR ADC2 as the working ADC, configure the ADC channel and attenuation,
based on the pattern table entry that the current pr points to.
PR
– According to the configuration information, output the corresponding en_pad and atten signals to the
analog side.
– Initiate the sar_start signal and start sampling.
• When the FSM receives the reader_done signal from ADC Reader (Digital_Reader0 or Digital_Reader1), it
will
– stop sampling,
– transfer the data to the filter, and then threshold monitor transfers the data to memory via DMA,
– update the pattern table pointer pr and wait for the next sampling. Note that if the pointer pr is smaller
than APB_SARADC_SAR_PATT_LEN (table_length), then pr = pr + 1, otherwise, pr is cleared.
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Pattern Table
There is one pattern table in the controller, consisting of the APB_SARADC_SAR_PATT_TAB1_REG and
APB_SARADC_SAR_PATT_TAB2_REG registers, see Figure 28-3 and Figure 28-4:
)
ed
rv
d3
d2
d1
d0
se
cm
cm
cm
cm
(re
31 24 23 18 17 12 11 6 5 0
0 0 0 0 0 0 0 0 0x0000 0x0000 0x0000 0x0000
cmd x represents pattern table entries. x here is the index, 0 ~ 3.
Figure 283. APB_SARADC_SAR_PATT_TAB1_REG and Pattern Table Entry 0 Entry 3
RY
d)
ve
r
d7
d6
d5
d4
se
cm
cm
cm
cm
(re
31 24 23 18 17 12 11 6 5 0
0 0 0 0 0 0 0 0 0x0000 0x0000 0x0000 0x0000
A
cmd x represents pattern table entries. x here is the index, 4 ~ 7.
Figure 284. APB_SARADC_SAR_PATT_TAB2_REG and Pattern Table Entry 4 Entry 7
IN
Each register consists of four 6-bit pattern table entries. Each entry is composed of three fields that contain
working ADC, ADC channel and attenuation information, as shown in Table 28-5.
IM el
el
_s
n
_s
te
r
ch
sa
at
5 4 3 1 0
x xx x x
Figure 285. Pattern Table Entry
EL
atten Attenuation. 0: 0 dB; 1: 2.5 dB; 2: 6 dB; 3: 12 dB.
ch_sel ADC channel, see Table 28-1.
sar_sel Working ADC. 0: SAR ARC1; 1: SAR ADC2.
PR
Configuration of multichannel scanning
In this example, two channels are selected for multi-channel scanning:
• Channel 2 of SAR ADC1, with the attenuation of 12 dB
• Channel 0 of SAR ADC2, with the attenuation of 2.5 dB
The detailed configuration is as follows:
• Configure the first pattern table entry (cmd0):
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l
se
el
n
_s
r_
te
ch
sa
at
5 4 3 1 0
0 2 3
Figure 286. cmd0 Configuration
atten write the value of 3 to this field, to set the attenuation to 12 dB.
ch_sel write the value of 2 to this field, to select channel 2 (see Table 28-1).
sar_sel write the value of 0 to this bit, to select SAR ADC1 as the working ADC.
• Configure the second pattern table entry (cmd1):
RY
l
se
el
n
_s
r_
te
ch
sa
at
5 4 3 1 0
1 0 1
Figure 287. cmd1 configuration
A
atten write the value of 1 to this field, to set the attenuation to 2.5 dB.
ch_sel write the value of 0 to this field, to select channel 0 (see Table 28-1).
IN
sar_sel write the value of 1 to this bit, to select SAR ADC2 as the working ADC.
• Configure APB_SARADC_SAR_PATT_LEN to 1, i.e., set pattern table length to (this value + 1 = 2). Then
pattern table entries cmd0 and cmd1 will be used.
IM
• Enable the timer, then DIG ADC controller starts scanning the two channels in cycles, as configured in the
pattern table entries.
DMA Data Format
The ADC eventually passes 32-bit data to the DMA, see the figure below.
EL d
ed
ve
l
se
l
se
v
er
er
r_
ta
_
s
s
ch
sa
da
re
re
31 17 16 15 13 12 11 0
xx x xxx x x x
PR
Figure 288. DMA Data Format
data SAR ADC read value, 12-bit
ch_sel Channel, 3-bit
sar_sel SAR ADC selection, 1-bit
28.2.3.7 ADC Filters
The DIG ADC controller provides two filters for automatic filtering of sampled ADC data. Both filters can be
configured to any channel of either SAR ADC and then filter the sampled data for the target channel. The filter’s
formula is shown below:
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(k − 1)dataprev datain
datacur = + − 0.5
k k
• datacur : the filtered data value.
• datain : the sampled data value from the ADC.
• dataprev : the last filtered data value.
• k: the filter coefficient.
The filters are configured as follows:
• Configure APB_SARADC_FILTER_CHANNELx to select the ADC channel for filter x;
RY
• Configure APB_SARADC_FILTER_FACTORx to set the coefficient for filter x;
Note that x is used here as the placeholder of filter index. 0: filter 0; 1: filter 1.
28.2.3.8 Threshold Monitoring
DIG ADC controller contains two threshold monitors that can be configured to monitor on any channel of SAR
A
ADC1 and SAR ADC2. A high threshold interrupt is triggered when the ADC sample value is larger than the
pre-configured high threshold, and a low threshold interrupt is triggered if the sample value is lower than the
pre-configured low threshold.
The configuration of threshold monitoring is as follows:
IN
• Set APB_SARADC_THRESx_EN to enable threshold monitor x.
• Configure APB_SARADC_THRESx_LOW to set a low threshold;
IM
• Configure APB_SARADC_THRESx_HIGH to set a high threshold;
• Configure APB_SARADC_THRESx_CHANNEL to select the SAR ADC and the channel to monitor.
Note that x is used here as the placeholder of monitor index. 0: monitor 0; 1: monitor 1.
EL
28.2.3.9 SAR ADC2 Arbiter
SAR ADC2 can be controlled by two controllers, namely, DIG ADC controller and PWDET controller. To avoid any
possible conflicts and to improve the efficiency of SAR ADC2, ESP32-C3 provides an arbiter for SAR ADC2. The
arbiter supports fair arbitration and fixed priority arbitration.
PR
• Fair arbitration mode (cyclic priority arbitration) can be enabled by clearing APB_SARADC_ADC_ARB_FIX_
PRIORITY.
• In fixed priority arbitration, users can set APB_SARADC_ADC_ARB_APB_PRIORITY (for DIG ADC
controller) and APB_SARADC_ADC_ARB_WIFI_PRIORITY (for PWDET controller), to configure the priorities
for these controllers. A larger value indicates a higher priority.
The arbiter ensures that a higher priority controller can always start a conversion (sample) when required,
regardless of whether a lower priority controller already has a conversion in progress. If a higher priority controller
starts a conversion whilst the ADC already has a conversion in progress from a lower priority controller, the
conversion in progress will be interrupted (stopped). The higher priority controller will then start its conversion. A
lower priority controller will not be able to start a conversion whilst the ADC has a conversion in progress from a
higher priority controller.
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Therefore, certain data flags are embedded into the output data value to indicate whether the conversion is valid
or not.
• The data flag for DIG ADC controller is the {sar_sel, ch_sel} bits in DMA data, see Figure 28-8.
– 4’b1111: Conversion is interrupted.
– 4’b1110: Conversion is not started.
– Corresponding channel No.: The data is valid.
• The data flag for PWDET controller is the two higher bits of the sampling result.
– 2’b10: Conversion is interrupted.
RY
– 2’b01: Conversion is not started.
– 2’b00: The data is valid.
Users can configure APB_SARADC_ADC_ARB_GRANT_FORCE to mask the arbiter, and set
APB_SARADC_ADC_ARB_WIFI_FORCE or APB_SARADC_ADC_ARB_APB_FORCE to authorize corresponding
controllers.
A
28.3 Temperature Sensor IN
28.3.1 Overview
ESP32-C3 provides a temperature sensor to monitor temperature changes inside the chip in real time.
28.3.2 Features
IM
The temperature sensor has the following features:
• Supports software triggering and, once triggered, the data can be read continuously
• Configurable temperature offset based on the environment, to improve the accuracy
EL
• Adjustable measurement range
28.3.3 Functional Description
The temperature sensor can be started by software as follows:
PR
• Set APB_SARADC_TSENS_PU to start XPD_SAR, and then to enable temperature sensor;
• Wait for APB_SARADC_TSENS_XPD_WAIT clock cycles till the reset of temperature sensor is released, the
sensor starts measuring the temperature;
• Wait for a while and then read the data from APB_SARADC_TSENS_OUT. The output value gradually
approaches the actual temperature linearly as the measurement time increases.
The actual temperature (°C) can be obtained by converting the output of temperature sensor via the following
formula:
T (°C) = 0.4386 ∗ V ALU E–27.88 ∗ of f set–20.52
VALUE in the formula is the output of the temperature sensor, and the offset is determined by the temperature
offset TSENS_DAC. Users can set I2C register I2C_SARADC_TSENS_ADC to configure TSENS_DAC according
to the actual environment (the temperature range) and Table 28-2.
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Table 282. Temperature Offset
TSENS_DAC Temperature Offset (°C) Measurement Range (°C)
5 -2 50 ~ 125
13 or 7 -1 20 ~ 100
15 0 -10 ~ 80
11 or 14 1 -30 ~ 50
10 2 -40 ~ 20
28.4 Interrupts
RY
• APB_SARADC_ADC1_DONE_INT: Triggered when SAR ADC1 completes one data conversion.
• APB_SARADC_ADC2_DONE_INT: Triggered when SAR ADC2 completes one data conversion.
• APB_SARADC_THRESx_HIGH_INT: Triggered when the sampling value is higher than the high threshold of
monitor x.
• APB_SARADC_THRESx_LOW_INT: Triggered when the sampling value is lower than the low threshold of
A
monitor x.
28.5 Register Summary
IN
The addresses in this section are relative to the ADC controller base address provided in Table 3-4 in Chapter 3
System and Memory.
IM
Name Description Address Access
Configuration Registers
APB_SARADC_CTRL_REG SAR ADC control register 1 0x0000 R/W
APB_SARADC_CTRL2_REG SAR ADC control register 2 0x0004 R/W
APB_SARADC_FILTER_CTRL1_REG Filtering control register 1 0x0008 R/W
EL
APB_SARADC_SAR_PATT_TAB1_REG Pattern table register 1 0x0018 R/W
APB_SARADC_SAR_PATT_TAB2_REG Pattern table register 2 0x001C R/W
APB_SARADC_ONETIME_SAMPLE_REG Configuration register for one-time 0x0020 R/W
sampling
APB_SARADC_APB_ADC_ARB_CTRL_REG SAR ADC2 arbiter configuration 0x0024 R/W
PR
register
APB_SARADC_FILTER_CTRL0_REG Filtering control register 0 0x0028 R/W
APB_SARADC_1_DATA_STATUS_REG SAR ADC1 sampling data register 0x002C RO
APB_SARADC_2_DATA_STATUS_REG SAR ADC2 sampling data register 0x0030 RO
APB_SARADC_THRES0_CTRL_REG Sampling threshold control register 0x0034 R/W
0
APB_SARADC_THRES1_CTRL_REG Sampling threshold control register 0x0038 R/W
1
APB_SARADC_THRES_CTRL_REG Sampling threshold control register 0x003C R/W
APB_SARADC_INT_ENA_REG Enable register of SAR ADC inter- 0x0040 R/W
rupts
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Name Description Address Access
APB_SARADC_INT_RAW_REG Raw register of SAR ADC inter- 0x0044 RO
rupts
APB_SARADC_INT_ST_REG State register of SAR ADC inter- 0x0048 RO
rupts
APB_SARADC_INT_CLR_REG Clear register of SAR ADC inter- 0x004C WO
rupts
APB_SARADC_DMA_CONF_REG DMA configuration register for SAR 0x0050 R/W
ADC
APB_SARADC_APB_ADC_CLKM_CONF_REG SAR ADC clock control register 0x0054 R/W
APB_SARADC_APB_TSENS_CTRL_REG Temperature sensor control regis- 0x0058 varies
RY
ter 1
APB_SARADC_APB_TSENS_CTRL2_REG Temperature sensor control regis- 0x005C R/W
ter 2
APB_SARADC_CALI_REG SAR ADC calibration register 0x0060 R/W
APB_SARADC_APB_CTRL_DATE_REG Version control register 0x03FC R/W
A
28.6 Register IN
The addresses in this section are relative to the ADC controller base address provided in Table 3-4 in Chapter 3
System and Memory.
IM
EL
PR
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Register 28.1. APB_SARADC_CTRL_REG (0x0000)
R
EA
E
D
CL
CL
RC
E
EN
E
AT
CY
V
P_
RC
O
DI
_L
_G
_F
B_
T_
O
TT
AR
LK
LK
AT
AR
_F
PA
_C
_C
_P
_S
_S R T
RT
T_
R_
AR
AR
AR
PD
DC STA
TA
AI
SA
W
_S
_S
_S
_X
C_
RA C_
DC
DC
DC
DC
DC
AD
SA D
RA
RA
RA
RA
RA
B_ RA
(re AR
)
ed
ed
ed
ed
SA
SA
SA
SA
SA
AP _SA
S
rv
rv
rv
rv
B_
B_
B_
B_
B_
B_
se
se
se
se
B
AP
AP
AP
AP
AP
AP
AP
(re
(re
(re
31 30 29 28 27 26 24 23 22 18 17 15 14 7 6 5 2 1 0
1 0 0 0 0 0 0 0 0 0 0 0 7 4 1 0 0 0 0 0 0 Reset
APB_SARADC_START_FORCE 0: select FSM to start SAR ADC. 1: select software to start SAR
RY
ADC. (R/W)
APB_SARADC_START Write 1 here to start the SAR ADC by software. Valid only when
APB_SARADC_START_FORCE = 1. (R/W)
APB_SARADC_SAR_CLK_GATED SAR ADC clock gate enable bit. (R/W)
A
APB_SARADC_SAR_CLK_DIV SAR ADC clock divider. This value should be no less than 2. (R/W)
APB_SARADC_SAR_PATT_LEN Configure how many pattern table entries will be used. If this field
IN
is set to 1, then pattern table entries (cmd0) and (cmd1) will be used. (R/W)
APB_SARADC_SAR_PATT_P_CLEAR Clear the pointer of pattern table entry for DIG ADC controller.
(R/W)
IM
APB_SARADC_XPD_SAR_FORCE Force select XPD SAR. (R/W)
APB_SARADC_WAIT_ARB_CYCLE The clock cycles of waiting arbitration signal stable after
SAR_DONE. (R/W)
EL
PR
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Register 28.2. APB_SARADC_CTRL2_REG (0x0004)
IT
M
IM
NU
ET
_L
G
S_
M
AR
N
EA
NU
1_ V
V
_E
_T
AR IN
IN
_M
S_
_S R2_
ER
ER
EA
AX
M
IM
DC SA
_M
_M
TI
_T
_
RA C_
DC
DC
DC
DC
SA D
RA
RA
B_ RA
RA
RA
d)
B d)
SA
SA
AP _SA
SA
SA
ve
AP rve
er
B_
B_
B_
B_
se
s
AP
AP
AP
AP
(re
(re
31 25 24 23 12 11 10 9 8 1 0
0 0 0 0 0 0 0 0 10 0 0 0 255 0 Reset
APB_SARADC_MEAS_NUM_LIMIT Enable the limitation of SAR ADCs maximum conversion times.
RY
(R/W)
APB_SARADC_MAX_MEAS_NUM The SAR ADCs maximum conversion times. (R/W)
APB_SARADC_SAR1_INV Write 1 here to invert the data of SAR ADC1. (R/W)
APB_SARADC_SAR2_INV Write 1 here to invert the data of SAR ADC2. (R/W)
A
APB_SARADC_TIMER_TARGET Set SAR ADC timer target. (R/W)
APB_SARADC_TIMER_EN Enable SAR ADC timer trigger. (R/W)
IN
Register 28.3. APB_SARADC_FILTER_CTRL1_REG (0x0008)
IM
R0
R1
TO
TO
C
AC
FA
_F
R_
ER
E
ILT
ILT
_F
_F
DC
DC
RA
RA
)
ed
SA
SA
EL
rv
B_
B_
se
AP
AP
(re
31 29 28 26 25 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_SARADC_FILTER_FACTOR1 The filter coefficient for SAR ADC filter 1. (R/W)
PR
APB_SARADC_FILTER_FACTOR0 The filter coefficient for SAR ADC filter 0. (R/W)
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Register 28.4. APB_SARADC_SAR_PATT_TAB1_REG (0x0018)
1
AB
_T
T
AT
_P
AR
_S
DC
RA
d)
SA
ve
er
B_
s
AP
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000 Reset
APB_SARADC_SAR_PATT_TAB1 Pattern table entries 0 ~ 3 (each entry is six bits). (R/W)
RY
Register 28.5. APB_SARADC_SAR_PATT_TAB2_REG (0x001C)
2
AB
_T
T
AT
A RA
DC
_S
AR
_P
d)
SA
ve
IN
r
B_
se
AP
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000 Reset
APB_SARADC_SAR_PATT_TAB2 Pattern table entries 4 ~ 7 (each entry is six bits). (R/W)
IM
Register 28.6. APB_SARADC_ONETIME_SAMPLE_REG (0x0020)
EL E_ M E
M SA L
TI E_ MP
AR LE
ST P
NN
T
EL
N
TE
HA
NE IM SA
AT
_C
_O NET E_
E_
E
DC _O TIM
M
TI
TI
RA C2 NE
NE
NE
SA D _O
_O
_O
B_ RA C1
DC
DC
AP SA D
B_ RA
RA
RA
)
ed
AP _SA
SA
SA
PR
rv
B_
B_
se
B
AP
AP
AP
(re
31 30 29 28 25 24 23 22 0
0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_SARADC_ONETIME_ATTEN Configure the attenuation for a one-time sampling. (R/W)
APB_SARADC_ONETIME_CHANNEL Configure the channel for a one-time sampling. (R/W)
APB_SARADC_ONETIME_START Start SAR ADC one-time sampling. (R/W)
APB_SARADC2_ONETIME_SAMPLE Enable SAR ADC2 one-time sampling. (R/W)
APB_SARADC1_ONETIME_SAMPLE Enable SAR ADC1 one-time sampling. (R/W)
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Register 28.7. APB_SARADC_APB_ADC_ARB_CTRL_REG (0x0024)
RC CE
TY
TY
_P TY
FO R
E
E
RI
RI
I_ O
RC
RI
O
IO
IF _F
_W RIO
_A _G PRI
O
R
_F
_W AN
P
B_
PB
FI
_A FIX_
RB R
AP
I
_A
_
B_
_A ARB
RB
RB
R
DC R
A
_A
DC C_
C_
B_ d) C_ C_
DC
DC
RA AD
B_ RA AD
AP rve AD AD
A
_A
_
AP SA C_
se R _
DC
DC
B_ AD
(re SA D
RA
RA
R
)
)
ed
ed
ed
SA
SA
SA
SA
rv
rv
rv
B_
B_
B_
se
se
se
AP
AP
AP
AP
(re
(re
(re
31 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 Reset
RY
APB_SARADC_ADC_ARB_APB_FORCE SAR ADC2 arbiter forces to enable DIG ADC controller.
(R/W)
APB_SARADC_ADC_ARB_WIFI_FORCE SAR ADC2 arbiter forces to enable PWDET controller.
(R/W)
A
APB_SARADC_ADC_ARB_GRANT_FORCE ADC2 arbiter force grant. (R/W)
APB_SARADC_ADC_ARB_APB_PRIORITY Set DIG ADC controller priority. (R/W) IN
APB_SARADC_ADC_ARB_WIFI_PRIORITY Set PWDET controller priority. (R/W)
APB_SARADC_ADC_ARB_FIX_PRIORITY ADC2 arbiter uses fixed priority. (R/W)
IM
Register 28.8. APB_SARADC_FILTER_CTRL0_REG (0x0028)
L0
1
EL
NE
NN
T
AN
SE
HA
CH
RE
_C
R_
R_
EL
ER
E
E
ILT
LT
LT
FI
FI
_F
C_
C_
DC
AD
AD
RA
AR
R
)
)
d
ed
SA
SA
ve
_S
rv
r
B_
B_
se
se
B
AP
AP
AP
(re
(re
31 30 26 25 22 21 18 17 0
0 0 0 0 0 0 13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PR
APB_SARADC_FILTER_CHANNEL1 The filter channel for SAR ADC filter 1. (R/W)
APB_SARADC_FILTER_CHANNEL0 The filter channel for SAR ADC filter 0. (R/W)
APB_SARADC_FILTER_RESET Reset SAR ADC1 filter. (R/W)
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Register 28.9. APB_SARADC_1_DATA_STATUS_REG (0x002C)
A
AT
_D
C1
AD
AR
_S
PB
_A
DC
RA
)
ed
SA
rv
B_
se
AP
(re
31 17 16 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
APB_SARADC_ADC1_DATA SAR ADC1 conversion data. (RO)
Register 28.10. APB_SARADC_2_DATA_STATUS_REG (0x0030)
TA
DA
A DC
RA
DC
_A
2_
d)
SA
ve
IN
r
B_
se
AP
(re
31 17 16 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IM
APB_SARADC_ADC2_DATA SAR ADC2 conversion data. (RO)
Register 28.11. APB_SARADC_THRES0_CTRL_REG (0x0034)
EL
L
NE
AN
H
W
CH
O
HI
_L
0_
0_
S0
ES
ES
RE
HR
HR
TH
_T
_T
C_
DC
DC
AD
RA
RA
AR
)
)
ed
ed
SA
SA
S
rv
rv
PR
B_
B_
B_
se
se
AP
AP
AP
(re
(re
31 30 18 17 5 4 3 0
0 0 0x1fff 0 13 Reset
APB_SARADC_THRES0_CHANNEL The channel for SAR ADC monitor 0. (R/W)
APB_SARADC_THRES0_HIGH The high threshold for SAR ADC monitor 0. (R/W)
APB_SARADC_THRES0_LOW The low threshold for SAR ADC monitor 0. (R/W)
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Register 28.12. APB_SARADC_THRES1_CTRL_REG (0x0038)
L
NE
AN
H
W
CH
LO
HI
1_
1_
1_
ES
ES
ES
HR
HR
HR
_T
_T
_T
DC
DC
DC
RA
RA
RA
d)
)
ed
SA
SA
SA
ve
rv
er
B_
B_
B_
se
s
AP
AP
AP
(re
(re
31 30 18 17 5 4 3 0
0 0 0x1fff 0 13 Reset
APB_SARADC_THRES1_CHANNEL The channel for SAR ADC monitor 1. (R/W)
RY
APB_SARADC_THRES1_HIGH The high threshold for SAR ADC monitor 1. (R/W)
APB_SARADC_THRES1_LOW The low threshold for SAR ADC monitor 1. (R/W)
A
Register 28.13. APB_SARADC_THRES_CTRL_REG (0x003C)
_ EN
S1 N
N
LL
IN
RE 0_E
_E
_A
TH S
ES
C_ RE
HR
AD TH
_T
(re AR C_
DC
S D
B_ RA
RA
)
)
ed
ed
AP _SA
SA
rv
rv
B_
se
se
B
AP
AP
(re
IM
31 30 29 28 27 26 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_SARADC_THRES_ALL_EN Enable the threshold monitoring for all configured channels. (R/W)
EL
APB_SARADC_THRES1_EN Enable threshold monitor 1. (R/W)
APB_SARADC_THRES0_EN Enable threshold monitor 0. (R/W)
PR
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Register 28.14. APB_SARADC_INT_ENA_REG (0x0040)
1_ W T_ A
W T_ A
NT A
NA
ES _LO _IN _EN
LO _IN EN
RA C_ RE _H INT NA
_T RES _HI _IN NA
_I EN
_E
SA D TH S0 E_ _E
DC TH S1 IGH _E
HR 0 GH T
B_ RA C_ RE ON INT
AP _SA AD TH _D E_
B R C_ C2 ON
AP _SA AD AD _D
B R C_ C1
AP _SA AD AD
B R C_
AP SA D
B_ RA
)
ed
AP _SA
rv
se
B
AP
(re
31 30 29 28 27 26 25 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
APB_SARADC_THRES1_LOW_INT_ENA Enable bit of APB_SARADC_THRES1_LOW_INT inter-
rupt. (R/W)
APB_SARADC_THRES0_LOW_INT_ENA Enable bit of APB_SARADC_THRES0_LOW_INT inter-
rupt. (R/W)
APB_SARADC_THRES1_HIGH_INT_ENA Enable bit of APB_SARADC_THRES1_HIGH_INT inter-
A
rupt. (R/W)
APB_SARADC_THRES0_HIGH_INT_ENA Enable bit of APB_SARADC_THRES0_HIGH_INT inter-
rupt. (R/W)
IN
APB_SARADC_ADC2_DONE_INT_ENA Enable bit of APB_SARADC_ADC2_DONE_INT interrupt.
(R/W)
IM
APB_SARADC_ADC1_DONE_INT_ENA Enable bit of APB_SARADC_ADC1_DONE_INT interrupt.
(R/W)
EL
PR
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Register 28.15. APB_SARADC_INT_RAW_REG (0x0044)
1_ W T_ W
W T_ W
NT AW
AW
RA C_ RE _H INT AW
_T RES _HI _IN AW
ES _LO _IN _RA
LO _IN RA
_I R
_R
SA D TH S0 E_ _R
DC TH S1 IGH _R
HR 0 GH T
B_ RA C_ RE ON INT
AP _SA AD TH _D E_
B R C_ C2 ON
AP _SA AD AD _D
B R C_ C1
AP _SA AD AD
B R C_
AP SA D
B_ RA
)
ed
AP _SA
rv
se
B
AP
(re
31 30 29 28 27 26 25 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
APB_SARADC_THRES1_LOW_INT_RAW Raw bit of APB_SARADC_THRES1_LOW_INT interrupt.
(RO)
APB_SARADC_THRES0_LOW_INT_RAW Raw bit of APB_SARADC_THRES0_LOW_INT interrupt.
(RO)
APB_SARADC_THRES1_HIGH_INT_RAW Raw bit of APB_SARADC_THRES1_HIGH_INT interrupt.
A
(RO)
APB_SARADC_THRES0_HIGH_INT_RAW Raw bit of APB_SARADC_THRES0_HIGH_INT interrupt.
(RO)
IN
APB_SARADC_ADC2_DONE_INT_RAW Raw bit of APB_SARADC_ADC2_DONE_INT interrupt.
(RO)
IM
APB_SARADC_ADC1_DONE_INT_RAW Raw bit of APB_SARADC_ADC1_DONE_INT interrupt.
(RO)
EL
PR
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Register 28.16. APB_SARADC_INT_ST_REG (0x0048)
ES _LO _IN _ST
LO _IN ST
_I ST
T
_S
RA C_ RE _H INT T
_T RES _HI _IN T
1_ W T_
SA D TH S0 E_ _S
DC TH S1 IGH _S
W T_
HR 0 GH T
NT
B_ RA C_ RE ON INT
AP _SA AD TH _D E_
B R C_ C2 ON
AP _SA AD AD _D
B R C_ C1
AP _SA AD AD
B R C_
AP SA D
B_ RA
)
ed
AP _SA
rv
se
B
AP
(re
31 30 29 28 27 26 25 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
APB_SARADC_THRES1_LOW_INT_ST Status of APB_SARADC_THRES1_LOW_INT interrupt.
(RO)
APB_SARADC_THRES0_LOW_INT_ST Status of APB_SARADC_THRES0_LOW_INT interrupt.
(RO)
APB_SARADC_THRES1_HIGH_INT_ST Status of APB_SARADC_THRES1_HIGH_INT interrupt.
A
(RO)
APB_SARADC_THRES0_HIGH_INT_ST Status of APB_SARADC_THRES0_HIGH_INT interrupt.
(RO)
IN
APB_SARADC_ADC2_DONE_INT_ST Status of APB_SARADC_ADC2_DONE_INT interrupt. (RO)
APB_SARADC_ADC1_DONE_INT_ST Status of APB_SARADC_ADC1_DONE_INT interrupt. (RO)
IM
EL
PR
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Register 28.17. APB_SARADC_INT_CLR_REG (0x004C)
1_ W T_ R
W T_ R
NT LR
LR
ES _LO _IN _CL
LO _IN CL
RA C_ RE _H INT LR
_T RES _HI _IN LR
_I C
_C
SA D TH S0 E_ _C
DC TH S1 IGH _C
HR 0 GH T
B_ RA C_ RE ON INT
AP _SA AD TH _D E_
B R C_ C2 ON
AP _SA AD AD _D
B R C_ C1
AP _SA AD AD
B R C_
AP SA D
B_ RA
)
ed
AP _SA
rv
se
B
AP
(re
31 30 29 28 27 26 25 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RY
APB_SARADC_THRES1_LOW_INT_CLR Clear bit of APB_SARADC_THRES1_LOW_INT interrupt.
(WO)
APB_SARADC_THRES0_LOW_INT_CLR Clear bit of APB_SARADC_THRES0_LOW_INT interrupt.
(WO)
APB_SARADC_THRES1_HIGH_INT_CLR Clear bit of APB_SARADC_THRES1_HIGH_INT interrupt.
A
(WO)
APB_SARADC_THRES0_HIGH_INT_CLR Clear bit of APB_SARADC_THRES0_HIGH_INT interrupt.
(WO)
IN
APB_SARADC_ADC2_DONE_INT_CLR Clear bit of APB_SARADC_ADC2_DONE_INT interrupt.
(WO)
IM
APB_SARADC_ADC1_DONE_INT_CLR Clear bit of APB_SARADC_ADC1_DONE_INT interrupt.
(WO)
Register 28.18. APB_SARADC_DMA_CONF_REG (0x0050)
EL SM
M
_F
NU
_R NS
ET
F_
ES
DC RA
O
_E
_A _T
PB DC
DC
_A B_A
_A
PB
DC AP
PR
_A
RA C_
DC
SA D
B_ RA
RA
d)
AP SA
SA
r ve
B_
B_
se
AP
AP
(re
31 30 29 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255 Reset
APB_SARADC_APB_ADC_EOF_NUM Generate dma_in_suc_eof when sample cnt = eof_num.
(R/W)
APB_SARADC_APB_ADC_RESET_FSM Reset DIG ADC controller status. (R/W)
APB_SARADC_APB_ADC_TRANS When this bit is set, DIG ADC controller uses DMA. (R/W)
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28 On-Chip Sensor and Analog Signal Processing
Register 28.19. APB_SARADC_APB_ADC_CLKM_CONF_REG (0x0054)
UM
_N
_B
_A
IV
IV
IV
EL
_D
_D
_D
N
DC K_S
_E
KM
LK
LK
LK
L
L
_C
_C
_C
_C
_C
DC
DC
DC
DC
RA
RA
RA
RA
RA
d)
SA
SA
SA
SA
SA
ve
er
B_
B_
B_
B_
B_
s
AP
AP
AP
AP
AP
(re
31 23 22 21 20 19 14 13 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 4 Reset
APB_SARADC_CLKM_DIV_NUM The integer part of ADC clock divider. Divider value =
RY
APB_SARADC_CLKM_DIV_NUM + APB_SARADC_CLKM_DIV_B/APB_SARADC_CLKM_DIV_A.
(R/W)
APB_SARADC_CLKM_DIV_B The numerator value of fractional clock divider. (R/W)
APB_SARADC_CLKM_DIV_A The denominator value of fractional clock divider. (R/W)
A
APB_SARADC_CLK_EN Enable the SAR ADC register clock. (R/W)
APB_SARADC_CLK_SEL 0: Use APB_CLK as clock source, 1: use divided-down PLL_240 as clock
source. (R/W)
IN
Register 28.20. APB_SARADC_APB_TSENS_CTRL_REG (0x0058)
IM
IV
_D
V
IN
UT
LK
N_
U
O
_C
_P
_I
S_
NS
NS
EN
EN
SE
SE
TS
TS
_T
_T
C_
C_
DC
DC
AD
AD
RA
RA
AR
AR
)
)
ed
ed
SA
SA
EL
_S
_S
rv
rv
B_
B_
se
se
B
B
AP
AP
AP
AP
(re
(re
31 23 22 21 14 13 12 8 7 0
0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0x0 Reset
APB_SARADC_TSENS_OUT Temperature sensor data out. (RO)
PR
APB_SARADC_TSENS_IN_INV Invert temperature sensor input value. (R/W)
APB_SARADC_TSENS_CLK_DIV Temperature sensor clock divider. (R/W)
APB_SARADC_TSENS_PU Temperature sensor power up. (R/W)
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28 On-Chip Sensor and Analog Signal Processing
Register 28.21. APB_SARADC_APB_TSENS_CTRL2_REG (0x005C)
T
EL
AI
_W
S
K_
D
CL
XP
_
_
NS
NS
SE
SE
_T
_T
DC
DC
RA
RA
)
)
ed
ed
SA
SA
rv
rv
B_
B_
se
se
AP
AP
(re
(re
31 16 15 13 12 10 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 Reset
APB_SARADC_TSENS_XPD_WAIT The wait time before temperature sensor is powered up. (R/W)
RY
APB_SARADC_TSENS_CLK_SEL Choose working clock for temperature sensor. 0: FOSC_CLK. 1:
XTAL_CLK. (R/W)
Register 28.22. APB_SARADC_CALI_REG (0x0060)
A AL
I_
CF
G
IN
_C
DC
RA
d)
SA
e
rv
B_
se
AP
(re
31 17 16 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x8000 Reset
IM
APB_SARADC_CALI_CFG Configure the SAR ADC calibration factor. (R/W)
EL
Register 28.23. APB_SARADC_APB_CTRL_DATE_REG (0x03FC)
E
AT
_D
DC
RA
SA
B_
AP
PR
31 0
0x2007171 Reset
APB_SARADC_DATE Version register. (R/W)
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29 Related Documentation and Resources
29 Related Documentation and Resources
Related Documentation
• ESP32-C3 Series Datasheet – Specifications of the ESP32-C3 hardware.
• Certificates
http://espressif.com/en/support/documents/certificates
• Documentation Updates and Update Notification Subscription
http://espressif.com/en/support/download/documents
Developer Zone
RY
• ESP-IDF Programming Guide for ESP32-C3 – Extensive documentation for the ESP-IDF development framework.
• ESP-IDF and other development frameworks on GitHub.
http://github.com/espressif
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.
http://esp32.com/
A
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
http://blog.espressif.com/
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
IN
http://espressif.com/en/support/download/sdks-demos
Products
• ESP32-C3 Series SoCs – Browse through all ESP32-C3 SoCs.
IM
http://espressif.com/en/products/socs?id=ESP32-C3
• ESP32-C3 Series Modules – Browse through all ESP32-C3-based modules.
http://espressif.com/en/products/modules?id=ESP32-C3
• ESP32-C3 Series DevKits – Browse through all ESP32-C3-based devkits.
EL
http://espressif.com/en/products/devkits?id=ESP32-C3
• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.
http://products.espressif.com/#/product-selector?language=en
Contact Us
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
PR
(Online stores), Become Our Supplier, Comments & Suggestions.
http://espressif.com/en/contact-us/sales-questions
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Glossary
Glossary
Abbreviations for Peripherals
AES AES (Advanced Encryption Standard) Accelerator
BOOTCTRL Chip Boot Control
DS Digital Signature
DMA DMA (Direct Memory Access) Controller
eFuse eFuse Controller
HMAC HMAC (Hash-based Message Authentication Code) Accelerator
RY
I2C I2C (Inter-Integrated Circuit) Controller
I2S I2S (Inter-IC Sound) Controller
LEDC LED Control PWM (Pulse Width Modulation)
MCPWM Motor Control PWM (Pulse Width Modulation)
PCNT Pulse Count Controller
RMT Remote Control Peripheral
A
RNG Random Number Generator
RSA RSA (Rivest Shamir Adleman) Accelerator
SDHOST SD/MMC Host Controller
SHA
SPI
IN
SHA (Secure Hash Algorithm) Accelerator
SPI (Serial Peripheral Interface) Controller
SYSTIMER System Timer
TIMG Timer Group
IM
TWAI Two-wire Automotive Interface
UART UART (Universal Asynchronous Receiver-Transmitter) Controller
ULP Coprocessor Ultra-low-power Coprocessor
USB OTG USB On-The-Go
WDT Watchdog Timers
EL
Abbreviations for Registers
ISO Isolation. When a module is power down, its output pins will be stuck in unknown
PR
state (some middle voltage). ”ISO” registers will control to isolate its output pins
to be a determined value, so it will not affect the status of other working modules
which are not power down.
NMI Non-maskable interrupt.
REG Register.
R/W Read/write. Software can read and write to these bits.
RO Read-only. Software can only read these bits.
SYSREG System Registers
WO Write-only. Software can only write to these bits.
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Revision History
Revision History
Date Version Release notes
Added the following chapters:
• Chapter 8 Interrupt Matrix (INTMTRX)
• Chapter 14 Debug Assist
• Chapter 23 I2C Controller (I2C)
• Chapter 28 On-Chip Sensor and Analog Signal Processing
2021-10-28 v0.4
• Chapter 29 Related Documentation and Resources
Updated the following Chapters:
RY
• Chapter 4 eFuse Controller (EFUSE)
• Chapter 27 Remote Control Peripheral (RMT)
Added the following chapters:
• Chapter 9 System Timer (SYSTIMER)
• Chapter 11 Watchdog Timers (WDT)
A
• Chapter 12 XTAL32K Watchdog Timers (XTWDT)
• Chapter 13 System Registers (SYSREG)
• Chapter 18 HMAC Accelerator (HMAC)
2021-08-05 v0.3
IN
• Chapter 19 Digital Signature (DS)
• Chapter 24 USB Serial/JTAG Controller (USB_SERIAL_JTAG)
• Chapter 27 Remote Control Peripheral (RMT)
Updated the following Chapters:
IM
• Chapter 4 eFuse Controller (EFUSE)
• Chapter 5 IO MUX and GPIO Matrix (GPIO, IO MUX)
• Chapter 7 Chip Boot Control
• Chapter 25 Two-wire Automotive Interface (TWAI)
EL
Added the following chapters:
• Chapter 2 GDMA Controller (GDMA)
• Chapter 4 eFuse Controller (EFUSE)
• Chapter 10 Timer Group (TIMG)
2021-05-27 v0.2
• Chapter 22 UART Controller (UART)
PR
• Chapter 26 LED PWM Controller (LEDC)
Updated the Chapter 5 IO MUX and GPIO Matrix (GPIO, IO MUX) Adjusted the
order of chapters
2021-04-08 v0.1 Preliminary release
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A RY
IN
IM
EL
PR
Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice.
ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO
WARRANTIES TO ITS AUTHENTICITY AND ACCURACY.
NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-
INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information
in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any
intellectual property rights are granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property
www.espressif.com of their respective owners, and are hereby acknowledged.
Copyright © 2021 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.
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