Lesson 4.

The Processor

FUNDAMENTALS OF COMPUTERS

Emilio J. Padrón <[email protected]>

http://gac.udc.es/~emilioj
Computer Architecture Group (GAC)

Department of Computer Engineering

(Universidade da Coruña)

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 1 / 115
Outline I
1 Introduction
2 Instruction Set
3 MIPS: an example of RISC ISA
4 CPU Design: Datapath and Control
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks

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Introduction

Outline

1 Introduction
2 Instruction Set
3 MIPS: an example of RISC ISA
4 CPU Design: Datapath and Control
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 3 / 115
Introduction

Computer Abstractions and Technology

From a High-level Language to the Language of Hardware
Computer
Electronic device composed of digital components and subsystems that
can be programmed to carry out data processing.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 4 / 115
Introduction

Computer Abstractions and Technology

From a High-level Language to the Language of Hardware
Computer
Electronic device composed of digital components and subsystems that
can be programmed to carry out data processing.

A simplified view of hardware and software as hierarchical layers:

Figure: Source: Computer Organization and Design, by Patterson and Hennessy.

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Introduction

Computer Abstractions and Technology

From a High-level Language to the Language of Hardware

Abstraction helps to cope

with complexity!

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 4 / 115
Introduction

Machine vs. Assembly code

Machine code is the pure binary code executed by the CPU

It’s not very human-readable
▶ hard to manage even expressing it in hexadecimal:
10110000 01100001 ⇒ B0 61 ← this is a real x86 instruction
Assembly/assembler language (asm): low-level programming
language with very strong correspondence to machine code
instructions (near one-to-one)
▶ mnemonics are used to represents instructions and operations
▶ adds some facilities to simplify programming: labels, meta-statements,
etc.

Example: x86 assembly code for 10110000 01100001

MOV AL, 61h ; Load reg AL with 97 decimal (61 hex)

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 5 / 115
Introduction

Machine vs. Assembly code

Machine code is the pure binary code executed by the CPU

It’s not very human-readable
▶ hard to manage even expressing it in hexadecimal:
10110000 01100001 ⇒ B0 61 ← this is a real x86 instruction
Assembly/assembler language (asm): low-level programming
language with very strong correspondence to machine code
instructions (near one-to-one)
▶ mnemonics are used to represents instructions and operations
▶ adds some facilities to simplify programming: labels, meta-statements,
etc.

Example: x86 assembly code for 10110000 01100001

MOV AL, 61h ; Load reg AL with 97 decimal (61 hex)

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 5 / 115
Introduction

Machine vs. Assembly code

Machine code is the pure binary code executed by the CPU

It’s not very human-readable
▶ hard to manage even expressing it in hexadecimal:
10110000 01100001 ⇒ B0 61 ← this is a real x86 instruction
Assembly/assembler language (asm): low-level programming
language with very strong correspondence to machine code
instructions (near one-to-one)
▶ mnemonics are used to represents instructions and operations
▶ adds some facilities to simplify programming: labels, meta-statements,
etc.

Example: x86 assembly code for 10110000 01100001

MOV AL, 61h ; Load reg AL with 97 decimal (61 hex)

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 5 / 115
Introduction

Computer Organization
Hardware level

PROCESSOR (CPU)

PC IR

Instructions
INPUT

REGISTERS
MEMORY
Data

OUTPUT
CONTROL
ALU
UNIT

Figure: 3 main subsystems of a computer: CPU, Memory and Input/Output.

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Introduction

Computer Operation
Instructions and Data

Instructions

PROCESSOR (CPU) Data

MEMORY I/O

A computer operates by executing instructions on data

▶ This is carried out on CPU
▶ Both data and instructions are binary encoded and
stored in main memory
A computer is designed to work with a fixed-sized piece of data: word
▶ The number of bits in a word (word size/width/length) is an important
characteristic of any specific processor design or computer architecture.
▶ Most computer components (registers, buses, memory, peripherals,
ALU) operate (transfer, store, process) in word-size units.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 7 / 115
Introduction

Computer Operation
Instructions and Data

Instructions

PROCESSOR (CPU) Data

MEMORY I/O

A computer operates by executing instructions on data

▶ This is carried out on CPU
▶ Both data and instructions are binary encoded and
stored in main memory
A computer is designed to work with a fixed-sized piece of data: word
▶ The number of bits in a word (word size/width/length) is an important
characteristic of any specific processor design or computer architecture.
▶ Most computer components (registers, buses, memory, peripherals,
ALU) operate (transfer, store, process) in word-size units.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 7 / 115
Introduction

Instruction cycle
fetch-decode-execute cycle
Basic operation cycle of a computer
⇒ Loop repeated continuously by CPU, from bootup to shutdown
4 basic steps:
1 Fetching the instruction: instruction to be executed is retrieved from
memory.
⇒ 2 registers involved: PC & IR
Instruction is fetched from mem address stored in Program Counter (PC)
and is stored in Instruction Register (IR)
IR ← MEM[PC]
2 Decode the instruction: encoded instruction in IR is interpreted by
the decoder.
3 Execute the instruction: Control Unit sends signals to perform
actions required by the decoded instructions (Registers, ALU, Mem).
4 Next instruction address calculation: PC is updated.
⇒ instructions are executed sequentially, or as otherwise directed by control
flow instructions (jump, branch. . . )

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 8 / 115
Introduction

Instruction cycle
fetch-decode-execute cycle
Basic operation cycle of a computer
⇒ Loop repeated continuously by CPU, from bootup to shutdown
4 basic steps:
1 Fetching the instruction: instruction to be executed is retrieved from
memory.
⇒ 2 registers involved: PC & IR
Instruction is fetched from mem address stored in Program Counter (PC)
and is stored in Instruction Register (IR)
IR ← MEM[PC]
2 Decode the instruction: encoded instruction in IR is interpreted by
the decoder.
3 Execute the instruction: Control Unit sends signals to perform
actions required by the decoded instructions (Registers, ALU, Mem).
4 Next instruction address calculation: PC is updated.
⇒ instructions are executed sequentially, or as otherwise directed by control
flow instructions (jump, branch. . . )

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 8 / 115
Introduction

Instruction cycle
fetch-decode-execute cycle
Basic operation cycle of a computer
⇒ Loop repeated continuously by CPU, from bootup to shutdown
4 basic steps:
1 Fetching the instruction: instruction to be executed is retrieved from
memory.
⇒ 2 registers involved: PC & IR
Instruction is fetched from mem address stored in Program Counter (PC)
and is stored in Instruction Register (IR)
IR ← MEM[PC]
2 Decode the instruction: encoded instruction in IR is interpreted by
the decoder.
3 Execute the instruction: Control Unit sends signals to perform
actions required by the decoded instructions (Registers, ALU, Mem).
4 Next instruction address calculation: PC is updated.
⇒ instructions are executed sequentially, or as otherwise directed by control
flow instructions (jump, branch. . . )

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 8 / 115
Introduction

Instruction cycle
fetch-decode-execute cycle
Basic operation cycle of a computer
⇒ Loop repeated continuously by CPU, from bootup to shutdown
4 basic steps:
1 Fetching the instruction: instruction to be executed is retrieved from
memory.
⇒ 2 registers involved: PC & IR
Instruction is fetched from mem address stored in Program Counter (PC)
and is stored in Instruction Register (IR)
IR ← MEM[PC]
2 Decode the instruction: encoded instruction in IR is interpreted by
the decoder.
3 Execute the instruction: Control Unit sends signals to perform
actions required by the decoded instructions (Registers, ALU, Mem).
4 Next instruction address calculation: PC is updated.
⇒ instructions are executed sequentially, or as otherwise directed by control
flow instructions (jump, branch. . . )

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 8 / 115
Introduction

Instruction cycle
fetch-decode-execute cycle
Basic operation cycle of a computer
⇒ Loop repeated continuously by CPU, from bootup to shutdown
4 basic steps:
1 Fetching the instruction: instruction to be executed is retrieved from
memory.
⇒ 2 registers involved: PC & IR
Instruction is fetched from mem address stored in Program Counter (PC)
and is stored in Instruction Register (IR)
IR ← MEM[PC]
2 Decode the instruction: encoded instruction in IR is interpreted by
the decoder.
3 Execute the instruction: Control Unit sends signals to perform
actions required by the decoded instructions (Registers, ALU, Mem).
4 Next instruction address calculation: PC is updated.
⇒ instructions are executed sequentially, or as otherwise directed by control
flow instructions (jump, branch. . . )

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 8 / 115
Instruction Set

Outline
1 Introduction
2 Instruction Set
Instruction types and format
ISA design aspects
Execution model
Addressing modes
3 MIPS: an example of RISC ISA
4 CPU Design: Datapath and Control
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 9 / 115
Instruction Set

Instruction Set Architecture (ISA)

CPU operation is determined by the instructions it executes

Instruction Set Architecture (or just Instruction Set): part of

computer architecture related to programming:
▶ instructions, native data types, registers, addressing modes, memory
architecture, interrupt and exception handling, and external I/O.
▶ examples: x86, x86-64, ARMv7-A, ARMv8-A, MIPS, POWER. . .
ISA vs. Microarchitecture
▶ microarchitecture: set of processor design techniques used to
implement the instruction set.
▶ computers with different microarchitectures can share a common
instruction set.
→ e.g. Intel Pentium and AMD Athlon implement x86 instruction set with
different internal designs

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 10 / 115
Instruction Set

Instruction Set Architecture (ISA)

CPU operation is determined by the instructions it executes

Instruction Set Architecture (or just Instruction Set): part of

computer architecture related to programming:
▶ instructions, native data types, registers, addressing modes, memory
architecture, interrupt and exception handling, and external I/O.
▶ examples: x86, x86-64, ARMv7-A, ARMv8-A, MIPS, POWER. . .
ISA vs. Microarchitecture
▶ microarchitecture: set of processor design techniques used to
implement the instruction set.
▶ computers with different microarchitectures can share a common
instruction set.
→ e.g. Intel Pentium and AMD Athlon implement x86 instruction set with
different internal designs

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 10 / 115
Instruction Set Instruction types and format

Machine instructions
a.k.a. machine code or machine language
Set of instructions executed directly by a CPU
Machine code (i.e., not assembly code) is the lowest-level
programming language
▶ it’s just binary code
▶ it’s completely hardware-dependent
Instruction types:
Data handling and memory operations
▶ Registers ↔ Memory transfers
▶ I/O operations (peripherals)
Arithmetic and logic operations
▶ ALU and related stuff
Control flow operations
▶ Branch/Jump (cond, uncond, indirect)
▶ Subroutine call
System control operations and others
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Instruction Set Instruction types and format

Machine instructions
a.k.a. machine code or machine language
Set of instructions executed directly by a CPU
Machine code (i.e., not assembly code) is the lowest-level
programming language
▶ it’s just binary code
▶ it’s completely hardware-dependent
Instruction types:
Data handling and memory operations
▶ Registers ↔ Memory transfers
▶ I/O operations (peripherals)
Arithmetic and logic operations
▶ ALU and related stuff
Control flow operations
▶ Branch/Jump (cond, uncond, indirect)
▶ Subroutine call
System control operations and others
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 11 / 115
Instruction Set Instruction types and format

Machine instructions
Instruction format
Parts of an instruction: (common fields)
▶ Operation code (opcode): operation to perform.
▶ Operand specifiers: zero or more.
⋆ registers, memory locations, or literal data
▶ Destination operand specifier: where to store result, if any.
▶ Predicate field: encode the specific condition in Conditional
Instructions.
▶ Next instruction reference: usually implicit: sequential order.
Otherwise, all necessary stuff to compute next instruction address is
provided.

4 bits 6 bits 6 bits

opcode operand1 ref operand2 ref

16 bits
Figure: Example of a simple 16-bit format.
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Instruction Set ISA design aspects

Instruction Set Architecture

Design aspects
Key ISA decisions:
Operations
▶ How many?
▶ What operations and how complex?
Operands
▶ How many?
▶ Data types?
▶ Location
▶ How to specify them?
Instruction formats
▶ How many formats? (most ISAs use more than one format)
▶ Size? In some architectures instructions are a fixed length, typically
corresponding with that architecture’s word size
Addressing modes
▶ How to specify operands in memory
▶ How to specify a memory address to jump
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Instruction Set ISA design aspects

Instruction Set Architecture

Design aspects
Key ISA decisions:
Operations
▶ How many?
▶ What operations and how complex?
Operands
▶ How many?
▶ Data types?
▶ Location
▶ How to specify them?
Instruction formats
▶ How many formats? (most ISAs use more than one format)
▶ Size? In some architectures instructions are a fixed length, typically
corresponding with that architecture’s word size
Addressing modes
▶ How to specify operands in memory
▶ How to specify a memory address to jump
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 13 / 115
Instruction Set ISA design aspects

Instruction Set Architecture

Design aspects
Key ISA decisions:
Operations
▶ How many?
▶ What operations and how complex?
Operands
▶ How many?
▶ Data types?
▶ Location
▶ How to specify them?
Instruction formats
▶ How many formats? (most ISAs use more than one format)
▶ Size? In some architectures instructions are a fixed length, typically
corresponding with that architecture’s word size
Addressing modes
▶ How to specify operands in memory
▶ How to specify a memory address to jump
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 13 / 115
Instruction Set ISA design aspects

Instruction Set Architecture

Design aspects
Key ISA decisions:
Operations
▶ How many?
▶ What operations and how complex?
Operands
▶ How many?
▶ Data types?
▶ Location
▶ How to specify them?
Instruction formats
▶ How many formats? (most ISAs use more than one format)
▶ Size? In some architectures instructions are a fixed length, typically
corresponding with that architecture’s word size
Addressing modes
▶ How to specify operands in memory
▶ How to specify a memory address to jump
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 13 / 115
Instruction Set ISA design aspects

Instruction Set Architecture

Design strategies
Two different architectural design philosophies:
CISC (Complex Instruction Set Computer)
▶ Rich instruction set, with many specialized instructions
▶ Complex and powerful addressing modes
▶ Machine programs with less (but complex) instructions
RISC (Reduced Instruction Set Computer)
▶ Simplified instruction set, efficiently implementing only the instructions
that are frequently used in programs
- few operations and instruction formats
▶ Load/Store architecture
▶ Machine programs with more instructions
Case study
We’ll study a classic RISC ISA this course: MIPS
RISC pioneer! Instruction set family introduced in 1981
Used in desktop and supercomputers for years, now is primarily used in embedded
systems
MIPS implementations were used by NEC, Nintendo, SGI, Sony. . .
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 14 / 115
Instruction Set ISA design aspects

Instruction Set Architecture

Design strategies
Two different architectural design philosophies:
CISC (Complex Instruction Set Computer)
▶ Rich instruction set, with many specialized instructions
▶ Complex and powerful addressing modes
▶ Machine programs with less (but complex) instructions
RISC (Reduced Instruction Set Computer)
▶ Simplified instruction set, efficiently implementing only the instructions
that are frequently used in programs
- few operations and instruction formats
▶ Load/Store architecture
▶ Machine programs with more instructions
Case study
We’ll study a classic RISC ISA this course: MIPS
RISC pioneer! Instruction set family introduced in 1981
Used in desktop and supercomputers for years, now is primarily used in embedded
systems
MIPS implementations were used by NEC, Nintendo, SGI, Sony. . .
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 14 / 115
Instruction Set Execution model

Execution model
How many operands and their internal storage in CPU

The execution model of an ISA specifies:

▶ where instruction’s operands are stored (mem, regs, etc.)
▶ how many are explicitly specified in the instruction
A same architecture can implement multiple execution models
Execution models are tighly coupled with architecture design decisions
Major choices:
▶ Accumulator
Old fashioned! Used in most early ma-
▶ Stack (POP/PUSH) chines
▶ General Purpose Regs & Memory (GPR)
+ register–register
+ register–memory
+ memory–memory

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 15 / 115
Instruction Set Execution model

Execution model
How many operands and their internal storage in CPU

The execution model of an ISA specifies:

▶ where instruction’s operands are stored (mem, regs, etc.)
▶ how many are explicitly specified in the instruction
A same architecture can implement multiple execution models
Execution models are tighly coupled with architecture design decisions
Major choices:
▶ Accumulator
Old fashioned! Used in most early ma-
▶ Stack (POP/PUSH) chines
▶ General Purpose Regs & Memory (GPR)
+ register–register
+ register–memory
+ memory–memory

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 15 / 115
Instruction Set Execution model

Execution model
Main models
Accumulator 1 explicit operand (reg or mem)
1 implicit operand (acc)
add A acc ← acc + A
Stack 0 explicit operands
All operands implicit (on TOS)
add tos ← tos + next
General Purpose Regs & Memory
all operands explicit either registers or mem. locat.
register–register (load/store arch.)
2 regs: add A B RA ← RA + RB
3 regs: add A B C RA ← RB + RC
register–memory
1 reg, 1 mem: add A B RA ← RA + mem(B)
memory–memory
3 mem: add A B C mem(A) ← mem(B) + mem(C )
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Instruction Set Execution model

Execution model
Main models
Accumulator 1 explicit operand (reg or mem)
1 implicit operand (acc)
add A acc ← acc + A
Stack 0 explicit operands
All operands implicit (on TOS)
add tos ← tos + next
General Purpose Regs & Memory
all operands explicit either registers or mem. locat.
register–register (load/store arch.)
2 regs: add A B RA ← RA + RB
3 regs: add A B C RA ← RB + RC
register–memory
1 reg, 1 mem: add A B RA ← RA + mem(B)
memory–memory
3 mem: add A B C mem(A) ← mem(B) + mem(C )
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 16 / 115
Instruction Set Execution model

Execution model
Main models
Accumulator 1 explicit operand (reg or mem)
1 implicit operand (acc)
add A acc ← acc + A
Stack 0 explicit operands
All operands implicit (on TOS)
add tos ← tos + next
General Purpose Regs & Memory
all operands explicit either registers or mem. locat.
register–register (load/store arch.)
2 regs: add A B RA ← RA + RB
3 regs: add A B C RA ← RB + RC
register–memory
1 reg, 1 mem: add A B RA ← RA + mem(B)
memory–memory
3 mem: add A B C mem(A) ← mem(B) + mem(C )
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 16 / 115
Instruction Set Execution model

Execution model
Main models
Accumulator 1 explicit operand (reg or mem)
1 implicit operand (acc)
add A acc ← acc + A
Stack 0 explicit operands
All operands implicit (on TOS)
add tos ← tos + next
General Purpose Regs & Memory
all operands explicit either registers or mem. locat.
register–register (load/store arch.)
2 regs: add A B RA ← RA + RB
3 regs: add A B C RA ← RB + RC
register–memory
1 reg, 1 mem: add A B RA ← RA + mem(B)
memory–memory
3 mem: add A B C mem(A) ← mem(B) + mem(C )
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 16 / 115
Instruction Set Execution model

Execution model
Main models
Accumulator 1 explicit operand (reg or mem)
1 implicit operand (acc)
add A acc ← acc + A
Stack 0 explicit operands
All operands implicit (on TOS)
add tos ← tos + next
General Purpose Regs & Memory
all operands explicit either registers or mem. locat.
register–register (load/store arch.)
2 regs: add A B RA ← RA + RB
3 regs: add A B C RA ← RB + RC
register–memory
1 reg, 1 mem: add A B RA ← RA + mem(B)
memory–memory
3 mem: add A B C mem(A) ← mem(B) + mem(C )
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 16 / 115
Instruction Set Execution model

Execution model
Comparison: number of instructions

Example:
Code sequence for C = A + B for four classes of instruction sets
Stack Accum Reg-Mem Reg-Reg
Push A Load A Load R1, A Load R1, A
Push B Add B Add R1, B Load R2, B
Add Store C Store C, R1 Add R3, R1, R2
Pop C Store C, R3

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Instruction Set Execution model

RISC philosophy & Load-Store architecture

Summary
Design principles
1 Simplicity favors regularity
2 Smaller is faster
3 Make the common case fast
4 Good design demands good compromises

Load-Store execution model fits with RISC principle designs:

Intense use of registers (regs faster than memory)
Simple Instruction Set:
▶ few operations and load/store-based
▶ regular instruction formats (short, few formats)
▶ fast and regular execution! (few CPU cycles per instruction)
Pipelining to achieve performace

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 18 / 115
Instruction Set Execution model

RISC philosophy & Load-Store architecture

Summary
Design principles
1 Simplicity favors regularity
2 Smaller is faster
3 Make the common case fast
4 Good design demands good compromises

Pipelining? overlapping parts of a large task to increase throughput

without decreasing latency

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Instruction Set Addressing modes

Addressing modes
how do we specify the operand we want?

Addressing mode: Algorithm applied to get the effective address of

an operand or an instruction
Some typical addressing modes:
▶ Immediate (literal) #25
▶ Direct (absolute) M[10000]
▶ Register direct R3
▶ Register indirect M[R3]
▶ Base+Displacement M[R3 + 10000]
(if register is the program counter, this is PC-relative)

▶ Memory Indirect M[ M[R3] ]

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Instruction Set Addressing modes

Addressing modes
Immediate addressing

Instruction
opcode ... operand (literal)

▶ Operand is a constant literal value in an instruction’s field.

✓ Advantage: no additional mem. ref. needed to get operand
✗ Drawback: value limited by field’s size

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Instruction Set Addressing modes

Addressing modes
Direct addressing
Instruction Memory
opcode ... address (literal)

operand
mem

Operand is stored in memory. Its address is literally in an instruction’s

field.
✗ Drawback: addressing space limited by field’s size
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 21 / 115
Instruction Set Addressing modes

Addressing modes
Register direct addressing

Instruction
Operand is located in a register.
opcode ... Reg.ID
Register ID is indicated in an
Bank of Registers instruction’s field.
+ Advantages:
R ✓ Few bits needed to index registers
⇒ small field
✓ Registers are much faster than
operand memory (lower access time)
✗ Drawback: few registers! (scarce
good)

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Instruction Set Addressing modes

Addressing modes
Register indirect addressing
Instruction Memory
opcode ... Reg.ID

Bank of Registers

R
operand
mem. address

mem

Operand’s address is in the register indexed by an instruction’s field:

operand := memory[R]
✓ Advantage: large address space with a short bit field
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Instruction Set Addressing modes

Addressing modes
Memory indirect addressing
Instruction Memory
opcode ... address (literal)

operand

mem2

operand's address
mem1

Operand’s address is in mem location indexed by the literal address in

an instruction’s field: operand := M[ M [mem1]]
✗ Drawback: two memory accesses to get operand
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 24 / 115
Instruction Set Addressing modes

Addressing modes
Base plus offset, and variations
Effective address is computed as the addition of a base address and
an offset or displacement
Common approach for data: base register plus offset
▶ Base address is in a register indicated in the instruction
▶ Offset is a literal constant also included in an instruction’s field
operand := memory[R + offset]
Instruction Memory
opcode ... Reg.ID offset

Bank of Registers
R dis

operand
effec.
mem
base address

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 25 / 115
Instruction Set Addressing modes

Addressing modes
Base plus offset, and variations
Effective address is computed as the addition of a base address and
an offset or displacement
Common approach for code: PC-relative addressing
▶ Base register is implicit (PC in this case)
▶ PC-relative offset in instruction’s field
instruction := memory[PC + offset]
Instruction Memory
opcode ... offset

Bank of Registers
dis

PC base address instruction

effec.
mem

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 25 / 115
MIPS: an example of RISC ISA

Outline
1 Introduction
2 Instruction Set
3 MIPS: an example of RISC ISA
MIPS R2000 architecture
MIPS instruction types
MIPS instruction formats
MIPS addressing modes
Subroutines/Functions in MIPS
MIPS assembly & machine code examples
4 CPU Design: Datapath and Control
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 26 / 115
MIPS: an example of RISC ISA MIPS R2000 architecture

MIPS R2000 architecture

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 27 / 115
MIPS: an example of RISC ISA MIPS R2000 architecture

MIPS R2000 architecture

Registers
Name Reg. Usage Preserved
number on call
$zero 0 the contant value 0 n.a.
$at 1 reserved for the assembler n.a.
$v0-$v1 2-3 values for results and expression evaluation no
$a0-$a3 4-7 arguments yes
$t0-$t7 8-15 temporaries no
$s0-$s7 16-23 saved yes
$t8-$t9 24-25 more temporaries no
$k0-$k1 26-27 reserved for the operating system n.a.
$gp 28 global pointer yes
$sp 29 stack pointer yes
$fp 30 frame pointer yes
$ra 31 return address yes
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 28 / 115
MIPS: an example of RISC ISA MIPS R2000 architecture

MIPS R2000 architecture

Some details: byte addressing and word size

Fixed-width instructions: 32 bits (also word size)

Byte-addressable memory: 1 address = 1 memory byte (8 bits)
Memory word: 4 bytes (32 bits)
▶ 1 word / transfer
▶ the address of a word is the address of its first byte
▶ 2 adjacent words are separated 4 bytes
▶ word alignment constraint: word quantities are word-aligned in
memory:
⋆ words are stored and accessed in addresses multiple of 4:
aligned address (first byte of every memory word is stored at an address
divisible by 4)
▶ attempting to access a unit larger than a byte at an unaligned address
causes a bus error

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 29 / 115
MIPS: an example of RISC ISA MIPS R2000 architecture

MIPS R2000 architecture

Endianness
Endianness refers to the order of the bytes in a word
▶ Big-endian: most significant byte is stored at a particular memory
address and the subsequent bytes are stored in the following higher
memory addresses
⇒ word address corresponds to word’s MSB
▶ Little-endian: stores the least significant byte at the lowest memory
address with the most significant byte being stored at the highest
memory address
⇒ word address corresponds to word’s LSB
▶ Bi-endian: configurable (MIPS)

4 byte word
Big Endian
MSB LSB
byte byte byte byte
3 2 1 0

Little Endian
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 30 / 115
MIPS: an example of RISC ISA MIPS instruction types

MIPS instruction types

Types of instructions in ISA:

▶ Data transfer (load/store)
▶ Arithmetic and Logical
▶ Program control:
⋆ Conditional jump/branch
⋆ Unconditional jump

Main features:
▶ Fixed width: 32 bits.
▶ Operands in arithmetic-logic operations are always registers.
▶ Memory access is always by means of load/store instructions (data
transfer).

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 31 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

R-type

op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

I-type

op rs rt address/immediate
6 bits 5 bits 5 bits 16 bits

J-type

op target immediate
6 bits 26 bits

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 32 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

Arithmetic-logic instructions
add, sub, or, and. . .
R-format type
Register direct addressing
add $7,$3,$6

0 3 6 7 0 32
op rs rt rd shamt funct

000000 00011 00110 00111 00000 100000

31 26 25 21 20 16 15 11 10 6 5 0

sub $7,$3,$6

0 3 6 7 0 34
op rs rt rd shamt funct

000000 00011 00110 00111 00000 100010

31 26 25 21 20 16 15 11 10 6 5 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 33 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

Arithmetic-logic instructions

Immediate operand version:

addi, andi, ori. . .
I-format type
Register direct addressing + immediate addressing
addi $8,$6,4

8 6 8 4
op rs rt immediate

001000 00110 01000 0000 0000 0000 0100

31 26 25 21 20 16 15 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 34 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

Data transfer instructions
lw (load word) & sw (store word)
I-format
Base+Displacement addressing
lw $8,1200($15)

35 15 8 1200
op rs rt address (offset)

100011 01111 01000 0000 0100 1011 0000

31 26 25 21 20 16 15 0

sw $8,1200($15)

43 15 8 1200
op rs rt address (offset)

101011 01111 01000 0000 0100 1011 0000

31 26 25 21 20 16 15 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 35 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

Data transfer instructions
Data transfer operations with immediate operands:
lui (load upper inmediate)
I-type
Register direct addressing (destination operand) + immediate
addressing
Code machine for this asm instruc: lui $8,255

001111 00000 01000 0000 0000 1111 1111

op rs rt immediate

Content of reg. $8
after its execution:
Reg.
$8 0000 0000 1111 1111 0000 0000 0000 0000

Figure: Result of this load operation: $rt = immediate « 16

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 36 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

Making decisions: Conditional branches (jumps)
beq (branch if equal) & bne (branch if not equal)
I-type
PC-relative addressing for jump address
register direct addressing for condition comparison

Example
beq $19, $20, Label ▶ Jump address is indicated wih a label in asm
bne $19, $20, Label
▶ Assembler computes a PC-relative offset for
machine code:
jump address − branch instr . address
offset =
4
▶ Then, when instr. is executed:
jump to (PC + 4) + 4 ∗ offset if $rs = $rt (beq)
| {z }
effective address

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 37 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

Making decisions: Conditional branches (jumps)
beq (branch if equal) & bne (branch if not equal)
I-type
PC-relative addressing for jump address
register direct addressing for condition comparison
beq $19,$20, Label
PC-relative offset
4 19 20 from LabelL1
op rs rt address (offset)

000100 10011 10100 0001 1000 0011 1101

31 26 25 21 20 16 15 0

bne $19,$20, Label

PC-relative offset
5 19 20 from LabelL1
op rs rt address (offset)

000101 10011 10100 0001 1000 0011 1101

31 26 25 21 20 16 15 0
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 37 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

Making decisions: other comparisons

Less than comparison: slt (set on less than) & slti

Compares to registers and sets a third register to 1 if the first is less
than the second
▶ slt $rd,$rs,$rt (R-type) ⇒ $rd = ($rs < $rt)
▶ slti $rd,$rs,inm (I-type) ⇒ $rd = ($rs < immediate)

slt $8,$19,$20

0 19 20 8 0 42
op rs rt rd shamt funct

slti $8,$19,10

10 19 8 10
op rs rt immediate

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 38 / 115
MIPS: an example of RISC ISA MIPS instruction formats

MIPS instruction formats

Unconditional jumps
j (jump): J-type, pseudo-direct addressing
▶ PC ← (PC + 4)31−28 IR25−0 00
| {z }
immediate
| {z }
jump effective address(32bits)
▶ Again, the immediate operand is compute by assembler from a label

jr (jump register): R-type, register indirect addressing

j Label

2 26 bits of the destination address

31 26 25 0
op immediate

jr $8

0 8 0 0 0 8
op rs rt rd shamt funct

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 39 / 115
MIPS: an example of RISC ISA MIPS addressing modes

MIPS addressing modes

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 40 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
Subroutine sequence of program instructions that perform a specific
task, packaged as a unit.
Powerful programming tool that allows a structured programming
approach
▶ Increasing code legibility
▶ Reducing duplicate code within a program and enabling reuse of code
across multiple programs
Steps to perform a subroutine call:
▶ Passing the arguments: place subroutine parametes in an appropriate
location, where they can be accessed.
▶ Branching: transfer control to the procedure’s body by a simple jump.
▶ Allocate required storage resources for the task
▶ Carry out the task
▶ Place subroutine result (return value) in an appropriate location, where
it can be found by the caller.
▶ Branching back to the caller: return control to the caller code.
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 41 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
Subroutine sequence of program instructions that perform a specific
task, packaged as a unit.
Powerful programming tool that allows a structured programming
approach
▶ Increasing code legibility
▶ Reducing duplicate code within a program and enabling reuse of code
across multiple programs
Steps to perform a subroutine call:
▶ Passing the arguments: place subroutine parametes in an appropriate
location, where they can be accessed.
▶ Branching: transfer control to the procedure’s body by a simple jump.
▶ Allocate required storage resources for the task
▶ Carry out the task
▶ Place subroutine result (return value) in an appropriate location, where
it can be found by the caller.
▶ Branching back to the caller: return control to the caller code.
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 41 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
Subroutine sequence of program instructions that perform a specific
task, packaged as a unit.
Steps to perform a subroutine call:
▶ Passing the arguments: place subroutine parametes in an appropriate
location, where they can be accessed.
▶ Branching: transfer control to the procedure’s body by a simple jump.
▶ Allocate required storage resources for the task
▶ Carry out the task
▶ Place subroutine result (return value) in an appropriate location, where
it can be found by the caller.
▶ Branching back to the caller: return control to the caller code.

Passing arguments/parameters to subroutines:

▶ Memory stack
▶ Registers

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 41 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
MIPS Memory Layout and Stack
$sp 7 f f f f f f f hex Stack

Stack: mem. space with

LIFO operation.
Register $sp points to most
recently used address (Top
Dynamic data
of Stack).
$gp 1000 8000 hex Grows downward
Static data
1000 0000 hex
Text
pc 0040 0000 hex

Reserved
0
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 42 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
Passing arguments through stack

Usually, caller passes parameters through stack.

Subroutine also uses stack for temporary data.
When finish, subroutine frees temporary memory and puts return
value(s) on stack.
Lastly, caller takes return value(s) from stack.
Managing stack:
▶ Storing two registers’ content in stack (push):
addi $sp, $sp, -8
sw $v0, 0($sp)
sw $v1, 4($sp)
▶ Recovering data from stack (pop):
lw $v0, 0($sp)
lw $v1, 4($sp)
addi $sp, $sp, 8

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 43 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
Passing arguments through registers

Accessing registers is faster than memory!

MIPS convention to use registers as a fast alternative to stack for
passing arguments/results across calls:
▶ $a0–$a3: passing arguments.
▶ $v0–$v1: returning results.
▶ $ra: storing return address.
If more arguments/results are needed, then it is neccessary to use the
Stack.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 44 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
Jumping to subroutine code and returning control when finish

jal Subroutine_label

3 26 bits of the destination address

31 26 25 0
op immediate

jal (jump-and-link): Unconditional jump to an arbitrary address,

storing return address ($ra = PC+4).
J-Type format.
Pseudodirect addressing. Assembler allows the use of labels.
Return jump is carried out through jr $ra.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 45 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
Jumping to subroutine code and returning control when finish

jal Subroutine_label

3 26 bits of the destination address

31 26 25 0
op immediate

Usage:
▶ Caller loads parameters in $a0–$a3 (or in stack) and calls jal.
▶ Subroutine perform the computation, puts results in $v0–$v1 (or in
stack) and return control.
▶ If more than 4 arguments are needed, or more than 2 results are
returned, stack is used.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 45 / 115
MIPS: an example of RISC ISA Subroutines/Functions in MIPS

Subroutine calls
Saving register contents

What if a subroutine modifies a register’s content but the caller

does’t know/expect that?
⇒ Values should be saved (before) and restored (after)
How? Calling conventions! Two approaches:
▶ Caller saves
▶ Callee (subroutine code) saves
To avoid save&restore non-important data, the next conventions are
used in MIPS:
▶ Temp regs ($t0–$t9): not save by callee. It is caller’s responsability to
save their value if needed.
▶ Saved regs ($s0–$s7): if callee needs to use them, it has to restore
their value before returning control.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 46 / 115
MIPS: an example of RISC ISA MIPS assembly & machine code examples

MIPS assembly & machine code examples

f = (g+h) – (i+j)
f, g, h, i, j → $s0,… $s4 ($16… $20)

$t0, $t1 temp. regs ($8, $9)

add $t0, $s1, $s2 0 17 18 8 0 32

000000 10001 10010 01000 00000 100000
0x 02324020

add $t1, $s3, $s4 0 19 20 9 0 32

000000 10011 10100 01001 00000 100000
0x 02744820

sub $s0, $t0, $t1 0 8 9 16 0 34

000000 01000 01001 10000 00000 100010
0x 01098022

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 47 / 115
MIPS: an example of RISC ISA MIPS assembly & machine code examples

MIPS assembly & machine code examples

g = h + A[8]
g → $s1 h → $s2 &A[0] → $s3

lw $t0, 32($s3)

add $s1, $s2, $t0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 48 / 115
MIPS: an example of RISC ISA MIPS assembly & machine code examples

MIPS assembly & machine code examples

while(save[i]==k)
i = i + 1
i → $s3 k → $s5 &save[0] → $s6

loop: add $t1, $s3, $s3

add $t1, $t1, $t1 } More efficient alternative:
add $t1, $t1, $s6 loop: sll $t1, $s3, 2
lw $t0, 0($t1) 0 0 $s3 St1 2 0
bne $t0, $s5, exit
addi $s3, $s3, 1
j loop bne machine code repr:
exit: … 5 $t0 $s5 2

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 49 / 115
MIPS: an example of RISC ISA MIPS assembly & machine code examples

MIPS assembly & machine code examples

C pseudo-code
$a0 $a1 $a2 $a3
operation ( g, h, i, j )
{
f = add(g, h) – add(i, j);
return f;
$v0
}

$a0 $a1
add ( a, b )
{
sum = a + b;
return sum;
} $v0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 50 / 115
MIPS: an example of RISC ISA MIPS assembly & machine code examples

MIPS assembly & machine code examples

C pseudo-code & MIPS asm
operation:
addi $sp, $sp, -8 # store $ra and $s0 contents
sw $ra, 0($sp) # in stack
sw $s0, 4($sp)
$a0 $a1 $a2 $a3
operation ( g, h, i, j ) jal add # $v0 = g+h
{ addi $s0, $v0, 0 # $s0 = g+h
f = add(g, h) – add(i, j); addi $a0, $a2, 0 # $a0 = i
return f; addi $a1, $a3, 0 # $a1 = j
} $v0 jal add # $v0 = i+j
$a0 $a1 sub $v0, $s0, $v0 # $v0 = (g+h)-(i+j)
add ( a, b )
{ lw $ra, 0($sp) # take back $ra and $0
sum = a + b; lw $s0, 4($sp) # from stack
return sum; addi $sp, $sp, 8
$v0
} jr $ra # return control
add:
add $v0, $a0, $a1 # $v0=a+b
jr $ra # return control
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 51 / 115
CPU Design: Datapath and Control

Outline
1 Introduction
2 Instruction Set
3 MIPS: an example of RISC ISA
4 CPU Design: Datapath and Control
MIPS Datapath Design
Datapath design: Control signals
Control Unit Design
Control Sequential System
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 52 / 115
CPU Design: Datapath and Control

CPU
Datapath and Control

Central Processing Unit (CPU)

Computer component in charge of executing instructions.

Two fundamental blocks:

▶ Datapath: performing the basic arithmetic, logical, control and
input/output (I/O) operations specified by the instructions. Includes:
⋆ ALU
⋆ Bank of registers
⋆ Special registers: IR, PC, etc.
⋆ Internal buses: channels connecting all the internal components of a
computer
▶ Control Unit (CU): manages the sequence of operations to be carried
out by the datapath.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 53 / 115
CPU Design: Datapath and Control

Instruction cycle in MIPS

5 steps to execute an instruction:

▶ Instruction fetching: take instr. from mem
▶ Instruction decoding: determine required actions
▶ Operand fetching: locate and obtain operand data
▶ Execution: compute result value or status
▶ Result storing: deposit results in storage for later use

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 54 / 115
CPU Design: Datapath and Control

CPU Design: Datapath and Control

Introduction

We’ll study a simple CPU design (datapath and control unit) able of
executing this subset from MIPS ISA:
▶ Data transfer instructions: lw and sw.
▶ Arithmetic-logic instructions: add, sub, and, or and slt.
▶ Control flow instructions: beq and j.

We start by building a datapath:

▶ Combinational and sequential digital circuits will be used
▶ Edge-triggered sync is assumed for seq. systems

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 55 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Instruction fetching
MIPS Datapath Design

Adder

PC Address
Instruction IR
Instruction
Memory

Next instruction to be executed is in memory address pointed by PC.

Instruction is fetched: taken from memory and loaded in
Instruction Register (IR).
PC is updated to move to next instruction: PC = PC + 4 bytes
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 56 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Arithmetic-logic instructions
MIPS Datapath Design
3
Reg. to Operation
read 1

REGISTERS
Instruction Reg. to
Operand 1 ALU
read 2 Zero
Reg. to
Result
write
Operand 2
Result to
write

WriteReg

R-Type instructions deal with 3 regs: two for reading, one for writing.
Operation is carried out by ALU
Example: add $t1, $t2, $t3

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 57 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Arithmetic-logic instructions
MIPS Datapath Design
3
Reg. to Operation
read 1

REGISTERS
Instruction Reg. to
Operand 1 ALU
read 2 Zero
Reg. to
Result
write
Operand 2
Result to
write

WriteReg

Register file (a.k.a. Bank of registers):

▶ 32-bit registers
▶ Two READ ports and one WRITE port in Register file
▶ WriteReg signal is used to write
▶ Inputs (reg. address to read/write): 5 bits
▶ Outputs: 32 bits (word size)
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 57 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Arithmetic-logic instructions
ALU: Arithmetic-Logic Unit

ALU
Operation

Control lines Function

a
000 and
Zero 001 or
ALU Result 010 add
Overflow
110 sub
b 111 slt

Carry out

This ALU’s design was depicted in the last slides of the Combinational Systems
lesson.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 58 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Data transfer instructions: Load & Store

MIPS Datapath Design
3
Reg. to Operation
read 1

REGISTERS
Instruction Reg. to
Operand 1 ALU WriteMem
read 2 Zero
Read
Reg. to Address
Result data
write
Operand 2 Data
Result to
write
Memory
Data
WriteReg to write
ReadMem

16 32
Sign
Extension

I-Type instructions
Addressing modes: base+displacement (base register) and
register-direct
Examples: lw $t1, offset($t2) sw $t1, offset($t2)
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 59 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Data transfer instructions: Load & Store

MIPS Datapath Design
3
Reg. to Operation
read 1

REGISTERS
Instruction Reg. to
Operand 1 ALU WriteMem
read 2 Zero
Read
Reg. to Address
Result data
write
Operand 2 Data
Result to
write
Memory
Data
WriteReg to write
ReadMem

16 32
Sign
Extension

ALU is used to compute effective memory addresses

OFFSET field is extended from 16 to 32 bits before the addition

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 59 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Data transfer instructions: Load & Store

MIPS Datapath Design
3
Reg. to Operation
read 1

REGISTERS
Instruction Reg. to
Operand 1 ALU WriteMem
read 2 Zero
Read
Reg. to Address
Result data
write
Operand 2 Data
Result to
write
Memory
Data
WriteReg to write
ReadMem

16 32
Sign
Extension

Memory (data segment)

▶ Inputs:
⋆ Control signal to Read and Write ▶ Outputs:
⋆ Address to access (32 bits) ⋆ Word to load (read) (32 bits)
⋆ Word to store (write) (32 bits)
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 59 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Branching: Conditional jumps

MIPS Datapath Design 3
Operation
PC+4 from Instruction fetching datapath
Adder

Result Jump
2-bit destination
left shifting

3
Reg. to Operation
read 1
comp
REGISTERS
Instruction Operand 1
Reg. to
read 2 Zero Jump decision
Reg. to
write ALU
Operand 2

WriteReg

16 32
Sign
Extension

I-Type instructions: beq $t1, $t2, loop

Jump condition: are $t1’s and $t2’s contents equal? ⇒ If TRUE, then jump to label
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 60 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Branching: Conditional jumps

MIPS Datapath Design 3
Operation
PC+4 from Instruction fetching datapath
Adder

Result Jump
2-bit destination
left shifting

3
Reg. to Operation
read 1
comp
REGISTERS
Instruction Operand 1
Reg. to
read 2 Zero Jump decision
Reg. to
write ALU
Operand 2

WriteReg

16 32
Sign
Extension

Comparison:
▶ a subtraction is performed, so ALU’s Zero output is used to check jump
condition
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 60 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Branching: Conditional jumps

MIPS Datapath Design 3
Operation
PC+4 from Instruction fetching datapath
Adder

Result Jump
2-bit destination
left shifting

3
Reg. to Operation
read 1
comp
REGISTERS
Instruction Operand 1
Reg. to
read 2 Zero Jump decision
Reg. to
write ALU
Operand 2

WriteReg

16 32
Sign
Extension

Effective jump address:

▶ PC-relative with signed offset: (PC+4)+4*offset
▶ 16-bit offset is extended to 32 bits and shifted left 2 bits
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 60 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Unconditional jumps
MIPS Datapath Design

j L1

6 bits 26 bits

J-Type with pseudo-direct addressing: j L1.

Substitutes the 28 least significant bits in PC with the 26 least
significant bits in the instruction code left-shifted 2 bits.
No additional hardware needed.

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CPU Design: Datapath and Control MIPS Datapath Design

Full MIPS Datapath Design

Final Datapath: Compound of the different elements needed to

process each instruction
Each one of the 5 steps in Instr. Cycle will need a specific clock cycle
Within an Instr. Cycle, a functional unit can be reused if it’s used in
different clock cycles
▶ Different memories or memory ports for accessing instructions and
operands are not needed since they are fetched in different cycles.
▶ ALU is used for computing next instruction address (PC+4 or jump
address) instead of specific Adders.
Data needed in next cycles are stored in regs or mem
▶ Within an Instr. Cycle, data needed in posterior cycles is stored in
temporary regs.
▶ Data needed for next instructions is stored in a storage element visible
to programmer (Register file, PC or Memory).

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 62 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full MIPS Datapath Design

Final Datapath: Compound of the different elements needed to

process each instruction
Each one of the 5 steps in Instr. Cycle will need a specific clock cycle
Within an Instr. Cycle, a functional unit can be reused if it’s used in
different clock cycles
▶ Different memories or memory ports for accessing instructions and
operands are not needed since they are fetched in different cycles.
▶ ALU is used for computing next instruction address (PC+4 or jump
address) instead of specific Adders.
Data needed in next cycles are stored in regs or mem
▶ Within an Instr. Cycle, data needed in posterior cycles is stored in
temporary regs.
▶ Data needed for next instructions is stored in a storage element visible
to programmer (Register file, PC or Memory).

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 62 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full MIPS Datapath Design

Final Datapath: Compound of the different elements needed to

process each instruction
Each one of the 5 steps in Instr. Cycle will need a specific clock cycle
Within an Instr. Cycle, a functional unit can be reused if it’s used in
different clock cycles
▶ Different memories or memory ports for accessing instructions and
operands are not needed since they are fetched in different cycles.
▶ ALU is used for computing next instruction address (PC+4 or jump
address) instead of specific Adders.
Data needed in next cycles are stored in regs or mem
▶ Within an Instr. Cycle, data needed in posterior cycles is stored in
temporary regs.
▶ Data needed for next instructions is stored in a storage element visible
to programmer (Register file, PC or Memory).

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 62 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath
High-level design ⇒ See complete datapath

Instruction Read
Register Reg. 1 Read
Memory A

REGISTERS
P Address Read Data 1
C Reg. 2 ALU
Instructions ALU
or Data Write output
Reg. 1 Read
Data B
Memory Write Data 2
Data Register Data

Just one ALU instead of 1 ALU + 2 additional Adders

A unified Memory to store both data and instructions
Temporary registers after each functional unit to store output until
being used in next cycle

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 63 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath
High-level design ⇒ See complete datapath

Instruction Read
Register Reg. 1 Read
Memory A

REGISTERS
P Address Read Data 1
C Reg. 2 ALU
Instructions ALU
or Data Write output
Reg. 1 Read
Data B
Memory Write Data 2
Data Register Data

ALU operations:
▶ Instruction fetching: Add PC+4.
▶ Data transfer instructions: computation of effective address to access
data.
▶ R-Type instructions: Arithmetic-logic operations.
▶ Conditional jumps:
⋆ Jump condition evaluation.
⋆ Computation of destination address to jump
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 63 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath
High-level design ⇒ See complete datapath

Instruction Read
Register Reg. 1 Read
Memory A

REGISTERS
P Address Read Data 1
C Reg. 2 ALU
Instructions ALU
or Data Write output
Reg. 1 Read
Data B
Memory Write Data 2
Data Register Data

Temporary registers:
▶ Instruction Register (IR) and Memory Data Register (MDR):
⋆ Storage for instructions and data read from memory, respectively.
▶ A and B Registers: operands read from Register File (bank of registers).
▶ ALU Output
▶ IR needs a Write control signal, since it keeps content for multiple
cycles.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 63 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath
High-level design ⇒ See complete datapath

Instruction Read
Register Reg. 1 Read
Memory A

REGISTERS
P Address Read Data 1
C Reg. 2 ALU
Instructions ALU
or Data Write output
Reg. 1 Read
Data B
Memory Write Data 2
Data Register Data

Multiplexers are needed to select inputs!

▶ Source of memory addresses to access memory:
⋆ ALU output (access to data)
⋆ PC (access to instructions)
▶ Destination register (Write Reg.1) :
⋆ R-Type instructions: rd (bits 11–15).
⋆ I-Type instructions (loads): rt (bits 16–20).
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 63 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath
High-level design ⇒ See complete datapath

Instruction Read
Register Reg. 1 Read
Memory A

REGISTERS
P Address Read Data 1
C Reg. 2 ALU
Instructions ALU
or Data Write output
Reg. 1 Read
Data B
Memory Write Data 2
Data Register Data

Multiplexers are needed to select inputs!

▶ Data to write:
⋆ From Memory (data loading)
⋆ From ALU (aritmethic-logic operation)
▶ First ALU input:
⋆ A Register (data access and arithmetic-logic instruction)
⋆ PC (instruction fetching and jumps)
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 63 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath
High-level design ⇒ See complete datapath

Instruction Read
Register Reg. 1 Read
Memory A

REGISTERS
P Address Read Data 1
C Reg. 2 ALU
Instructions ALU
or Data Write output
Reg. 1 Read
Data B
Memory Write Data 2
Data Register Data

Multiplexers are needed to select inputs!

▶ Second ALU input:
⋆ B Register (arithmetic-logic instruction and conditional jump)
⋆ Constant 4 (PC increase)
⋆ Extended offset field (data transfer)
⋆ Extended and shifted offset field (conditional jump)

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 63 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath
High-level design ⇒ See complete datapath

Instruction Read
Register Reg. 1 Read
Memory A

REGISTERS
P Address Read Data 1
C Reg. 2 ALU
Instructions ALU
or Data Write output
Reg. 1 Read
Data B
Memory Write Data 2
Data Register Data

Multiplexers are needed to select inputs!

▶ Address of next instruction to execute:
⋆ ALU Result: PC+4
⋆ ALU Output: Jump address computed by ALU for conditional jumps
⋆ Jump address included in instruction for unconditional jumps

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 63 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

⇒ Come back to high level datapath

⇒ See full datapath with signals

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 64 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: Instruction Fetching

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Memory is addressed using PC.

2 Memory read operation is performed and instruction is written in IR.
3 PC update: PC’s address is incremented 4 bytes.
4 Edge-triggered: PC increase is not visible until next cycle.
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 65 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: Arithmetic-logic Instructions

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Read regs addressed by rs and rt and store in temporary regs A and B.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 66 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: Arithmetic-logic Instructions

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Read regs addressed by rs and rt and store in temporary regs A and B.

2 ALU operation: execution of computation specified by opcode and storage
of result in ALU Output.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 66 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: Arithmetic-logic Instructions

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Read regs addressed by rs and rt and store in temporary regs A and B.

2 ALU operation: execution of computation specified by opcode and storage
of result in ALU Output.
3 Write result in register specified by rd.
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 66 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: lw instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Read base reg and store content in temp reg A.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 67 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: lw instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Read base reg and store content in temp reg A.

2 Compute effective mem. address: base reg. + offset

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 67 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: lw instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Read base reg and store content in temp reg A.

2 Compute effective mem. address: base reg. + offset
3 Memory access and load data in MDR

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 67 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: lw instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Read base reg and store content in temp reg A.

2 Compute effective mem. address: base reg. + offset
3 Memory access and load data in MDR
4 Write data from memory in Register File
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 67 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: sw instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Concurrent load base register (temp reg A) and data to store (temp reg B)

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 68 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: sw instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Concurrent load base register (temp reg A) and data to store (temp reg B)
2 Compute effective mem. address: base reg. + offset

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 68 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: sw instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Concurrent load base register (temp reg A) and data to store (temp reg B)
2 Compute effective mem. address: base reg. + offset
3 Memory access and save date from reg B (mem write)
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 68 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: beq instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Load of both operands to compare (temp regs A and B). Concurrently,

computation of effective jump address

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 69 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: beq instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

1 Load of both operands to compare (temp regs A and B). Concurrently,

computation of effective jump address
2 Subtract operands. ALU’s Zero signal is used to enable PC writing. If
condition is true PC is written with the new value.
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 69 / 115
CPU Design: Datapath and Control MIPS Datapath Design

Full Datapath: j instruction

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

Just one step: write PC with jump address

Two cycles are enough to execute it, but we will use 3 to simplify control
unit (as we will see)
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 70 / 115
CPU Design: Datapath and Control Datapath design: Control signals

Control signals

Control signals for writing: PC, IR, Memory, Register File

Control signal for reading memory
MUXes:
▶ 2 inputs: 1 control line
▶ 4 inputs: 2 control lines
ALU control logic
▶ ALUop + Instr. function code (R-Type instr.) = 3 control bits

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 71 / 115
CPU Design: Datapath and Control Datapath design: Control signals

Control signals
ALU Control Unit

ALUOp Funct. field Action ALU control lines

00 XXXXXX add 010
01 XXXXXX sub 110
10 100000 add 010
10 100010 sub 110
10 100100 AND 000
10 100101 OR 001
10 101010 slt 111

00 (add): Used for memory address computations: PC updates,

jumps and memory accesses (instructions lw, sw and beq).
01 (sub): Used in beq for performing comparison condition.
10 (funct. field): R-Type instructions: operations depends on
instruction function code.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 72 / 115
CPU Design: Datapath and Control Datapath design: Control signals

Control signals ⇒ Come back to full datapath without signals

PCWrite MemRead MemWrite IRWrite DestReg RegWrite ALUSrcA ALUSrcB PCSrc

0
I/D Mem2Reg 1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit ALU
Sign
shift Control
16 Ext. 32
left Unit
ALUop

ALUop, ALUSrcB and PCSrc are 2-bit signals

1-bit signals the rest
Only two registers need an specific write signal: IR and PC
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 73 / 115
CPU Design: Datapath and Control Datapath design: Control signals

Control signals
Datapath and Control Unit

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite Control ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0]
26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
4 1
Register Data u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit ALU
Sign
shift Control
Ext.
16 32 left Unit

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 74 / 115
CPU Design: Datapath and Control Control Unit Design

Control Unit Design

Control Unit is in charge of handling:

▶ Control signals to assert (set/unset) in every step
▶ Next step in the sequence
It’s a sync sequential system!
▶ Every state goes for a clock cycle and represents an step in the
instruction execution cycle.
Inputs: Instruction’s bits and internal control systems (eg. ALU Zero output).
Outputs: Control signals to activate

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 75 / 115
CPU Design: Datapath and Control Control Unit Design

Control Unit Design

Instruction Cycle: Sequential machine

First two states/stages are common to every instruction:

▶ Instruction fetching
▶ Instruction decoding
The rest depends on the type of instruction and its operands
After finishing with an instruction, the automaton recovers the initial
state to process next instruction.

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 76 / 115
CPU Design: Datapath and Control Control Unit Design

Control Unit Design

Actions required for every step in instruction cycle and high level graph

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 77 / 115
CPU Design: Datapath and Control Control Unit Design

Stage 1. Instruction Fetching

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 78 / 115
CPU Design: Datapath and Control Control Unit Design

Stage 1. Instruction Fetching

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
State 0 [15-0] u 3
MemRead
Memory 1x
ALUSrcA = 0 Data Reg. 2-bit
Sign ALU
ALUSrcB = 01 shift
Init ALUOp = 00
to State 1 16 Ext. 32
left
Control
Unit
I/D = 0
IRWrite
PCWrite
PCSrc = 00

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 78 / 115
CPU Design: Datapath and Control Control Unit Design

Stage 2. Instruction Decoding and Register Indexing

0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

Instruction is decoded
Some potentially useful tasks get ahead:
▶ Regs rt and rs are read and content load in A and B
GAC (Dpt.▶ Potential
Computer jump addressLesson
Engineering) is computed (beq)
4. The Processor Fundamentals of Computers 79 / 115
CPU Design: Datapath and Control Control Unit Design

Stage 2. Instruction Decoding and Register Indexing

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3
State 1
Memory 1x
Data Reg. 2-bit ALU
Sign
ALUSrcA = 0 shift
from State 0 to State ? 16 Ext. 32
left
Control
ALUSrcB = 11 Unit
ALUOp = 00

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 79 / 115
CPU Design: Datapath and Control Control Unit Design

Common states to every instruction

Instruction fetching and decoding

State 0
(Instruction fetch) State 1
(Instruction decode/Register fetch)
MemRead
ALUSrcA = 0
Init ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
I/D = 0 ALUOp = 00
IRWrite
PCWrite )
w' ) ic
= 's og (O
PCSrc = 00
(Op l p

(Op
) or ic- =
'j
= 'lw' m et ')

= 'b
(Op h
it
ar

eq')
=
( Op

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 80 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

Stage 3. Memory address computation
0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 81 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

Stage 3. Memory address computation

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3
State 2 (lw/sw)
Memory 1x
Data Reg. 2-bit ALU
Sign
ALUSrcA = 1 shift
from State 1 to State ? 16 Ext. 32
left
Control
ALUSrcB = 10 Unit
ALUOp = 00 select base reg.
select sign-extended
offset
ALU op: addition
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 81 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

lw stage 4. Memory acces (read)
0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 82 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

lw stage 4. Memory acces (read)

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3
State 3 (lw)
Memory 1x
Data Reg. 2-bit ALU
Sign
shift Control
16 Ext. 32
left
MemRead: memory read operation Unit

I/D = 1: mem addressed by data from ALU

MDR reg does NOT need control signal
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 82 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

lw stage 5. Write data from MDR in bank of registers
0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 83 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

lw stage 5. Write data from MDR in bank of registers

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3
State 4 (lw)
Memory 1x
Data Reg. 2-bit ALU
Sign RegWrite: write operation in Reg. File
shift Control
16 Ext. 32
left
Mem2Reg = 1: data to write
Unit comes from
mem.
DestReg = 0: dest. reg indexed by bits 16:20
of instruction (field rt)

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 83 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

sw stage 4. Storing data in memory (write)
0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 84 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

sw stage 4. Storing data in memory (write)

PCWriteCond State 5 (sw)

PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA MemWrite: memory write operation
Mem2Reg 0
RegWrite
I/D = 1: mem addressed by data from ALUM
IRWrite OPCODE DestReg 1
[31-26] u
-> Data from temp. regUncond.
2-bit 28 B is written
Jump [31-0] x
Instruction [25-0] 26
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit ALU
Sign
shift Control
16 Ext. 32
left Unit

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 84 / 115
CPU Design: Datapath and Control Control Unit Design

Memory access instructions (lw & sw)

State diagram From State 1
(Op = 'lw') or (Op = 'sw')
State 2

ALUSrcA = 1 Memory address

ALUSrcB = 10 computation
ALUOp = 00

(Op = 'lw') (Op = 'sw')

State 3 State 5

MemRead MemWrite
I/D = 1 I/D = 1
Memory Memory
access access

State 4
Memory read completion:
RegWrite write stage
Mem2Reg = 1 Return to
DestReg = 0 State 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 85 / 115
CPU Design: Datapath and Control Control Unit Design

Arithmetic-logic Instructions
Stage 3. Execution
0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 86 / 115
CPU Design: Datapath and Control Control Unit Design

Arithmetic-logic Instructions
Stage 3. Execution

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3
State 6 (arithmetic-logic)
Memory 1x
Data Reg. 2-bit ALU
Sign
shift Control
16 Ext. 32
left
ALUSrcA = 1: Reg A is ALU's 1st operand (rs) Unit

ALUSrcB = 00: Reg B is ALU's 2nd operand (rt)

ALUop = 10: Funct. code determines operation
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 86 / 115
CPU Design: Datapath and Control Control Unit Design

Arithmetic-logic Instructions
Stage 4. Execution
0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 87 / 115
CPU Design: Datapath and Control Control Unit Design

Arithmetic-logic Instructions
Stage 4. Execution

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0
M State 7 (arithmetic-logic)
2
x
[15-0] u 3

Memory 1x RegWrite: Write operation in Register file

Data Reg. 2-bit ALUcomes from ALU
Sign Mem2Reg
shift
= 0: Data to write
Ext. 32 Control
16 left output Unit
DestReg = 1: Destination register is indexed
by bits 11:15 of instruction

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 87 / 115
CPU Design: Datapath and Control Control Unit Design

Arithmetic-logic Instructions
State diagram
From State 1
(Op = arithmetic-logic)
State 6

ALUSrcA = 1
ALUSrcB = 00 Execution
ALUOp = 10

State 7
RegWrite R-Type completion:
Mem2Reg = 0
DestReg = 1
write result stage

Return to
State 0
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 88 / 115
CPU Design: Datapath and Control Control Unit Design

Conditional Jump Instructions (beq)

Stage 3. Comparison and PC new value
0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 89 / 115
CPU Design: Datapath and Control Control Unit Design

Conditional Jump Instructions (beq)

Stage 3. Comparison and PC new value

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr.
State 8 (beq) [15-0]
[15-11]
u Reg. 1 Read
ALU ALU
B 0 Result output
Data Instruction 1x Write Data 2 M
Comparison: Register Data 4 1
u
0 2
ALUSrcA = 1: Reg A is ALU's 1st operandInstr.
(rs) M x
[15-0] u 3
ALUSrcB = 00: Reg B is ALU's 2nd operand (rt)
Memory 1x

ALUop = 01: Subtraction Data Reg. 2-bit ALU

Sign
shift Control
16 Ext. 32
PC new value: left Unit
PCWriteCond: Sets PC Write signal if
ALU's Zero = 1
PCSrc = 01: PC new value is in ALU output
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 89 / 115
CPU Design: Datapath and Control Control Unit Design

Conditional Jump Instructions (beq)

State diagram

From State 1
(Op = 'beq')
State 8
ALUSrcA = 1 Branch completion
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSrc = 01

Return to
State 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 90 / 115
CPU Design: Datapath and Control Control Unit Design

Unconditional Jump Instructions (jump)

Stage 3. Write new PC
0
1
M
Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x
Data Reg. 2-bit
Sign
shift
16 Ext. 32
left

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 91 / 115
CPU Design: Datapath and Control Control Unit Design

Unconditional Jump Instructions (jump)

Stage 3. Write new PC

PCWriteCond
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg 0
RegWrite
M
IRWrite OPCODE DestReg 1
[31-26] Uncond. u
Instruction [25-0] 26 2-bit 28 Jump [31-0] x
shift 2
left

PC [31-28]
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
State 3 (j) Instr. 0
M 2
x
[15-0] u 3

Memory 1x
PCWrite: sets unconditional PCData
write
Reg. 2-bit ALU
Sign
PCSrc = 10: new PC is obtained by shifting 16 Ext. 32
shift Control
left
left 2 bits Instruction's 0:25 bits and Unit
concatenating with 4 most significant bits
from PC

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 91 / 115
CPU Design: Datapath and Control Control Unit Design

Unconditional Jump Instructions (jump)

State diagram

From State 1
(Op = 'j')
State 9

PCWrite
Jump completion
PCSrc = 10

Return to
State 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 92 / 115
CPU Design: Datapath and Control Control Sequential System

Complete Finite State Machine

State 0
MemRead State 1
ALUSrcA = 0
Init ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
I/D = 0 ALUOp = 00
IRWrite
PCWrite )
w') ic
= 's og (O
PCSrc = 00
(Op -l p

(Op
) or c =
ti 'j
= 'lw' me ')

= 'b
(Op th
i
ar

eq')
=
p
State 2 (O
State 6 State 8 State 9
ALUSrcA = 1 Memory address
ALUSrcB = 10 computation ALUSrcA = 1 Branch completion
ALUSrcA = 1
ALUSrcB = 00 PCWrite
ALUOp = 00 Execution
ALUSrcB = 00 PCSrc = 10
ALUOp = 01
ALUOp = 10
PCWriteCond
PCSrc = 01 Jump completion
(Op = 'lw') (Op = 'sw')

State 3 State 5
State 7
MemRead MemWrite
I/D = 1 I/D = 1 RegWrite R-Type completion:
Memory Memory Mem2Reg = 0
write result stage
access DestReg = 1
access

State 4
Memory read completion:
RegWrite write stage
Mem2Reg = 1
DestReg = 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 93 / 115
CPU Design: Datapath and Control Control Sequential System

Finite State Machine

Control Unit Implementation

Two main implementation alternatives:

Hardwired Control Unit Using sequential logic elements: logic gates,
flip-flops, etc.
Microprogram Control Unit The Finite State Machine is represented
as a control program: sequence of microinstructions
stored in a special control memory.
✓ more simple structure
✓ easier to debug, modify and improve
✓ better options to complex systems, and now clearly the
most popular

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 94 / 115
Microprogram Control Unit

Outline

1 Introduction
2 Instruction Set
3 MIPS: an example of RISC ISA
4 CPU Design: Datapath and Control
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 95 / 115
Microprogram Control Unit

Microprogram Control Unit

The Finite State Machine is implemented as a control program

Instructions in that control program are called microinstructions
Each microinstruction defines the set of control signals to
enable/disable in every specific state
The set of microinstructions is called microprogram
The microprogram is stored in a ROM

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 96 / 115
Microprogram Control Unit

Microprogram Control Unit

General overview
Operation code
Sequencer Datapath conditions
CLOCK

Sequencing: two main alternatives

Explicit: each microinstr. includes next

Control Memory
microinstruction’s address.
(ROM) Implicit: by default, next instructr. to
execute is next instructr. in memory.
⇒ Jump microinstr. allows control flow

Microinstruction Register
.......

control signals
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 97 / 115
Microprogram Control Unit

Sequencing
Let’s implement a microprogram Control Unit with explicit
sequencing for our subset of MIPS ISA.
Every finite state is transformed into a microinstruction.
Next microinstruction? Three possible actions:
▶ Increase current microinstruction address:
⇒ so next contiguous microinstruction
▶ Reset microprogram (set state to 0):
⇒ so jump to first microinstruction to start execution of a new instruction
▶ Choose next microinstruction as a function of current state and
instruction’s opcode being executed.
⋆ this operation is called ‘a dispatch’
⋆ ‘dispatch table’: table with the possible destination addresses
⋆ one ‘dispatch table’ is needed for each state with multiple destination
states
According to these possibilities, an additional set of control outputs
indicates what’s the next instruction to be executed (reset, next or
dispatch): AddrCtl
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 98 / 115
Microprogram Control Unit

Sequencing
Two Dispatch tables are needed for implementing our MIPS subset
Control Unit.
Two AddrCtl bits are needed to specify next microinstructions:

AddrCtl Action
0 (00) Set state to 0
1 (01) Dispatch with table 1
2 (10) Dispatch with table 2
3 (11) Use the incremented state

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 98 / 115
Microprogram Control Unit

Implementation
PCSrc (2)
ALUop (2)
ALUSrcA
ALUSrcB (2)
RegWrite
DestReg
Outputs PCWriteCond
PCWrite
Control Logic I/D
MemRead

(ROM) MemWrite Each control point from

Mem2Reg
IRWrite datapath corresponds with
a bit in microinstructions
AddrCtl (2)
Inputs ▶ 18-bit microinstr.
(16 control points +
1
4
2 2-bit AddrCtl)
▶ Control point could
Adder State Register
be codified to save
6 bits
Address select logic

Operation Code
Bits [31-26] from
instruction register
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 99 / 115
Microprogram Control Unit

Implementation
Logic for obtaining next microinstruction

ROM AddrCtl
Inputs

1
2

Adder State Register

MUX
3 2 1 0

Dispatch table 2 Dispatch table 1

Address
select logic
Operation Code
Bits [31-26] from
instruction register

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 100 / 115
Microprogram Control Unit

Implementation
Microprogram

PCWriteCond

ALUSrcB (2)

AddrCtl (2)
PCSrc (2)
ALUOp (2)
MemWrite

RegWrite
PCWrite

MemRead

IRWrite
Mem2Reg

ALUSrcA

DestReg
I/D
1 0 1 1 0 0 1 0 3 State 0
0 3 0 1 State 1
Mem1 0 2 1 2State 2
Lw2 1 1 3 State 3
1 1 0 0 State 4
Sw2 1 1 0 State 5
Rformat1 2 0 1 3 State 6
0 1 1 0 State 7
Beq1 1 1 1 0 1 0 State 8
Jump1 1 2 0 State 9

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 101 / 115
Microprogram Control Unit

Implementation
Microprogram and dispatch tables

PCWriteCond

ALUSrcB (2)

AddrCtl (2)
PCSrc (2)
ALUOp (2)
MemWrite

RegWrite
PCWrite

MemRead

IRWrite
Mem2Reg

ALUSrcA

DestReg
I/D
1 0 1 1 0 0 1 0 3 State 0
0 3 0 1 State 1
Mem1 0 2 1 2State 2
Lw2 1 1 3 State 3
1 1 0 0 State 4
Sw2 1 1 0 State 5
Rformat1 2 0 1 3 State 6
0 1 1 0 State 7
Beq1 1 1 1 0 1 0 State 8
Jump1 1 2 0 State 9
Opcode field Opcode name Value ⇐ Dispatch table 1
000000 R-format Rformat1
⇓ Dispatch table 2
000010 jmp Jump1
000100 beq Beq1 Opcode field Opcode name Value
100011 lw Mem1 100011 lw lw2
101011 sw Mem1 101011 sw sw2
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 101 / 115
Timing

Outline

1 Introduction
2 Instruction Set
3 MIPS: an example of RISC ISA
4 CPU Design: Datapath and Control
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 102 / 115
Timing

Timing
Clock cycle
Clock cycle must be at least as long as the longest operation in
datapath takes
Example:
Reg. RegFile Mem. ALU Mem.
Update Access Read Write Total
(5 ns) (10 ns) (25 ns) (15 ns) (30 ns)
Load instruction ✓ ✓ 30 ns
Decodification ✓ ✓ 20 ns
Computation ✓ ✓ 20 ns
Memory read ✓ ✓ 30 ns
Memory write ✓ ✓ 35 ns
Write register ✓ ✓ 15 ns
⇒ Clock cycle ≥ 35 ns
⇒ Instruction latency:
▶ lw: 175 ns (5 cycles)
▶ sw & A-L instructions: 140 ns (4 cycles)
▶ beq & j: 105 ns (3 cycles)
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 103 / 115
Exception Handling

Outline

1 Introduction
2 Instruction Set
3 MIPS: an example of RISC ISA
4 CPU Design: Datapath and Control
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 104 / 115
Exception Handling

Exceptions

Exception: Unexpected event while executing instructions in CPU

▶ eg. arithmetic overflow
▶ changes normal flow of instr. execution:
⋆ jump to execute managing code for exeption
⋆ return to normal flow
Actions to process an exception:
▶ Store address of instruction causing the exception in reg. EPC
(Exception Program Counter, 32-bit reg.)
▶ Transfer control to OS for taking the appropriate action
▶ OS decision: terminate the program or continue its execution by
returning control (EPC’s address)

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 105 / 115
Exception Handling

Exception Handling

Exception types in our MIPS subset:

▶ Undefined instruction
▶ Arithmetic overflow
OS’s routine to execute depends on exception type.
Cause register is used in MIPS to record the cause of the exception:
(1 bit)
▶ Cause = 1: undefined instruction
▶ Cause = 0: arithmetic overflow

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 106 / 115
Exception Handling

Modified Datapath
Exception Handling
CauseWrite
IntCause
PCWriteCond EPCWrite
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg RegWrite
IRWrite OPCODE DestReg 0
[31-26] Uncond. 1
M
26 2-bit 28 Jump [31-0] u
Instruction [25-0] 2
shift x
left 3

PC [31-28] 0xC0000000
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output EPC
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x 0 0
Data Reg. 2-bit
M
Sign ALU u Cause
shift Control
Ext. 32
16 left 1 1x
Unit

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 107 / 115
Exception Handling

Modified Datapath
Exception Handling
CauseWrite
IntCause
PCWriteCond EPCWrite
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg RegWrite
IRWrite OPCODE DestReg 0
[31-26] Uncond. 1
M
26 2-bit 28 Jump [31-0] u
Instruction [25-0] 2
shift x
left 3

PC [31-28] 0xC0000000
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output EPC
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x 0 0
Data Reg. 2-bit
M
Sign ALU u Cause
shift Control
Ext. 32
16 left 1 1x
Unit

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 107 / 115
Exception Handling

Exception processing
CauseWrite
IntCause
PCWriteCond EPCWrite
PCWrite PCSrc
I/D ALUop
MemRead ALUSrcB
MemWrite ALUSrcA
Mem2Reg RegWrite
OPCODE
IRWrite DestReg 0
[31-26] Uncond. 1
M
26 2-bit 28 Jump [31-0] u
Instruction [25-0] 2
shift x
left 3

PC [31-28] 0xC0000000
Instruction Read 0
P [25-21] Reg. 1 M
0
C M Read u

REGISTERS
Memory Instruction Read A
u Address Data 1
1x
ALU
[20-16] Reg. 2
1x Instructions 0 Zero
Instruction M Write
or Data Instr. ALU ALU
[15-0] u Reg. 1 Read
[15-11] B 0 Result output EPC
Data Instruction 1x Write Data 2 M
Register Data 4 1
u
Instr. 0 2
M x
[15-0] u 3

Memory 1x 0 0
Data Reg. 2-bit
M
Sign ALU u Cause
shift Control
Ext. 32
16 left 1 1x
Unit

1 Write 0 or 1 in Cause Reg.

2 Write address of affected instruction in EPC.
3 Load address of SO’s exception managing routine in SO.
GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 108 / 115
Exception Handling

Exception processing
New states in Control Automaton

State 10 State 11
IntCause = 0 IntCause = 1
CauseWrite CauseWrite
ALUSrcA = 0 ALUSrcA = 0
ALUSrcB = 01 ALUSrcB = 01
ALUOp = 01 ALUOp = 01
EPCWrite EPCWrite
PCWrite PCWrite
PCSrc = 11 PCSrc = 11

Return to State 0
Init new instruction

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 109 / 115
Exception Handling

Control Finite State Machine with Exception Managing

State 0
MemRead State 1
ALUSrcA = 0
Init ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
I/D = 0 ALUOp = 00
IRWrite
PCWrite )
w') ic
= 's og (O
PCSrc = 00
(Op -l p

(Op = 'b
) or c =
ti 'j
'lw' ')

(O
(Op
= me
th

p
i

=
ar

ot
eq')
=

he
p
State 2 (O State 9

r)
State 6 State 8
ALUSrcA = 1 Memory address Jump PCWrite
ALUSrcA = 1
ALUSrcB = 10 computation
ALUSrcA = 1 ALUSrcB = 00 completion PCSrc = 10
ALUOp = 00 Execution
ALUSrcB = 00 ALUOp = 01
Branch
ALUOp = 10 PCWriteCond
Ov PCSrc = 01 completion
(Op = 'lw') (Op = 'sw') er
fl
ow
State 3 State 5 !
State 10 State 11
State 7 IntCause = 0 IntCause = 1
MemRead MemWrite CauseWrite CauseWrite
I/D = 1 I/D = 1 RegWrite R-Type completion: ALUSrcA = 0 ALUSrcA = 0
Memory Memory Mem2Reg = 0 ALUSrcB = 01 ALUSrcB = 01
DestReg = 1
write result stage ALUOp = 01
access access ALUOp = 01
EPCWrite EPCWrite
PCWrite PCWrite
PCSrc = 11 PCSrc = 11
State 4
Memory read completion:
RegWrite write stage
Mem2Reg = 1
DestReg = 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 110 / 115
Exception Handling

Control Finite State Machine with Exception Managing

State 0
MemRead State 1
ALUSrcA = 0
Init ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
I/D = 0 ALUOp = 00
IRWrite
PCWrite )
w') ic
= 's og (O
PCSrc = 00
(Op -l p

(Op = 'b
r =
w') o
c 'j
= 'l ti ')

(O
(Op me
th

p
i

=
ar

ot
eq')
=

he
p
State 2 (O State 9

) r
State 6 State 8
ALUSrcA = 1 Memory address Jump PCWrite
ALUSrcA = 1
ALUSrcB = 10 computation
ALUSrcA = 1 ALUSrcB = 00 completion PCSrc = 10
ALUOp = 00 Execution
ALUSrcB = 00 ALUOp = 01
Branch
ALUOp = 10 PCWriteCond
Ov PCSrc = 01 completion
(Op = 'lw') (Op = 'sw') er
fl
ow
State 3 State 5 !
State 10 State 11
State 7 IntCause = 0 IntCause = 1
MemRead MemWrite CauseWrite CauseWrite
I/D = 1 I/D = 1 RegWrite R-Type completion: ALUSrcA = 0 ALUSrcA = 0
Memory Memory Mem2Reg = 0 ALUSrcB = 01 ALUSrcB = 01
DestReg = 1
write result stage ALUOp = 01
access access ALUOp = 01
EPCWrite EPCWrite
PCWrite PCWrite
PCSrc = 11 PCSrc = 11
State 4
Memory read completion:
RegWrite write stage
Mem2Reg = 1
DestReg = 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 110 / 115
Exception Handling

Control Finite State Machine with Exception Managing

State 0
MemRead State 1
ALUSrcA = 0
Init ALUSrcB = 01 ALUSrcA = 0
ALUOp = 00 ALUSrcB = 11
I/D = 0 ALUOp = 00
IRWrite
PCWrite )
w') ic
= 's og (O
PCSrc = 00
(Op -l p

(Op = 'b
r =
w') o
c 'j
= 'l ti ')

(O
(Op me
th

p
i

=
ar

ot
eq')
=

he
p
State 2 (O State 9

) r
State 6 State 8
ALUSrcA = 1 Memory address Jump PCWrite
ALUSrcA = 1
ALUSrcB = 10 computation
ALUSrcA = 1 ALUSrcB = 00 completion PCSrc = 10
ALUOp = 00 Execution
ALUSrcB = 00 ALUOp = 01
Branch
ALUOp = 10 PCWriteCond
Ov PCSrc = 01 completion
(Op = 'lw') (Op = 'sw') er
fl
ow
State 3 State 5 !
State 10 State 11
State 7 IntCause = 0 IntCause = 1
MemRead MemWrite CauseWrite CauseWrite
I/D = 1 I/D = 1 RegWrite R-Type completion: ALUSrcA = 0 ALUSrcA = 0
Memory Memory Mem2Reg = 0 ALUSrcB = 01 ALUSrcB = 01
DestReg = 1
write result stage ALUOp = 01
access access ALUOp = 01
EPCWrite EPCWrite
PCWrite PCWrite
PCSrc = 11 PCSrc = 11
State 4
Memory read completion:
RegWrite write stage
Mem2Reg = 1
DestReg = 0

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 110 / 115
Exception Handling

Control Finite State Machine

Microprogramming

Modifications to microprogram control unit:

▶ 2 new microinstructions (states 10 and 11)
▶ Modified dispatch table 1
▶ New dispatch table 3 for bifurcation at State 6
▶ 22-bit microinstructions (instead of 18-bit):
⋆ AddrCtl can take now 5 different values: extension to 3 bits
⋆ New control signals: IntCause, CauseWrite, EPCWrite

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 111 / 115
Exception Handling

Microprogram Control Unit

Dispatch tables

Table: Dispatch table 2

Table: Dispatch table 1 Opcode field Opcode name Value

100011 lw lw2
Opcode field Opcode name Value 101011 sw sw2
000000 R-format Rformat1
000010 jmp Jump1
000100 beq Beq1
100011 lw Mem1 Table: Dispatch table 3 (new)
101011 sw Mem1
other other Nodef1 Overflow signal Value
0 Arit3
1 Ov3

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 112 / 115
Exception Handling

Microprogram Control Unit

PCWriteCond

ALUSrcB (2)

AddrCtl (3)

CauseWrite
PCSrc (2)
ALUOp (2)
MemWrite

RegWrite

IntCause

EPCWrite
PCWrite

MemRead

IRWrite
Mem2Reg

ALUSrcA

DestReg
1 I/D
0 1 1 0 0 1 0 3 State 0
0 3 0 1 State 1
Mem1 0 2 1 2 State 2
Lw2 1 1 3 State 3
1 1 0 0 State 4
Sw2 1 1 0 State 5
Rformat1 2 0 1 4 State 6
Arit3 0 1 1 0 State 7
Beq1 1 1 1 0 1 0 State 8
Jump1 1 2 0 State 9
Ov3 1 3 1 1 0 0 0 1 1 State 10
Nodef1 1 3 1 1 0 0 1 1 1 State 11

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 113 / 115
Final Remarks

Outline

1 Introduction
2 Instruction Set
3 MIPS: an example of RISC ISA
4 CPU Design: Datapath and Control
5 Microprogram Control Unit
6 Timing
7 Exception Handling
8 Final Remarks

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 114 / 115
Final Remarks

Improving performance in current processors

Two main ways of increasing CPU performance:

▶ Improving technology of integrated circuits and components, reducing
time needed to executed the different steps what makes it possible to
reduce clock cycle.

▶ Enhance processor design to improve ILP (Instruction-level parallelism)

⋆ Pipelining
⋆ Superscalar processors

Additionally: Include more processors/cores (multi-processor/multi-core

systems)
▶ Improving TLP and DLP (Task-level parallelism and Data-level
parallelism).

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 115 / 115
Final Remarks

Improving performance in current processors

Two main ways of increasing CPU performance:

▶ Improving technology of integrated circuits and components, reducing
time needed to executed the different steps what makes it possible to
reduce clock cycle.

▶ Enhance processor design to improve ILP (Instruction-level parallelism)

⋆ Pipelining
⋆ Superscalar processors

Additionally: Include more processors/cores (multi-processor/multi-core

systems)
▶ Improving TLP and DLP (Task-level parallelism and Data-level
parallelism).

GAC (Dpt. Computer Engineering) Lesson 4. The Processor Fundamentals of Computers 115 / 115