Design for Testability

-Built in Self Test

Sources:
i. Book :Bushnell and Agrawal
ii. NPTEL Lecture notes
iii. Book: Miron Abramovici
Introduction
Ø Here, we shall discuss the VLSI testing, only from the context where the circuit needs to
be put to a “test mode” for validating that it is free of faults.
• Circuits tested OK are shipped to the customers with the assumption that they would
not fail within their expected life time; this is called off-line testing
• However, this assumption does not hold for modern day ICs, based on deep sub-
micron technology, because they may develop failures even during operation within
expected life time.
Ø To cater to this problem sometimes redundant circuitry are kept on-chip which replace
the faulty parts.
Ø Testing a circuit every time before they startup, is called Built-In- Self-Test (BIST).
BIST
Built-in self-test is the capability of a circuit (chip, board, or system) to test itself.
BIST represents a merger of the concepts of built-in test (BIT) and self-test, and has
come to be synonymous with these terms. Forms of Testing (BIST)

BIST techniques can be classified into two categories as shown

Ø In on-line BIST, testing occurs during normal functional operating

conditions; i.e., the circuit under test (CUT) is not placed into a test
mode where normal functional operation is locked out.
Concurrent on-line BIST is a form of testing that occurs
simultaneously with normal functional operation.
• This form of testing is usually accomplished using coding
techniques or duplication and comparison etc.
In nonconcurrent on-line BIST, testing is carried out while a system is
in an idle state.
• This is often accomplished by executing diagnostic software
routines (macrocode) or diagnostic firmware routines
(microcode). The test process can be interrupted at any time so
that normal operation can resume.
BIST
Off-line BIST: It deals with testing a system when it is not carrying out its normal functions. Systems, boards,
and chips can be tested in this mode.
• This form of testing is also applicable at the manufacturing, field, depot, and operational
levels.
• Often Off-line testing is carried out using on-chip or on-board test-pattern generators (TPGs) and
output response analyzers (ORAs) or microdiagnostic routines.
• Off-line testing does not detect errors in real time, i.e., when they first occur, as is possible with
many on-line concurrent BIST techniques.
q Functional off-line BIST: deals with the execution of a test based on a functional description of the CUT
and often employs a functional, or high-level, fault model. Normally such a test is implemented as
diagnostic software or firmware.
q Structural off-line BIST: deals with the execution of a test based on the structure of the CUT. An explicit
structural fault model may be used. Fault coverage is based on detecting structural faults. Usually tests
are generated and responses are compressed using some form of an Linear Feedback Shift registers
(LFSR)
BIST
Several types of test structures are used in BIST circuits

Ø Two common TPG circuits exist. A pseudorandom

pattern generator (PRPG) is a multioutput device
normally implemented using an LFSR,
Ø While a shift register pattern generator (SRPG) is a
single-output autonomous LFSR.
Ø For simplicity a PRPG represent a "parallel random-
pattern generator," and a SRPG represent "serial random-
pattern generator."
Ø Two common ORA circuits also exist.
• One is a multiple-input signature register (MISR),
• The other a single-input signature register (SISR).
Both are implemented using an LFSR
BIST

Ø A digital system is tested and diagnosed during its lifetime on numerous

occasions.
Ø Test and diagnosis must be quick and have very high fault coverage. One way
to ensure this is to specify test as one of the system functions, so it becomes
self-test.
Ø At the highest level of systems test, the testing function is frequently
implemented in software. Its most common use is e.g in maintenance and
repair diagnostics.
BIST
Ø Although this approach provided flexibility, it also had disadvantages:
i. The fault coverage and the diagnostic resolution of those software-implemented
tests were not as high as desired.
ii. The diagnostic resolution may be poor because the software must test parts that are
difficult to test, and therefore it may not effectively determine which part is at fault.
iii. Also, software tests can be long, slow, and expensive to develop.
Ø Therefore, it becomes increasingly attractive to build the self-test function into the
hardware.
Ø It is also most effective to consider testing as early in the design cycle as possible.
Otherwise, costly prototyping turns (cycles of redesign and refabrication of the prototype)
result, and these lead to schedule slippages for product introduction.
BIST

Ø With properly designed BIST, the cost of added test hardware will be ‘more than
balanced’ by the benefits in terms of reliability and the reduced maintenance cost
Ø Thus, these benefits, rather than the cost, can be passed on to the customers.
Ø The savings from BIST include:
• Reduced test generation effort at all levels,
• Reduced test effort at chip through system levels,
• Improved system-level maintenance and repair,
• Improved component repair.
BIST

It seems that customer is paying for the BIST hardware, however ultimately, It may not
be true
• Slight increase in chip cost due to BIST, say (1-2%), may overall decrease the
manufacturing and test costs (upto 5-10%) e.g. via decrease in other materials
and other test costs needed earlier. So, overall chip cost may be still be
decreased while increasing the reliability and self-maintenance of the system
Basic architecture of BIST
Basic architecture of BIST
Hardware Test Pattern Generator:

•This module generates the test patterns required to sensitize the faults and propagate the
effect to the outputs

• As the test pattern generator is a circuit (not equipment) its area is limited.
•So storing and then generating test patterns obtained by ATPG algorithms on the CUT
(discussed in earlier topics) using the hardware test pattern generator is not feasible.

•Instead, the test pattern generator is basically a type of register which generates
random patterns which act as test patterns. The main emphasis of the register design is to
have low area yet generate as many different patterns (from 0 to 2n-1, if there are n flip-flops
in the register) as possible.
Basic architecture of BIST

• Input Mux: This multiplexer is to allow normal inputs to the circuit when it is operational and
test inputs from the pattern generator when BIST is executed. The control input of the
multiplexer is fed by a central test controller.

• Output response compactor: Output response compacter performs lossy compression of the
outputs of the CUT. The output of the CUT is to be compared with the expected response
(called golden signature)

• Similar to the situation for test pattern generator, expected output responses cannot be
stored explicitly in a memory and compared with the responses of the CUT. So, CUT response
needs to be compacted such that comparisons with expected responses (golden signatures)
become simpler in terms of area of the memory that stores the golden signatures.
Basic architecture of BIST

ROM: Stores golden signature that needs to be compared with the compacted CUT response.

Comparator: Hardware to compare compacted CUT response and golden signature (from
ROM).

Test Controller: Circuit to control the BIST. Whenever an IC is powered up (signal start BIST is
made active) the test controller starts the BIST procedure. Once the test is over, the status line is
made high if fault is found. Following that, the controller connects normal inputs to the CUT via
the multiplexer, thus making it ready for operation.
BIST
There are some chip-level testability problems:
1. There is an extremely high and still increasing logic-to-pin ratio on the chip. This
increasingly makes it harder to accurately observe signals on the device, which is
essential for testing.
2. VLSI devices are increasingly dense and faster with sub-micron feature sizes. There are
increasingly long test-pattern generation and test application times.
3. Prohibitive amounts of test data must be stored in the automatic test equipment (ATE)
BIST
There are some chip-level testability problems (Continued…):
4. There is increasing difficulty in performing at-speed (rated clock) testing using external
ATE. For clock rates approaching 1 GHz, at-speed testing with an ATE is very expensive
due to pin inductance and high tester pin costs.
5. Designers are unfamiliar with the gate-level structure of their designs, since logic is now
automatically synthesized from the VHDL or Verilog hardware description languages.
This compounds the problem of testability insertion.
6. There is a lack of skilled test engineers.
BIST
Ø Complexity: One unfortunate property of large VLSI circuits is that testing cannot be easily
partitioned.
• Testing is a global problem
• BIST provides a way to hierarchically decompose the electronic system-under-test, so
this allows sub-assemblies to be first run through a BIST cycle, and if there are no
faults, then boards in the system are run through a BIST cycle. Finally, if there are no
board faults, then the entire system can be run through a BIST cycle.

Ø Quality. Typical quality requirements are 98% single stuck-fault coverage or 100%
interconnect fault coverage. The goal of testing at many companies is a low reject ratio. In
huge systems, this is attainable only through design for testability (DFT), and BIST is the
preferred form of DFT.
BIST
Ø Test Generation Problems. It is difficult to carry a test stimulus involving hundreds of chip inputs
through many layers of circuitry to the chip-under-test, and then convey the test result back through
the many circuit layers to an observable point. BIST localizes testing, which eliminates these
problems.
Ø Test Application Problems: In the past, in-circuit testing (ICT) used a bed-of- nails fixture
customized for the PCB-under-test:
• However, ICT is not effective unless the PCB is removed from the system, so it is not
helpful in system-level diagnosis.
• Also, surface-mount technology (SMT) components are often mounted densely on both
sides of the board, and the PCB wire pitch is also too small for accurate probing of the back
of the board by the bed of-nails tester. Therefore, ICT is no longer a solution.
BIST

At all three levels, BIST reduces testing costs.

Ø If we do not use on-chip BIST hardware, there is a huge initial capital cost for the ATE, but there is no
recurring chip area cost on each chip for test hardware.
Ø If, instead, we provide BIST hardware, then the need for a very high-speed ATE is eliminated, except to
test the wires from the circuit pins to the Input MUX, and from the circuit outputs to the output pins.
Ø Therefore, BIST doing all stuck-fault and transition delay fault testing, ATE only to provide DC
command signals to tell the microprocessor to perform BIST and finally, again ATE to read out the
success or failure DC signal for BIST from a circuit pin
BIST

Metrics for Evaluating BIST

BIST
Metrics for Evaluating BIST
BIST
Metrics for Evaluating BIST

BIST does cost reduction for diagnosis and repair

BIST

Ø BIST solves these problems by eliminating expensive ATE, and BIST also lets us use the same
tests and test circuits that are used at the system level.
Ø With BIST, there can be virtually unlimited circuit access via test points designed into the circuit
through scan chains, resulting in an electronic bed-of-nails.
Ø Another advantage of BIST is that the testing capability grows with the VLSI technology, whereas
with external testing, the test capability always lags behind the VLSI technology capability.
• Logic gates and transistors are relatively cheap compared to the labour needed to develop test
programs, the cost of automatic test equipment, and the cost of real time for the tests to be run
on production chips with ATE
BIST

Ø An additional benefit of BIST is lower test development cost, because BIST can be
automatically added to a circuit with a CAD tool.
Ø Also, BIST generally provides a 90 to 95% fault coverage, and even 99% in exceptional
cases. The test engineer need no longer worry about back-driving problems of in-circuit
test (where electrical stimuli provided to the middle of the circuitry damage outputs of
logic gates), or how much memory is available in the ATE.
Basic architecture of BIST
Hardware pattern generator
There are two main targets for the hardware pattern generator—
(i)low area and
(ii) pseudo-exhaustive pattern generation (i.e., generate as many

different patterns from 0 to 2 -1 as possible, if there are n

n

flip-flops in the register).

Linear feedback shift register (LFSR) pattern generator is most
commonly used for test pattern generation in BIST because it satisfies
the above two conditions.
There are basically two types of LFSRs,
(i). Standard LFSR
(ii) Modular LFSR.
Standard LFSRs
+ + + +
hn-1 hn-2 h1
h2

DFF DFF DFF DFF

Xn-1 Xn-2 X1 X0

hn-1 hn-2 h1
h2
DFF DFF DFF DFF

D Q D Q D Q D Q
Xn-1 Xn-2 X1
X0

A properly-designed LFSR can generate as a near-exhaustive set of patters, as it can cycle through
distinct 2n -1 states (except 0s is all flip-flops). Such a properly designed LFSR is known as a
maximal length LFSR.
Standard LFSRs
This LFSR in terms of the matrix can be written as X (t +1) = TS X (t) .
Standard LFSRs

Leaving behind the first column and the last row TS is an identity matrix; this indicates that
X 0 gets input from X1 , X1 gets input from X 2 and so on. Finally, the first element in the last
row is 1 to indicate that Xn-1 gets input from X 0 . Other elements of the last row are the tap
points h1,h2 ,... hn-2 ,hn-1 . The value of hi = 1, (1 £ i £ n -1) , indicates that output of flip-flop X i
provides feedback to the linear XOR function. Similarly, the value of hi = 0, (1 £ i £ n -1) ,
indicates that output of flip-flop X i does not provide feedback to the linear XOR function.
Standard LFSR: Example

It may be noted that output of flip-flop X 2 provides feedback to the XOR network, while
flip-flop X1 does not; so h1 = 0 and h2 = 1 . The characteristic polynomial of the LFSR is
f (x) = 1+ x 2 + x3 .
Standard LFSR: Example

So, the LFSR generates 7 patterns (excluding all 0s) after which a pattern is repeated. It may be noted that
this LFSR generates all patters (except all 0s) which are generated by a 3 bit counter, however, the area of
the LFSR is much lower compared to a counter. In a real life scenario, the number of inputs of a CUT is
of the order of hundreds. So LFSR has minimal area compared to counters (of order of hundreds).
Modular LFSRs

hn-1
h1 h2
DFF DFF
DFF DFF
+ + +
X0
X1 Xn-2 Xn-1

h1 DFF h2 hn-1
DFF DFF DFF

D D D D Q
Q Q Q
X0 X1 Xn-2 Xn-1

The difference in modular LFSR compared to standard LFSR is due to the positions of the XOR gates in the
feedback function; in modular LFSR XOR gates are in between adjacent flip-flops. Modular LFSR works
faster than standard LFSR, because it has at most one XOR gate between adjacent flip-flops, while there can
be several levels of XOR gates in the feedback of standard LFSR.
Modular LFSRs
In modular LSFR the output of any flip-flop may or may not participate in the XOR
function; if output of any flip-flop X i say, provides input to the XOR gate which feeds the

input of flip-flop Xi+1 then corresponding tap point hi is 1. In the circuit representation of

hi =1, then there is an XOR gate from output of flip-flop X i to input of flip-flop Xi+1 ; else

output of flip-flop X i is directly fed to input of flip-flop Xi+1 .

Modular LFSRs
This LFSR given the matrix can be written as X (t +1) = TS X (t) . In this

case X 0 (t +1) = Xn-1 (t) , which implies that Xn-1 directly feedbacks X 0 .
X1(t +1) = X 0 (t) + h1Xn-1 (t) , which implies that depending on h1 =0 (or 1),

input to X1 is X 0 (or X 0 XORed with output of Xn-1 ). Similar logic

holds for inputs to all flip-flops from X1 to Xn-1 .

This LFSR can also be described by the characteristic polynomial:

f (x) = 1+ h x + h x 2 + ...h x n-2 + h x n-1 + x n
1 2 n-2 n-1
Modular LFSRs: Example

DFF h3
DFF DFF DFF

D D D D Q
Q Q Q
X0 X1 X2 X3

The characteristic polynomial of the LFSR is f (x) = 1+ x3 + x 4 .

If the initial values of the flip-flops are X 0 = 1, X 1 = 0, X 2 = 0, X 3 = 0

Modular LFSRs: Example

Now, the question arises, whether any LFSR would generate all 2n -1 patters? The
answer is no. Only for a few characteristic polynomials the LFSR is maximal length; such
polynomials are called primitive polynomials (List of such polynomials can be found in
Bardell et al.

P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom

Techniques. New York: John Wiley and Sons, Inc., 1987.
Basic architecture of BIST
Hardware response compactor

•Expected output (i.e., golden response) of the CUT cannot be sorted explicitly in a
memory and compared with response obtained from the CUT.

In other words, in BIST, it is necessary to compress the large number of CUT responses to a manageable size that
can be stored in a memory and compared. In response compaction, sometimes it may happen that the compacted
response of the CUT under normal and failure conditions are same. This is called aliasing during compaction.

•Simple techniques to compress CUT responses namely

(i) number of 1s in the output and
(ii) transition count at the output.

•Other complex techniques like LFSR based compaction, multiple input signature register based compaction,
built-in logic observer based compaction etc.
Number of 1s compaction
•Number of 1s compaction, is a very simple technique where we count the number of
ones in the output responses from the CUT.

X0 1001110
0001100
X1 0011101
0001000

X2 0111010
Number of 1s = 1

(a) Normal Circuit

1001110
X0 0001100
X1 0011101
0001100
X2 0111010 1111111
Number of 1s = 2
s-a-1

h2 (b) Circuit with s-a-1 fault

DFF DFF DFF

D Q D Q D Q
X2 X1
X0

X2 X1 X0
Number of 1s compaction
•It may be noted that 7 patterns (non-similar) were generated by the LFSR, which when given as input to
the CUT generates output as 0001000, making number of 1s as 1.

•The same circuit with s-a-1 fault--When the same inputs are given to the CUT the output is 0001100,
making number of 1s as 2.

•So fault can be detected by the compaction as there is difference in number of 1s at the output of the
CUT for the given input patterns.

•In other words, for the input patterns (from the LFSR), “number of 1s” based compaction is not aliasing.
It may be noted that corresponding to the input patterns, value of 1 is stored (as golden signature) in the
memory which is compared with compacted response of the CUT.
Number of 1s compaction
0000100

X0 1001110 1000101
X1 0011101 0000110
X2 0111010
Number of 1s = 2
1100010
0000010

(a) Normal Circuit

1111101 1000100

X0 1001110 1000101
X1 0011101 1000100
s-a-1
X2 0111010
Number of 1s = 2
0000000
0000000

(b) Circuit with s-a-fault

Number of 1s compaction

The CUT generates output as 0000110, making number of 1s as 2.

The same circuit with s-a-1 fault--When the same inputs are given to the CUT the
output is 1000100, making number of 1s as 2.

So fault cannot be detected by the compaction; the number of 1s at the output of the
CUT for the given input patterns is same under normal and s-a-1 conditions. In other
words, for the input patterns (from the LFSR), “number of 1s” based compaction is
aliasing.
Transition count response compaction
•In this method of response compaction the number of transitions from 0 to 1 and 1 to 0 at
outputs of the CUT are counted.

•The CUT generates output as 0001000, making transition count as 2; in the output sequence
there is a transition from 0 to 1 and then from 1 to 0.
•The same circuit with s-a-1 fault. When the same inputs are given to the CUT the output is
0001100, making transition count as 2.
•So fault cannot be detected by the compaction.

X0 1001110
0001100
X1 0011101
0001000

X2 0111010
Transition Count = 2

(a) Normal Circuit

1001110
X0 0001100
X1 0011101
0001100
1111111
X2 0111010

s-a-1 Transition Count = 2

(a) Circuit with s-a-1 fault

Transition count response compaction

0000100

X0 1001110 1000101
X1 0011101 0000110
X2 0111010
Transition Count = 2
1100010
0000010

(a) Normal Circuit

1111101 1000100

X0 1001110 1000101
X1 0011101 1000100
s-a-1
X2 0111010
Transition Count = 3
0000000
0000000

(b) Circuit with s-a-fault

Questions and Answers
Question: In BIST how do we know which LFSR is to be used pattern generation?
Answer:
Ø Firstly, (obviously) the width of the LFSR is same as that of the number of inputs of the circuit.
Ø Secondly, the characteristic polynomial of the LFSR should be primitive polynomial. This ensures that the LFSR
generates all possible patterns (except all 0s).
Ø Thirdly, the seed will decide the sequence of patterns. By fault simulation the test patterns can be
decided.
Ø Following that a proper compaction technique with minimal aliasing property for the circuit needs to be
chosen.
Ø Then the seed is to be chosen in a manner so that the required test patterns among all the patterns generated
by the LFSR should be generated initially.
• In other words, the seed should be chosen such that patterns of LFSR which do not test any faults (or
any new faults compared to previous patterns) should be generated at latter phases.
Ø When all the required patterns have been generated and all faults have been tested the LFSR can be stopped
(without requirement to generate the full cycle of patterns).
Questions and Answers

Question: Why LFSR cannot have all 0 state?

Answer:
If the seed is all 0 state, then the LFSR will be stuck at all 0 state as the feedback logic is
XOR gates.
Thank You