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EC 311 Microprocessor

This document provides information about the architecture and instruction set of an 8-bit microprocessor. It describes the central processing unit, memory components, registers, instruction format, and examples of different instruction types including data transfer, arithmetic, logic, branching, and machine control instructions. It also includes a table showing the machine cycles and signals involved in executing different types of instructions.
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© © All Rights Reserved
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0% found this document useful (0 votes)
20 views

EC 311 Microprocessor

This document provides information about the architecture and instruction set of an 8-bit microprocessor. It describes the central processing unit, memory components, registers, instruction format, and examples of different instruction types including data transfer, arithmetic, logic, branching, and machine control instructions. It also includes a table showing the machine cycles and signals involved in executing different types of instructions.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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I

(Perfinal)
I/0

Acu Registere I
- . . .

w
T
-> System
Bus

Central Unit
Memory
Ram/Rlum
menstruction
Sets A-accumulatin

· MVI
me

L
A 324
,

00ll
Op Code

3EH (0011 1110)



0010
-ht/re
it

are -

-
at

Shyt
leat

In
2
registers (16
.
bit)
- Styte
ene

#
B 2050M
,

2 (-opcode 2005 I
D
,

45 stule

ene
INR A


Lode
ID-OP

2005 r
45 stule

+stan37T
= 55. e
-

2005 r

(Exe I Ive)
A Instruction
- Cycle-
.

L Tstates
*
cycle- -Ine Cycl
machine =

↓ A
Ates
-
44
-/ -4 - 4-S
-
↳- - -


machine lyde .
7654321 O
D Flag ->

S2 Al P LY
B C

D E

I L

SP

PL
-is 8 tit date
·

Capy Instructions ·
MVIB YEH ↳ B

[
,

·
MOV B A A- B
Louddate to
,
-

LXI B 20504 16Litdal-B


registen
·

· OUT 014 D- Output

·
IN O7H Input -D

LDA 20SON 16 it ->


D
E
·

STD 20504 A - 16 tit

3
·
LDAX B(RD Be A

·
STAX B(Rp) D - B
-

↳ anyfur BCADE
·
Arithmetic Instruction- ·

ADD B Accumulaten +B

10010011 ·
ADI 324 324+ Daumubarm
1011 0111 ·
ADD M
-
0100 101
·
SUB C D-C
0011 010 1
SUI 7 FH
IIII
·

11
01
·
SUB M
7 F

S
INRA innement
ofRegister
·

content
.

not aut Cy ·

DCR D Decrement

INRX

DCRX
·
Logic and bit manipulation-
·

3
·
AND B BID
-

·
ANI Stit 8Lit & D

I
·
ORA B

·
ORI 8Lit

Sa
· XRDR Exclusive OR .

·
XRI 8- tit

·
CP it Gene

·
Branch Instruction-

IMP 250 4 changefreguan Sep to


specified/6-lit
·

.
adde
-

· Oplagis Let
if

·
J2 20804- " "
= a .
-
.

·
JNZ2070K - e Reset .

JNC
-
M2T-halt
pousing& wait
·

· NOp- Noderation hufum .


Mo e Cycles : Star Signal consal Signal
I01in Si S⑧
OP Code
fetch O I I RD = 0

memay Read O I O D =
0
-

Men 0 0 I WR
=

0
by write
-

Intercept Acknowledge I I I INTD = 0

Halt

E
I O

3
O

Mald 2 x X -> RD R =
Z
,
,

- -

Reset TriState 2 X X I NTD


-
= 1

ALE-adde Lach Enable .


T T2 T3 54
OPede Lett
->
CLK --

VIII
A15

e
-204 - --
A8
A=

AO
--------
05 H

a en
Folte
RI
-
D, 8B4

Oe
mul 2memlos
MVI C
INRC
,
6 FH 2
O
Mov A D ! S =
1
11 =

1
0
2 = 0
,
P =
1AC =

ADD C I

out OH A
2
B -

654
-

B
Mat I
A -
974

24 0 = 0 110 0101
I 11I
101 1
100 1
011 1
1001

C = 0 1010
- 304 MVl B, 304
B
394
(e 34H MVI ,,
MON Do

SUB C

Cut Part I

HLT
brIN CY

I
2000 opcode JL
2001 PORTI

S
JNC
2002 opcode b out
J2
2003 PORTZ
JNZ
2004 IMP IP
-M
200s :
2005
IPE
JPO
Load BH ATH in D E add numbers
registe resp and
·

, ,

if Sum in ger then FF4 displ oi at awport 0


.

else Su 11 I I
diskhery -
/
1001 1011
1010 0111

MVI D , 9B4 Il
-
4 2
, o

MVL E &74
,
2000 obsoch MUID
MOV A, D
2001 9BH
ADD E 2002 obsee MVIE
2003 A7
JNL SKIP 2004 obeach MOVD
2005 D

MV1 A M
,
Ol 2006 onherdeADDE
2007 JNC (2010)
SKIP
-On : 2008 of code for MVIA
2009 01M
HLT 2010 out -

2011 oon
2012 rect
to add
·
write
lotyles of Dava Stad in men los
stating at a given
achers and Sum
diskay
,

2050

LXB

LDAX
,
ZOSOH

B
i
2039
INRXB
ADD
O
I6 Dava stred memol XXSOH-XX5F
hyss of in at

Heckofdeve to
transport entime new mem Loc .

Starting atXXI
salS MVl B, 16H DCRB SO
-
-

MVl A oor END

St
,
52
LXIM XXSOH
,
LX B XXzon END : HLT
,
-> LDAX m
;
STDX B ;
INRXM
IWRXB
M - XX50

6 A
Fo
B L3 XX70 Iz
↓--- d WR
-

STDX -
I/pBuffer ↳
IOlm+D

Memory Interfacing -emt


-

-
Addres
Line
->

Bitten a
-Emm
-
-

WR
Do-iwi

4x4- (bit)

no-of Registers
STE
-
obs on
111
Fo
-
1sI
l I

/
Os O20 , 00
and I of
·

zno's Uk6 EPROM no 8K6 Ram with 8005


up
-

Alkrate to IC's
Binaryarchers
·

& 15 mumay
I Al
-

=>
- .
N N
Als
An
11 A12
All
-
- -

Dis

-
-

A Do Do
gInbDIIIIII OSSEFE

5 F F F

4k6 - -
O - 2 FFF (3FFA)
001-11111111111
-

OS IFFF OFFF
,
000
0000 - I FFE
000

"
!

111
L
EOOO -FFP

2k6 RAM & 256X8 ROM

8K6RAM & IK6 Rom


Logic Operation :
ROTATE .

RLC ! Basse Acumuturn left

RAL
. -

Throug any
RRC : -
Right
camy
RAR ! - 11

10101010 (4 =
0 RLC

01010101 (7 = 1

55m ,
LY =
1

RAL

10101010 CY =
0

01010100 24 = 1

excr
10101001 24 =
0

194

Roteste
Right (Divby2)
Palate Let I must by2]

Logical : compone
·
CMP 8 CMP R/M
·
CPI CP1 80 it
-
-

CMP A<(R1m) 17 = 1 z = 0
,

A =

(R(m) (Y =
0
,
7 =

1
A >(R(m) (Y
=

z = 0
Sauter ↓
days-

L
time
2MAg
↳ mUl B
. FFr 7T 1410-5)
Loop : DLRB 45 + 1410 -

5)(25s)
JNZ(Loops 10/7 T
s
TEL + To257x0-5 +TMVI
7 x0.5
L

[10+) x255x0-5-310 -

5)]
-de
To tal time
1790-5MS
-
-
=1 .
8mS
>
-
(7 4) xo 5 7x0 5
(10+4)
.

j
-

x254 x
+
+

0

-
-

104a2
Last beauties
first 28 4 itrations
15
-
->
-
5
①) wite
dayprogram using Rp .
x

10 F
↳X B 2384

(L0+1)
,

6T
DLX B : Loop x 9001 x0
e
-

5)
Mov A C UT

5))
.

2T -
3(0 -

ORD B
JNZ LOOP 1017T + 10x0 5
.
B 38H
MVI ,

MVI , FER LOOP2

C 700P1
DCR
LOOP1
JNZ
DCR B

2002
JNz
C
MVI FF M 7 10- fr Gand True

n
, .

DCR : coop
= -
fu (and. Mul
JNZ LOOP 1017
Total time
f
2maG
=

SMS
T=
Detay KingRps ↑ 10X0 .
5

LX B , FFFF 10
(24x65535x0 5) .

i
Loop DCXB us

3
:

MOV AoC
ORA B 3X0 5
MS
.

- >

JNZ 200p
1017 en

423 US
786 5
.

843218
786 4mS.

00111000
25 +
2 + 23
Allay using 2-looks ->

S6(T4 +21x0
.

5)
MVI B 384 z

LOOP2 : MVIC
.

FF4
7
S6(17835 +
10 .

5)
,

2001 : DCR S 4
100 46mS
1017
=
.

INZLoop1
D(RB

INZ 100P2
Yolz
Zerotonin Gener :
Start !
MVIB OOH ,

Display OUT PORT#


:

3
(X1 5 16-bit count
,

LOOP : DCX i -

MOV A L
,
Detay
ORD H

JNZ LOOP

INR B
MOV A B
,

CPIODH

JNZ
Display
IZ Start
Scare Kube Generaten- MVl D
,
DDM

ROTATE : MOV A D y

3
,

RIC 4

MoVD D ↳
,
To2-46
BNI OL M 7 -

~
Out Part I 10

MVI Bocant 7
Delay DCR B
JNZ

IMP
Delay
Rotate
-My
107

Stack and Subroutine
(X) SP16-bit LX1 SP 2010
,

PUSH RP LX HL AABCh
,

POD RP PUSH H

Delay 1
POP H
LX) SP 24004
,

LXI H
,
21504

LX1 B 22804
,

Mov A m
,

Pus H

PUSH B
DUSH PSW

t
sw
pop
po H
1) Chen all
flags
2) Load accumulatio demonstrat sewo
flag
On that
in

not decix
in
affectedby
LX1 SP ,
24004 Mul D
,
ooM

ORD D
mus L 004
,

POS PSW
PUSH
POPU
POD PSW
MOV DoL
Mul D ,
ooM

PUSH PSW
OUT PORT I
POP ↳
MLF
MOU AsL

out PORTO
Subrentine -

cal-166 it addres
Ret

Interupts

I /See I
(XISP
EI
,
XX994 Delay : e

MVIA Don
(NXT(NT)
,


OUT PORT I
-

MVs C 01,

↳ Delay
call
Delay
D
INR
IMP NXTCNT
Port
Service : PUSH B

I
PUSH PSW
MVL BODM
MVID ,
00n

Floch : OUT PORTI


MVl C
,
01M
call
CMD
delay
DCR B

stlach
ae
VIC UND -su

II
veC CNB =

I I I I
7

-
6 =
S -

->
E
2 - -

y -

-
-
3 -

2 -


I
-

EinsBu
-

Ig El

- B (Satter
INTR
-

08
maskable
TRAD Juch - -

I
RST 7-5
masbable
RST 6 5
.

RSTS ·
5

INTR
INTD

Sensitive

level and edge
TRAP highest Priority
->
0024

RST 7 5

easasim]
003 (the edae
-

-maskable
RST 6 5
3
.

· os"

RST S 5
.

002C
zu
RST D ①

e
A

RST7 5
INTERRUPT
:


-

RECOGONIZED
O

RST
-

6 .

53
-

RSF
S5 .

A
TRAP
,
DE
El
2
-

-
AusReft)- ->

INTB retrigen
S
SIM
SOD SDE XXXR7-5 MSE M75 M6 5
.

M5 5
.


to

Serial Output
Date
Iguned
b Emork
mosk Set enable
bitz in
If / output speet
to Scial Output Data 7 8 .

Latch


all Ive in 8085
System
El
MUl A 08m
,

Sim
-> Mul A 184 -
,

SIM

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