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DLD Lab Main Project

This project involves designing a finite state machine to control a 7-segment display using a D flip-flop. The group will take the given state diagram and convert it into a state table and equations using K-maps. These equations will then be implemented in a logic diagram using software tools like Proteus. The logic diagram will be simulated to verify the circuit's functionality and observe its behavior. Overall, this systematic approach helps reliably design a digital system from a high-level state representation.

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131 views9 pages

DLD Lab Main Project

This project involves designing a finite state machine to control a 7-segment display using a D flip-flop. The group will take the given state diagram and convert it into a state table and equations using K-maps. These equations will then be implemented in a logic diagram using software tools like Proteus. The logic diagram will be simulated to verify the circuit's functionality and observe its behavior. Overall, this systematic approach helps reliably design a digital system from a high-level state representation.

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Project Title: Finite State Machine Control of Co

DLD PROJECT

anees DIGITAL LOGIC DESIGN


DLD PROJECT

Group Members:
M.Haroon Raza:RP21-EE-401
Nabeel Shaukat:RP21-EE-434
Anees Sohail:RP21-EE-419
IEECE ,University of the Punjab
Email : [email protected]
Email : [email protected]
Email : [email protected]

ABSTRACT:
inputs and # external Inputs).So after
Firstly we will make a state table
making table we will make equations
from state diagram by assuming the
by simplifying the next states
State Diagram values and also the
through K-map . From this we will get
Flip-Flop Input Values. So after
equations. After that we will make
Observing from the State-diagram it
logic Diagram on the modern
is founded that the state table to be
software tools like Proteus,Multisim
Constructed is of 6 bits (3 Flip-Flop
and Matlab etc
KEYWORDS:

Logic gates
Flip flop( d-flip flop)
7-segment display
555-timer/switch(pulse)

Page no# 01
DLD PROJECT

INTRODUCTION :
A seven segment display is a device made up of seven LEDs is an acronym for light
emitting diode .LEDs work very similarly to the normal diodes . the project given
is a type of finite state machine and it works like a code converter under some
condition and it’s state diagram is given by the instructor and then convert into
logical diagram using the concept of the k-map and it converts the binary form to
the digital form .
STATE DIAGRAM :

WORKING:
State Table:
Page no# 02
DLD PROJECT

input Present state Next state

D E F A B C A(t+1) B(t+1) C(t+1)


0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 1 0
0 0 0 0 1 1 0 1 1
0 0 1 0 0 0 0 0 0
0 0 1 0 1 0 0 1 0
0 0 1 0 1 1 0 1 1
0 1 0 0 0 1 0 0 1
0 1 0 1 0 0 1 0 0
0 1 0 1 0 1 1 0 1
0 1 1 0 1 0 0 1 0
0 1 1 0 0 0 0 0 0
0 1 1 0 1 1 0 1 1
1 0 0 1 0 0 1 0 0
1 0 0 0 0 1 0 0 1
1 0 0 1 0 1 1 0 1
1 0 1 1 0 1 1 0 1
1 0 1 1 0 0 1 0 0
1 0 1 0 0 1 0 0 1

Table no # 01
K-MAP SOLVING:
Page no# 03
DLD PROJECT

Solving Through K-MAP For B(t+1)

ABC

DEF

1 1 1
1 1 1

Table no # 01

B(t+1)=D’EF(A’B+A’B’C’) eq:(1)

Page no# 04
DLD PROJECT

Solving Through K-MAP For A(t+1)


ABC

DEF

1 1 1
1 1 1

Table no # 02
A(t+1) =DE’B’(A’C+A) eq:(2)
Solving Through K-MAP For C(t+1)
ABC

DEF

1 1 1

1 1 1

1 1 1

Page no# 05
DLD PROJECT

Table no # 03
C(t+1)=D’E’FA’B’C’+D’EFA’B’C’ eq:(3)
Equations:
now, by the using of equations , forming the logic diagram of the circit.

B(t+1)=D’EF(A’B+A’B’C’) eq:(1)
A(t+1) =DE’B’(A’C+A) eq:(2)
C(t+1)=D’E’FA’B’C’+D’EFA’B’C’ eq:(3)
Implementation:
There is a type of implementation form by the using of logic diagram;
1 : simulation (here the diagram is form on the modern tools such as multisims)

Simulation:
In this project, we will utilize Proteus to simulate and analyze a specific
circuit design, enabling us to observe its behavior, verify its
functionality, and gain insights into its performance characteristics.

Page no# 06
DLD PROJECT

Conclusion :
In this process, we started with a state diagram to capture the system's
behavior. We then transformed it into a state table, organizing the
states, inputs, and outputs. Using Proteus, we implemented a logic
circuit based on the state table. This allowed us to simulate and verify
the circuit's functionality. Overall, this systematic approach helped us
design a reliable digital system from a high-level representation.
Acknowledgement:
We express our gratitude and very thankful to the our guider and supporter for completing our
project:
 SIR Dr. UMER FAROOQ [ institute of the ELECTRICAL ENGINEERING
(University of the PUNJAB) ]

Page no# 07
DLD PROJECT

We express our gratitude and very thankful to the our following supporter for completing our
project:

References:

This project made references to the various sources for it’s completion:
1 : SIR Dr. UMER FAROOQ [ institute of the ELECTRICAL ENGINEERING (University of
the PUNJAB) ]
2 : ARTICLES ( lecture)
3 : BOOKS
 DIGITAL DESIGN by MORRIS MANO

Page no# 08

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