80C196KB

User’s Guide

November 1990

Order Number: 270651-003

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
80C196KB USER’S GUIDE
CONTENTS PAGE CONTENTS PAGE

1.0 CPU OPERATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1 6.0 Pulse Width Modulation Output

1.1 Memory Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2 (D/A) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33
1.2 CPU Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2 6.1 Analog Outputs ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35
1.3 Internal Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 2 7.0 TIMERS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
2.0 MEMORY SPACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 7.1 Timer1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
2.1 Register File ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 7.2 Timer2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
2.2 Special Function Registers ÀÀÀÀÀÀÀÀÀÀ 4 7.3 Sampling on External Timer
Pins ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36
2.3 Reserved Memory Spaces ÀÀÀÀÀÀÀÀÀÀÀ 8
7.4 Timer Interrupts ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
2.4 Internal ROM and EPROM ÀÀÀÀÀÀÀÀÀÀÀ 8
2.5 System Bus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 8.0 HIGH SPEED INPUTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38
8.1 HSI Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
3.0 SOFTWARE OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
8.2 HSI Status ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
3.1 Operand Types ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
8.3 HSI Interrupts ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
3.2 Operand Addressing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
8.4 HSI Input Sampling ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
3.3 Program Status Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
8.5 Initializing the HSI ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
3.4 Instruction Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
3.5 80C196KB Instruction Set 9.0 HIGH SPEED OUTPUTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40
Additions and Differences ÀÀÀÀÀÀÀÀÀÀÀÀ 22 9.1 HSO Interrupts and Software
3.6 Software Standards and Timers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41
Conventions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 9.2 HSO CAM ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
3.7 Software Protection Hints ÀÀÀÀÀÀÀÀÀÀÀ 23 9.3 HSO Status ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43
4.0 PERIPHERAL OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀ 23 9.4 Clearing the HSO and Locked
Entries ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43
4.1 Pulse Width Modulation Output
(D/A) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 9.5 HSO Precautions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
4.2 Timers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 9.6 PWM Using the HSO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
4.3 High Speed Inputs (HSI) ÀÀÀÀÀÀÀÀÀÀÀÀ 24 9.7 HSO Output Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
4.4 High Speed Outputs (HSO) ÀÀÀÀÀÀÀÀÀ 24 10.0 SERIAL PORT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
4.5 Serial Port ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 10.1 Serial Port Status and Control ÀÀÀÀÀ 47
4.6 A/D Converter ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 10.2 Serial Port Interrupts ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49
4.7 I/O Ports ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 10.3 Serial Port Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49
4.8 Watchdog Timer ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 10.4 Multiprocessor
Communications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51
5.0 INTERRUPTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27
5.1 Interrupt Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 11.0 A/D CONVERTER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51
5.2 Interrupt Priorities ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 11.1 A/D Conversion Process ÀÀÀÀÀÀÀÀÀÀ 53
5.3 Critical Regions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31 11.2 A/D Interface Suggestions ÀÀÀÀÀÀÀÀ 53
5.4 Interrupt Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31 11.3 The A/D Transfer Function ÀÀÀÀÀÀÀÀ 54
5.5 Interrupt Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32 11.4 A/D Glossary of Terms ÀÀÀÀÀÀÀÀÀÀÀÀ 58
80C196KB USER’S GUIDE
CONTENTS PAGE CONTENTS PAGE

12.0 I/O PORTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 60 15.0 EXTERNAL MEMORY

12.1 Input Ports ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 60 INTERFACING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 71
12.2 Quasi-Bidirectional Ports ÀÀÀÀÀÀÀÀÀÀ 60 15.1 Bus Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 71
12.3 Output Ports ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 62 15.2 Chip Configuration Register ÀÀÀÀÀÀÀ 72
12.4 Ports 3 and 4/AD0 – 15 ÀÀÀÀÀÀÀÀÀÀÀÀ 63 15.3 Bus Width ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 75
15.4 HOLD/HLDA Protocol ÀÀÀÀÀÀÀÀÀÀÀÀÀ 76
13.0 MINIMUM HARDWARE 15.5 AC Timing Explanations ÀÀÀÀÀÀÀÀÀÀÀ 78
CONSIDERATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 64
15.6 Memory System Examples ÀÀÀÀÀÀÀÀ 83
13.1 Power Supply ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 64
15.7 I/O Port Reconstruction ÀÀÀÀÀÀÀÀÀÀÀ 85
13.2 Noise Protection Tips ÀÀÀÀÀÀÀÀÀÀÀÀÀ 64
13.3 Oscillator and Internal Timings ÀÀÀÀ 64 16.0 USING THE EPROM ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 85
13.4 Reset and Reset Status ÀÀÀÀÀÀÀÀÀÀÀ 65 16.1 Power-Up and Power-Down ÀÀÀÀÀÀÀ 85
13.5 Minimum Hardware 16.2 Reserved Locations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 86
Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 68 16.3 Programming Pulse Width
Register (PPW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87
14.0 SPECIAL MODES OF
OPERATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 69 16.4 Auto Configuration Byte
Programming Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 88
14.1 Idle Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 69
16.5 Auto Programming Mode ÀÀÀÀÀÀÀÀÀÀ 88
14.2 Powerdown Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 69
16.6 Slave Programming Mode ÀÀÀÀÀÀÀÀÀ 90
14.3 ONCE and Test Modes ÀÀÀÀÀÀÀÀÀÀÀÀ 70
16.7 Run-Time Programming ÀÀÀÀÀÀÀÀÀÀÀ 92
16.8 ROM/EPROM Memory Protection
Options ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 93
16.9 Algorithms ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94
80C196KB USER’S GUIDE

The 80C196KB family is a CHMOS branch of the There are many members of the 80C196KB family, so
MCSÉ-96 family. Other members of the MCS-96 fami- to provide easier reading this manual will refer to the
ly include the 8096BH and 8098. All of the MCS-96 80C196KB family generically as the 80C196KB.
components share a common instruction set and archi- Where information applies only to specific components
tecture. However the CHMOS components have en- it will be clearly indicated.
hancements to provide higher performance at lower
power consumptions. To further decrease power usage, The 80C196KB can be separated into four sections for
these parts can be placed into idle and powerdown the purpose of describing its operation. A block dia-
modes. gram is shown in Figure 1-1. There is the CPU and
architecture, the instruction set, the peripherals and the
MCS-96 family members are all high-performance mi- bus unit. Each of the sections will be sub-divided as the
crocontrollers with a 16-bit CPU and at least 230 bytes discussion progresses. Let us first examine the CPU.
of on-chip RAM. They are register-to-register ma-
chines, so no accumulator is needed, and most opera-
tions can be quickly performed from or to any of the 1.0 CPU OPERATION
registers. In addition, the register operations can con-
trol the many peripherals which are available on the The major components of the CPU on the 80C196KB
chips. These peripherals include a serial port, A/D con- are the Register File and the Register/Arithmetic Log-
verter, PWM output, up to 48 I/O lines and a High- ic Unit (RALU). Communication with the outside
Speed I/O subsystem which has 2 16-bit timer/coun- world is done through either the Special Function Reg-
ters, an 8-level input capture FIFO and an 8-entry pro- isters (SFRs) or the Memory Controller. The RALU
grammable output generator. does not use an accumulator. Instead, it operates di-
rectly on the 256-byte register space made up of the
Typical applications for MCS-96 products are closed- Register File and the SFRs. Efficient I/O operations
loop control and mid-range digital signal processing. are possible by directly controlling the I/O through the
MCS-96 products are being used in modems, motor SFRs. The main benefits of this structure are the ability
controls, printers, engine controls, photocopiers, anti- to quickly change context, absence of accumulator bot-
lock brakes, air conditioner temperature controls, disk tleneck, and fast throughput and I/O times.
drives, and medical instrumentation.

270651 – 1

Figure 1-1. 80C196KB Block Diagram

1
80C196KB USER’S GUIDE

The CPU on the 80C196KB is 16 bits wide and con- REGISTER/ALU (RALU)
nects to the interrupt controller and the memory con-
troller by a 16-bit bus. In addition, there is an 8-bit bus Most calculations performed by the 80C196KB take
which transfers instruction bytes from the memory con- place in the RALU. The RALU, shown in Figure 1-2,
troller to the CPU. An extension of the 16-bit bus con- contains a 17-bit ALU, the Program Status Word
nects the CPU to the peripheral devices. (PSW), the Program Counter (PC), a loop counter, and
three temporary registers. All of the registers are 16-
bits or 17-bits (16 a sign extension) wide. Some of the
1.1 Memory Controller registers have the ability to perform simple operations
to off-load the ALU.
The RALU talks to the memory, except for the loca-
tions in the register file and SFR space, through the A separate incrementor is used for the Program Coun-
memory controller. Within the memory controller is a ter (PC) as it accesses operands. However, PC changes
bus controller, a four byte queue and a Slave Program due to jumps, calls, returns and interrupts must be han-
Counter (Slave PC). Both the internal ROM/EPROM dled through the ALU. Two of the temporary registers
bus and the external memory bus are driven by the bus have their own shift logic. These registers are used for
controller. Memory access requests to the bus control- the operations which require logical shifts, including
ler can come from either the RALU or the queue, with Normalize, Multiply, and Divide. The ‘‘Lower Word’’
queue accesses having priority. Requests from the and ‘‘Upper Word’’ are used together for the 32-bit
queue are always for instruction at the address in the instructions and as temporary registers for many in-
slave PC. structions. Repetitive shifts are counted by the 6-bit
‘‘Loop Counter’’.
By having program fetches from memory referenced to
the slave PC, the processor saves time as addresses sel- A third temporary register stores the second operand of
dom have to be sent to the memory controller. If the two operand instructions. This includes the multiplier
address sequence changes because of a jump, interrupt, during multiplications and the divisor during divisions.
call or return, the slave PC is loaded with a new value, To perform subtractions, the output of this register can
the queue is flushed, and processing continues. be complemented before being placed into the ‘‘B’’ in-
put of the ALU.
Execution speed is increased by using a queue since it
usually keeps the next instruction byte available. The Several constants, such as 0, 1 and 2 are stored in the
instruction execution times shown in Section 3 show RALU to speed up certain calculations. (e.g. making a
the normal execution times with no wait states added 2’s complement number or performing an increment or
and the 16-bit bus selected. Reloading the slave PC and decrement instruction.) In addition, single bit masks for
fetching the first byte of the new instruction stream bit test instructions are generated in the constant regis-
takes 4 state times. This is reflected in the jump taken/ ter based on the 3-bit Bit Select register.
not-taken times shown in the table.

When debugging code using a logic analyzer, one must 1.3 Internal Timing
be aware of the queue. It is not possible to determine
when an instruction will begin executing by simply The 80C196KB requires an input clock on XTAL1 to
watching when it is fetched, since the queue is filled in function. Since XTAL1 and XTAL2 are the input and
advance of instruction execution. output of an inverter a crystal can be used to generate
the clock. Details of the circuit and suggestions for its
use can be found in Section 13.
1.2 CPU Control
Internal operation of the 80C196KB is based on the
A microcode engine controls the CPU, allowing it to crystal or external oscillator frequency divided by 2.
perform operations with any byte, word or double word Every 2 oscillator periods is referred to as one ‘‘state
in the 256 byte register space. Instructions to the CPU time’’, the basic time measurement for all 80C196KB
are taken from the queue and stored temporarily in the operations. With a 12 MHz oscillator, a state time is
instruction register. The microcode engine decodes the 167 nanoseconds. With an 8 MHz oscillator, a state
instructions and generates the correct sequence of time is 250 nanoseconds, the same as an 8096BH run-
events to have the RALU perform the desired function. ning with a 12 MHz oscillator. Since the 80C196KB
Figure 1-2 shows the memory controller, RALU, in- will be run at many frequencies, the times given
struction register and the control unit. throughout this chapter will be in state times or
‘‘states’’, unless otherwise specified. A clock out

2
80C196KB USER’S GUIDE

270651– 2

Figure 1-2. RALU and Memory Controller Block Diagram

3
80C196KB USER’S GUIDE

(CLKOUT) signal, shown in Figure 1-3, is provided as 2.1 Register File

an indication of the internal machine state. Details on
timing relationships can be found in Section 13. Locations 00H through 0FFH contain the Register File
and Special Function Registers, (SFRs). The RALU
can operate on any of these 256 internal register loca-
tions, but code can not be executed from them. If an
attempt to execute instructions from locations 000H
through 0FFH is made, the instructions will be fetched
from external memory. This section of external memo-
ry is reserved for use by Intel development tools

The internal RAM from location 018H (24 decimal) to

0FFH is the Register File. It contains 232 bytes of
270651 – 3
RAM which can be accessed as bytes (8 bits), words
(16 bits), or double-words (32 bits). Since each of these
Figure 1-3. Internal Clock Waveforms locations can be used by the RALU, there are essential-
ly 232 ‘‘accumulators’’. This memory region, as well as
the status of the majority of the chip, is kept intact
2.0 MEMORY SPACE while the chip is in the Powerdown Mode. Details on
Powerdown Mode are discussed in Section 14.
The addressable memory space on the 80C196KB con-
sists of 64K bytes, most of which is available to the user Locations 18H and 19H contain the stack pointer.
for program or data memory. Locations which have These are not SFRs and may be used as standard RAM
special purposes are 0000H through 00FFH and if stack operations are not being performed. Since the
1FFEH through 2080H. All other locations can be stack pointer is in this area, the RALU can easily oper-
used for either program or data storage or for memory ate on it. The stack pointer must be initialized by the
mapped peripherals. A memory map is shown in Figure user program and can point anywhere in the 64K mem-
2-1. ory space. Operations to the stack cause it to build
down, so the stack pointer should be initialized to 2
bytes above the highest stack location, and must be
0FFFFH word aligned.
EXTERNAL MEMORY OR I/O
4000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY* 2.2 Special Function Registers
2080H
RESERVED Locations 00H through 17H are the I/O control regis-
2040H ters or SFRs. All of the peripheral devices on the
UPPER 8 INTERRUPT VECTORS 80C196KB (except Ports 3 and 4) are controlled
(NEW ON 80C196KB) through these registers. As shown in Figure 2-2, three
2030H
SFR windows are provided on the 80C196KB.
ROM/EPROM SECURITY KEY
2020H
RESERVED
Switching between the windows is done using the Win-
2019H dow Select Register (WSR) at location 14H in all of the
CHIP CONFIGURATION BYTE windows. The PUSHA and POPA instructions push
2018H and pop the WSR so it is easy to change between win-
RESERVED dows. Only three values may be written to the WSR, 0,
2014H 14 and 15. Other values are reserved for use in future
LOWER 8 INTERRUPT VECTORS parts and will cause unpredictable operation.
PLUS 2 SPECIAL INTERRUPTS
2000H
Window 0, the register window selected with WSR e 0,
PORT 3 AND PORT 4
1FFEH
is a superset of the one used on the 8096BH. As depict-
EXTERNAL MEMORY OR I/O
ed in Figure 2-3, it has 24 registers, some of which have
0100H different functions when read than when written. Reg-
INTERNAL DATA MEMORY - REGISTER FILE isters which are new to the 80C196KB or have changed
(STACK POINTER, RAM AND SFRS) functions from the 8096 are indicated in the figure.
EXTERNAL PROGRAM CODE MEMORY
0000H

Figure 2-1. 80C196KB Memory Map

4
80C196KB USER’S GUIDE

Listed registers
are present in
all three windows

16H 16H 16H

WSR WSR WSR
14H 14H 14H
INT MASK1/PEND1 INT MASK1/PEND1 INT MASK1/PEND1
12H 12H 12H
10H 10H 10H
0EH 0EH 0EH
TIMER2 T2 CAPTURE T2 CAPTURE
0CH 0CH 0CH
0AH 0AH 0AH
INT MASK/PEND INT MASK/PEND INT MASK/PEND
08H 08H 08H
06H 06H 06H
04H 04H 04H
02H 02H 02H
ZERO REG ZERO REG ZERO REG
00H 00H 00H
READ/WRITE PROGRAMMING WRITE/READ
WSR e 0 WSR e 14 WSR e 15

Figure 2-2. Multiple Register Windows

19H 19H
STACK POINTER STACK POINTER
18H 18H
17H *IOS2 17H PWMÐCONTROL
16H IOS1 16H IOC1
15H IOS0 15H IOC0
14H *WSR 14H *WSR
13H *INTÐMASK 1 13H *INTÐMASK 1
12H *INTÐPEND 1 12H *INTÐPEND 1
11H *SPÐSTAT 11H *SPÐCON
10H PORT2 10H PORT2 10H RESERVED**
0FH PORT1 0FH PORT1 0FH RESERVED**
0EH PORT0 0EH BAUD RATE 0EH RESERVED**
0DH TIMER2 (HI) 0DH TIMER2 (HI) 0DH *T2 CAPTURE (HI)
0CH TIMER2 (LO) 0CH TIMER2 (LO) 0CH *T2 CAPTURE (LO)
0BH TIMER1 (HI) 0BH *IOC2
WSR e 15
0AH TIMER1 (LO) 0AH WATCHDOG
09H INTÐPEND 09H INTÐPEND OTHER SFRS IN WSR 15 BECOME
08H INTÐMASK 08H INTÐMASK READABLE IF THEY WERE WRITABLE
IN WSR e 0, AND WRITABLE IF THEY
07H SBUF(RX) 07H SBUF(TX) WERE READABLE IN WSR e 0
06H HSIÐSTATUS 06H HSOÐCOMMAND
05H HSIÐTIME (HI) 05H HSOÐTIME (HI)
04H HSIÐTIME (LO) 04H HSOÐTIME (LO) 04H PPW
03H ADÐRESULT (HI) 03H HSIÐMODE WSR e 14
02H ADÐRESULT (LO) 02H ADÐCOMMAND
01H ZERO REG (HI) 01H ZERO REG (HI) *NEW OR CHANGED REGISTER
00H ZERO REG (LO) 00H ZERO REG (LO) FUNCTION FROM 8096BH
**RESERVED REGISTERS SHOULD NOT
WHEN READ WHEN WRITTEN
WSR e 0 BE WRITTEN OR READ

Figure 2-3. Special Function Registers

5
80C196KB USER’S GUIDE

Register Description
R0 Zero Register - Always reads as a zero, useful for a base when indexing and as a
constant for calculations and compares.
ADÐRESULT A/D Result Hi/Low - Low and high order results of the A/D converter
ADÐCOMMAND A/D Command Register - Controls the A/D
HSIÐMODE HSI Mode Register - Sets the mode of the High Speed Input unit.
HSIÐTIME HSI Time Hi/Lo - Contains the time at which the High Speed Input unit was triggered.
HSOÐTIME HSO Time Hi/Lo - Sets the time or count for the High Speed Output to execute the
command in the Command Register.
HSOÐCOMMAND HSO Command Register - Determines what will happen at the time loaded into the
HSO Time registers.
HSIÐSTATUS HSI Status Registers - Indicates which HSI pins were detected at the time in the HSI
Time registers and the current state of the pins. In Window 15 - Writes to pin
detected bits, but not current state bits.
SBUF(TX) Transmit buffer for the serial port, holds contents to be outputted. Last written value
is readable in Window 15.
SBUF(RX) Receive buffer for the serial port, holds the byte just received by the serial port.
Writable in Window 15.
INTÐMASK Interrupt Mask Register - Enables or disables the individual interrupts.
INTÐPEND Interrupt Pending Register - Indicates that an interrupt signal has occurred on one of
the sources and has not been serviced. (also INTÐPENDING)
WATCHDOG Watchdog Timer Register - Written periodically to hold off automatic reset every 64K
state times. Returns upper byte of WDT counter in Window 15.
TIMER1 Timer 1 Hi/Lo - Timer1 high and low bytes.
TIMER2 Timer 2 Hi/Lo - Timer2 high and low bytes.
IOPORT0 Port 0 Register - Levels on pins of Port 0. Reserved in Window 15.
BAUDÐRATE Register which determines the baud rate, this register is loaded sequentially.
Reserved in Window 15.
IOPORT1 Port 1 Register - Used to read or write to Port 1. Reserved in Window 15
IOPORT2 Port 2 Register - Used to read or write to Port 2. Reserved in Window 15
SPÐSTAT Serial Port Status - Indicates the status of the serial port.
SPÐCON Serial Port Control - Used to set the mode of the serial port.
IOS0 I/O Status Register 0 - Contains information on the HSO status. Writes to HSO pins
in Window 15.
IOS1 I/O Status Register 1 - Contains information on the status of the timers and of the
HSI.
IOC0 I/O Control Register 0 - Controls alternate functions of HSI pins, Timer 2 reset
sources and Timer 2 clock sources.
IOC1 I/O Control Register 1 - Controls alternate functions of Port 2 pins, timer interrupts
and HSI interrupts.
PWMÐCONTROL Pulse Width Modulation Control Register - Sets the duration of the PWM pulse.
INTÐPEND1 Interrupt Pending register for the 8 new interrupt vectors (also INTÐPENDING1)
INTÐMASK1 Interrupt Mask register for the 8 new interrupt vectors
IOC2 I/O Control Register 2 - Controls new 80C196KB features
IOS2 I/O Status Register 2 - Contains information on HSO events
WSR Window Select Register - Selects register window
Figure 2-4. Special Function Register Description

6
80C196KB USER’S GUIDE

Programming control and test operations are done in in Window 15. (Timer2 was read-only on the 8096.)
Window 14. Registers in this window that are not la- Registers which can be read and written in Window 0
beled should be considered reserved and should not be can also be read and written in Window 15.
either read or written.
Figure 2-4 contains brief descriptions of the SFR regis-
In register Window 15 (WSR e 15), the operation of ters. Detailed descriptions are contained in the section
the SFRs is changed, so that those which were read- which discusses the peripheral controlled by the regis-
only in Window 0 space are write-only and vice versa. ter. Figure 2-5 contains a description of the alternate
The only major exception to this is that Timer2 is read/ function in Window 15.
write in Window 0, and T2 Capture is read/write

ADÐCOMMAND (02H) Ð Read the last written command

ADÐRESULT (02H, 03H) Ð Write a value into the result register
HSIÐMODE (03H) Ð Read the value in HSIÐMODE
HSIÐTIME (04H, 05H) Ð Write to FIFO Holding register
HSOÐTIME (04H, 05H) Ð Read the last value placed in the holding register
HSIÐSTATUS (06H) Ð Write to status bits but not to HSI pin bits. (Pin bits are 1, 3, 5, 7)
HSOÐCOMMAND (06H) Ð Read the last value placed in the holding register
SBUF(RX) (07H) Ð Write a value into the receive buffer
SBUF(TX) (07H) Ð Read the last value written to the transmit buffer
WATCHDOG (0AH) Ð Read the value in the upper byte of the WDT
TIMER1 (0AH, 0BH) Ð Write a value to Timer1
TIMER2 (0CH, 0DH) Ð Read/Write the Timer2 capture register.
(Timer2 read/write is done with WSR e 0)
IOC2 (0BH) Ð Last written value is readable, except bit 7 (Note 1)
BAUDÐRATE (0EH) Ð No function, cannot be read
PORT0 (0EH) Ð No function, no output drivers on the pins
SPÐSTAT (11H) Ð Set the status bits, TI and RI can be set, but it will not cause an interrupt
SPÐCON (11H) Ð Read the current control byte
IOS0 (15H) Ð Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for
writes.
IOC0 (15H) Ð Last written value is readable, except bit 1 (Note 1)
IOS1 (16H) Ð Writing to this register will set the status bits, but not cause interrupts. Bits
6 and 7 are not functional.
IOC1 (16H) Ð Last written value is readable
IOS2 (17H) Ð Writing to this register will set the status bits, but not cause interrupts.
PWMÐCONTROL (17H) Ð Read the duty cycle value written to PWMÐCONTROL
NOTE:
1. IOC2.7 (CAM CLEAR) and IOC0.1 (T2RST) are not latched and will read as a 1 (precharged bus).

Being able to write to the read-only registers and vice-versa provides a lot of flexibility. One of the most useful
advantages is the ability to set the timers and HSO lines for initial conditions other than zero.

Figure 2-5. Alternate SFR Function in Window 15

7
80C196KB USER’S GUIDE

Within the SFR space are several registers and bit loca- change the contents of this location. Refer to Section
tions labeled ‘‘RESERVED’’. These locations should 15.2 for more information about bus contention during
never be written or read. A reserved bit location should CCB fetch.
always be written with 0 to maintain compatibility with
future parts. Values read from these locations may
change from part to part or over temperature and volt- FFFFH
EXTERNAL MEMORY
age. Registers and bits which are not labeled should be OR I/O
treated as reserved registers and bits. Note that the de- 4000H
fault state of internal registers is 0, while that for exter- INTERNAL PROGRAM
nal memory is 1. This is because SFR functions are STORAGE ROM/EPROM
typically disabled with a zero, while external memory is OR
EXTERNAL MEMORY 2080H
typically erased to all 1s.
RESERVED 2074H–207FH
VOLTAGE LEVELS 2072H–2073H
Caution must be taken when using the SFRs as sources
of operations or as base or index registers for indirect or SIGNATURE WORD 2070H–2071H

indexed operations. It is possible to get undesired re- RESERVED 2040H–206FH

sults, since external events can change SFRs and some INTERRUPT VECTORS 2030H–203FH
SFRs clear when read. The potential for an SFR to SECURITY KEY 2020H–202FH
change value must be taken into account when operat- RESERVED 2019H–201FH
ing on these registers. This is particularly important CHIP CONFIGURATION BYTE 2018H
when high level languages are used as they may not RESERVED 2015H–2017H
always make allowances for SFR-type registers. SFRs PPW 2014H
can be operated on as bytes or words unless otherwise INTERRUPT VECTORS 2000H–2013H
specified.
Figure 2-6. Reserved Memory Spaces
2.3 Reserved Memory Spaces Resetting the 80C196KB causes instructions to be
Locations 1FFEH and 1FFFH are used for Ports 3 and fetched starting from location 2080H. This location was
4 respectively, allowing easy reconstruction of these chosen to allow a system to have up to 8K of RAM
ports if external memory is used. An example of recon- continuous with the register file. Further information
structing the I/O ports is given in Section 15. If ports 3 on reset can be found in Section 13.
and 4 are not going to be reconstructed and internal
ROM/EPROM is not used, these locations can be
treated as any other external memory location. 2.4 Internal ROM and EPROM
When a ROM part is ordered, or an EPROM part is
Many reserved and special locations are in the memory
programmed, the internal memory locations 2080H
area between 2000H and 2080H. In this area the 18
through 3FFFH are user specified, as are the interrupt
interrupt vectors, chip configuration byte, and security
vectors, Chip Configuration Register and Security Key
key are located. Figure 2-6 shows the locations and
in locations 2000H through 207FH. Location 2014H
functions of these registers. The interrupts, chip config-
contains the PPW (Programming Pulse Width) regis-
uration, and security key registers are discussed in Sec-
ter. The PPW is used solely to program 87C196KB
tions 5, 16, and 17 respectively. With one exception, all
EPROM devices and is a reserved location on ROM
unspecified addresses in locations 2000H through
and ROMless devices.
207FH, including those marked ‘‘Reserved’’ are re-
served by Intel for use in testing or future products.
Instruction and data fetches from the internal ROM or
They must be filled with the Hex value FFH to insure
EPROM occur only if the part has ROM or EPROM,
compatibility with future devices. Location 2019H
EA is tied high, and the address is between 2000H and
should contain 20H to prevent possible bus contention
3FFFH. At all other times data is accessed from either
during the CCB fetch cycle. NOTE: 1. This exception
the internal RAM space or external memory and in-
applies only to systems with a 16-bit bus and external
structions are fetched from external memory. The EA
program memory. 2. Previously designed systems
pin is latched on RESET rising. Information on pro-
which do not experience bus contention don’t need to
gramming EPROMs can be found in Section 16.

8
80C196KB USER’S GUIDE

The 80C196KB provides a ROM/EPROM lock feature These are the same as the names for the general data
to allow the program to be locked against reading registers used in the 8086. It is important to note that in
and/or writing the internal program memory. In order the 80C196KB these are not dedicated registers but
to maintain security, code can not be executed out of merely the symbolic names assigned by the program-
the last three locations of internal ROM/EPROM if mer to an eight byte region within the on-board register
the lock is enabled. Details on this feature are in Sec- file.
tion 17.

3.1 Operand Types

2.5 System Bus
The MCS-96 architecture supports a variety of data
There are several modes of system bus operation on the types likely to be useful in a control application. To
80C196KB. The standard bus mode uses a 16-bit multi- avoid confusion, the name of an operand type is capital-
plexed address/data bus. Other bus modes include an ized. A ‘‘BYTE’’ is an unsigned eight bit variable; a
8-bit mode and a mode in which the bus size can dy- ‘‘byte’’ is an eight bit unit of data of any type.
namically be switched between 8-bits and 16-bits.

Hold/Hold Acknowledge (HOLD/HLDA) and Ready BYTES

signals are available to create a variety of memory sys- BYTES are unsigned 8-bit variables which can take on
tems. The READY line extends the width of the RD the values between 0 and 255. Arithmetic and relational
(read) and WR (write) pulses to allow access of slow operators can be applied to BYTE operands but the
memories. Multiple processor systems with shared result must be interpreted in modulo 256 arithmetic.
memory can be designed using HOLD/HLDA to keep Logical operations on BYTES are applied bitwise. Bits
the 80C196KB off the bus. Details on the System Bus within BYTES are labeled from 0 to 7, with 0 being the
are in Section 15. least significant bit.

3.0 SOFTWARE OVERVIEW WORDS

This section provides information on writing programs WORDS are unsigned 16-bit variables which can take
to execute in the 80C196KB. Additional information on the values between 0 and 65535. Arithmetic and
can be found in the following documents: relational operators can be applied to WORD operands
but the result must be interpreted modulo 65536. Logi-
MCSÉ-96 MACRO ASSEMBLER USER’S GUIDE cal operations on WORDS are applied bitwise. Bits
Order Number 122048 (Intel Systems) within words are labeled from 0 to 15 with 0 being the
Order Number 122351 (DOS Systems) least significant bit. WORDS must be aligned at even
byte boundaries in the MCS-96 address space. The least
MCSÉ-96 UTILITIES USER’S GUIDE significant byte of the WORD is in the even byte ad-
Order Number 122049 (Intel Systems) dress and the most significant byte is in the next higher
Order Number 122356 (DOS Systems) (odd) address. The address of a word is the address of
its least significant byte. Word operations to odd ad-
PL/M-96 USER’S GUIDE dresses are not guaranteed to operate in a consistent
Order Number 122134 (Intel Systems) manner.
Order Number 122361 (DOS Systems)

C-96 USER’S GUIDE SHORT-INTEGERS

Order Number 167632 (DOS Systems) SHORT-INTEGERS are 8-bit signed variables which
can take on the values between b 128 and a 127.
Throughout this chapter short sections of code are used
Arithmetic operations which generate results outside of
to illustrate the operation of the device. For these sec-
the range of a SHORT-INTEGER will set the overflow
tions it is assumed that the following set of temporary
indicators in the program status word. The actual nu-
registers has been declared:
meric result returned will be the same as the equivalent
AX, BX, CX, and DX are 16-bit registers. operation on BYTE variables.
AL is the low byte of AX, AH is the high byte.
BL is the low byte of BX
CL is the low byte of CX
DL is the low byte of DX

9
80C196KB USER’S GUIDE

INTEGERS LONG-INTEGERS can also be normalized. For these

operations a LONG-INTEGER variable must reside in
INTEGERS are 16-bit signed variables which can take the onboard register file of the 80C196KB and be
on the values between b 32,768 and a 32,767. Arith- aligned at an address which is evenly divisible by 4. A
metic operations which generate results outside of the LONG-INTEGER is addressed by the address of its
range of an INTEGER will set the overflow indicators least significant byte.
in the program status word. The actual numeric result
returned will be the same as the equivalent operation on LONG-INTEGER operations which are not directly
WORD variables. INTEGERS conform to the same supported can be easily implemented with two INTE-
alignment and addressing rules as do WORDS. GER operations. For consistency with Intel provided
software, the user should adopt the conventions for ad-
dressing LONG operands which are discussed in Sec-
BITS tion 3.6.
BITS are single-bit operands which can take on the
Boolean values of true and false. In addition to the nor-
mal support for bits as components of BYTE and 3.2 Operand Addressing
WORD operands, the 80C196KB provides for the di-
Operands are accessed within the address space of the
rect testing of any bit in the internal register file. The
80C196KB with one of six basic addressing modes.
MCS-96 architecture requires that bits be addressed as
Some of the details of how these addressing modes
components of BYTES or WORDS, it does not support
work are hidden by the assembly language. If the pro-
the direct addressing of bits that can occur in the MCS-
grammer is to take full advantage of the architecture, it
51 architecture.
is important that these details be understood. This sec-
tion will describe the addressing modes as they are han-
DOUBLE-WORDS dled by the hardware. At the end of this section the
addressing modes will be described as they are seen
DOUBLE-WORDS are unsigned 32-bit variables through the assembly language. The six basic address
which can take on the values between 0 and modes which will be described are termed register-di-
4,294,967,295. The MCS-96 architecture provides di- rect, indirect, indirect with auto-increment, immediate,
rect support for this operand type for shifts, as the divi- short-indexed, and long-indexed. Several other useful
dend in a 32-by-16 divide and the product of a 16-by-16 addressing operations can be achieved by combining
multiply, and for double-word comparisons. For these these basic addressing modes with specific registers
operations a DOUBLE-WORD variable must reside in such as the ZERO register or the stack pointer.
the on-board register file of the 80C196KB and be
aligned at an address which is evenly divisible by 4. A
DOUBLE-WORD operand is addressed by the address REGISTER-DIRECT REFERENCES
of its least significant byte. DOUBLE-WORD opera-
The register-direct mode is used to directly access a
tions which are not directly supported can be easily
register from the 256 byte on-board register file. The
implemented with two WORD operations. For consist-
register is selected by an 8-bit field within the instruc-
ency with Intel provided software the user should adopt
tion and the register address must conform to the oper-
the conventions for addressing DOUBLE-WORD op-
and type’s alignment rules. Depending on the instruc-
erands which are discussed in Section 3.5.
tion, up to three registers can take part in the calcula-
tion.
LONG-INTEGERS
LONG-INTEGERS are 32-bit signed variables which Examples
can take on the values between b 2,147,483,648 and
a 2,147,483,647. The MCS-96 architecture provides di-
ADD AX,BX,CX ; AX:4BX0CX
MUL AX,BX ; AX:4AX*BX
rect support for this data type for shifts, as the dividend INCB CL ; CL:4CL01
in a 32-by-16 divide and the product of a 16-by-16 mul-
tiply, and for double-word comparisons.

10
80C196KB USER’S GUIDE

INDIRECT REFERENCES

The indirect mode is used to access an operand by plac- file. The register which contains the indirect address is
ing its address in a WORD variable in the register file. selected by an eight bit field within the instruction. An
The calculated address must conform to the alignment instruction can contain only one indirect reference and
rules for the operand type. Note that the indirect ad- the remaining operands of the instruction (if any) must
dress can refer to an operand anywhere within the ad- be register-direct references.
dress space of the 80C196KB, including the register

Examples
LD AX,[AX] ; AX:4MEM WORD(AX)
ADDB AL,BL,[CX] ; AL:4BL0MEM BYTE(CX)
POP [AX] ; MEM WORD(AX):4MEM WORD(SP); SP:4SP02

INDIRECT WITH AUTO-INCREMENT REFERENCES

This addressing mode is the same as the indirect mode SHORT-INTEGERS the indirect address variable will
except that the WORD variable which contains the in- be incremented by one. If the instruction operates on
direct address is incremented after it is used to address WORDS or INTEGERS the indirect address variable
the operand. If the instruction operates on BYTES or will be incremented by two.

Examples
LD AX,[BX]0 ; AX:4MEM WORD(BX); BX:4BX02
ADDB AL,BL,[CX]0 ; AL:4BL0MEM BYTE(CX); CX:4CX01
PUSH [AX]0 ; SP:4SP12;
; MEM WORD(SP):4MEM WORD(AX)
; AX:4AX02

IMMEDIATE REFERENCES
This addressing mode allows an operand to be taken INTEGER operands the field is 16 bits wide. An in-
directly from a field in the instruction. For operations struction can contain only one immediate reference and
on BYTE or SHORT-INTEGER operands this field is the remaining operand(s) must be register-direct refer-
eight bits wide. For operations on WORD or ences.

Examples
ADD AX,#340 ; AX:4AX0340
PUSH #1234H ; SP:4SP12; MEM WORD(SP):41234H
DIVB AX,#10 ; AL:4AX/10; AH:4AX MOD 10

SHORT-INDEXED REFERENCES
In this addressing mode an eight bit field in the instruc- Since the eight bit field is sign-extended, the effective
tion selects a WORD variable in the register file which address can be up to 128 bytes before the address in the
contains an address. A second eight bit field in the in- WORD variable and up to 127 bytes after it. An in-
struction stream is sign-extended and summed with the struction can contain only one short-indexed reference
WORD variable to form the address of the operand and the remaining operand(s) must be register-direct
which will take part in the calculation. references.

Examples
LD AX,12[BX] ; AX:4MEM WORD(BX012)
MULB AX,BL,3[CX] ; AX:4BL*MEM BYTE(CX03)

11
80C196KB USER’S GUIDE

LONG-INDEXED REFERENCES

This addressing mode is like the short-indexed mode struction can contain only one long-indexed reference
except that a 16-bit field is taken from the instruction and the remaining operand(s) must be register-direct
and added to the WORD variable to form the address references.
of the operand. No sign extension is necessary. An in-

Examples
AND AX,BX,TABLE[CX] ; AX:4BX AND MEM WORD(TABLE0CX)
ST AX,TABLE[BX] ; MEM WORD(TABLE0BX):4AX
ADDB AL,BL,LOOKUP[CX] ; AL:4BL0MEM BYTE(LOOKUP0CX)

ZERO REGISTER ADDRESSING

The first two bytes in the register file are fixed at zero variable in a long-indexed reference. This combination
by the 80C196KB hardware. In addition to providing a of register selection and address mode allows any loca-
fixed source of the constant zero for calculations and tion in memory to be addressed directly.
comparisons, this register can be used as the WORD

Examples
ADD AX,1234[0] ; AX:4AX0MEM WORD(1234)
POP 5678[0] ; MEM WORD(5678):4MEM WORD(SP)
; SP:4SP02

STACK POINTER REGISTER ADDRESSING

The system stack pointer in the 80C196KB is accessed accessed by using the stack pointer as the WORD vari-
as register 18H of the internal register file. In addition able in an indirect reference. In a similar fashion, the
to providing for convenient manipulation of the stack stack pointer can be used in the short-indexed mode to
pointer, this also facilitates the accessing of operands in access data within the stack.
the stack. The top of the stack, for example, can be

Examples
PUSH [SP] ; DUPLICATE TOP OF STACK
LD AX,2[SP] ; AX:4NEXT TO TOP

ASSEMBLY LANGUAGE ADDRESSING MODES These features of the assembly language simplify the
programming task and should be used wherever possi-
The MCS-96 assembly language simplifies the choice of
ble.
addressing modes to be used in several respects:
Direct Addressing. The assembly language will choose
between register-direct addressing and long-indexed 3.3 Program Status Word
with the ZERO register depending on where the oper-
and is in memory. The user can simply refer to an oper- The program status word (PSW) is a collection of Boo-
and by its symbolic name: if the operand is in the regis- lean flags which retain information concerning the state
ter file, a register-direct reference will be used, if the of the user’s program. There are two bytes in the PSW;
operand is elsewhere in memory, a long-indexed refer- the actual status word and the low byte of the interrupt
ence will be generated. mask. Figure 3-1 shows the status bits of the PSW. The
PSW can be saved in the system stack with a single
Indexed Addressing. The assembly language will operation (PUSHF) and restored in a like manner
choose between short and long indexing depending on (POPF). Only the interrupt section of the PSW can be
the value of the index expression. If the value can be accessed directly. There is no SFR for the PSW status
expressed in eight bits then short indexing will be used, bits.
if it cannot be expressed in eight bits then long indexing
will be used.

12
80C196KB USER’S GUIDE

CONDITION FLAGS VT: The oVerflow Trap flag is set when the V flag is
set, but it is only cleared by the CLRVT, JVT and
The PSW bits on the 80C196KB are set as follows: JNVT instructions. The operation of the VT flag
allows for the testing for a possible overflow con-
7 6 5 4 3 2 1 0 dition at the end of a sequence of related arithme-
PSW: tic operations. This is normally more efficient
Z N V VT C X I ST than testing the V flag after each instruction.
Figure 3-1. PSW Register C: The Carry flag is set to indicate the state of the
arithmetic carry from the most significant bit of
Z: The Z (Zero) flag is set to indicate that the opera-
the ALU for an arithmetic operation, or the state
tion generated a result equal to zero. For the add-
of the last bit shifted out of an operand for a shift.
with-carry (ADDC) and subtract-with-borrow
Arithmetic Borrow after a subtract operation is
(SUBC) operations the Z flag is cleared if the re-
the complement of the C flag (i.e. if the operation
sult is non-zero but is never set. These two in-
generated a borrow then C e 0.)
structions are normally used in conjunction with
the ADD and SUB instructions to perform multi- X: Reserved. Should always be cleared when writing
ple precision arithmetic. The operation of the Z to the PSW for compatibility with future prod-
flag for these instructions leaves it indicating the ucts.
proper result for the entire multiple precision cal- I: The global Interrupt disable bit disables all inter-
culation. rupts when cleared except NMI, TRAP, and un-
N: The Negative flag is set to indicate that the opera- implemented opcode.
tion generated a negative result. Note that the N ST: The ST (STicky bit) flag is set to indicate that
flag will be in the algebraically correct state even during a right shift a 1 has been shifted first into
if an overflow occurs. For shift operations, includ- the C flag and then been shifted out. The ST flag
ing the normalize operation and all three forms is undefined after a multiply operation. The ST
(SHL, SHR, SHRA) of byte, word and double flag can be used along with the C flag to control
word shifts, the N flag will be set to the same rounding after a right shift. Consider multiplying
value as the most significant bit of the result. This two eight bit quantities and then scaling the result
will be true even if the shift count is 0. down to 12 bits:
V: The oVerflow flag is set to indicate that the opera-
tion generated a result which is outside the range MULUB AX,CL,DL ;AX:4CL*DL
for the destination data type. For the SHL, SHLB SHR AX,#4 ;Shift right 4
and SHLL instructions, the V flag will be set if the places
most significant bit of the operand changes at any
time during the shift. For divide operations, the If the C flag is set after the shift, it indicates that the
following conditions are used to determine if the V bits shifted off the end of the operand were greater-than
flag is set: or equal-to one half the least significant bit (LSB) of the
result. If the C flag is clear after the shift, it indicates
For the
that the bits shifted off the end of the operand were less
operation: V is set if Quotient is:
than half the LSB of the result. Without the ST flag,
UNSIGNED the rounding decision must be made on the basis of the
BYTE DIVIDE l 255(0FFH) C flag alone. (Normally the result would be rounded up
if the C flag is set.) The ST flag allows a finer resolution
UNSIGNED in the rounding decision:
WORD DIVIDE l 65535(0FFFFH)

SIGNED k b 127(81H) C ST Value of the Bits Shifted Off

BYTE or 0 0 Value e 0
DIVIDE l 127(7FH)
0 1 0 k Value k (/2 LSB
SIGNED k b 32767(8001H)
1 0 Value e (/2 LSB
WORD or
DIVIDE l 32767(7FFFH) 1 1 Value l (/2 LSB
Figure 3-2. Rounding Alternatives

Imprecise rounding can be a major source of error in a

numerical calculation; use of the ST flag improves the
options available to the programmer.

13
80C196KB USER’S GUIDE

INTERRUPT FLAGS WORDS can be converted to DOUBLE-WORDS by

simply clearing the upper WORD of the DOUBLE-
The lower eight bits of the PSW individually mask the WORD (CLR) and INTEGERS can be converted to
lowest 8 sources of interrupt to the 80C196KB. These LONGS with the EXT (sign extend) instruction.
mask bits can be accessed as an eight bit byte (INTÐ
MASKÐaddress 8) in the on-board register file. A sep- The MCS-96 instructions for addition, subtraction, and
arate register (INTÐMASK1Ðaddress 13H) contains comparison do not distinguish between unsigned words
the control bits for the higher 8 interrupts. A logical ‘1’ and signed integers. Conditional jumps are provided to
in these bit positions enables the servicing of the corre- allow the user to treat the results of these operations as
sponding interrupt. Bit 9 in the PSW is the global inter- either signed or unsigned quantities. As an example, the
rupt disable. If this bit is cleared then interrupts will be CMPB (compare byte) instruction is used to compare
locked out. Note that the interrupts are collected in the both signed and unsigned eight bit quantities. A JH
INTÐPEND registers even if they are locked out. Exe- (jump if higher) could be used following the compare if
cution of the corresponding service routines will pro- unsigned operands were involved or a JGT (jump if
ceed according to their priority when they become en- greater-than) if signed operands were involved.
abled. Further information on the interrupt structure of
the 80C196KB can be found in Section 5. Tables 3-1 and 3-2 summarize the operation of each of
the instructions. Complete descriptions of each instruc-
tion and its timings can be found in the MCS-96 family
3.4 Instruction Set Instruction Set chapter.

The MCS-96 instruction set contains a full set of arith- The execution times for the instruction set are given in
metic and logical operations for the 8-bit data types Figure 3-3. These times are given for a 16-bit bus with
BYTE and SHORT INTEGER and for the 16-bit data no wait states. On-chip EPROM/ROM space is a 16-
types WORD and INTEGER. The DOUBLE-WORD bit, zero wait state bus. When executing from an 8-bit
and LONG data types (32 bits) are supported for the external memory system or adding wait states, the CPU
products of 16-by-16 multiplies and the dividends of becomes bus limited and must sometimes wait for the
32-by-16 divides, for shift operations, and for 32-bit prefetch queue. The performance penalty for an 8-bit
compares. The remaining operations on 32-bit variables external bus is difficult to measure, but has shown to be
can be implemented by combinations of 16-bit opera- between 10 and 30 percent based on the instruction
tions. As an example the sequence: mix. The best way to measure code performance is to
actually benchmark the code and time it using an emu-
ADD AX,CX lator or with TIMER1.
ADDC BX,DX
The indirect and indexed instruction timings are given
performs a 32-bit addition, and the sequence for two memory spaces: SFR/Internal RAM space (0 –
0FFH), and a memory controller reference (100H –
SUB AX,CX 0FFFFH). Any instruction that uses an operand that is
SUBC BX,DX referenced through the memory controller (ex. Add
r1,5000H [0] ) takes 2 – 3 states longer than if the oper-
performs a 32-bit subtraction. Operations on REAL and was in the SFR/Internal RAM space. Any data
(i.e. floating point) variables are not supported directly access to on-chip ROM/EPROM is considered to be a
by the hardware but are supported by the floating point memory controller reference.
library for the 80C196KB (FPAL-96) which imple-
ments a single precision subset of draft 10 of the IEEE Flag Settings. The modification to the flag setting is
standard for floating point arithmetic. The performance shown for each instruction. A checkmark (&) means
of this software is significantly improved by the that the flag is set or cleared as appropriate. A hyphen
80C196KB NORML instruction which normalizes a means that the flag is not modified. A one or zero (1) or
32-bit variable and by the existence of the ST flag in the (0) indicates that the flag will be in that state after the
PSW. u
instruction. An up arrow ( ) indicates that the in-
struction may set the flag if it is appropriate but will
In addition to the operations on the various data types, v
not clear the flag. A down arrow ( ) indicates that the
the 80C196KB supports conversions between these flag can be cleared but not set by the instruction. A
types. LDBZE (load byte zero extended) converts a question mark (?) indicates that the flag will be left in
BYTE to a WORD and LDBSE (load byte sign extend- an indeterminant state after the operation.
ed) converts a SHORT-INTEGER into an INTEGER.

14
80C196KB USER’S GUIDE

Table 3-1A. Instruction Summary

Flags
Mnemonic Operands Operation (Note 1) Notes
Z N C V VT ST
ADD/ADDB 2 DwDaA & & & & u b

ADD/ADDB 3 DwBaA & & & & u b

ADDC/ADDCB 2 DwDaAaC v & & & u b

SUB/SUBB 2 DwDbA & & & & u b

SUB/SUBB 3 DwBbA & & & & u b

SUBC/SUBCB 2 DwDbAaCb1 v & & & u b

CMP/CMPB 2 DbA & & & & u b

MUL/MULU 2 D,D a 2 wDcA b b b b b b 2

MUL/MULU 3 D,D a 2wBcA b b b b b b 2
MULB/MULUB 2 D,D a 1 w D c A b b b b b b 3
MULB/MULUB 3 D,D a 1 w B c A b b b b b b 3
DIVU 2 D w (D,D a 2) /A,D a 2 w remainder b b b & u b 2
DIVUB 2 D w (D,D a 1) /A,D a 1 w remainder b b b & u b 3
DIV 2 D w (D,D a 2) /A,D a 2 w remainder b b b & u b

DIVB 2 D w (D,D a 1) /A,D a 1 w remainder b b b & u b

AND/ANDB 2 D w D AND A & & 0 0 b b

AND/ANDB 3 D w B AND A & & 0 0 b b

OR/ORB 2 D w D OR A & & 0 0 b b

XOR/XORB 2 D w D (ecxl. or) A & & 0 0 b b

LD/LDB 2 DwA b b b b b b

ST/STB 2 AwD b b b b b b

LDBSE 2 D w A; D a 1 w SIGN(A) b b b b b b 3,4

LDBZE 2 D w A; D a 1 w 0 b b b b b b 3,4
PUSH 1 SP w SP b 2; (SP) w A b b b b b b

POP 1 A w (SP); SP a 2 b b b b b b

PUSHF 0 SP w SP b 2; (SP) w PSW; 0 0 0 0 0 0

PSW w 0000H; I w 0
POPF 0 PSW w (SP); SP w SP a 2; I w & & & & & & &

SJMP 1 PC w PC a 11-bit offset b b b b b b 5

LJMP 1 PC w PC a 16-bit offset b b b b b b 5
BR [indirect] 1 PC w (A) b b b b b b

SCALL 1 SP w SP b 2; b b b b b b 5
(SP) w PC; PC w PC a 11-bit offset
LCALL 1 SP w SP b 2; (SP) w PC; b b b b b b 5
PC w PC a 16-bit offset

15
80C196KB USER’S GUIDE

Table 3-1B. Instruction Summary

Flags
Mnemonic Operands Operation (Note 1) Notes
Z N C V VT ST
RET 0 PC w (SP); SP w SP a 2 b b b b b b

J (conditional) 1 PC
b w PC a 8-bit offset (if taken) b b b b b b 5
JC 1 Jump if C e 1 b b b b b b 5
JNC 1 jump if C e 0 b b b b b b 5
JE 1 jump if Z e 1 b b b b b b 5
JNE 1 Jump if Z e 0 b b b b b b 5
JGE 1 Jump if N e 0 b b b b b b 5
JLT 1 Jump if N e 1 b b b b b b 5
JGT 1 Jump if N e 0 and Z e 0 b b b b b b 5
JLE 1 Jump if N e 1 or Z e 1 b b b b b b 5
JH 1 Jump if C e 1 and Z e 0 b b b b b b 5
JNH 1 Jump if C e 0 or Z e 1 b b b b b b 5
JV 1 Jump if V e 1 b b b b b b 5
JNV 1 Jump if V e 0 b b b b b b 5
JVT 1 Jump if VT e 1; Clear VT b b b b 0 b 5
JNVT 1 Jump if VT e 0; Clear VT b b b b 0 b 5
JST 1 Jump if ST e 1 b b b b b b 5
JNST 1 Jump if ST e 0 b b b b b b 5
JBS 3 Jump if Specified Bit e 1 b b b b b b 5,6
JBC 3 Jump if Specified Bit e 0 b b b b b b 5,6
DJNZ/ 1 D w D b 1; b b b b b b 5
DJNZW If D i 0 then PC w PC a 8-bit offset 10
DEC/DECB 1 D wDb1 & & & & u b

NEG/NEGB 1 Dw0bD & & & & u b

INC/INCB 1 DwDa1 & & & & u b

EXT 1 D w D; D a 2 w Sign (D) & & 0 0 b b 2

EXTB 1 D w D; D a 1 w Sign (D) & & 0 0 b b 3
NOT/NOTB 1 D w Logical Not (D) & & 0 0 b b

CLR/CLRB 1 Dw0 1 0 0 0 b b

SHL/SHLB/SHLL 2 C w msb - - - - - lsb w 0 & & & & u b 7

SHR/SHRB/SHRL 2 0 x msb - - - - - lsb x C & & & 0 b & 7
SHRA/SHRAB/SHRAL 2 msb x msb - - - - - lsb x C & & & 0 b & 7
SETC 0 Cw1 b b 1 b b b

CLRC 0 Cw0 b b 0 b b b

16
80C196KB USER’S GUIDE

Table 3-1C. Instruction Summary

Flags
Mnemonic Operands Operation (Note 1) Notes
Z N C V VT ST
CLRVT 0 VT w0 b b b b 0 b

RST 0 PC w 2080H 0 0 0 0 0 0 8
DI 0 Disable All Interupts (I w 0) b b b b b b

EI 0 Enable All Interupts (I w 1) b b b b b b

NOP 0 PC w PC a 1 b b b b b b

SKIP 0 PC w PC a 2 b b b b b b

NORML 2 w shift count

Left shift till msb e 1; D & & 0 b b b 7
TRAP 0 SP w SP b 2; b b b b b b 9
(SP) w PC; PC w (2010H)
PUSHA 1 SP w SP-2; (SP) w PSW; 0 0 0 0 0 0
PSW w 0000H; SP w SP-2;
(SP) w IMASK1/WSR; IMASK1 w 00H
POPA 1 IMASK1/WSR w (SP); SP w SP a 2 & & & & & &
PSW w (SP); SP w SP a 2
IDLPD 1 IDLE MODE IF KEY e 1; b b b b b b
POWERDOWN MODE IF KEY e 2;
CHIP RESET OTHERWISE
CMPL 2 D-A & & & & u b

BMOV 2 [PTRÐHI] a w [PTRÐLOW] a ; b b b b b b

UNTIL COUNT e 0

NOTES:
1. If the mnemonic ends in ‘‘B’’ a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the Register File; A can be
located anywhere in memory.
2. D,D a 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D,D a 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2’s complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The ‘‘L’’ (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.
10. The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

17
80C196KB USER’S GUIDE

Table 3-2A. Instruction Length (in Bytes)/Opcode

INDIRECT INDEXED
MNEMONIC DIRECT IMMED
NORMAL*(1) A-INC*(1) SHORT*(1) LONG*(1)
ADD (3-op) 4/44 5/45 4/46 4/46 5/47 6/47
SUB (3-op) 4/48 5/49 4/4A 4/4A 5/4B 6/4B
ADD (2-op) 3/64 4/65 3/66 3/66 4/67 5/67
SUB (2-op) 3/68 4/69 3/6A 3/6A 4/6B 5/6B
ADDC 3/A4 4/A5 3/A6 3/A6 4/A7 5/A7
SUBC 3/A8 4/A9 3/AA 3/AA 4/AB 5/AB
CMP 3/88 4/89 3/AB 3/AB 4/8B 5/8B
ADDB (3-op) 4/54 4/55 4/56 4/56 5/57 6/57
SUBB (3-op) 4/58 4/59 4/5A 4/5A 5/5B 6/5B
ADDB (2-op) 3/74 3/75 3/76 3/76 4/77 5/77
SUBB (2-op) 3/78 3/79 3/7A 3/7A 4/7B 5/7B
ADDCB 3/B4 3/B5 3/B6 3/B6 4/B7 5/B7
SUBCB 3/B8 3/B9 3/BA 3/BA 4/BB 5/BB
CMPB 3/98 3/99 3/9A 3/9A 4/9B 5/9B
MUL (3-op) 5/(2) 6/(2) 5/(2) 5/(2) 6/(2) 7/(2)
MULU (3-op) 4/4C 5/4D 4/4E 4/4E 5/4F 6/4F
MUL (2-op) 4/(2) 5/(2) 4/(2) 4/(2) 5/(2) 6/(2)
MULU (2-op) 3/6C 4/6D 3/6E 3/6E 4/6F 5/6F
DIV 4/(2) 5/(2) 4/(2) 4/(2) 5/(2) 6/(2)
DIVU 3/8C 4/8D 3/8E 3/8E 4/8F 5/8F
MULB (3-op) 5/(2) 5/(2) 5/(2) 5/(2) 6/(2) 7/(2)
MULUB (3-op) 4/5C 4/5D 4/5E 4/5E 5/5F 6/5F
MULB (2-op) 4/(2) 4/(2) 4/(2) 4/(2) 5/(2) 6/(2)
MULUB (2-op) 3/7C 3/7D 3/7E 3/7E 4/7F 5/7F
DIVB 4/(2) 4/(2) 4/(2) 4/(2) 5/(2) 6/(2)
DIVUB 3/9C 3/9D 3/9E 3/9E 4/9F 5/9F
AND (3-op) 4/40 5/41 4/42 4/42 5/43 6/43
AND (2-op) 3/60 4/61 3/62 3/62 4/63 5/63
OR (2-op) 3/80 4/81 3/82 3/82 4/83 5/83
XOR 3/84 4/85 3/86 3/86 4/87 5/87
ANDB (3-op) 4/50 4/51 4/52 4/52 5/53 5/53
ANDB (2-op) 3/70 3/71 3/72 3/72 4/73 4/73
ORB (2-op) 3/90 3/91 3/92 3/92 4/93 5/93
XORB 3/94 3/95 3/96 3/96 4/97 5/97
PUSH 2/C8 3/C9 2/CA 2/CA 3/CB 4/CB
POP 2/CC Ð 2/CE 2/CE 3/CF 4/CF

NOTES:
1. Indirect and indirect a share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for signed multiply and divide are the unsigned opcode with an ‘‘FE’’ prefix.

18
80C196KB USER’S GUIDE

Table 3-2B. Instruction Length (in Bytes)/Opcode

INDIRECT INDEXED
MNEMONIC DIRECT IMMED
NORMAL A-INC SHORT LONG
LD 3/A0 4/A1 3/A2 3/A2 4/A3 5/A3
LDB 3/B0 3/B1 3/B2 3/B2 4/B3 5/B3
ST 3/C0 Ð 3/C2 3/C2 4/C3 5/C3
STB 3/C4 Ð 3/C6 3/C6 4/C7 5/C7
LDBSE 3/BC 3/BD 3/BE 3/BE 4/BF 5/BF
LBSZE 3/AC 3/AD 3/AE 3/AE 4/AF 5/AF

Mnemonic Length/Opcode Mnemonic Length/Opcode

PUSHF 1/F2 DJNZ 3/E0
POPF 1/F3 DJNZW 3/E1(4)
PUSHA 1/F4 NORML 3/0F
POPA 1/F5 SHRL 3/0C
SHLL 3/0D
TRAP 1/F7 SHRAL 3/0E
LCALL 3/EF SHR 3/08
SCALL 2/28–2F(3) SHRB 3/18
RET 1/F0 SHL 3/09
LJMP 3/E7 SHLB 3/19
SJMP 2/20–27(3) SHRA 3/0A
BR [ ] 2/E3 SHRAB 3/1A

JNST 1/D0 CLRC 1/F8

JST 1/D8 SETC 1/F9
JNH 1/D1 DI 1/FA
JH 1/D9 EI 1/FB
JGT 1/D2 CLRVT 1/FC
JLE 1/DA NOP 1/FD
JNC 1/B3 RST 1/FF
JC 1/D8 SKIP 2/00
JNVT 1/D4 IDLPD 1/F6
JVT 1/DC BMOV 3/C1
JNV 1/D5
JV 1/DD
JGE 1/D6
JLT 1/DE
JNE 1/D7
JE 1/DF
JBC 3/30–37
JBS 3/38–3F
NOTES:
3. The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11-bit, 2’s complement offset.
4. The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

19
80C196KB USER’S GUIDE

Table 3.3A. Instruction Execution State Times (1)

INDIRECT INDEXED
MNEMONIC DIRECT IMMED
NORMAL* A-INC* SHORT* LONG*
ADD (3-op) 5 6 7/10 8/11 7/10 8/11
SUB (3-op) 5 6 7/10 8/11 7/10 8/11
ADD (2-op) 4 5 6/8 7/9 6/8 7/9
SUB (2-op) 4 5 6/8 7/9 6/8 7/9
ADDC 4 5 6/8 7/9 6/8 7/9
SUBC 4 5 6/8 7/9 6/8 7/9
CMP 4 5 6/8 7/9 6/8 7/9
ADDB (3-op) 5 5 7/10 8/11 7/10 8/11
SUBB (3-op) 5 5 7/10 8/11 7/10 8/11
ADDB (2-op) 4 4 6/8 7/9 6/8 7/9
SUBB (2-op) 4 4 6/8 7/9 6/8 7/9
ADDCB 4 4 6/8 7/9 6/8 7/9
SUBCB 4 4 6/8 7/9 6/8 7/9
CMPB 4 4 6/8 7/9 6/8 7/9
MUL (3-op) 16 17 18/21 19/22 19/22 20/23
MULU (3-op) 14 15 16/19 17/19 17/20 18/21
MUL (2-op) 16 17 18/21 19/22 19/22 20/23
MULU (2-op) 14 15 16/19 17/19 17/20 18/21
DIV 26 27 28/31 29/32 29/32 30/33
DIVU 24 25 26/29 27/30 27/30 28/31
MULB (3-op) 12 12 14/17 13/15 15/18 16/19
MULUB (3-op) 10 10 12/15 12/16 12/16 14/17
MULB (2-op) 12 12 14/17 15/18 15/18 16/19
MULUB (2-op) 10 10 12/15 13/15 12/16 14/17
DIVB 18 18 20/23 21/24 21/24 22/25
DIVUB 16 16 18/21 19/22 19/22 20/23
AND (3-op) 5 6 7/10 8/11 7/10 8/11
AND (2-op) 4 5 6/8 7/9 6/8 7/9
OR (2-op) 4 5 6/8 7/9 6/8 7/9
XOR 4 5 6/8 7/9 6/8 7/9
ANDB (3-op) 5 5 7/10 8/11 7/10 8/11
ANDB (2-op) 4 4 6/8 7/9 6/8 7/9
ORB (2-op) 4 4 6/8 7/9 6/8 7/9
XORB 4 4 6/8 7/9 6/8 7/9
LD, LDB 4, 4 5, 4 5/8 6/8 6/9 7/10
ST, STB 4, 4 b 5/8 6/9 6/9 7/10
LDBSE 4 4 5/8 6/8 6/9 7/10
LDBZE 4 4 5/8 6/8 6/9 7/10
BMOV internal/internal: 6 a 8 per word
external/internal: 6 a 11 per word
external/external: 6 a 14 per word
PUSH (int stack) 6 7 9/12 10/13 10/13 11/14
POP (int stack) 8 b 10/12 11/13 11/13 12/14
PUSH (ext stack) 8 9 11/14 12/15 12/15 13/16
POP (ext stack) 11 b 13/15 14/16 14/16 15/17
*Times for operands as: SFRs and internal RAM (0–1FFH)/memory controller (200H – 0FFFFH)
NOTE:
1. Execution times for memory controller references may be one to two states higher depending on the number of bytes in
the prefetch queue. Internal stack is 200H–1FFH and external stack is 200H – 0FFFFH.
20
80C196KB USER’S GUIDE

Table 3.3B. Instruction Execution State Times

MNEMONIC MNEMONIC
PUSHF (int stack) 6 PUSHF (ext stack) 8
POPF (int stack) 7 POPF (ext stack) 10
PUSHA (int stack) 12 PUSHA (ext stack) 18
POPA (int stack) 12 POPA (ext stack) 18
TRAP (int stack) 16 TRAP (ext stack) 18
LCALL (int stack) 11 LCALL (ext stack) 13
SCALL (int stack) 11 SCALL (ext stack) 13
RET (int stack) 11 RET (ext stack) 14
CMPL 7 DEC/DECB 3
CLR/CLRB 3 EXT/EXTB 4
NOT/NOTB 3 INC/INCB 3
NEG/NEGB 3
LJMP 7
SJMP 7
BR [indirect] 7
JNST, JST 4/8 jump not taken/jump taken
JNH, JH 4/8 jump not taken/jump taken
JGT, JLE 4/8 jump not taken/jump taken
JNC, JC 4/8 jump not taken/jump taken
JNVT, JVT 4/8 jump not taken/jump taken
JNV, JV 4/8 jump not taken/jump taken
JGE, JLT 4/8 jump not taken/jump taken
JNE, JE 4/8 jump not taken/jump taken
JBC, JBS 5/9 jump not taken/jump taken
DJNZ 5/9 jump not taken/jump taken
DJNZW (Note 1) 5/9 jump not taken/jump taken
NORML 8 a 1 per shift (9 for 0 shift)
SHRL 7 a 1 per shift (8 for 0 shift)
SHLL 7 a 1 per shift (8 for 0 shift)
SHRAL 7 a 1 per shift (8 for 0 shift)
SHR/SHRB 6 a 1 per shift (7 for 0 shift)
SHL/SHLB 6 a 1 per shift (7 for 0 shift)
SHRA/SHRAB 6 a 1 per shift (7 for 0 shift)
CLRC 2
SETC 2
DI 2
EI 2
CLRVT 2
NOP 2
RST 15 (includes fetch of configuration byte)
SKIP 3
IDLPD 8/25 (proper key/improper key)

NOTE:
1. The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

21
80C196KB USER’S GUIDE

3.5 80C196KB Instruction Set language and PLM-96 environment and it offers com-
Additions and Differences patibility between these environments. Another advan-
tage is that it allows the user access to the same floating
For users already familiar with the 8096BH, there are point arithmetics library that PLM-96 uses to operate
six instructions added to the standard MCS-96 instruc- on REAL variables.
tion set to form the 80C196KB instruction set. All of
the former instructions perform the same function, ex-
REGISTER UTILIZATION
cept as indicated in the next section. The new instruc-
tions and their descriptions are listed below: The MCS-96 architecture provides a 256 byte register
PUSHA Ð PUSHes the PSW, INTÐMASK, IM- file. Some of these registers are used to control register-
ASK1, and WSR mapped I/O devices and for other special functions
POPA Ð POPs the PSW, INTÐMASK, IMASK1, such as the ZERO register and the stack pointer. The
and WSR remaining bytes in the register file, some 230 of them,
are available for allocation by the programmer. If these
IDLPD Ð Sets the part into IDLE or Powerdown registers are to be used effectively, some overall strategy
mode for their allocation must be adopted. PLM-96 adopts
CMPL Ð Compare 2 long direct values the simple and effective strategy of allocating the eight
BMOV Ð Block move using 2 auto-incrementing bytes between addresses 1CH and 23H as temporary
pointers and a counter storage. The starting address of this region is called
PLMREG. The remaining area in the register file is
DJNZW Ð Decrement Jump Not Zero using a Word treated as a segment of memory which is allocated as
counter (Not functional on current step- required.
ping.)

ADDRESSING 32-BIT OPERANDS

INSTRUCTION DIFFERENCES
These operands are formed from two adjacent 16-bit
Instruction times on the 80C196KB are shorter than words in memory. The least significant word of the
those on the 8096 for many instructions. For example a double word is always in lower address, even when the
16 c 16 unsigned multiply has been reduced from 25 to data is in the stack (which means that the most signifi-
14 states. In addition, many zero and one operand in- cant word must be pushed into the stack first). A dou-
structions and most instructions using external data ble word is addressed by the address of its least signifi-
take one or two fewer state times. cant byte. Note that the hardware supports some opera-
tions on double words. For these operations the double
Indexed and indirect operations relative to the stack word must be in the internal register file and must have
pointer (SP) work differently on the 80C196KB than an address which is evenly divisible by four.
on the 8096BH. On the 8096BH, the address is calcu-
lated based on the un-updated version of the stack
pointer. The 80C196KB uses the updated version. The SUBROUTINE LINKAGE
offset for POP [SP] and POP nn [SP] instructions may
need to be changed by a count of 2. Parameters are passed to subroutines in the stack. Pa-
rameters are pushed into the stack in the order that
they are encountered in the scanning of the source text.
3.6 Software Standards and Eight-bit parameters (BYTES or SHORT-INTE-
GERS) are pushed into the stack with the high order
Conventions byte undefined. Thirty-two bit parameters (LONG-IN-
For a software project of any size it is a good idea to TEGERS, DOUBLE-WORDS, and REALS) are
modularize the program and to establish standards pushed onto the stack as two 16-bit values; the most
which control the communication between these mod- significant half of the parameter is pushed into the
ules. The nature of these standards will vary with the stack first.
needs of the final application. A common component of
all of these standards, however, must be the mechanism As an example, consider the following PLM-96 proce-
for passing parameters to procedures and returning re- dure:
sults from procedures. In the absence of some overrid-
ing consideration which prevents their use, it is suggest- exampleÐprocedure: PROCEDURE
ed that the user conform to the conventions adopted by (param1,param2,param3);
the PLM-96 programming language for procedure link- DECLARE param1 BYTE,
age. It is a very usable standard for both the assembly param2 DWORD,
param3 WORD;

22
80C196KB USER’S GUIDE

When this procedure is entered at run time the stack It is recommended that unused areas of code be filled
will contain the parameters in the following order: with NOPs and periodic jumps to an error routine or
RST (reset chip) instructions. This is particularly im-
portant in the code around lookup tables, since if look-
?????? : param1
up tables are executed undesired results will occur.
high word of param2 Wherever space allows, each table should be surround-
ed by 7 NOPs (the longest 80C196KB instruction has 7
low word of param2 bytes) and a RST or jump to error routine instruction.
param3 Since RST is a one-byte instruction, the NOPs are not
needed if RSTs are used instead of jumps to an error
return address w StackÐpointer routine. This will help to ensure a speedy recovery
Figure 3-5. Stack Image should the processor have a glitch in the program flow.

If a procedure returns a value to the calling code (as The Watchdog Timer (WDT) further protects against
opposed to modifying more global variables) then the software and hardware errors. When using the WDT to
result is returned in the variable PLMREG. PLMREG protect software it is desirable to reset it from only one
is viewed as either an 8-, 16- or 32-bit variable depend- place in code, lessening the chance of an undesired
ing on the type of the procedure. WDT reset. The section of code that resets the WDT
should monitor the other code sections for proper oper-
The standard calling convention adopted by PLM-96 ation. This can be done by checking variables to make
has several key features: sure they are within reasonable values. Simply using a
software timer to reset the WDT every 10 milliseconds
a) Procedures can always assume that the eight bytes of will provide protection only for catastrophic failures.
register file memory starting at PLMREG can be
used as temporaries within the body of the proce-
dure.
4.0 PERIPHERAL OVERVIEW
b) Code which calls a procedure must assume that the
eight bytes of register file memory starting at There are five major peripherals on the 80C196KB: the
PLMREG are modified by the procedure. pulse-width-modulated output (PWM), Timer1 and
c) The Program Status Word (PSWÐsee Section 3.3) is Timer2, High Speed I/O Unit, Serial Port and A/D
not saved and restored by procedures so the calling Converter. With the exception of the high speed I/O
code must assume that the condition flags (Z, N, V, unit (HSIO), each of the peripherals is a single unit that
VT, C, and ST) are modified by the procedure. can be discussed without further separation.
d) Function results from procedures are always re- Four individual sections make up the HSIO and work
turned in the variable PLMREG. together to form a very flexible timer/counter based
I/O system. Included in the HSIO are a 16-bit timer
PLM-96 allows the definition of INTERRUPT proce- (Timer1), a 16-bit up/down counter (Timer2), a pro-
dures which are executed when a predefined interrupt grammable high speed input unit (HSI), and a pro-
occurs. These procedures do not conform to the rules of grammable high speed output unit (HSO). With very
a normal procedure. Parameters cannot be passed to little CPU overhead the HSIO can measure pulse
these procedures and they cannot return results. Since widths, generate waveforms, and create periodic inter-
they can execute essentially at any time (hence the term rupts. Depending on the application, it can perform the
interrupt), these procedures must save the PSW and work of up to 18 timer/counters and capture/compare
PLMREG when they are entered and restore these val- registers.
ues before they exit.
A brief description of the peripheral functions and in-
terractions is included in this section. It provides over-
3.7 Software Protection Hints view information prior to the detailed discussions in the
following sections. All of the details on control bits and
Several features to assist in recovery from hardware precautions are in the individual sections for each pe-
and software errors are available on the 80C196KB. ripheral starting with Section 5.
Protection is also provided against executing unimple-
mented opcodes by the unimplemented opcode inter-
rupt. In addition, the hardware reset instruction (RST)
can cause a reset if the program counter goes out of
bounds. This instruction has an opcode of 0FFH, so if
the processor reads in bus lines which have been pulled
high it will reset itself.

23
80C196KB USER’S GUIDE

4.1 Pulse Width Modulation Output HSIÐTIME register. When the time register is read
(D/A) the next FIFO location is loaded into the holding regis-
ter.
Digital to analog conversion can be done with the Pulse
Width Modulation output. The output waveform is a Three forms of HSI interrupts can be generated: when a
variable duty cycle pulse which repeats every 256 state value moves from the FIFO into the holding register;
times or 512 state times if the prescaler is enabled. when the FIFO (independent of the holding register)
Changes in the duty cycle are made by writing to the has 4 or more events stored; and when the FIFO has 6
PWM register. There are several types of motors which or more events stored. This flexibility allows optimiza-
require a PWM waveform for most efficient operation. tion of the HSI for the expected frequency of interrupts.
Additionally, if this waveform is integrated it will pro-
duce a DC level which can be changed in 256 steps by Independent of the HSI operation, the state of the HSI
varying the duty cycle. Details on the PWM are in Sec- pins is indicated by 4 bits of the HSIÐSTATUS regis-
tion 6. ter. Also independent of the HSI operation is the HSI.0
pin interrupt, which can be used as an extra external
interrupt even if the pin is not enabled to the HSI unit.
4.2 Timers
Two 16-bit timers are available for use on the 4.4 High Speed Outputs (HSO)
80C196KB. The first is designated ‘‘Timer1’’, the sec-
ond ‘‘Timer2’’. Timer1 is used to synchronize events to The High Speed Output (HSO) unit can generate events
real time, while Timer2 is clocked externally and syn- at specified times or counts based on Timer1 or Timer2
chronizes events to external occurrences. The timers with minimal CPU overhead. A block diagram of the
are the time bases for the High Speed Input (HSI) and HSO unit is shown in Figure 4-4. Up to 8 pending
High Speed Output (HSO) units and can be considered events can be stored in the CAM (Content Addressable
an integral part of the HSI/O. Details on the timers are Memory) of the HSO unit at one time. Commands are
in Section 7. placed into the HSO unit by first writing to HSOÐ
COMMAND with the event to occur, and then to
Timer1 is a free-running timer which is incremented HSOÐTIME with the timer match value.
every eight state times, just as it is on the 8096BH.
Timer1 can cause an interrupt when it overflows. Fourteen different types of events can be triggered by
the HSO: 8 external and 6 internal. There are two inter-
Timer2 counts transitions, both positive and negative, rupt vectors associated with the HSO, one for external
on its input which can be either the T2CLK pin or the events, and one for internal events. External events con-
HSI.1 pin. Timer2 can be read and written and can be sist of switching one or more of the 6 HSO pins
reset by hardware, software or the HSO unit. It can be (HSO.0-HSO.5). Internal events include setting up 4
used as an up/down counter based on Port 2.6 and it’s Software Timers, resetting Timer2, and starting an A/
value can be captured into the T2CAPture register. In- D conversion. The software timers are flags that can be
terrupts can be generated on capture events and if Tim- set by the HSO and optionally cause interrupts. Details
er2 crosses the 0FFFFH/0000H boundary or the on the HSO Unit are in Section 9.
7FFFH/8000H boundary in either direction.

4.5 Serial Port

4.3 High Speed Inputs (HSI) The serial port on the 80C196KB is functionally com-
The High Speed Input (HSI) unit can capture the value patible with the serial port on the MCS-51 and MCS-96
of Timer1 when an event takes place on one of four families of microcontrollers. One synchronous and
input pins (HSI.0-HSI.3). Four types of events can trig- three asynchronous modes are available. The asynchro-
ger a capture: rising edges only, falling edges only, ris- nous modes are full duplex, meaning they can transmit
ing or falling edges, or every eighth rising edge. A block and receive at the same time. Double buffering is pro-
diagram of this unit is shown in Figure 4-3. Details on vided for the receiver so that a second byte can be re-
the HSI unit are in Section 8. ceived before the first byte has been read. The transmit-
ter is also double buffered, allowing bytes to be written
When events occur, the Timer1 value gets stored in the while transmission is still in progress.
FIFO along with 4 status bits which indicate the input
line(s) that caused the event. The next event ready to be The Serial Port STATus (SPÐSTAT) register contains
unloaded from the FIFO is placed in the HSI Holding bits to indicate receive overrun, parity, and framing er-
Register, so a total of 8 pieces of data can be stored in rors, and transmit and receive interrupts. Details on the
the FIFO. Data is taken off the FIFO by reading the Serial Port are in Section 10.
HSIÐSTATUS register, followed by reading the

24
80C196KB USER’S GUIDE

HSI Trigger Options

270651 – 18

270651 – 19

Figure 4-3. HSI Block Diagram

HIGH SPEED OUTPUT CONTROLS

6 PINS
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE A/D CONVERSION
RESET TIMER2
270651 – 8

Figure 4-4. HSO Block Diagram

25
80C196KB USER’S GUIDE

MODES OF OPERATION input at a time using successive approximation with a

result equal to the ratio of the input voltage divided by
Mode 0 is a synchronous mode which is commonly the analog supply voltage. If the ratio is 1.00, then the
used for shift register based I/O expansion. Sets of 8 result will be all ones. A conversion can be started by
bits are shifted in or out of the 80C196KB with a data writing to the A/DÐCommand register or by an HSO
signal and a clock signal. Command. Details on the A/D converter are in Section
11.
Mode 1 is the standard asynchronous communications
mode: the data frame used in this mode consists of 10
bits: a start bit (0), 8 data bits (LSB first), and a stop bit 4.7 I/O Ports
(1). Parity can be enabled to send an even parity bit
instead of the 8th data bit and to check parity on recep- There are five 8-bit I/O ports on the 80C196KB. Some
tion. of these ports are input only, some are output only,
some are bidirectional and some have multiple func-
Modes 2 and 3 are 9-bit modes commonly used for tions. In addition to these ports, the HSI/O pins can be
multi-processor communications. The data frame used used as standard I/O pins if their timer related features
in these modes consist of a start bit (0), 9 data bits (LSB are not needed.
first), and a stop bit (1). When transmitting, the 9th
data bit can be set to a one to indicate an address or Port 0 is an input port which is also the analog input
other global transmission. Devices in Mode 2 will be for the A/D converter. Port 1 is a quasi-bidirectional
interrupted only if this bit is set. Devices in Mode 3 will port and the 3MSBs of Port 1 are multiplexed with the
be interrupted upon any reception. This provides an HOLD/HLDA functions. Port 2 contains three types
easy way to have selective reception on a data link. of port lines: quasi-bidirectional, input and output. Its
Mode 3 can also be used to send and receive 8 bits of input and output lines are shared with other functions
data plus even parity. such as serial port receive and transmit and Timer2
clock and reset. Ports 3 and 4 are open-drain bidirec-
tional ports which share their pins with the address/
BAUD RATES data bus.
Baud rates are generated in an independent 15-bit
Quasi-bidirectional pins can be used as input and out-
counter based on either the T2CLK pin or XTAL1 pin.
put pins without the need for a data direction register.
Common baud rates can be easily generated with stan-
They output a strong low value and a weak high value.
dard crystal frequencies. A maximum baud rate of 750
The weak high value can be externally pulled low pro-
Kbaud is available in the asynchronous modes with
viding an input function. A detailed explanation of
12MHz on XTAL1. The synchronous mode has a max-
these ports can be found in Section 12.
imum rate of 3.0 Mbaud with a 12 MHz clock.

4.8 Watchdog Timer

4.6 A/D Converter
The Watchdog Timer (WDT) provides a means to re-
The 80C196KB’s Analog interface consists of a sample- cover gracefully from a software upset. When the
and-hold, an 8-channel multiplexer, and a 10-bit suc- watchdog is enabled it will initiate a hardware reset
cessive approximation analog-to-digital converter. unless the software clears it every 64K state times.
Hardware resets on the 80C196KB cause the RESET
Analog signals can be sampled by any of the 8 analog input pin to be pulled low, providing a reset signal to
input pins (ACH0 through ACH7) which are shared other components on the board. The WDT is indepen-
with Port 0. An A/D conversion is performed on one dent of the other timers on the 80C196KB.

26
80C196KB USER’S GUIDE

5.0 INTERRUPTS Special Interrupts

Twenty-eight (28) sources of interrupts are available on Three special interrupts are available on the
the 80C196KB. These sources are gathered into 15 vec- 80C196KB: NMI, TRAP and Unimplemented opcode.
tors plus special vectors for NMI, the TRAP instruc- The external NMI pin generates an unmaskable inter-
tion, and Unimplemented Opcodes. Figure 5-1 shows rupt for implementation of critical interrupt routines.
the routing of the interrupt sources into their vectors as The TRAP instruction is useful in the development of
well as the control bits which enable some of the custom software debuggers or generation of software
sources. interrupts. The unimplemented opcode interrupt gener-
ates an interrupt when unimplemented opcodes are exe-

270651 – 9

Figure 5-1. 80C196KB Interrupt Sources

27
80C196KB USER’S GUIDE

cuted. This provides software recovery from random The programmer must initialize the interrupt vector ta-
execution during hardware and software failures. Al- ble with the starting addresses of the appropriate inter-
though available for customer use, these interrupts may rupt service routines. It is suggested that any unused
be used in Intel development tools or evaluation boards. interrupts be vectored to an error handling routine. In a
debug environment, it may be desirable to have the rou-
tine lock into a jump to self loop which would be easily
NMI traceable with emulation tools. More sophisticated rou-
tines may be appropriate for production code recover-
NMI, the external Non-Maskable Interrupt, is the
ies.
highest priority interrupt. It vectors indirectly through
location 203EH. For design symmetry, a mask bit ex-
ists in INTÐMASK1 for the NMI. To prevent acci-
dental masking of an NMI, the bit does not function
and will not stop an NMI from occurring. For future
compatibility, the NMI mask bit must be set to zero.

NMI on the 8096 vectored directly to location 0000H,

so for the 80C196KB to be compatible with 8096 soft-
ware, which uses the NMI, location 203EH must be
loaded with 0000H. The NMI interrupt vector and in-
terrupt vector location is used by some Intel develop-
ment tools. For example, the EV80C196KB evaluation
board uses the NMI to process serial communication
interrupts from the host. The NMI interrupt routine
executes monitor commands passed from the host.

The NMI interrupt is sampled during PH1 or

CLKOUT low and is latched internally. If the pin is
held high, multiple interrupts will not occur.

TRAP
Opcode 0F7H, the TRAP instruction, causes an indi- 270651 – 10
rect vector through location 2010H. The TRAP in-
Figure 5-2. 80C196KB Interrupt Structure
struction provides a single instruction interrupt useful
in designing software debuggers. The TRAP instruc- Block Diagram
tion prevents the acknowledgement of interrupts until
after execution of the next instruction. Five registers control the operation of the interrupt sys-
tem: INTÐPEND, INTÐPEND1, INTÐMASK and
INTÐMASK1 and the PSW which contains a global
Unimplemented Opcode disable bit. A block diagram of the system is shown in
Figure 5-2. The transition detector looks for 0 to 1 tran-
Opcodes which are not implemented on the 80C196KB sitions on any of the sources. External sources have a
will cause an indirect vector through location 2012H. maximum transition speed of one edge every state time.
User code or hardware which may have failed and run Sampling will be guaranteed if the level on the interrupt
into an unimplemented opcode can software recover line is held for at least one state time. If the interrupt
through this interrupt. The DJNZW instruction is not line is not held for at least one state time, the interrupt
supported on the 80C196KB but remains a valid op- may not be detected.
code, therefore, no interrupt will occur.

28
80C196KB USER’S GUIDE

5.1 Interrupt Control format of these registers is the same as that of the Inter-
rupt Pending Register shown in Figure 5-3.
Interrupt Pending Register The INTÐMASK and INTÐMASK1 registers can be
read or written as byte registers. A one in any bit posi-
When the hardware detects one of the sixteen inter-
tion will enable the corresponding interrupt source and
rupts it sets the corresponding bit in one of two pending
a zero will disable the source. The hardware will save
interrupt registers (INTÐPEND-09H and INTÐ
any interrupts that occur by setting bits in the pending
PEND1-12H). When the interrupt vector is taken, the
register, even if the interrupt mask bit is cleared. The
pending bit is cleared. These registers, the formats of
INTÐMASK register is the lower eight bits of the
which are shown in Figure 5-3, can be read or modified
PSW so the PUSHF and POPF instructions save and
as byte registers. They can be read to determine which
restore the INTÐMASK register as well as the global
of the interrupts are pending at any given time or modi-
interrupt lockout and the arithmetic flags. Both the
fied to either clear pending interrupts or generate inter-
INTÐMASK and INTÐMASK1 registers can be
rupts under software control. Any software which
saved with the PUSHA and POPA Instructions.
modifies the INTÐPEND registers should ensure that
the entire operation is inseparable. The easiest way to
do this is to use the logical instructions in the two or Global Disable
three operand format, for example:
The processing of all interrupts except the NMI, TRAP
ANDB INT PEND,#11111101B and unimplemented opcode interrupts can be disabled
; Clears the A/D Interrupt by clearing the I bit in the PSW. Setting the I bit will
ORB INT PEND,#00000010B enable interrupts that have mask register bits which are
; Sets the A/D Interrupt set. The I bit is controlled by the EI (Enable Interrupts)
and DI (Disable Interrupts) instructions. Note that the
Caution must be used when writing to the pending reg- I bit only controls the actual servicing of interrupts.
ister to clear interrupts. If the interrupt has already Interrupts that occur during periods of lockout will be
been acknowledged when the bit is cleared, a 5 state held in the pending register and serviced on a priori-
time ‘‘partial’’ interrupt cycle will occur. This is be- tized basis when the lockout period ends.
cause the 80C196KB will have to fetch the next instruc-
tion of the normal instruction flow, instead of proceed-
ing with the interrupt processing. The effect on the pro- 5.2 Interrupt Priorities
gram will be essentially that of an extra two NOPs.
This can be prevented by clearing the bits using a 2 The priority encoder looks at all of the interrupts which
operand immediate logical, as the 80C196KB holds off are both pending and enabled, and selects the one with
acknowledging interrupts during these ‘‘read/modify/ the highest priority. The priorities are shown in Figure
write’’ instructions. 5-4 (15 is highest, 0 is lowest). The interrupt generator
then forces a call to the location in the indicated vector
location. This location would be the starting location of
Interrupt Mask Register the Interrupt Service Routine (ISR).
Individual interrupts can be enabled or disabled by set-
ting or clearing bits in the interrupt mask registers
(INTÐMASK-08H and INTÐMASK1-13H). The

7 6 5 4 3 2 1 0
12H IPEND1: FIFO EXT T2 T2
NMI HSI4 RI TI
13H IMASK1: FULL INT1 OVF CAP

7 6 5 4 3 2 1 0
09H IPEND: EXT SER SOFT HSI.0 HSO HSI A/D TIMER
08H IMASK: INT PORT TIMER PIN PIN DATA DONE OVF
Figure 5-3. Interrupt Mask and Pending Registers

29
80C196KB USER’S GUIDE

Note that location 200CH in the interrupt vector table

Vector
Number Source Priority would have to be loaded with the label serialÐioÐisr
Location and the interrupt be enabled for this routine to execute.
INT15 NMI 203EH 15
There is an interesting chain of instruction side-effects
INT14 HSI FIFO Full 203CH 14 which makes this (or any other) 80C196KB interrupt
INT13 EXTINT1 203AH 13 service routine execute properly:
A) After the interrupt controller decides to process an
INT12 TIMER2 Overflow 2038H 12
interrupt, it executes a ‘‘CALL’’, using the location
INT11 TIMER2 Capture 2036H 11 from the corresponding interrupt vector table entry
as the destination. The return address is pushed
INT10 4th Entry into HSI FIFO 2034H 10 onto the stack. Another interrupt cannot be serviced
INT09 RI 2032H 9 until after the first instruction following the inter-
rupt call is executed.
INT08 TI 2030H 8
B) The PUSHA instruction, which is now guaran-
SPECIAL Unimplemented Opcode 2012H N/A teed to execute, saves the PSW, INTÐMASK,
INTÐMASK1, and the WSR on the stack as two
SPECIAL Trap 2010H N/A
words, and clears them. An interrupt cannot be
INT07 EXTINT 200EH 7 serviced immediately following a PUSHA instruc-
tion. (If INTÐMASK1 and the WSR register are
INT06 Serial Port 200CH 6 not used, or 8096BH code is being executed,
INT05 Software Timer 200AH 5 PUSHF, which saves only the PSW and
INTÐMASK, can be used in place of PUSHA).
INT04 HSI.0 Pin 2008H 4
C) LD INTÐMASK, which is guaranteed to execute,
INT03 High Speed Outputs 2006H 3 enables those interrupts that are allowed to inter-
rupt this ISR. This allows the software to establish
INT02 HSI Data Available 2004H 2
its own priorities independent of the hardware.
INT01 A/D Conversion Complete 2002H 1 D) The EI instruction reenables the processing of inter-
INT00 Timer Overflow 2000H 0 rupts with the new priorities.
E) At the end of the ISR, the POPA instruction re-
Figure 5-4. 80C196KB Interrupt Priorities
stores the PSW, INTÐMASK, INTÐMASK1, and
WSR to their original state when the interrupt oc-
This priority selection controls the order in which
curred. Interrupts cannot occur immediately follow-
pending interrupts are passed to the software via inter-
ing a POPA instruction so the RET instruction is
rupt calls. The software can then implement its own
guaranteed to execute. This prevents the stack from
priority structure by controlling the mask registers
overflowing if interrupts are occurring at high fre-
(INTÐMASK and INTÐMASK1). To see how this is
quency. (If INTÐMASK1 and the WSR are not
done, consider the case of a serial I/O service routine
being used, or 8096BH code is being executed,
which must run at a priority level which is lower than
POPF, which restores only the PSW and
the HSI data available interrupt but higher than any
INTÐMASK, can be used in place of POPA.)
other source. The ‘‘preamble’’ and exit code for this
interrupt service routine would look like this:

serial io isr:
PUSHA ; Save the PSW, INT MASK
; INT MASK1, and WSR
LDB INT MASK,#00000100B
EI ; Enable interrupts again
;
;
;
; Service the interrupt
;
;
;
POPA
– ; Restore
RET

30
80C196KB USER’S GUIDE

Notice that the ‘‘preamble’’ and exit code for the inter- if interrupts are disabled. Depending on system config-
rupt service routine does not include any code for sav- urations, several other SFRs might also need to be
ing or restoring registers. This is because it has been changed in a single instruction for the same reason.
assumed that the interrupt service routine has been al-
located its own private set of registers from the on- When variables must be modified without interruption,
board register file. The availability of some 230 bytes of and a single instruction can not be used, the program-
register storage makes this quite practical. mer must create what is termed a critical region in
which it is safe to modify the variable. One way to do
this is to simply disable interrupts with a DI instruc-
5.3 Critical Regions tion, perform the modification, and then re-enable in-
terrupts with an EI instruction. The problem with this
Interrupt service routines must sometimes share data approach is that it leaves the interrupts enabled even if
with other routines. Whenever the programmer is cod- they were not enabled at the start. A better solution is
ing those sections of code which access these shared to enter the critical region with a PUSHF instruction
pieces of data, great care must be taken to ensure that which saves the PSW and also clears the interrupt en-
the integrity of the data is maintained. Consider clear- able flags. The region can then be terminated with a
ing a bit in the interrupt pending register as part of a POPF instruction which returns the interrupt enable to
non-interrupt routine: the state it was in before the code sequence. It should be
noted that some system configurations might require
LDB AL,INT PEND more protection to form a critical region. An example
ANDB AL,#bit mask is a system in which more than one processor has ac-
STB AL,INT PEND cess to a common resource such as memory or external
I/O devices.
This code works if no other routines are operating con-
currently, but will cause occasional but serious prob-
lems if used in a concurrent environment. (All pro- 5.4 Interrupt Timing
grams which make use of interrupts must be considered
to be part of a concurrent environment.) To demon- The 80C196KB can be interrupted from four different
strate this problem, assume that the INTÐPEND reg- external sources; NMI, P2.2, HSI.0 and P0.7. All exter-
ister contains 00001111B and bit 3 (HSO event inter- nal interrupts are sampled during PH1 or CLKOUT
rupt pending) is to be reset. The code does work for this low and are latched internally. Holding levels on exter-
data pattern but what happens if an HSI interrupt oc- nal interrupts for at least one state time will ensure
curs somewhere between the LDB and the STB instruc- recognition of the interrupts.
tions? Before the LDB instruction INTÐPEND con-
tains 00001111B and after the LDB instruction so does The external interrupts on the 80C196KB, although
AL. If the HSI interrupt service routine executes at this sampled during PH1, are edge triggered interrupts as
point then INTÐPEND will change to 00001011B. opposed to level triggered. Edge triggered interrupts
The ANDB changes AL to 00000111B and the STB will generate only one interrupt if the input is held
changes INTÐPEND to 00000111B. It should be high. On the other hand, level triggered interrupts will
00000011B. This code sequence has managed to gener- generate multiple interrupts when held high.
ate a false HSI interrupt The same basic process can
generate an amazing assortment of problems and head- Interrupts are not always acknowledged immediately.
aches. These problems can be avoided by assuring mu- If the interrupt signal does not occur prior to 4 state-
tual exclusion which basically means that if more than times before the end of an instruction, the interrupt
one routine can change a variable, then the program- may not be acknowledged until after the next instruc-
mer must ensure exclusive access to the variable during tion has been executed. This is because an instruction is
the entire operation on the variable. fetched and prepared for execution a few state times
before it is actually executed.
In many cases the instruction set of the 80C196KB al-
lows the variable to be modified with a single instruc- There are 6 instructions which always inhibit interrupts
tion. The code in the above example can be implement- from being acknowledged until after the next instruc-
ed with a single instruction. tion has been executed. These instructions are:
EI, DI Ð Enable and disable all interrupts by tog-
ANDB INT PEND,#bit mask gling the global disable bit (PSW.9).
Instructions are indivisible so mutual exclusion is en- PUSHF Ð PUSH Flags pushes the PSW/INTÐ
sured in this case. Changes to the INTÐPEND or MASK pair then clears it, leaving both
INTÐPEND1 register must be made as a single in- INTÐMASK and PSW.9 clear.
struction, since bits can be changed in this register even

31
80C196KB USER’S GUIDE

POPF Ð POP Flags pops the PSW/INTÐMASK following EI. The DI, PUSHF, POPF, PUSHA, POPA
pair off the stack and TRAP instructions will also cause the same situa-
PUSHA Ð PUSH All does a PUSHF, then pushes tion. Typically these instructions would only effect la-
the INTÐMASK1/WSR pair and clears tency when one interrupt routine is already in process,
INTÐMASK1 as these instructions are seldom used at other times.
POPA Ð POP All pops the INTÐMASK1/WSR
pair and then does a POPF
5.5 Interrupt Summary
Interrupts can also not occur immediately after execu- Many of the interrupt vectors on the 8096BH were
tion of: shared by multiple interrupts. The interrupts which
Unimplemented Opcodes were shared on the 8096BH are: Transmit Interrupt,
TRAP Ð The software trap instruction Receive Interrupt, HSI FIFO Full, Timer2 Overflow
and EXTINT. On the 80C196KB, each of these inter-
SIGND Ð The signed prefix for multiply and divide rupts have their own interrupt vectors. The source of
instructions the interrupt vectors are typically programmed through
control registers. These registers can be read in Win-
When an interrupt is acknowledged the interrupt pend- dow 15 to determine the source of any interrupt. Inter-
ing bit is cleared, and a call is forced to the location rupt sources with two possible interrupt vectors, serial
indicated by the specified interrupt vector. This call oc- receive interrupt sharing serial port and receive inter-
curs after the completion of the instruction in process, rupt vectors for example, should be configured for only
except as noted above. The procedure of getting the one interrupt vector.
vector and forcing the call requires 16 state times. If the
stack is in external RAM an additional 2 state times are Interrupts with separate vectors include: NMI, TRAP,
required. Unimplemented Opcode, Timer2 Capture, 4th Entry
into HSI FIFO, Software timer, HSI.0 Pin, High Speed
The maximum number of state times required from the Outputs, and A/D conversion Complete. The NMI,
time an interrupt is generated (not acknowledged) until TRAP and Unimplemented Opcode interrupts were
the 80C196KB begins executing code at the desired lo- covered in section 5.0.
cation is the time of the longest instruction, NORML
(Normalize Ð 39 state times), plus the 4 state times
prior to the end of the previous instruction, plus the EXTINT and P0.7
response time (16(internal stack) or 18(external stack)
state times). Therefore, the maximum response time is The 80C196KB has two external interrupt vectors;
61 (39 a 4 a 18) state times. This does not include the EXTINT (200EH) and EXTINT1 (203AH). The
10 state times required for PUSHF if it is used as the EXTINT vector has two alternate sources selectable by
first instruction in the interrupt routine or additional IOC1.1, the external interrupt pin (Port 2.2) and Port
latency caused by having the interrupt masked or dis- 0.7. The external interrupt pin is the only source for the
abled. Refer to Figure 5-5, Interrupt Response Time, to EXTINT1 interrupt vector. The external interrupt pin
visualize an example of worst case scenario. should not be programmed to interrupt through both
vectors. Both external interrupt sources are rising edge
Interrupt latency time can be reduced by careful selec- triggered.
tion of instructions in areas of code where interrupts
are expected. Using ‘EI’ followed immediately by a
long instruction (e.g. MUL, NORML, etc.) will in-
crease the maximum latency by 4 state times, as an
interrupt cannot occur between EI and the instruction

270651 – 11

Figure 5-5. Interrupt Response Time

32
80C196KB USER’S GUIDE

Serial Port Interrupts are individually enabled by setting bits 2 and 3 of IOC1:
bit 2 for Timer1, and bit 3 for Timer2. Which timer
The serial port generates one of three possible inter- actually caused the interrupt can be determined by bits
rupts: Transmit interrupt TI(2030H), Receive Interrupt 4 and 5 of IOS1: bit 4 for Timer2 and 5 for Timer1. On
RI(2032H) and SERIAL(200CH). Refer to section 10 the 80C196KB Timer2 overflow(0H or 8000H) has a
for information on the serial port interrupts. The separate interrupt vector through location 2038H.
8096BH shared the TI and RI interrupts on the SERI-
AL interrupt vector. On the 80C196KB, these inter-
rupts share both the serial interrupt vector and have Timer2 Capture
their own interrupt vectors. Ideally, the transmit and The 80C196KB can generate an interrupt in response
receive interrupts should be programmed as separate to a Timer2 capture triggered by a rising edge on P2.7.
interrupt vectors while disabling the SERIAL inter- Timer2 Capture vectors through location 2036H.
rupt. For 8096BH compatibility, the interrupts can still
use the SERIAL interrupt vector.
High Speed Outputs
HSI FIFO FULL and HSI DATA AVAILABLE The High Speed Outputs interrupt can be generated in
response to a programmed HSO command which caus-
HSI FIFO FULL and HSI DATA AVAILABLE in- es an external event. HSO commands which set or clear
terrupts shared the HSI DATA AVAILABLE inter- the High Speed Output pins are considered external
rupt vector on the 8096BH. The source of the HSI events. Status Register IOS2 indicates which HSO
DATA AVAILABLE interrupt is controlled by the events have occured and can be used to arbitrate which
setting of I/O Control Register 1,(IOC1.7). Setting HSO command caused the interrupt. The High Speed
IOC1.7 to zero will generate an interrupt when a time Output interrupt vectors indirectly through location
value is loaded into the holding register. Setting the bit 2006H. For more information on High Speed Outputs,
to one generates an interrupt when the FIFO, indepen- refer to Section 9.
dent of the holding register, has six entries in it.

On the 80C196KB, separate interrupt vectors are avail- Software Timers

able for the HSI FIFO FULL(203CH) and HSI DATA
AVAILABLE(2004H) interrupts. The interrupts HSO commands which create internal events can inter-
should be programmed for separate interrupt vector lo- rupt through the Software Timer interrupt vector. In-
cations. Refer to Section 8 for more information on the ternal events include triggering an A/D conversion, re-
High Speed Inputs. setting Timer2 and software timers. Status registers
IOS2 and IOS1 can be used to determine which internal
HSO event has occured. Location 200AH is the inter-
HSI FIFOÐ4 rupt vector for the Software Timer interrupt. Refer to
Section 9 for more information on software timers and
The HSI FIFO can generate an interrupt when the HSI the HSO.
has four or more entries in the FIFO. The HSI FIFOÐ
4 interrupt vectors through location 2034H. Refer to
Section 8 for more information on the High Speed In- A/D Conversion Complete
puts.
The A/D Conversion Complete interrupt can generate
an interrupt in response to a completed A/D conver-
HSI.0 External Interrupt sion. The interrupt vectors indirectly through location
2002H. Refer to section 11 for more information on the
The rising edge on HSI.0 pin can be used as an external A/D Converter.
interrupt. The HSI.0 pin is sampled during PH1 or
CLKOUT low. Sampling is guaranteed if the pin is
held for at least one state time. The interrupt vectors
through location 2008H. The pin does not need to be 6.0 Pulse Width Modulation Output
enabled to the HSI FIFO in order to generate the inter- (D/A)
rupt.
Digital to analog conversion can be done with the Pulse
Width Modulation output; a block diagram of the cir-
Timer2 and Timer1 overflow cuit is shown in Figure 6-1. The 8-bit counter is incre-
mented every state time. When it equals 0, the PWM
Timer2 and Timer1 can interrupt on overflow. These output is set to a one. When the counter matches the
interrupts shared the same interrupt vector TIMER value in the PWM register, the output is switched low.
OVERFLOW(2000H) on the 8096BH. The interrupts When the counter overflows, the output is once again
switched high. A typical output waveform is shown in

33
80C196KB USER’S GUIDE

Figure 6-2. Note that when the PWM register equals

00, the output is always low. Additionally, the PWM
register will only be reloaded from the temporary latch
when the counter overflows. This means the compare
circuit will not recognize a new value until the counter
has expired preventing missed PWM edges.

The 80C196KB PWM unit has a prescaler bit (divide

by 2) which is enabled by setting IOC2.2 e 1. The
PWM frequencies are shown in Figure 6-3. The output
waveform is a variable duty cycle pulse which repeats
every 256 or 512 state times (42.75 ms or 85.5 ms at
12 MHz). Changes in the duty cycle are made by writ-
ing to the PWM register at location 17H. The value
programmed into the PWM register can be read in
Window 15 (WSR e 15). There are several types of mo-
tors which require a PWM waveform for more efficient
operation. Additionally, if this waveform is integrated
it will produce a DC level which can be changed in 256
steps by varying the duty cycle. as described in the next
section.
270651 – 12
XTAL1 e 8 MHz 10 MHz 12 MHz # Duty Cycle Programmable in 256 Steps
IOC2.2 e 0 15.6 KHz 19.6 KHz 23.6 KHz Figure 6-1. PWM Block Diagram
IOC2.2 e 1 7.8 KHz 9.8 KHz 11.8 KHz
Figure 6-3. PWM Frequencies

The PWM output shares a pin with Port 2, pin 5 so

that these two features cannot be used at the same time.
IOC1.0 equal to 1 selects the PWM function instead of
the standard port function.

270651 – 13

Figure 6-2. Typical PWM Outputs

34
80C196KB USER’S GUIDE

6.1 Analog Outputs drift, a highly accurate 8-bit D to A converter can be

made using either the HSO or the PWM output. Figure
Analog outputs can be generated by two methods, ei- 6-5 shows two typical circuits. If the HSO is used the
ther by using the PWM output or the HSO. See Section accuracy could be theoretically extended to 16-bits,
9.7 for information on generating a PWM with the however the temperature and noise related problems
High Speed Output Unit. Either device will generate a would be extremely hard to handle.
rectangular pulse train that varies in duty cycle and
period. If a smooth analog signal is desired as an out- When driving some circuits it may be desirable to use
put, the rectangular waveform must be filtered. unfiltered Pulse Width Modulation. This is particularly
true for motor drive circuits. The PWM output can
In most cases this filtering is best done after the signal generate these waveforms if a fixed period on the order
is buffered to make it swing from 0 to 5 volts since both of 64 ms is acceptable. If this is not the case then the
of the outputs are guaranteed only to low current lev- HSO unit can be used. The HSO can generate a vari-
els. A block diagram of the type of circuit needed is able waveform with a duty cycle variable in up to 65536
shown in Figure 6-4. By proper selection of compo- steps and a period of up to 87.5 milliseconds. Both of
nents, accounting for temperature and power supply these outputs produce CHMOS levels.

270651 – 14

Figure 6-4. D/A Buffer Block Diagram

270651 – 15

270651 – 16

Figure 6-5. Buffer Circuits for D/A

35
80C196KB USER’S GUIDE

7.0 TIMERS Capture Register

The value in Timer2 can be captured into the T2CAP-
7.1 Timer1 ture register by a rising edge on P2.7. The edge must be
held for at least one state time as discussed in the next
Timer1 is a 16-bit free-running timer which is incre- section. T2CAP is located at 0CH in Window 15. The
mented every eight state times. An interrupt can be interrupt generated by a capture vectors through loca-
generated in response to an overflow. It is read through tion 2036H.
location 0AH in Window 0 and written in Window 15.
Figure 7-1 shows a block diagram of the timers.
Fast Increment Mode
Care must be taken when writing to it if the High Speed
Timer2 can be programmed to run in fast increment
I/O (HSIO) Subsystem is being used. HSO time entries
mode to count transitions every state time. Setting
in the CAM depend on exact matches with Timer1.
IOC2.0 programs Timer2 in the Fast Increment mode.
Writes to Timer1 should be taken into account in soft-
In this mode, the events programmed on the HSO unit
ware to ensure events in the HSO CAM are not missed
with Timer2 as a reference will not execute properly
or occur in an order which may be unexpected. Chang-
since the HSO requires eight state times to compare
ing Timer1 with incoming events on the High Speed
every location in the HSO CAM. With Timer2 as a
Input lines may corrupt relative references between
reference for the HSO unit, Timer2 transitioning every
captured inputs. Further information on the High
state time may cause programmed HSO events to be
Speed Outputs and High Speed Inputs can be found in
missed. For this reason, Timer2 should not be used as a
Sections 8 and 9 respectively.
reference for the HSO if transitions occur faster than
once every eight state times.
7.2 Timer2 Timer2 should not be RESET in the fast increment
Timer2 on the 80C196KB can be used as an external mode. All Timer2 resets are synchronized to an eight
reference for the HSO unit, an up/down counter, an state time clock. If Timer2 is reset when clocking faster
external event capture or as an extra counter. Timer2 is than once every 8 states, it may reset on a different
clocked externally using either the T2CLK pin (P2.3) count.
or the HSI.1 pin depending on the state of IOC0.7.
Timer 2 counts both positive and negative transitions. Up/Down Counter Mode
The maximum transition speed is once per state time in
the Fast Increment mode, and once every 8 states oth- Timer2 can be made to count up or down based on the
erwise. CLKOUT cannot be used directly to clock Tim- Port 2.6 pin if IOC2.1 e 1. However, caution must be
er2. It must first be divided by 2. Timer2 can be read used when this feature is working in conjunction with
and written through location 0CH in Window 0. Figure the HSO. If Timer2 does not complete a full cycle it is
7-1 shows a block diagram of the timers. possible to have events in the CAM which never match
the timer. These events would stay in the CAM until
Timer2 can be reset by hardware, software or the HSO the CAM is cleared or the chip is reset.
unit. Either T2RST (P2.4) or HSI.0 can reset Timer2
externally depending on the setting of IOC0.5. Figure
7-2 shows the configuration and input pins of Timer2. 7.3 Sampling on External Timer Pins
Figure 7-3 shows the reset and clocking options for
Timer2. The appropriate control registers can be read The T2UP/DN, T2CLK, T2RST, and T2CAP pins are
in Window 15 to determine the programmed modes. sampled during PH1. PH1 roughly corresponds to
However, IOC0.1(T2RST) is not latched and will read CLKOUT low externally. For valid sampling, the in-
a 1. puts should be present 30 nsec prior to the rising edge
of CLKOUT or it may not be sampled until the next
Caution should be used when writing to the timers if CLKOUT. If the T2UP/DN signal changes and be-
they are used as a reference to the High Speed Output comes stable before, or at the same time that the
Unit. Programmed HSO commands could be missed if T2CLK signal changes, the count will go into the new
the timers do not count continuously in one direction. direction.
High Speed Output events based on Timer2 must be
carefully programmed when using Timer2 as an
up/down counter or is reset externally. Programmed
events could be missed or occur in the wrong order.
Refer to section 9 for more information on using the
timers with the High Speed Output Unit.

36
80C196KB USER’S GUIDE

270651 – 5

Figure 7-1. Timer Block Diagram

Bit e 1 Bit e 0
IOC0.1 Reset Timer2 each write No action
IOC0.3 Enable external reset Disable
IOC0.5 HSI.0 is ext. reset source T2RST is reset source
IOC0.7 HSI.1 is T2 clock source T2CLK is clock source
IOC1.3 Enable Timer2 overflow int. Disable overflow interrupt
IOC2.0 Enable fast increment Disable fast increment
IOC2.1 Enable downcount feature Disable downcount
P2.6 Count down if IOC2.1 e 1 Count up
IOC2.5 Interrupt on 7FFFH/8000H Interrupt on 0FFFFH/0000H
P2.7 Capture Timer2 into
T2CAPture on rising edge
Figure 7-2. Timer2 Configuration and Control Pins
7.4 Timer Interrupts
Both Timer1 and Timer2 can trigger a timer overflow
interrupt and set a flag in the I/O Status Register 1
(IOS1). Timer1 overflow is controlled by setting
IOC1.2 and the interrupt status is indicated in IOS1.5.
The TIMER OVERFLOW interrupt is enabled by set-
ting INTÐMASK.0.
A Timer2 overflow condition interrupts through loca-
tion 2000H by setting IOC1.3 and setting INTÐ
MASK.0. Alternatively, Timer2 overflow can interrupt
through location 2038H by setting INTÐMASK1.3.
The status of the Timer2 overflow interrupt is indicated
in IOS1.4.
Interrupts can be generated if Timer2 crosses the
270651 – 17
0FFFFH/0000H boundary or the 7FFFH/8000H
Figure 7-3. Timer2 Clock and Reset Options boundary in either direction. By having two interrupt
points it is possible to have interrupts enabled even if

37
80C196KB USER’S GUIDE

Timer2 is counting up and down centered around one timer interrupts are controlled by the Interrupt Mask
of the interrupt points. The boundaries used to control Register bit 0. In all cases, setting a bit enables a func-
the Timer2 interrupt is determined by the setting of tion, while clearing a bit disables it.
IOC2.5. When set, Timer2 will interrupt on the
7FFFH/8000H boundary, otherwise, the 0FFFFH/
0000H boundary interrupts. 8.0 HIGH SPEED INPUTS
A T2CAPTURE interrupt is enabled by setting INTÐ The High Speed Input Unit (HSI) can record the time
MASK1.3. The interrupt will vector through location an event occurs with respect to Timer1. There are 4
2036H. lines (HSI.0 through HSI.3) which can be used in this
mode and up to a total of 8 events can be recorded.
Caution must be used when examining the flags, as any HSI.2 and HSI.3 are bidirectional pins which can also
access (including Compare and Jump on Bit) of IOS1 be used as HSO.4 and HSO.5. The I/O Control Regis-
clears bits 0 through 5 including the software timer ters (IOC0 and IOC1) determine the functions of these
flags. It is, therefore, recommended to copy the byte to pins. The values programmed into IOC0 and IOC1 can
a temporary register before testing bits. Writing to be read in Window 15. A block diagram of the HSI unit
IOS1 in Window 15 will set the status bits but not cause is shown in Figure 8-1.
interrupts. The general enabling and disabling of the

HSI Trigger Options

270651 – 18

270651 – 19

Figure 8-1. High Speed Input Unit

HSI Status Register (HSIÐStatus)

270651 – 22

Figure 8-2. HSI Status Register Diagram

38
80C196KB USER’S GUIDE

When an HSI event occurs, a 7 c 20 FIFO stores the 16

bits of Timer1, and the 4 bits indicating which pins
recorded events associated with that time tag. There-
fore, if multiple pins are being used as HSI inputs, soft-
ware must check each status bits when processing on
HSI event. Multiple pins can recognize events with the
same time tag. It can take up to 8 state times for this
information to reach the holding register. For this rea-
son, 8 state times must elapse between consecutive
reads of HSIÐTIME. When the FIFO is full, one addi-
tional event, for a total of 8 events, can be stored by
considering the holding register part of the FIFO. If the
FIFO and holding register are full, any additional
events will not be recorded.

8.1 HSI Modes 270651 – 21

There are 4 possible modes of operation for each of the Figure 8-4. IOC0 Control of HSI Pin Functions
HSI pins. The HSIÐMODE register at location 03H
controls which pins will look for what type of events. In
Window 15, reading the register will read back the pro-
8.2 HSI Status
grammed HSI mode. The 8-bit register is set up as Bits 6 and 7 of the I/O Status Register 1 (IOS1Ðsee
shown in Figure 8-3. Figure 8-5) indicate the status of the HSI FIFO. If bit 7
is set, the HSI holding register is loaded. The FIFO
may or may not contain 1 – 5 events. If bit 6 is set, the
FIFO contains 6 entries. If the FIFO fills, future events
will not be recorded. Reading IOS1 clears bits 0 – 5, so
keep an image of the register and test the image to
retain all 6 bits.
Reading the HSI holding register must be done in a
certain order. The HSIÐSTATUS Register (Figure 8-
2) is read first to obtain the status and input bits. Sec-
ond, the HSIÐTIME Register (04H) is read to obtain
the time tag. Reading HSIÐTIME unloads one level of
the FIFO. If the HSIÐTIME is read before
HSIÐSTATUS, the contents of HSIÐSTATUS associ-
ated with that HSIÐTIME tag are lost.

270651 – 20

Figure 8-3. HSI Mode Register 1

The maximum input speed is 1 event every 8 state times

except when the 8 transition mode is used, in which
case it is 1 transition per state time.

The HSI pins can be individually enabled and disabled

using bits in IOC0 as shown in Figure 8-4. If the pin is
disabled, transitions are not entered in the FIFO. How-
ever, the input bits of the HSIÐSTATUS register (Fig-
ure 8-2) are always valid regardless of whether the pin
is enabled to the FIFO. This allows the HSI pins to be 270651 – 23
used as general purpose input pins.
Figure 8-5. I/O Status Register 1

39
80C196KB USER’S GUIDE

If the HSIÐTIME register is read without the holding The HSI.0 pin can generate an interrupt on the rising
register being loaded, the returned value will be indeter- edge even if its not enabled to the HSI FIFO. An inter-
minate. Under the same conditions, the four bits in rupt generated by this pin vectors through location
HSIÐSTATUS indicating which events have occurred 2008H.
will also be indeterminate. The four HSIÐSTATUS
bits which indicate the current state of the pins will
always return the correct value. 8.4 HSI Input Sampling
It should be noted that many of the Status register con- The HSI pins are sampled internally once each state
ditions are changed by a reset, see section 13. Writing time. Any value on these pins must remain stable for at
to HSIÐTIME in window 15 will write to the HSI least 1 full state time to guarantee that it is recognized.
FIFO holding register. Writing to HSIÐSTATUS in The actual sampling occurs during PH1 or during
Window 15 will set the status bits but will not affect the CLKOUT low. The HSI inputs should be valid at least
input bits. 30 nsec before the rising of CLKOUT. Otherwise, the
HSI input may be sampled in the next CLKOUT.
Therefore, if information is to be synchronized to the
8.3 HSI Interrupts HSI it should be latched on the rising edge of
CLKOUT.
Interrupts can be generated by the HSI unit in three
ways: when a value moves from the FIFO into the
holding register; when the FIFO (independent of the 8.5 Initializing the HSI
holding register) has 4 or more event stored; when the
FIFO has 6 or more events. To start the HSI, the following steps and the sequence
must be observed; 1) flush the FIFO, 2) enable the HSI
The HSI DATA AVAILABLE and HSI FIFO FULL interrupts, and 3) initialize and enable the HSI pins.
interrupts are shared on the 8096BH. The source for The following section of code can be used to flush the
the HSI DATA AVAILABLE interrupt is controlled FIFO:
by IOC1.7. When IOC1.7 is cleared, the HSI will gen-
erate an interrupt when the holding register is loaded. reflush: ld 0, HSI TIME ;clear an event
The interrupt indicates at least one HSI event has oc- skip0 ;wait 8 state times
curred and is ready to be processed. The interrupt vec- skip0
tors through location 2004H. The interrupt is enabled jbs IOS1, 7, reflush
by setting INTÐMASK.2. The generation of a HSI
DATA AVAILABLE interrupt will set IOS1.7. The Enabling the HSI pins before enabling the interrupts
HSI FIFO FULL interrupt will vector through HSI can cause a FIFO lockout condition. For example, if
DATA AVAILABLE if IOC1.7 is set. On the the HSI pins were enabled first, an event could get
80C196KB, the HSI FIFO FULL has a separate inter- loaded into the holding register before the HSIÐ
rupt vector at location 203CH. DATAÐAVAILABLE interrupt is enabled. If this
happens, no HSIÐDATAÐAVAILABLE interrupts
A HSI FIFO FULL interrupt occurs when the HSI will ever occur.
FIFO has six or more entries loaded independent of the
holding register. Since all interrupts are rising edge trig-
gered, the processor will not be reinterrupted until the 9.0 HIGH SPEED OUTPUTS
FIFO first contains 5 or less records, then contains six
or more. The HSI FIFO FULL interrupt mask bit is The High Speed Output unit (HSO) trigger events at
INTÐMASK1.6. The occurrence of a HSI FIFO specific times with minimal CPU overhead. Events are
FULL interrupt is indicated by IOS1.6. Earlier warning generated by writing commands to the HSOÐCOM-
of a impending FIFO full condition can be achieved by MAND register and the relative time at which the
the HSI FIFO 4th Entry interrupt. events are to occur into the HSOÐTIME register. In
Window 15, these registers will read the last value pro-
The HSIÐFIFOÐ4 interrupt generates an interrupt grammed in the holding register. The programmable
when four or more events are stored in the HSI FIFO events include: starting an A/D conversion, resetting
independent of the holding register. The interrupt is Timer2, setting 4 software flags, and switching 6 output
enabled by setting INTÐMASK1.2. The HSIÐ lines (HSO.0 through HSO.5). The format of the
FIFOÐ4 vectors indirectly through location 2034H. HSOÐCOMMAND register is shown in Figure 9-1.
There is no status flag associated with the HSIÐ Commands 0CH and 0DH are reserved for use on fu-
FIFOÐ4 interrupt since it has its own independent in- ture products. Up to eight events can be pending at one
terrupt vector. time and interrupts can be generated whenever any of
these events are triggered. HSO.4 and HSO.5 are bi-

40
80C196KB USER’S GUIDE

7 6 5 4 3 2 1 0
HSOÐ CAM TMR2/ SET/ INT/
CHANNEL 06H
COMMAND LOCK TMR1 CLEAR INT
CAM Lock Ð Locks event in CAM if this is enabled by IOC2.6 (ENAÐLOCK)
TMR/TMR1 Ð Events Based on Timer2/Based on Timer1 if 0
SET/CLEAR Ð Set HSO pin/Clear HSO pin if 0
INT/INT Ð Cause interrupt/No interrupt if 0
CHANNEL: 0–5: HSO pins 0–5 separately
(in Hex) 6: HSO pins 0 and 1 together
7: HSO pins 2 and 3 together
8–B: Software Timers 0 – 3
C–D: Unflagged Events (Do not use for future compatibility)
E: Reset Timer2
F: Start A to D Conversion

Figure 9-1. HSO Command Register

directional pins which are multiplexed with HSI.2 and HSO Interrupt Status
HSI.3 respectively. Bits 4 and 6 of I/O Control Regis-
ter 1 (IOC1.4, IOC1.6) enable HSO.4 and HSO.5 as Register IOS2 at location 17H displays the HSO events
outputs. The Control Registers can be read in Window which have occurred. IOS2 is shown in Figure 9-2. The
15 to determine the programmed modes for the HSO. events displayed are HSO.0 through HSO.5, Timer2
However, the IOC2.7(CAM CLEAR) bit is not latched Reset and start of an A/D conversion. IOS2 is cleared
and will read as a one. Entries can be locked in the when accessed, therefore, the register should be saved
CAM to generate periodic events or waveforms. in an image register if more than one bit is being tested.
The status register is useful in determining which
events have caused an HSO generated interrupt. Writ-
9.1 HSO Interrupts and Software ing to this register in Window 15 will set the status bits
Timers but not cause interrupts. In Window 15, writing to
IOS2 can set the High Speed Output lines to an initial
The HSO unit can generate two types of interrupts. The value. Refer to Section 2.2 for more information on
High Speed Output execution interrupt can be generat- Window 15.
ed (if enabled) for HSO commands which change one
or more of the six output pins. The other HSO inter-
rupt is the interrupt which can be generated by any
other HSO command, (e.g. triggering the A/D, reset-
ting Timer2 or generating a software time delay).

IOS2: 7 6 5 4 3 2 1 0
START T2
HSO.5 HSO.4 HSO.3 HSO.2 HSO.1 HSO.0
A/D RESET
17H
read Indicates which HSO event occcured
START A/D: HSOÐCMD 15, start A/D
T2RESET: HSOÐCMD 14, Timer2 Reset
HSO.0–5: Output pins HSO.0 through HSO.5

Figure 9-2. I/O Status Register 2

41
80C196KB USER’S GUIDE

SOFTWARE TIMERS 9.2 HSO CAM

The HSO can be programmed to generate interrupts at A block diagram of the HSO unit is shown in Figure 9-
preset times. Up to four such ‘‘Software Timers’’ can be 3. The Content Addressable Memory (CAM) file is the
in operation at a time. As each preprogrammed time is center of control. One CAM register is compared with
reached, the HSO unit sets a Software Timer Flag. If the timer values every state time, taking 8 state times to
the interrupt bit in the HSO command register was set compare all CAM registers with the timers. This de-
then a Software Timer Interrupt will also be generated. fines the time resolution of the HSO to be 8 state times
The interrupt service routine can then examine I/O (1.33 microseconds at an oscillator frequency of 12
Status register 1 (IOS1) to determine which software MHz).
timer expired and caused the interrupt. When the HSO
resets Timer2 or starts an A/D conversion, it can also Each CAM register is 24 bits wide. Sixteen bits specify
be programmed to generate a software timer interrupt. the time at which the action is to be carried out, one bit
for the lock bit and 7 bits specify both the nature of the
If more than one software timer interrupt occurs in the action and whether Timer1 or Timer2 is the reference.
same time frame, multiple status bits will be set. Each The format of the command to the HSO unit is shown
read or test of any bit in IOS1 (see Figure 9-5) will clear in Figure 9-1. Note that bit 5 is ignored for command
bits 0 through 5. Be certain to save the byte before channels 8 through 0FH.
testing it unless you are only concerned with 1 bit. See
also Section 11.5. To enter a command into the CAM file, write the 8-bit
‘‘Command Tag’’ into location 0006H followed by the
time the action is to be carried out into word address
0004H. The typical code would be:

LDB HSO COMMAND,#what to do

ADD HSO TIME,Timer1,#when to do it

HIGH SPEED OUTPUT CONTROLS

6 PINS
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE A/D CONVERSION
RESET TIMER2
270651 – 24

Figure 9-3. High Speed Output Unit

42
80C196KB USER’S GUIDE

270651 – 25 270651 – 26

Figure 9-4. I/O Status Register 0 Figure 9-5. I/O Status Register 1 (IOS1)

Writing the time value loads the HSO Holding Register this register in Window 15. The format for I/O Status
with both the time and the last written command tag. Register 0 is shown in Figure 9-4.
The command does not actually enter the CAM file
until an empty CAM register becomes available. The expiration of software timer 0 through 4, and the
overflow of Timer1 and Timer2 are indicated in IOS1.
Commands in the holding register will not execute even The status bits can be set in Window 15 but not cause
if their time tag is reached. Commands must be in the interrupts. The register is shown in Figure 9-5.
CAM to execute. Commands in the holding register
can also be overwritten. Since it can take up to 8 state Whenever the processor reads this register all of the
times for a command to move from the holding register time-related flags (bits 5 through 0) are cleared. This
to the CAM, 8 states must be allowed between succes- applies not only to explicit reads such as:
sive writes to the CAM.
LDB AL,IOS1
To provide proper synchronization, the minimum time
that should be loaded to Timer1 is Timer1 a 2. Small- but also to implicit reads such as:
er values may cause the Timer match to occur 65,636
counts later than expected. A similar restriction applies JBS IOS1,3,somewhere else
if Timer2 is used.
which jumps to somewhereÐelse if bit 3 of IOS1 is set.
Care must be taken when writing the command tag for In most cases this situation can best be handled by hav-
the HSO, because an interrupt can occur between writ- ing a byte in the register file which maintains an image
ing the command tag and loading the time value. If the of the register. Any time a hardware timer interrupt or
interrupt service routine writes to the HSO, the com- a HSO software timer interrupt occurs the byte can be
mand tag used in the interrupt routine will overwrite updated:
the command tag from the main routine. One way of
avoiding this problem would be to disable interrupts ORB IOS1 image,IOS1
when writing to the HSO unit.
leaving IOS1Ðimage containing all the flags that were
set before plus all the new flags that were read and
9.3 HSO Status cleared from IOS1. Any other routine which needs to
sample the flags can safely check IOS1Ðimage. Note
Before writing to the HSO, it is desirable to ensure that that if these routines need to clear the flags that they
the Holding Register is empty. If it is not, writing to the have acted on, then the modification of IOS1Ðimage
HSO will overwrite the value in the Holding Register. must be done from inside a critical region.
I/O Status Register 0 (IOS0) bits 6 and 7 indicate the
status of the HSO unit. If IOS0.6 equals 0, the holding
register is empty and at least one CAM register is emp- 9.4 Clearing the HSO and Locked
ty. If IOS0.7 equals 0, the holding register is empty. Entries
The programmer should carefully decide which of these
two flags is the best to use for each application. This All 8 CAM locations of the HSO are compared before
register also shows the current status of the HSO.0 any action is taken. This allows a pending external
through HSO.5. The HSO pins can be set by writing to

43
80C196KB USER’S GUIDE

event to be cancelled by simply writing the opposite be carefully done. The user should ensure writing to
event to the CAM. However, once an entry is placed in Timer1 will not cause programmed HSO events to be
the CAM, it cannot be removed until either the speci- missed or occur in the wrong order. The same precau-
fied timer matches the written value , a chip reset oc- tion applies to Timer2.
curs or IOC2.7 is set. IOC2.7 is the CAM clear bit
which clears all entries in the CAM. The HSO requires at least eight state times to compare
each entry in the CAM. Therefore, the fast increment
Internal events cannot be cleared by writing an oppo- mode for Timer2 cannot be used as a reference for the
site event. This includes events on HSO channels 8 HSO if transitions occur faster then once every eight
through F. The only method for clearing these events state times.
are by a reset or setting IOC2.7.
Referencing events when Timer2 is being used as an
up/down counter could cause events to occur in oppo-
HSO LOCKED ENTRIES site order or be missed entirely. Additionally, locked
The CAM Lock bit (HSOÐCommand.7) can be set to entries could possibly occur several times if Timer2 is
keep commands in the CAM, otherwise the commands oscillating around the time tag for an entry.
will clear from the CAM as soon as they cause an
event. This feature allows for generation periodic events When using Timer2 as the HSO reference, caution
based on Timer2 and must be enabled by setting must be taken that Timer2 is not reset prior to the
IOC2.6. To clear locked events from the CAM, the en- highest value for a Timer2 match in the CAM. If that
tire CAM can be cleared by writing a one to the CAM match is never reached, the event will remain pending
clear bit IOC2.7. A chip reset will also clear the CAM. in the CAM until the part is reset or CAM is cleared.

Locked entries are useful in applications requiring peri-

odic or repetitive events to occur. Timer2 used as an 9.6 PWM Using the HSO
HSO reference can generate periodic events with the
The HSO unit can generate PWM waveforms with very
use of the HSO T2RST command. HSO events pro-
little CPU overhead using Timer2 as a reference. A
grammed with a HSO time less then the Timer2 reset
PWM is generated by programming an HSO line to a
time will occur repeatedly as Timer2 resets. Recurrent
high and a T2RST to occur at the same time. An HSO
software tasks can be scheduled by locking software
low time is programmed on the CAM to generate the
timers commands into the High Speed Output Unit.
duty cycle of the PWM. A repetitive PWM waveform is
Continuous sampling of the A/D converter can be ac-
generated by locking the commands into the CAM. Re-
compished by programming a locked HSO A/D con-
programming of the duty cycle or PWM frequency can
version command. One of the most useful features is
be accomplished by generating a software interrupt and
the generation of multiple PWM’s on the High Speed
reprogramming the HSO high, HSO low and T2RST
Output lines. Locked entries provide the ability to pro-
commands.
gram periodic events while minimizing the software
overhead. Section 9.6 describes the generation of four
Multiple PWMs can be programmed using Timer2 as a
PWMs using locked entries.
reference and locked CAM entries. Up to four PWM’s
can be generated by locking a PWM(High) and
Individual external events setting or clearing an HSO
PWM(low) into the CAM for each HSO.0 through
pin can by cancelled by writing the opposite event to
HSO.3. Timer2 is used as a reference and set to zero by
the CAM. The HSO events do not occur until the timer
programming a T2RST command at the same time an
reference has changed state. An event programmed to
HSO command sets all the lines high. Two CAM en-
set and clear an HSO event at the same time will cancel
tries program the four PWM (high) times by setting
each other out. Locked entries can correspondingly be
HSO.0/HSO.1 and HSO.2/HSO.3 high with the same
cancelled using this method. However, the entries re-
command. Four entries in the CAM set each of the
main in the HSO CAM and can quickly fill up the
HSO lines low. One entry is used to reset Timer2. This
available eight locations. As an alternative, all entries in
method uses a total of seven CAM entries with little or
the HSO CAM can be cleared by setting IOC2.7.
no software overhead. The PWMs can change their
duty cycle by reprogramming the CAM with different
HSO levels.
9.5 HSO Precautions
Changing the duty cycle for each PWM requires the
Timer1 is incremented once every 8 state-times. When
flushing of the CAM and reprogramming of all seven
it is being used as the reference timer for an HSO com-
entries in the CAM. The 80C196KB can flush the en-
mand, the comparator has a chance to look at all 8
tire CAM by setting bit 7 in the IOC2 register (location
CAM registers before Timer1 changes its value. Writ-
16H). Each HSO(high) and HSO(low) times should be
ing to Timer1, which is allowed in Window 15, should

44
80C196KB USER’S GUIDE

reprogrammed in addition to the Timer2 reset com- er changes every eight state times during Phase1. From
mand. This method provides for up to four PWM’s an external perspective the HSO pin should change just
with no software overhead except when reprogramming prior to the falling edge of CLKOUT and be stable by
the duty cycle of any particular PWM. The code to its rising edge. Information from the HSO can be
generate these PWMs is shown in Figure 9-6. latched on the CLKOUT rising edge. Internal events
also occur when the reference timer increments.
9.7 HSO Output Timing
Changes in the HSO lines are synchronized to either 10.0 SERIAL PORT
Timer1 or Timer2. All of the external HSO lines due to
change at a certain value of a timer will change just The serial port on the 80C196KB has one synchronous
after the incrementing of the timer. Internally, the tim- and 3 asynchronous modes. The asynchronous modes

$include (reg196.inc)
; **********************************************************
; *
; * GENERATION OF FOUR PWM’S USING LOCKED ENTRIES *
; *
; * Timer2 is used as a reference and is clocked *
; * externally by T2CLK. The High Speed outputs are *
; * used as PWMs by programming each individual *
; * PWM(low) and PWM(High) time as a locked entry. *
; * The period of the PWM is programmed by resetting *
; * timer2 and setting all the HSO lines high at the *
; * same time. The PWMs are reprogrammed by *
; * clearing the HSO CAM and reloading new values *
; * for the PWM period and duty cycle. *
; *
; **********************************************************

RSEG at 60h
pwm0timl: dsw 1
pwm1timl: dsw 1
pwm2timl: dsw 1
pwm3timl: dsw 1
PWM period: dsw 1
temp: dsw 1

cseg at 2080h
ld sp,#0d0h ; initialize stack pointer
ld PWM period,#0f000h ; intialize pwm period
ld pwm0timl,#2000h ; initialize pwm 0-3 duty cycle
ld pwm1timl,#4000h
ld pwm2timl,#6000h
ld pwm3timl,#8000h
ldb ioc2,#40h ; Enable locked entries
ldb ioc0,#0h ; Enable t2clk for timer2 clock
; source
call pwm program ; program pwm’s on CAM
here: sjmp here ; loop forever

Figure 9-6. Generating Four PWMs Using Locked Entries

45
80C196KB USER’S GUIDE

pwm program:
ldb ioc2,#0c0h ; flush entire cam
ldb hso command,#0ceh ; program timer2 reset time
ld hso time,PWM period
nop ; delay eight state times before
nop ; next load
nop
nop
ldb hso command,#0e6h ; HSO 0/1 high, locked, timer2 as
; reference
ld hso time,PWM period ; set hso high on t2rst
nop
nop
nop
nop
ldb hso command,#0e7h ; HSO 2/3 high, locked, timer2
; as reference
ld hso time,PWM period ; set hso high on t2rst
nop
nop
nop
nop
ldb hso command,#0c0h ; set HSO.0 low, locked, timer2
; as reference
ld hso time,pwm0timl ; HSO.0 time low
nop
nop
nop
nop
ldb hso command,#0c1h ; set HSO.1 low, locked, timer2
; reference
ld hso time,pwm1timl ; HSO.1 time low
nop
nop
nop
nop
ldb hso command,#0c2h ; set HSO.2 low, locked,timer2
; as reference
ld hso time,pwm2timl ; HSO.2 time low
nop
nop
nop
nop
ldb hso command,#0c3h ; set HSO.3 low, locked,timer2
; as reference
ld hso time,pwm3timl ; HSO.3 time low
ret
end

Figure 9-6. Generating Four PWMs Using Locked Entries (Continued)

46
80C196KB USER’S GUIDE

are full duplex, meaning they can transmit and receive reading it accesses SPÐSTAT. The upper 3 bits of
at the same time. The receiver is double buffered so that SPÐCON must be written as 0s for future compatibil-
the reception of a second byte can begin before the first ity. On the 80C196KB the SPÐSTAT register contains
byte has been read. The transmitter on the 80C196KB new bits to indicate receive Overrun Error (OE), Fram-
is also double buffered allowing continuous transmis- ing Error (FE), and Transmitter Empty (TXE). The
sions. The port is functionally compatible with the seri- bits which were also present on the 8096BH are the
al port on the MCS-51 family of microcontrollers, al- Transmit Interrupt (TI) bit, the Receive Interrupt (RI)
though the software controlling the ports is different. bit, and the Received Bit 8 (RB8) or Receive Parity
Error (RPE) bit. SPÐSTAT is read-only in Window 0
Data to and from the serial port is transferred through and is shown in Figure 10-1.
SBUF(RX) and SBUF(TX), both located at 07H.
SBUF(TX) holds data ready for transmission and In all modes, the RI flag is set after the last data bit is
SBUF(RX) contains data received by the serial port. sampled, approximately in the middle of a bit time.
SBUF(TX) and SBUF(RX) can be read and can be Data is held in the receive shift register until the last
written in Window 15. data bit is received, then the data byte is loaded into
SBUF (RX). The receiver on the 80C196KB also
Mode 0, the synchronous shift register mode, is de- checks for a valid stop bit. If a stop bit is not found
signed to expand I/O over a serial line. Mode 1 is the within the appropriate time, the Framing Error (FE)
standard 8 bit data asynchronous mode used for normal bit is set.
serial communications. Modes 2 and 3 are 9 bit data
asynchronous modes typically used for interprocessor Since the receiver is double-buffered, reception on a
communications. Mode 2 provides monitoring of a second data byte can begin before the first byte is read.
communication line for a 1 in the 9th bit position before However, if data in the shift register is loaded into
causing an interrupt. Mode 3 causes interrupts indepen- SBUF (RX) before the previous byte is read, the Over-
dant of the 9th bit value. flow Error (OE) bit is set. Regardless, the data in SBUF
(RX) will always be the latest byte received; it will nev-
er be a combination of the two bytes. The RI, FE, and
10.1 Serial Port Status and Control OE flags are cleared when SPÐSTAT is read. Howev-
er, RI does not have to be cleared for the serial port to
Control of the serial port is done through the Serial receive data.
Port Control (SPÐCON) register shown in Figure 10-
1. Writing to location 11H accesses SPÐCON while

SPÐCON: 7 6 5 4 3 2 1 0
X X X TB8 REN PEN M2 M1 11H
TB8 Ð Sets the ninth data bit for transmission. Cleared after each transmission. Not valid
if parity is enabled.
REN Ð Enables the receiver
PEN Ð Enables the Parity function (even parity)
M2, M1 Ð Sets the mode. Mode0 e 00, Mode1 e 01, Mode2 e 10, Mode3 e 11

SPÐSTAT 7 6 5 4 3 2 1 0
RB8/
RI TI FE TXE OE X X 11H
RPE
RB8 Ð Set if the 9th data bit is high on reception (parity disabled)
RPE Ð Set if parity is enabled and a parity error occurred
RI Ð Set after the last data bit is sampled
TI Ð Set at the beginning of the STOP bit transmission
FE Ð Set if no STOP bit is found at the end of a reception
TXE Ð Set if two bytes can be transmitted
OE Ð Set if the receiver buffer is overwritten

Figure 10-1. Serial Port Control and Status Registers

47
80C196KB USER’S GUIDE

The Transmitter Empty (TXE) bit is set if the transmit BAUD RATES
buffer is empty and ready to take up to two characters.
TXE gets cleared as soon as a byte is written to SBUF. Baud rates are generated based on either the T2CLK
Two bytes may be written consecutively to SBUF if pin or XTAL1 pin. The values used are different than
TXE is set. One byte may be written if TI alone is set. those used for the 8096BH because the 80C196KB uses
By definition, if TXE has just been set, a transmission a divide-by-2 clock instead of a divide-by-3 clock to
has completed and TI will be set. The TI bit is reset generate the internal timings. Baud rates are calculated
when the CPU reads the SPÐSTAT registers. using the following formulas where BAUDÐREG is
the value loaded into the baud rate register:
The TB8 bit is cleared after each transmission and both
TI and RI are cleared when SPÐSTAT read. The RI Asynchronous Modes 1, 2 and 3:
and TI status bits can be set by writing to SPÐSTAT in
window 15 but they will not cause an interrupt. Read- XTAL1 T2CLK
ing of SPÐCON in Window 15 will read the last value BAUDÐREG e b 1 OR
Baud Rate * 16 Baud Rate * 8
written. Whenever the TXD pin is used for the serial
port it must be enabled by setting IOC1.5 to a 1. I/O
Synchronous Mode 0:
control register 1 can be read in window 15 to deter-
mine the setting.
XTAL1 T2CLK
BAUDÐREG e b 1 OR
Baud Rate * 2 Baud Rate
STARTING TRANSMISSIONS AND RECEPTIONS
The most significant bit in the baud register value is set
In Mode 0, if REN e 0, writing to SBUF (TX) will
to a one to select XTAL1 as the source. If it is a zero
start a transmission. Causing a rising edge on REN, or
the T2CLK pin becomes the source. The following ta-
clearing RI with REN e 1, will start a reception. Set-
ble shows some typical baud rate values.
ting REN e 0 will stop a reception in progress and
inhibit further receptions. To avoid a partial or com-
plete undesired reception, REN must be set to zero be- BAUD RATES AND BAUD REGISTER VALUES
fore RI is cleared. This can be handled in an interrupt
environment by using software flags or in straight-line Baud XTAL1 Frequency
code by using the Interrupt Pending register to signal Rate
8.0 MHz 10.0 MHz 12.0 MHz
the completion of a reception.
300 1666 / b 0.02 2082 / 0.02 2499 / 0.00
In the asynchronous modes, writing to SBUF (TX) 1200 416 / b 0.08 520 / b 0.03 624 / 0.00
starts a transmission. A falling edge on RXD will begin 2400 207 / 0.16 259 / 0.16 312 / b 0.16
a reception if REN is set to 1. New data placed in 4800 103 / 0.16 129 / 0.16 155 / 0.16
SBUF (TX) is held and will not be transmitted until the 9600 51 / 0.16 64 / 0.16 77 / 0.16
end of the stop bit has been sent. 19.2K 25 / 0.16 32 / 1.40 38 / 0.16
In all modes, the RI flag is set after the last data bit is Baud Register Value / % Error
sampled approximately in the middle of the bit time.
Also for all modes, the TI flag is set after the last data A maximum baud rate of 750 Kbaud is available in the
bit (either 8th or 9th) is sent, also in the middle of the asynchronous modes with 12 MHz on XTAL1. The
bit time. The flags clear when SPÐSTAT is read, but synchronous mode has a maximum rate of 3.0 Mbaud
do not have to be clear for the port to receive or trans- with a 12 MHz clock. Location 0EH is the Baud Regis-
mit. The serial port interrupt bit is set as a logical OR ter. It is loaded sequentially in two bytes, with the low
of the RI and TI bits. Note that changing modes will byte being loaded first. This register may not be loaded
reset the Serial Port and abort any transmission or re- with zero in serial port Mode 0.
ception in progress on the channel.

48
80C196KB USER’S GUIDE

10.2 Serial Port Interrupts mode the TXD pin outputs a set of 8 pulses while the
RXD pin either transmits or receives data. Data is
The serial port generates one of three possible inter- transferred 8 bits at a time with the LSB first. A dia-
rupts: Transmit Interrupt TI(2030H), Receive Inter- gram of the relative timing of these signals is shown in
rupt RI(2032H) and SERIAL(200CH). When the RI Figure 10-2. Note that this is the only mode which uses
bit gets set an interrupt is generated through either RXD as an output.
200CH or 2032H depending on which interrupt is en-
abled. INTÐMASK1.1 controls the serial port receive
interrupt through location 2032H and INTÐMASK.6 Mode 0 Timings
controls serial port interrupts through location 200CH. In Mode 0, the TXD pin sends out a clock train, while
The 8096BH shared the TI and RI interrupts on the the RXD pin transmits or receives the data. Figure 10-
SERIAL interrupt vector. On the 80C196KB, these in- 2 shows the waveforms and timing.
terrupts share both the serial interrupt vector and have
their own interrupt vectors. In this mode the serial port expands the I/O capability
of the 80C196KB by simply adding shift registers. A
When the TI bit is set it can cause an interrupt through schematic of a typical circuit is shown in Figure 10-3.
the vectors at locations 200CH or 2030. Interrupt This circuit inverts the data coming in, so it must be
through location 2030 is determined by INTÐ reinverted in software.
MASK1.0. Interrupts through the serial interrupt is
controlled by the same bit as the RI interrupt(INTÐ
MASK.6). The user should not mask off the serial port MODE 1
interrupt when using the double-buffered feature of the
transmitter, as it could cause a missed count in the Mode 1 is the standard asynchronous communications
number of bytes being transmitted. mode. The data frame used in this mode is shown in
Figure 10-4. It consists of 10 bits; a start bit (0), 8 data
bits (LSB first), and a stop bit (1). If parity is enabled
10.3 Serial Port Modes by setting SPCON.2, an even parity bit is sent instead
of the 8th data bit and parity is checked on reception.
MODE 0
Mode 0 is a synchronous mode which is commonly
used for shift register based I/O expansion. In this

270651 – 28

Figure 10-2. Mode 0 Timing

49
80C196KB USER’S GUIDE

270651 – 29

Figure 10-3. Typical Shift Register Circuit

270651 – 30

270651 – 31

Figure 10-4. Serial Port Frames, Mode 1, 2, and 3

The transmit and receive functions are controlled by port will hold off transmission until the stop bit is com-
separate shift clocks. The transmit shift clock starts plete. RI is set when 8 data bits are received, not when
when the baud rate generator is initialized, the receive the stop bit is received. Note that when the serial port
shift clock is reset when a ‘1 to 0’ transition (start bit) is status register is read both TI and RI are cleared.
received. The transmit clock may therefore not be in
sync with the receive clock, although they will both be Caution should be used when using the serial port to
at the same frequency. connect more than two devices in half-duplex, (i.e. one
wire for transmit and receive). If the receiving proces-
The TI (Transmit Interrupt) and RI (Receive Inter- sor does not wait for one bit time after RI is set before
rupt) flags are set to indicate when operations are com- starting to transmit, the stop bit on the link could be
plete. TI is set when the last data bit of the message has corrupted. This could cause a problem for other devices
been sent, not when the stop bit is sent. If an attempt to listening on the link.
send another byte is made before the stop bit is sent the

50
80C196KB USER’S GUIDE

MODE 2 bit is set. Two types of frames are used: address frames
which have the 9th bit set and data frames which have
Mode 2 is the asynchronous 9th bit recognition mode. the 9th bit cleared. When the master processor wants to
This mode is commonly used with Mode 3 for multi- transmit a block of data to one of several slaves, it first
processor communications. Figure 10-4 shows the data sends out an address frame which identifies the target
frame used in this mode. It consists of a start bit (0), 9 slave. Slaves in Mode 2 will not be interrupted by a data
data bits (LSB first), and a stop bit (1). When transmit- frame, but an address frame will interrupt all slaves.
ting, the 9th bit can be set to a one by setting the TB8 Each slave can examine the received byte and see if it is
bit in the control register before writing to SBUF (TX). being addressed. The addressed slave switches to Mode
The TB8 bit is cleared on every transmission, so it must 3 to receive the coming data frames, while the slaves
be set prior to writing to SBUF (TX). During recep- that were not addressed stay in Mode 2 continue exe-
tion, the serial port interrupt and the Receive Interrupt cuting.
will not occur unless the 9th bit being received is set.
This provides an easy way to have selective reception
on a data link. Parity cannot be enabled in this mode. 11.0 A/D CONVERTER
Analog Inputs to the 80C196KB System are handled
MODE 3 by the A/D converter System. As shown in Figure
11-4, the converter system has an 8 channel multiplex-
Mode 3 is the asynchronous 9th bit mode. The data
er, a sample-and-hold, and a 10 bit successive approxi-
frame for this mode is identical to that of Mode 2. The
mation A/D converter. Conversions can be performed
transmission differences between Mode 3 and Mode 2
on one of eight channels, the inputs of which share pins
are that parity can be enabled (PEN e 1) and cause the
with port 0. A conversion can be done in as little as 91
9th data bit to take the even parity value. The TB8 bit state times.
can still be used if parity is not enabled (PEN e 0).
When in Mode 3, a reception always causes an inter- Conversions are started by loading the ADÐCOM-
rupt, regardless of the state of the 9th bit. The 9th bit is MAND register at location 02H with the channel num-
stored if PEN e 0 and can be read in bit RB8. If ber. The conversion can be started immediately by set-
PEN e 1 then RB8 becomes the Receive Parity Error ting the GO bit to a one. If it is cleared the conversion
(RPE) flag. will start when the HSO unit triggers it. The A/D com-
mand register must be written to for each conversion,
Mode 2 and 3 Timings even if the HSO is used as the trigger. The result of
the conversion is read in the ADÐRESULT(High)
Modes 2 and 3 operate in a manner similar to that of and ADÐRESULT(Low) registers. The ADÐRE-
Mode 1. The only difference is that the data is now SULT(High) contains the most significant eight bits of
made up of 9 bits, so 11-bit packages are transmitted the conversion. The ADÐRESULT(Low) register con-
and received. This means that TI and RI will be set on tains the remaining two bits and the A/D channel num-
the 9th data bit rather than the 8th. The 9th bit can be ber and A/D status. The format for the ADÐCOM-
used for parity or multiple processor communications. MAND register is shown in Figure 11-1. In Window
15, reading the ADÐCOMMAND register will read
the last command written. Writing to the ADÐRE-
10.4 Multiprocessor Communications SULT register will write a value into the result register.

Mode 2 and 3 are provided for multiprocessor commu-

nications. In Mode 2 if the received 9th data bit is zero,
the RI bit is not set and will not cause an interrupt. In
Mode 3, the RI bit is set and always causes an interrupt
regardless of the value in the 9th bit. The way to use
this feature in multiprocessor systems is described be-
low.

The master processor is set to Mode 3 so it always gets

interrupts from serial receptions. The slaves are set in
Mode 2 so they only have receive interrupts if the 9th 270651 – 33

Figure 11-1. A/D Command Register

51
80C196KB USER’S GUIDE

The A/D converter can cause an interrupt through the started. The upper byte of the result register contains
vector at location 2002H when it completes a conver- the most significant 8 bits of the conversion. The lower
sion. It is also possible to use a polling method by byte format is shown in Figure 11-2.
checking the Status (S) bit in the lower byte of the
ADÐRESULT register, also at location 02H. The At high crystal frequencies, more time is needed to al-
status bit will be a 1 while a conversion is in progress. It low the comparator to settle. For this reason IOC2.4 is
takes 8 state times to set this bit after a conversion is provided to adjust the speed of the A/D conversion by
disabling/enabling a clock prescaler.

A summary of the conversion time for the two options

is shown below. The numbers represent the number of
state times required for conversion, e.g., 91 states is
22.7 ms with an 8 MHz XTAL1 (providing a 250 ns
state time.)

Clock Prescaler On Clock Prescaler Off

IOC2.4 e 0 IOC2.4 e 1
158 States 91 States
26.33 ms @ 12 MHz 22.75 ms @ 8 MHz.
Figure 11-3. A/D Conversion Times
270651 – 32

Figure 11-2. A/D Result Lo Register

270651 – 34

Figure 11-4. A/D Converter Block Diagram

52
80C196KB USER’S GUIDE

11.1 A/D Conversion Process The total number of state times required for a conver-
sion is determined by the setting of IOC2.4 clock pre-
The conversion process is initiated by the execution of scaler bit. With the bit set the conversion time is 91
HSO command 0FH, or by writing a one to the GO Bit states and 158 states when the bit is cleared.
in the A/D Control Register. Either activity causes a
start conversion signal to be sent to the A/D converter
control logic. If an HSO command was used, the con- 11.2 A/D Interface Suggestions
version process will begin when Timer1 increments.
This aids applications attempting to approach spectral- The external interface circuitry to an analog input is
ly pure sampling, since successive samples spaced by highly dependent upon the application, and can impact
equal Timer1 delays will occur with a variance of about converter characteristics. In the external circuit’s de-
g 50 ns (assuming a stable clock on XTAL1). Howev- sign, important factors such as input pin leakage, sam-
er, conversions initiated by writing a one to the AD- ple capacitor size and multiplexer series resistance from
CON register GO Bit will start within three state times the input pin to the sample capacitor must be consid-
after the instruction has completed execution resulting ered.
in a variance of about 0.50 ms (XTAL1 e 12 MHz).
For the 80C196KB, these factors are idealized in Fig-
Once the A/D unit receives a start conversion signal, ure 11-5. The external input circuit must be able to
there is a one state time delay before sampling (Sample charge a sample capacitor (CS) through a series resist-
Delay) while the successive approximation register is ance (RI) to an accurate voltage given a D.C. leakage
reset and the proper multiplexer channel is selected. (IL). On the 80C196KB, CS is around 2 pF, RI is
After the sample delay, the multiplexer output is con- around 5 KX and IL is specified as 3 mA maximum. In
nected to the sample capacitor and remains connected determining the necessary source impedance RS, the
for 8 state times in fast mode or 15 state times for slow value of VBIAS is not important.
mode (Sample Time). After this 8/15 state time ‘‘sam-
ple window’’ closes, the input to the sample capacitor is
disconnected from the multiplexer so that changes on
the input pin will not alter the stored charge while the
conversion is in progress. The comparator is then auto-
zeroed and the conversion begins. The sample delay
and sample time uncertainties are each approximately
g 50 ns, independent of clock speed.

To perform the actual analog-to-digital conversion the

80C196KB implements a successive approximation al- 270651 – 35
gorithm. The converter hardware consists of a 256-re-
sistor ladder, a comparator, coupling capacitors and a Figure 11-5. Idealized A/D Sampling Circuitry
10-bit successive approximation register (SAR) with
logic that guides the process. The resistor ladder pro- External circuits with source impedances of 1 KX or
vides 20 mV steps (VREF e 5.12V), while capacitive less will be able to maintain an input voltage within a
coupling creates 5 mV steps within the 20 mV ladder tolerance of about g 0.61 LSB (1.0 KX c 3.0 mA e
voltages. Therefore, 1024 internal reference voltages are 3.0 mV) given the D.C. leakage. Source impedances
available for comparison against the analog input to above 2 KX can result in an external error of at least
generate a 10-bit conversion result. one LSB due to the voltage drop caused by the 3 mA
leakage. In addition, source impedances above 25 KX
A successive approximation conversion is performed by may degrade converter accuracy as a result of the inter-
comparing a sequence of reference voltages, to the ana- nal sample capacitor not being fully charged during the
log input, in a binary search for the reference voltage 1 ms (12 MHz clock) sample window.
that most closely matches the input. The (/2 full scale
reference voltage is the first tested. This corresponds to If large source impedances degrade converter accuracy
a 10-bit result where the most significant bit is zero, because the sample capacitor is not charged during the
and all other bits are ones (0111.1111.11b). If the ana- sample time, an external capacitor connected to the pin
log input was less than the test voltage, bit 10 of the compensates for this. Since the sample capacitor is
SAR is left a zero, and a new test voltage of (/4 full scale 2 pF, a 0.005 mF capacitor (2048 * 2 pF) will charge
(0011.1111.11b) is tried. If this test voltage was lower the sample capacitor to an accurate input voltage of
than the analog input, bit 9 of the SAR is set and bit 8 g 0.5 LSB. An external capacitor does not compensate
is cleared for the next test (0101.1111.11b). This binary for the voltage drop across the source resistance, but
search continues until 10 tests have occurred, at which charges the sample capacitor fully during the sample
time the valid 10-bit conversion result resides in the time.
SAR where it can be read by software.

53
80C196KB USER’S GUIDE

Placing an external capacitor on each analog input will ANGND must be connected even if the A/D converter
also reduce the sensitivity to noise, as the capacitor is not being used. Remember that Port 0 receives its
combines with series resistance in the external circuit to power from the VREF and ANGND pins even when it
form a low-pass filter. In practice, one should include a is used as digital I/O.
small series resistance prior to the external capacitor on
the analog input pin and choose the largest capacitor
value practical, given the frequency of the signal being 11.3 The A/D Transfer Function
converted. This provides a low-pass filter on the input,
while the resistor will also limit input current during The conversion result is a 10-bit ratiometric representa-
over-voltage conditions. tion of the input voltage, so the numerical value ob-
tained from the conversion will be:
Figure 11-6 shows a simple analog interface circuit
based upon the discussion above. The circuit in the fig- INT [1023 c (VIN b ANGND)/(VREF b ANGND)].
ure also provides limited protection against over-volt-
age conditions on the analog input. Should the input This produces a stair-stepped transfer function when
voltage inappropriately drop significantly below the output code is plotted versus input voltage (see Fig-
ground, diode D2 will forward bias at about 0.8 DCV. ure 11-7). The resulting digital codes can be taken as
Since the specification of the pin has an absolute maxi- simple ratiometric information, or they provide infor-
mum low voltage of b 0.3V, this will leave about 0.5V mation about absolute voltages or relative voltage
across the 270X resistor, or about 2 mA of current. changes on the inputs. The more demanding the appli-
This should limit the current to a safe amount. cation is on the A/D converter, the more important it
is to fully understand the converter’s operation. For
However, before any circuit is used in an actual applica- simple applications, knowing the absolute error of the
tion, it should be thoroughly analyzed for applicability to converter is sufficient. However, closing a servo-loop
the specific problem at hand. with analog inputs necessitates a detailed understand-
ing of an A/D converter’s operation and errors.

The errors inherent in an analog-to-digital conversion

process are many: quantizing error, zero offset, full-
scale error, differential non-linearity, and non-linearity.
These are ‘‘transfer function’’ errors related to the A/D
converter. In addition, converter temperature drift,
VCC rejection, sample-hold feedthrough, multiplexer
off-isolation, channel-to-channel matching and random
noise should be considered. Fortunately, one ‘‘Absolute
Error’’ specification is available which describes the
270651 – 36 sum total of all deviations between the actual conver-
sion process and an ideal converter. However, the vari-
Figure 11-6. Suggested A/D Input Circuit ous sub-components of error are important in many
applications. These error components are described in
Section 11.5 and in the text below where ideal and actu-
ANALOG REFERENCES
al converters are compared.
Reference supply levels strongly influence the absolute
accuracy of the conversion. For this reason, it is recom- An unavoidable error simply results from the conver-
mended that the ANGND pin be tied to the two VSS sion of a continuous voltage to an integer digital repre-
pins at the power supply. Bypass capacitors should also sentation. This error is called quantizing error, and is
be used between VREF and ANGND. ANGND should always g 0.5 LSB. Quantizing error is the only error
be within about a tenth of a volt of VSS. VREF should seen in a perfect A/D converter, and is obviously pres-
be well regulated and used only for the A/D converter. ent in actual converters. Figure 11-7 shows the transfer
The VREF supply can be between 4.5V and 5.5V and function for an ideal 3-bit A/D converter (i.e. the Ideal
needs to be able to source around 5 mA. See Section 13 Characteristic).
for the minimum hardware connections.
Note that in Figure 11-7 the Ideal Characteristic pos-
Note that if only ratiometric information is desired, sesses unique qualities: it’s first code transition occurs
VREF can be connected to VCC. In addition, VREF and when the input voltage is 0.5 LSB; it’s full-scale code
transition occurs when the input voltage equals the full-

54
80C196KB USER’S GUIDE

270651– 37

Figure 11-7. Ideal A/D Characteristic

55
80C196KB USER’S GUIDE

270651– 38

Figure 11-8. Actual and Ideal Characteristics

56
80C196KB USER’S GUIDE

270651– 39

Figure 11-9. Terminal Based Characteristic

57
80C196KB USER’S GUIDE

scale reference minus 1.5 LSB; and it’s code widths are Undesired signals come from three main sources. First,
all exactly one LSB. These qualities result in a digitiza- noise on VCCÐVCC Rejection. Second, input signal
tion without offset, full-scale or linearity errors. In oth- changes on the channel being converted after the sam-
er words, a perfect conversion. ple window has closedÐFeedthrough. Third, signals
applied to channels not selected by the multiplexerÐ
Figure 11-8 shows an Actual Characteristic of a hypo- Off-Isolation.
thetical 3-bit converter, which is not perfect. When the
Ideal Characteristic is overlaid with the imperfect char- Finally, multiplexer on-channel resistances differ slight-
acteristic, the actual converter is seen to exhibit errors ly from one channel to the next causing Channel-to-
in the location of the first and final code transitions and Channel Matching errors, and random noise in general
code widths. The deviation of the first code transition results in Repeatability errors.
from ideal is called ‘‘zero offset’’, and the deviation of
the final code transition from ideal is ‘‘full-scale error’’.
The deviation of the code widths from ideal causes two 11.4 A/D Glossary of Terms
types of errors. Differential Non-Linearity and Non-
Linearity. Differential Non-Linearity is a local linearity Figures 11-7, 11-8, and 11-9 display many of these
error measurement, whereas Non-Linearity is an over- terms. Refer to AP-406 ‘MCS-96 Analog Acquisition
all linearity error measure. Primer‘ for additional information on the A/D terms.

Differential Non-Linearity is the degree to which actual ABSOLUTE ERRORÐThe maximum difference be-
code widths differ from the ideal one LSB width. It tween corresponding actual and ideal code transitions.
gives the user a measure of how much the input voltage Absolute Error accounts for all deviations of an actual
may have changed in order to produce a one count converter from an ideal converter.
change in the conversion result. Non-Linearity is the
worst case deviation of code transitions from the corre- ACTUAL CHARACTERISTICÐThe characteristic of
sponding code transitions of the Ideal Characteristic. an actual converter. The characteristic of a given con-
Non-Linearity describes how much Differential Non- verter may vary over temperature, supply voltage, and
Linearities could add up to produce an overall maxi- frequency conditions. An Actual Characteristic rarely
mum departure from a linear characteristic. If the Dif- has ideal first and last transition locations or ideal code
ferential Non-Linearity errors are too large, it is possi- widths. It may even vary over multiple conversion un-
ble for an A/D converter to miss codes or exhibit non- der the same conditions.
monotonicity. Neither behavior is desirable in a closed-
loop system. A converter has no missed codes if there BREAK-BEFORE-MAKEÐThe property of a multi-
exists for each output code a unique input voltage range plexer which guarantees that a previously selected
that produces that code only. A converter is monotonic channel will be deselected before a new channel is se-
if every subsequent code change represents an input lected. (e.g. the converter will not short inputs togeth-
voltage change in the same direction. er.)

Differential Non-Linearity and Non-Linearity are CHANNEL-TO-CHANNEL MATCHINGÐThe dif-

quantified by measuring the Terminal Based Linearity ference between corresponding code transitions of actu-
Errors. A Terminal Based Characteristic results when al characteristics taken from different channels under
an Actual Characteristic is shifted and rotated to elimi- the same temperature, voltage and frequency condi-
nate zero offset and full-scale error (see Figure 11-9). tions.
The Terminal Based Characteristic is similar to the Ac-
tual Characteristic that would be seen if zero offset and CHARACTERISTICÐA graph of input voltage ver-
full-scale error were externally trimmed away. In prac- sus the resultant output code for an A/D converter. It
tice, this is done by using input circuits which include describes the transfer function of the A/D converter.
gain and offset trimming. In addition, VREF on the
80C196KB could also be closely regulated and trimmed CODEÐThe digital value output by the converter.
within the specified range to affect full-scale error.
CODE CENTERÐThe voltage corresponding to the
Other factors that affect a real A/D Converter system midpoint between two adjacent code transitions.
include sensitivity to temperature, failure to completely
reject all unwanted signals, multiplexer channel dissim- CODE TRANSITIONÐThe point at which the con-
ilarities and random noise. Fortunately these effects are verter changes from an output code of Q, to a code of
small. Q a 1. The input voltage corresponding to a code tran-
sition is defined to be that voltage which is equally like-
Temperature sensitivities are described by the rate at ly to produce either of two adjacent codes.
which typical specifications change with a change in
temperature. CODE WIDTHÐThe voltage corresponding to the
difference between two adjacent code transitions.

58
80C196KB USER’S GUIDE

CROSSTALKÐSee ‘‘Off-Isolation’’. REPEATABILITYÐThe difference between corre-

sponding code transitions from different actual charac-
D.C. INPUT LEAKAGEÐLeakage current to ground teristics taken from the same converter on the same
from an analog input pin. channel at the same temperature, voltage and frequency
conditions.
DIFFERENTIAL NON-LINEARITYÐThe differ-
ence between the ideal and actual code widths of the RESOLUTIONÐThe number of input voltage levels
terminal based characteristic of a converter. that the converter can unambiguously distinguish be-
tween. Also defines the number of useful bits of infor-
FEEDTHROUGHÐAttenuation of a voltage applied mation which the converter can return.
on the selected channel of the A/D converter after the
sample window closes. SAMPLE DELAYÐThe delay from receiving the start
conversion signal to when the sample window opens.
FULL SCALE ERRORÐThe difference between the
expected and actual input voltage corresponding to the SAMPLE DELAY UNCERTAINTYÐThe variation
full scale code transition. in the Sample Delay.

IDEAL CHARACTERISTICÐA characteristic with SAMPLE TIMEÐThe time that the sample window is
its first code transition at VIN e 0.5 LSB, its last code open.
transition at VIN e (VREF b 1.5 LSB) and all code
widths equal to one LSB. SAMPLE TIME UNCERTAINTYÐThe variation in
the sample time.
INPUT RESISTANCEÐThe effective series resistance
from the analog input pin to the sample capacitor. SAMPLE WINDOWÐBegins when the sample capac-
itor is attached to a selected channel and ends when the
LSBÐLEAST SIGNIFICANT BIT: The voltage value sample capacitor is disconnected from the selected
corresponding to the full scale voltage divided by 2n, channel.
where n is the number of bits of resolution of the con-
verter. For a 10-bit converter with a reference voltage SUCCESSIVE APPROXIMATIONÐAn A/D con-
of 5.12 volts, one LSB is 5.0 mV. Note that this is version method which uses a binary search to arrive at
different than digital LSBs, since an uncertainty of two the best digital representation of an analog input.
LSBs, when referring to an A/D converter, equals
10 mV. (This has been confused with an uncertainty of TEMPERATURE COEFFICIENTSÐChange in the
two digital bits, which would mean four counts, or stated variable per degree centigrade temperature
20 mV.) change. Temperature coefficients are added to the typi-
cal values of a specification to see the effect of tempera-
MONOTONICÐThe property of successive approxi- ture drift.
mation converters which guarantees that increasing in-
put voltages produce adjacent codes of increasing value, TERMINAL BASED CHARACTERISTICÐAn Ac-
and that decreasing input voltages produce adjacent tual Characteristic which has been rotated and translat-
codes of decreasing value. ed to remove zero offset and full-scale error.

NO MISSED CODESÐFor each and every output VCC REJECTIONÐAttenuation of noise on the VCC
code, there exists a unique input voltage range which line to the A/D converter.
produces that code only.
ZERO OFFSETÐThe difference between the expected
NON-LINEARITYÐThe maximum deviation of code and actual input voltage corresponding to the first code
transitions of the terminal based characteristic from the transition.
corresponding code transitions of the ideal characteris-
tics.

OFF-ISOLATIONÐAttenuation of a voltage applied

on a deselected channel of the A/D converter. (Also
referred to as Crosstalk.)

59
80C196KB USER’S GUIDE

12.0 I/O PORTS In addition to acting as a digital input, each line of Port
0 can be selected to be the input of the A/D converter
There are five 8-bit I/O ports on the 80C196KB. Some as discussed in Section 11. The capacitance on these
of these ports are input only, some are output only, pins is approximately 1 pF and will instantaneously in-
some are bidirectional and some have alternate func- crease by around 2 pF when the pin is being sampled by
tions. In addition to these ports, the HSI/O unit pro- the A/D converter.
vides extra I/O lines if the timer related features of
these lines are not needed. Port 0 pins are special in that they may individually be
used as digital inputs and analog inputs at the same
Port 0 is an input port which is also used as the analog time. A Port 0 pin being used as a digital input acts as
input for the A/D converter. Port 0 is read at location the high impedance input ports just described. Howev-
0EH. Port 1 is a quasi-bidirectional port and is read or er, Port 0 pins being used as analog inputs are required
written to through location 0FH. The three most signif- to provide current to the internal sample capacitor
icant bits of Port 1 are the control signals for the when a conversion begins. This means that the input
HOLD/HLDA bus port pins. Port 2 contains three characteristics of a pin will change if a conversion is
types of port lines: quasi-bidirectional, input and out- being done on that pin. In either case, if Port 0 is to be
put. Port2 is read or written from location 10H. The used as analog or digital I/O, it will be necessary to
ports cannot be read or written in Window 15. The provide power to this port through the VREF pin and
input and output lines are shared with other functions ANGND pins.
in the 80C196KB as shown in Figure 12-1. Ports 3 and
4 are open-drain bidirectional ports which share their Port 0 is only sampled when the SFR is read to reduce
pins with the address/data bus. On EPROM and ROM the noise in the A/D converter. The data must be stable
parts, Port 3 and 4 are read and written through loca- one state time before the SFR is read.
tion 1FFEH.

ALTERNATE CONTROL
PIN FUNC.
FUNCTION REG.
2.0 Output TXD (Serial Port Transmit) IOC1.5
2.1 Input RXD (Serial Port Receive) SPCON.3
P2.2 Input EXTINT IOC1.1
2.3 Input T2CLK (Timer2 Clock & Baud) IOC0.7
2.4 Input T2RST (Timer2 Reset) IOC0.5
2.5 Output PWM Output IOC1.0
2.6 QBD* Timer2 up/down select IOC2.1
2.7 QBD* Timer2 Capture N/A
*QBD e Quasi-bidirectional
Figure 12-1. Port 2 Multiple Functions
270651 – 76
While discussing the characteristics of the I/O pins
some approximate current or voltage specifications will NOTE:
be given. The exact specifications are available in the *Q1 and Q2 are ESD Protection Devices
latest version of the data sheet that corresponds to the
part being used. Figure 12-2. Input Port Structure

12.1 Input Ports 12.2 Quasi-Bidirectional Ports

Input ports and pins can only be read. There are no Port 1 and Port 2 have quasi-bidirectional I/O pins.
output drivers on these pins. The input leakage of these When used as inputs the data on these pins must be
pins is in the microamp range. The specific values can stable one state time prior to reading the SFR. This
be found in the data sheet for the device being consid- timing is also valid for the input-only pins of Port 2 and
ered. Figure 12-2 shows the input port structure. is similar to the HSI in that the sample occurs during
PH1 or during CLKOUT low. When used as outputs,
The high impedance input pins on the 80C196KB have the quasi-bidirectional pins will change state shortly af-
an input leakage of a few microamps and are predomi- ter CLKOUT falls. If the change was from ‘0’ to a ‘1’
nantly capacitive loads on the order of 10 pF.

60
80C196KB USER’S GUIDE

270651 – 40
CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q makes a 0-to-1 transition. During this time, pFET 1
also turns on pFET 3 through the inverter to form a latch which holds the 1. pFET 2 is also on.

Figure 12-3. CHMOS Quasi-Bidirectional Port Circuit

the low impedance pullup will remain on for one state turns on for two oscillator periods. P2 remains on until
time after the change. a zero is written to the pin. P3 is used as a latch, so it is
turned on whenever the pin is above the threshold value
Port 1, Port 2.6 and Port 2.7 are quasi-bidirectional (around 2 volts).
ports. When the processor writes to the pins of a quasi-
bidirectional port it actually writes into a register which To reduce the amount of current which flows when the
in turn drives the port pin. When the processor reads pin is externally pulled low, P3 is turned off when the
these ports, it senses the status of the pin directly. If a pin voltage drops below the threshold. The current re-
port pin is to be used as an input then the software quired to pull the pin from a high to a low is at its
should write a one to its associated SFR bit, this will maximum just prior to the pull-up turning off. An ex-
cause the low-impedance pull-down device to turn off ternal driver can switch these pins easily. The maxi-
and leave the pin pulled up with a relatively high im- mum current required occurs at the threshold voltage
pedance pullup device which can be easily driven down and is approximately 700 microamps.
by the device driving the input.
When the Port 1 pins are used as their alternate func-
If some pins of a port are to be used as inputs and some tions (HOLD, HLDA, and BREQ), the pins act like a
are to be used as outputs the programmer should be standard output port.
careful when writing to the port.

Particular care should be exercised when using XOR HARDWARE CONNECTION HINTS
opcodes or any opcode which is a read-modify-write
When using the quasi-bidirectional ports as inputs tied
instruction. It is possible for a Quasi-Bidirectional Pin
to switches, series resistors may be needed if the ports
to be written as a one, but read back as a zero if an
will be written to internally after the part is initialized.
external device (i.e., a transistor base) is pulling the pin
The amount of current sourced to ground from each
below VIH.
pin is typically 7 mA or more. Therefore, if all 8 pins
are tied to ground, 56 mA will be sourced. This is
Quasi-bidirectional pins can be used as input and out- equivalent to instantaneously doubling the power used
put pins without the need for a data direction register. by the chip and may cause noise in some applications.
They output a strong low value and a weak high value.
The weak high value can be externally pulled low pro- This potential problem can be solved in hardware or
viding an input function. Figure 12-3 shows the config- software. In software, never write a zero to a pin being
uration of a CHMOS quasi-bidirectional port. used as an input.
Outputting a 0 on a quasi-bidirectional pin turns on the In hardware, a 1K resistor in series with each pin will
strong pull-down and turns off all of the pull-ups. limit current to a reasonable value without impeding
When a 1 is output the pull-down is turned off and 3 the ability to override the high impedance pullup. If all
pull-ups (strong-P1, weak-P3, very weak-P2) are turned 8 pins are tied together a 120X resistor would be rea-
on. Each time a pin switches from 0 to 1 transistor P1 sonable. The problem is not quite as severe when the

61
80C196KB USER’S GUIDE

inputs are tied to electronic devices instead of switches, the voltage present on the port pin. The second case can
as most external pulldowns will not hold 20 mA to 0.0 be taken care of in the software fairly easily:
volts.
LDB AL, IOPORT1
Writing to a Quasi-Bidirectional Port with electronic XORB AL, #010B
devices attached to the pins requires special attention. ORB AL, #001B
Consider using P1.0 as an input and trying to toggle STB AL, IOPORT1
P1.1 as an output:
A software solution to both cases is to keep a byte in
ORB IOPORT1, #00000001B ; Set P1.0 RAM as an image of the data to be output to the port;
; for input any time the software wants to modify the data on the
XORB IOPORT1, #00000010B ; Complement port it can then modify the image byte and copy it to
; P1.1 the port.

The first instruction will work as expected but two If a switch is used on a long line connected to a quasi-
problems can occur when the second instruction exe- bidirectional pin, a pullup resistor is recommended to
cutes. The first is that even though P1.1 is being driven reduce the possibility of noise glitches and to decrease
high by the 80C196KB it is possible that it is being held the rise time of the line. On extremely long lines that
low externally. This typically happens when the port are handling slow signals, a capacitor may be helpful in
pin drives the base of an NPN transistor which in turn addition to the resistor to reduce noise.
drives whatever there is in the outside world which
needs to be toggled. The base of the transistor will
clamp the port pin to the transistor’s Vbe above 12.3 Output Ports
ground, typically 0.7V. The 80C196KB will input this
value as a zero even if a one has been written to the port Output pins include the bus control lines, the HSO
pin. When this happens the XORB instruction will al- lines, and some of Port 2. These pins can only be used
ways write a one to the port pin’s SFR and the pin will as outputs as there are no input buffers connected to
not toggle. them. The output pins are output before the rising edge
of PH1 and is valid some time during PH1. Externally,
The second problem, which is related to the first, is that PH1 corresponds to CLKOUT low. It is not possible to
if P1.0 happens to be driven to a zero when Port 1 is use immediate logical instructions such as XOR to tog-
read by the XORB instruction, then the XORB will gle these pins.
write a zero to P1.0 and it will no longer be useable as
an input. The control outputs and HSO pins have output buffers
with the same output characteristics as those of the bus
The first situation can best be solved by the external pins. Included in the category of control outputs are:
driver design. A series resistor between the port pin and TXD, RXD (in Mode 0), PWM, CLKOUT, ALE,
the base of the transistor often works by bringing up BHE, RD, and WR. The bus pins have 3 states: output
high, output low, and high impedance. Figure 12-4
shows the internal configuration of an output pin.

270651 – 77

Figure 12-4. Output Port

62
80C196KB USER’S GUIDE

12.4 Ports 3 and 4/AD0–15 be used as inputs. Reading Port 3 and 4 from a previ-
ously written zero condition is as follows . . .
These pins have two functions. They are either bidirec-
tional ports with open-drain outputs or System Bus LD intregA, #0FFFFH ; setup port
pins which the memory controller uses when it is ac- ; change mode
cessing off-chip memory. If the EA line is low, the pins ; pattern
always act as the System Bus. Otherwise they act as bus
pins only during a memory access. If these pins are ST intregA, 1FFEH ; register x
being used as ports and bus pins, ones must be written ; Port 3 and 4
to them prior to bus operations. ; LD & ST not
; needed if
Accessing Port 3 and 4 as I/O is easily done from inter- ; previously
nal registers. Since the LD and ST instructions require ; written as ones
the use of internal registers, it may be necessary to first
move the port information into an internal location be- LD intregB, 1FFEH ; register w
fore utilizing the data. If the data is already internal, ; Port 3 and 4
the LD is unnecessary. For instance, to write a word
value to Port 3 and 4 . . . Note that while the format of the LD and ST instruc-
tions are similar, the source and destination directions
LD intreg, portdata ; register w change.
; data
; not needed if When acting as the system bus the pins have strong
; already drivers to both VCC and VSS. These drivers are used
; internal whenever data is being output on the system bus and
are not used when data is being output by Ports 3 and
ST intreg, 1FFEH ; register x 4. The pins, external input buffers and pulldowns are
; Port 3 and 4 shared between the bus and the ports. The ports use
different output buffers which are configured as open-
To read Port 3 and 4 requires that ‘‘ones’’ be written to drain, and require external pullup resistors. (open-drain
the port registers to first setup the input port configura- is the MOS version of open-collector.) The port pins
tion circuit. Note that the ports are reset to this input and their system bus functions are shown in Figure
condition, but if zeroes have been written to the port, 12-5.
then ones must be re-written to any pins which are to

270651 – 41

Figure 12-5. Port 3, 4/AD0-15 Pins

63
80C196KB USER’S GUIDE

Ports 3 and 4 on the 80C196KB are open drain ports. follow good design and board layout techniques to keep
There is no pullup when these pins are used as I/O noise to a minimum. Liberal use of decoupling caps,
ports. A diagram of the output buffers connected to VCC and ground planes, and transient absorbers can all
Ports 3 and 4 and the bus pins is shown in Figure 12-5. be of great help. It is much easier to design a board
with these features then to search for random noise on
When Ports 3 and 4 are to be used as inputs, or as bus a poorly designed PC board. For more information on
pins, they must first be written with a ‘1’. This will put noise, refer to Applications Note AP-125, ‘Designing
the ports in a high impedance mode. When they are Microcontroller Systems for Noisy Environments’ in
used as outputs, a pullup resistor must be used external- the Embedded Control Application Handbook.
ly. A 15K pullup resistor will source a maximum of
0.33 milliamps, so it would be a reasonable value to
choose if no other circuits with pullups were connected 13.3 Oscillator and Internal Timings
to the pin.

Ports 3 and 4 are addressed as off-chip memory- ON-CHIP OSCILLATOR

mapped I/O. The port pins will change state shortly The on-chip oscillator circuitry for the 80C196KB, as
after the falling edge of CLKOUT. When these pins are shown in Figure 13.1, consists of a crystal-controlled,
used as Ports 3 and 4 they are open drains, their struc- positive reactance oscillator. In this application, the
ture is different when they are used as part of the bus. crystal is operated in its fundamental response mode as
an inductive reactance in parallel resonance with capac-
Port 3 and 4 can be reconstructed as I/O ports from the itance external to the crystal.
Address/Data bus. Refer to Section 15.7 for details.

13.0 MINIMUM HARDWARE

CONSIDERATIONS
The 80C196KB requires several external connections to
operate correctly. Power and ground must be connect-
ed, a clock source must be generated, and a reset circuit
must be present. We will look at each of these areas in
detail.

13.1 Power Supply

Power to the 80C196KB flows through 5 pins. VCC
supplies the positive voltage to the digital portion of the
chip while VREF supplies the A/D converter and Port0
with a positive voltage. These two pins need to be con- 270651 – 42
nected to a 5 volt power supply. When using the A/D
converter, it is desirable to connect VREF to a separate Figure 13-1. On-chip Oscillator Circuitry
power supply, or at least a separate trace to minimize
the noise in the A/D converter. The feedback resistor, Rf, consists of paralleled n-chan-
nel and p-channel FETs controlled by the PD (power-
The four common return pins, VSS1, VSS2, VSS3, and down) bit. Rf acts as an open when in Powerdown
Angd, must all be nominally at 0 volts. Even if the Mode. Both XTAL1 and XTAL2 also have ESD pro-
A/D converter is not being used, VREF and Angd must tection on the pins which is not shown in the figure.
still be connected for Port0 to function.
The crystal specifications and capacitance values in
Figure 13-2 are not critical. 20 pF is adequate for any
13.2 Noise Protection Tips frequency above 1 MHz with good quality crystals. Ce-
ramic resonators can be used instead of a crystal in cost
Due to the fast rise and fall times of high speed CMOS sensitive applications. For ceramic resonators, the man-
logic, noise glitches on the power supply lines and out- ufacturer should be contacted for values of the capaci-
puts at the chip are not uncommon. The 80C196KB is tors.
no exception to this rule. So it is extremely important to

64
80C196KB USER’S GUIDE

INTERNAL TIMINGS
Internal operation of the chip is based on the oscillator
frequency divided by two, giving the basic time unit,
known as a ‘state time‘. With a 12 Mhz crystal, a state
time is 167 nS. Since the 80C196KB can operate at
many frequencies, the times given throughout this over-
view will be in state times.

Two non-overlapping internal phases are created by the

clock generator: phase 1 and phase 2 as shown in Fig-
ure 13-4. CLKOUT is generated by the rising edge of
phase 1 and phase 2. This is not the same as the
8096BH, which uses a three phase clock. Changing
270651 – 43 from a three phase clock to a two phase one speeds up
operation for a set oscillator frequency. Consult the lat-
Figure 13-2. External Crystal Connections est data sheet for AC timing specifications.

To drive the 80C196KB with an external clock source,

apply the external clock signal to XTAL1 and let
XTAL2 float. An example of this circuit is shown in
Figure 13-3. The required voltage levels on XTAL1 are
specified in the data sheet. The signal on XTAL1 must
be clean with good solid levels.

It is important that the minimum high and low times

are met to avoid having the XTAL1 pin in the tran-
sition range for long periods of time. The longer the 270651 – 44
signal is in the transition region, the higher the proba-
bility that an external noise glitch could be seen by the Figure 13-4. Internal Clock Phases
clock generator circuitry. Noise glitches on the
80C196KB internal clock lines will cause unreliable op-
eration. 13.4 Reset and Reset Status
Reset starts the 80C196KB off in a known state. To
reset the chip, the RESET pin must be held low for at
least four state times after the power supply is within
tolerance and the oscillator has stabilized. As soon as
the RESET pin is pulled low, the I/O and control pins
are asynchronously driven to their reset condition.

After the RESET pin is brought high, a ten state reset

sequence occurs as shown in Figure 13-5. During this
time the CCB (Chip Configuration Byte) is read from
location 2018H and stored in the CCR (Chip Configu-
ration Register). The EA (External Access) pin quali-
fies whether the CCB is read from external or internal
memory. Figure 13-6 gives the reset status of all the
pins and Special Function Registers.

270651 – 78

Figure 13-3. External Clock Drive

65
80C196KB USER’S GUIDE

270651– 45
80C196KB Reset Sequence

Figure 13-5. Reset Sequence

66
80C196KB USER’S GUIDE

WATCHDOG TIMER RST INSTRUCTION

There are three ways in which the 80C196KB can reset Executing a RST instruction will also reset the
itself. The watchdog timer will reset the 80C196KB if it 80C196KB. The opcode for the RST instruction is
is not cleared in 64K state times. The watchdog timer is 0FFH. By putting pullups on the Addr/data bus, unim-
enabled the first time it is cleared. To clear the watch- plemented areas of memory will read 0FFH and cause
dog, write a ‘1E‘ followed immediately by an ‘E1‘ to the 80C196KB to be reset.
location 0AH. Once enabled, the watchdog can only be
disabled by a reset.

Pin Multiplexed Value of the Register Name Value

Name Port Pins Pin on Reset ADÐRESULT 7FF0H
RESET Mid-sized Pullup
HSIÐSTATUS x0x0x0x0B
ALE Weak Pullup
SBUF(RX) 00H
RD Weak Pullup
INTÐMASK 00000000B
BHE Weak Pullup
INTÐPENDING 00000000B
WR Weak Pullup
TIMER1 0000H
INST Weak Pullup
TIMER2 0000H
EA Undefined Input *
IOPORT1 11111111B
READY Undefined Input *
IOPORT2 11000001B
NMI Undefined Input *
SPÐSTAT/SPÐCON 00001011B
BUSWIDTH Undefined Input *
IMASK1 00000000B
CLKOUT Phase 2 of Clock
IPEND1 00000000B
System Bus P3.0–P4.7 Weak Pullups
WSR XXXX0000B
ACH0–7 P0.0–P0.7 Undefined Input *
HSIÐMODE 11111111B
PORT1 P1.0–P1.7 Weak Pullups
IOC2 X0000000B
TXD P2.0 Weak Pullup IOC0 000000X0B
RXD P2.1 Undefined Input *
IOC1 00100001B
EXTINT P2.2 Undefined Input * PWMÐCONTROL 00H
T2CLK P2.3 Undefined Input *
IOPORT3 11111111B
T2RST P2.4 Undefined Input * IOPORT4 11111111B
PWM P2.5 Weak Pulldown
IOS0 00000000B
Ð P2.6–P2.7 Weak Pullups
IOS1 00000000B
HSI0–HSI1 Undefined Input *
IOS2 00000000B
HSI2/HSO4 Undefined Input *
*These pins must be driven and not left floating.
HSI3/HSO5 Undefined Input *
HSO0–HSO3 Weak Pulldown

Figure 13-6. Chip Reset Status

67
80C196KB USER’S GUIDE

RESET CIRCUITS is only asserted for four state times. If this is done, it is
possible for the 80C196KB to start running before oth-
The simplest way to reset an 80C196KB is to insert a er chips in the system are out of reset. Software must
capacitor between the RESET pin and VSS. The take this condition into account. A capacitor cannot be
80C196KB has an internal pullup which has a value connected directly to RESET if it is to drive the reset
between 6K and 50K ohms. A 5 uF or greater capaci- pins of other chips in the circuit. The capacitor may
tor should provide sufficient reset time as long as Vcc keep the voltage on the pin from going below guaran-
rises quickly. teed VIL for circuits connected to the RESET pin. Fig-
ure 13-8 shows an example of a system reset circuit.
Figure 13-7 shows what the RESET pin looks like in-
ternally. The RESET pin functions as an input and as
an output to reset an entire system with a watchdog 13.5 Minimum Hardware Connections
timer overflow, or by executing a RST instruction. For
a system reset application, the reset circuit should be a Figure 13-9 shows the minimum connections needed to
one-shot with an open collector output. The reset pulse get the 80C196KB up and running. It is important to
may have to be lengthened and buffered since RESET tie all unused inputs to VCC or VSS. If these pins are

270651 – 46

Figure 13-7. Reset Pin

270651 – 47

NOTE:
1. The diode will provide a faster cycle time repetitive power-on-resets.

Figure 13-8. System Reset Circuit

68
80C196KB USER’S GUIDE

270651 – 48

NOTE:
*Must be driven high or low.
**VSS3 was formerly the CDE pin. The CDE function is no longer available. This pin must be connectd to VSS.

Figure 13-9. 80C196KB Minimum Hardware Connections

left floating, they can float to a mid voltage level and the CPU out of the Idle Mode, the CPU vectors to the
draw excessive current. Some pins such as NMI or corresponding interrupt service routine and begins exe-
EXTINT may generate spurious interrupts if left un- cuting. The CPU returns from the interrupt service
connected. routine to the next instruction following the ‘IDLPD
Ý1’ instruction that put the CPU in the Idle Mode.

14.0 SPECIAL MODES OF In the Idle Mode, the system bus control pins (ALE,
OPERATION RD, WR, INST, and BHE), go to their inactive states.
Ports 3 and 4 will retain the value present in their data
The 80C196KB has Idle and Powerdown Modes to re- latches if being used as I/O ports. If these ports are the
duce the amount of current consumed by the chip. The ADDR/DATA bus, the pins will float.
80C196KB also has an ONCE (ON-Circuit-Emulation)
Mode to isolate itself from the rest of the components It is important to note the Watchdog Timer continues
in the system. to run in the Idle Mode if it is enabled. So the chip
must be awakened every 64K state times to clear the
Watchdog or the chip will reset.
14.1 Idle Mode
The Idle Mode is entered by executing the instruction
‘IDLPD Ý1’. In the Idle Mode, the CPU stops execut-
14.2 Powerdown Mode
ing. The CPU clocks are frozen at logic state zero, but The Powerdown Mode is entered by executing the in-
the peripheral clocks continue to be active. CLKOUT struction, ‘IDLPD Ý2’. In the Powerdown Mode, all
continues to be active. Power consumption in the Idle internal clocks are frozen at logic state zero and the
Mode is reduced to about 40% of the active Mode. oscillator is shut off. All 232 bytes of registers and most
peripherals hold their values if VCC is maintained.
The CPU exits the Idle Mode by any enabled interrupt Power is reduced to the device leakage and is in the uA
source or a hardware reset. Since all of the peripherals range. The 87C196KB (EPROM part) will consume
are running, the interrupt can be generated by the HSI, more power if the EPROM window is not covered.
HSO, A/D, serial port, etc. When an interrupt brings

69
80C196KB USER’S GUIDE

270651 – 49

Figure 14-1. Power Up and Power Down Sequence

In Powerdown, the bus control pins go to their inactive If the external interrupt brings the chip out of Power-
states. All of the output pins will assume the value in down, the corresponding bit will be set in the interrupt
their data latches. Ports 3 and 4 will continue to act as pending register. If the interrupt is unmasked, the part
ports in the single chip mode or will float if acting as will immediately execute the interrupt service routine,
the ADDR/DATA bus. and return to the instruction following the IDLPD in-
struction that put the chip into Powerdown. If the in-
To prevent accidental entry into the Powerdown Mode, terrupt is masked, the chip will start at the instruction
this feature may be disabled at reset by clearing bit 0 of following the IDLPD instruction. The bit in the pend-
the CCR (Chip Configuration Register). Since the de- ing register will remain set, however.
fault value of the CCR bit 0 is 1, the Powerdown Mode
is normally enabled. All peripherals should be in an inactive state before
entering Powerdown. If the A/D converter is in the
The Powerdown Mode can be exited by a chip reset or middle of a conversion, it is aborted. If the chip comes
a high level on the external interrupt pin. If the RESET out of Powerdown by an external interrupt, the serial
pin is used, it must be asserted long enough for the port will continue where it left off. Make sure that the
oscillator to stabilize. serial port is done transmitting or receiving before en-
tering Powerdown. The SFRs associated with the A/D
When exiting Powerdown with an external interrupt, a and the serial port may also contain incorrect informa-
positive level on the pin mapped to INT7 (either tion when returning from Powerdown.
EXTINT or port0.7) will bring the chip out of Power-
down Mode. The interrupt does not have to be un- When the chip is in Powerdown, it is impossible for the
masked to exit Powerdown. An internal timing circuit watchdog timer to time out because its clock has
ensures that the oscillator has time to stabilize before stopped. Systems which must use the Watchdog and
turning on the internal clocks. Figure 14-1 shows the Powerdown, should clear the Watchdog right before
power down and power up sequence using an external entering Powerdown. This will keep the Watchdog
interrupt. from timing out when the oscillator is stabilizing after
leaving Powerdown.
During normal operation, before entering Powerdown
Mode, the VPP pin will rise to VCC through an internal
pullup. The user must connect a capacitor between VPP
14.3 ONCE and Test Modes
and VSS. A positive level on the external interrupt pin Test Modes can be entered on the 80C196KB by hold-
starts to discharge this capacitor. The internal current ing ALE, INST or RD in their active state on the rising
source that discharges the capacitor can sink approxi- edge of RESET. The only Test Mode not reserved for
mately 100 uA. When the voltage goes below about 1 use by Intel is the ONCE, or ON-Circuit-Emulation
volt on the VPP pin, the chip begins executing code. A Mode.
1uF capacitor would take about 4 ms to discharge to 1
volt.

70
80C196KB USER’S GUIDE

ONCE is entered by driving ALE high, INST low and Address Latch Enable (ALE) provides a strobe to
RD low on the rising edge of RESET. All pins except transparent latches (74AC373s) to demultiplex the bus.
XTAL1 and XTAL2 are floated. Some of the pins are To avoid confusion, the latched address signals will be
not truly high impedance as they have weak pullups or called MA0-MA15 and the data signals will be named
pulldowns. The ONCE Mode is useful in electrically MD0-MD15.
removing the 80C196KB from the rest of the system. A
typical application of the ONCE Mode would be to The data returned from external memory must be on
program discrete EPROMs onboard without removing the bus and stable for a specified setup time before the
the 80C196KB from its socket. rising edge of RD (read). The rising edge of RD signals
the end of the sampling window. Writing to external
ALE, INST, and RD are weakly pulled high or low memory is controlled with the WR (write) pin. Data is
during reset. It is important that a circuit does not in- valid on MD0-MD15 on the rising edge of WR. At this
advertantly drive these signals during reset, or a Test time data must be latched by the external system. The
Mode could be entered by accident. 80C196KB has ample setup and hold times for writes.

When BHE is asserted, the memory connected to the

15.0 EXTERNAL MEMORY high byte of the data bus is selected. When MA0 is a 0,
INTERFACING the memory connected to the low byte of the data bus is
selected. In this way accesses to a 16-bit wide memory
can be to the low (even) byte only (MA0 e 0, BHE e 1),
15.1 Bus Operation to the high (odd) byte only (MA0 e 1, BHE e 0), or the
both bytes (MA0 e 0, BHE e 0).
There are several different external operating modes on
the 80C196KB. The standard bus mode uses a 16 bit When a block of memory is decoded for reads only, the
multiplexed address/data bus. Other bus modes include system does not have to decode BHE and MA0. The
an 8 bit external bus mode and a mode in which the bus 80C196KB will discard the byte it does not need. For
size can be dynamically switched between 8-bits and systems that write to external memory, a system must
16-bits. In addition, there are several options available generate separate write strobes to both the high and low
on the type of bus control signals which make an exter- byte of memory. This is discussed in more detail later.
nal bus simple to design.
All of the external bus signals are gated by the rising
In the standard mode, external memory is addressed and falling edges of CLKOUT. A zero waitstate bus
through lines AD0-AD15 which form a 16 bit multi- cycle consists of two CLKOUT periods. Therefore,
plexed bus. The address/data bus shares pins with ports there are 4 clock edges that generate a complete bus
3 and 4. Figure 15-1 shows an idealized timing diagram cycle. The first falling edge of CLKOUT asserts ALE
for the external bus signals. and drives an address on the bus. The rising edge of

270651 – 50

Figure 15-1. Idealized Bus Timings

71
80C196KB USER’S GUIDE

CLKOUT drives ALE inactive. The next falling edge Mode. Before the CCB fetch, if the program memory is
of CLKOUT asserts RD (read) and floats the bus for a external, the CPU assumes that the bus is configured as
read cycle. During a WR (write) cycle, this edge asserts an 8-bit bus. In the 8-bit bus mode, during the CCB
WR and drives valid data on the bus. On the last rising fetch, address lines 8 – 15 use only the weak drivers.
edge of CLKOUT, data is latched into the 80C196KB However, in a 16-bit bus system, the external memory
for a read cycle, or data is valid for a write cycle. device will be driving the high byte of the bus while
outputting the CCB. This could cause bus contention if
location 2019H contains FFH. A value 20H in location
READY Pin 2019H will help prevent the contention.
The READY pin can insert wait states into the bus
cycle for interfacing to slow memory or peripherals. A
wait state is 2 Tosc in length. Since the bus is synchro-
nized to CLKOUT, it can only be held for an integral
number of waitstates. Because the 80C196KB is a com-
pletely static part, the number of waitstates that can be
inserted into a bus cycle is unbounded. Refer to the
next section for information on internally controlling
the number of waitstates inserted into a bus cycle.

There are several setup and hold times associated with

the READY signal. If these timings are not met, the
part may insert the incorrect number of waitstates.

INST Pin
The INST pin is useful for decoding more than 64K of 270651 – 51
addressing space. The INST pin allows both 64K of
code space and 64K of data space. For instruction Figure 15-2. Chip Configuration Register
fetches from external memory, the INST pin is assert-
ed, or high for the entire bus cycle. For data reads and
READY control
writes, the INST pin is low. The INST pin is low for
the Chip Configuration Byte fetch and for interrupt To simplify ready control, four modes of internal ready
vector fetches. control are available. The modes are chosen by bits 4
and 5 of the CCR and are shown in Figure 15-3.

15.2 Chip Configuration Register IRC1 IRC0 Description

The CCR (Chip Configuration Register) is the first 0 0 Limit to one wait state
byte fetched from memory following a chip reset. The
0 1 Limit to two wait states
CCR is fetched from the CCB (Chip Configuration
Byte) at location 2018H in either internal or external 1 0 Limit to three wait states
memory depending on the state of the EA pin. The 1 1 Wait states not limited internally
CCR is only written once during the reset sequence. Figure 15-3. Ready Control Modes
Once loaded, the CCR cannot be changed until the next
reset. The internal ready control logic limits the number of
waitstates that slow devices can insert into the bus cy-
The CCR is shown in Figure 15-2. The two most signif- cle. When the READY pin is pulled low, waitstates are
icant bits control the level of ROM/EPROM protec- inserted into the bus cycle until the READY pin goes
tion. ROM/EPROM protection is covered in the last high, or the number of waitstate equal the number pro-
section. The next two bits control the internal READY grammed into the CCR. So the ready control is a sim-
mode. The next three bits determine the bus control ple logical OR between the READY pin and the inter-
signals. The last bit enables or disables the Powerdown nal ready control.

72
80C196KB USER’S GUIDE

This feature gives very simple and flexible ready con- hardware. The ALE, WR, and BHE pins serve dual
trol. For example, every slow memory chip select line functions. Bits 2 and 3 of the CCR specify the function
could be ORed together and connected to the READY performed by these control lines.
pin with Internal Ready Control programmed to insert
the desired number of waitstates into the bus cycle.
Standard Bus Control
If the READY pin is pulled low during the CCR fetch,
If CCR bits 2 and 3 are 1s, the standard bus control
the bus controller will automatically insert 3 waitstates
signals ALE, WR, and BHE are generated as shown in
into the CCR bus cycle. This allows the CCR fetch to
Figure 15-4. ALE rises as the address starts to be driv-
come from slow memory without having to assert the
en, and falls to externally latch the address. WR is driv-
READY pin.
en for every write. BHE and MA0 can be combined to
form WRL and WRH for even and odd byte writes.
Bus Control

Using the CCR, the 80C196KB can generate several

types of control signals designed to reduce external

270651 – 52 270651 – 53
16-Bit Bus Cycle 8-Bit Bus Cycle

Figure 15-4. Standard Bus Control

270651 – 79

Figure 15-5. Decoding WRL and WRH

73
80C196KB USER’S GUIDE

Figure 15-5 is an example of external circuitry to de- Address Valid Strobe Mode
code WRL and WRH.
Address Valid strobe replaces ALE if CCR bit 3 is 0.
When Address valid Strobe mode is selected, ADV will
Write Strobe Mode be asserted after an external address is setup. It will
stay asserted until the end of the bus cycle as shown in
The Write Strobe Mode eliminates the need to external-
Figure 15-7. ADV can be used as a simple chip select
ly decode for odd and even byte writes. If CCR bit 2 is
0, and the bus is a 16-bit cycle, WRL and WRH are for external memory. ADV looks exactly like ALE for
back to back bus cycles. The only difference is ADV
generated in place of WR and BHE. WRL is asserted
for all byte writes to an even address and all word will be inactive when the external bus is idle.
writes. WRH is asserted for all byte writes to odd ad-
dresses and all word writes. The Write Strobe mode is Address Valid with Write Strobe
shown in Figure 15-6.
If CCR bits 2 and 3 are 0, the Address Valid with Write
In the eight bit mode, WRL and WRH are asserted for Strobe mode is enabled. Figure 15-8 shows the signals.
both even and odd addresses.

270651 – 55 270651 – 56
16-Bit Bus Cycle 8-Bit Bus Cycle

Figure 15-6. Write Strobe Mode

270651 – 57 270651 – 58
16-Bit Bus Cycle 8-Bit Bus Cycle

Figure 15-7. Address Valid Strobe Mode

74
80C196KB USER’S GUIDE

15.3 Bus Width During 16 bit bus cycles, Ports 3 and 4 contain the
address multiplexed with data using ALE to latch the
The 80C196KB external bus width can be run-time address. In 8-bit bus cycles, Port 3 is multiplexed with
conFigured to operate as a 16 bit multiplexed address/ address/data but Port 4 only outputs the upper 8 ad-
data bus, or as an MCS-51 style multiplexed 16 bit ad- dress bits. The Addresses on Port 4 are valid through-
dress/8 bit data bus. out the entire bus cycle. Figure 15-9 shows the two bus
width options.

270651 – 59 270651 – 60
16-Bit Bus Cycle 8-Bit Bus Cycle

Figure 15-8. Address Valid with Write Strobe Mode

270651 – 61 270651 – 62
(a) 16-Bit Bus (b) 8-Bit Bus

Figure 15-9. Bus Width Options

75
80C196KB USER’S GUIDE

The external bus width can be changed every bus cycle protocol consists of three signals, HOLD, HLDA, and
if a 1 was loaded into bit CCR.1 at reset. The bus width BREQ. HOLD is an input asserted by a device which
is changed on the fly by using the BUSWIDTH pin. If requests the 80C196KB bus. Figure 15-10 shows the
the BUSWIDTH pin is a 1, the bus cycle is 16-bits. For timing for HOLD/HLDA. The 80C196KB responds
an 8-bit bus cycle, the BUSWIDTH pin is a zero. The by releasing the bus and asserting HLDA. When the
BUSWIDTH is sampled by the 80C196KB after the device is done accessing the 80C196KB memory, it re-
address is on the bus. The BUSWIDTH pin has about linquishes the bus by deactivating the HOLD pin. The
the same timing as the READY pin. 80C196KB will remove its HDLA and assume control
of the bus. The third signal, BREQ, is asserted by the
Applications for the BUSWIDTH pin are numerous. 80C196KB during the hold sequence when it has a
For example, a system could have code fetched from 16 pending external bus cycle. The 80C196KB deactivates
bit memory, while data would come from 8 bit memo- BREQ at the same time it deactivates HDLA.
ry. This saves the cost of using two 8 bit static RAMS if
only the capacity of one is needed. This system could be The HOLD, HLDA, and BREQ pins are multiplexed
easily implemented by tying the chip select input of the with P1.7, P1.6, and P1.5, respectively. To enable
8-bit memory to the BUSWIDTH pin. HOLD, HLDA and BREQ, the HLDEN bit (WSR.7)
must be 1. HLDEN is cleared during reset. Once this
If CCR bit 1 is a 0, the 80C196KB is locked into the 8 bit is set, the port1 pins cannot be returned to being
bit mode and the BUSWIDTH pin is ignored. quasi-bidirectional pins until the device is reset, but can
still be read. The HOLD/HLDA feature, however, can
When executing code from a 8-bit bus, some perform- be disabled by clearing the HLDEN bit.
ance degradation is to be expected. The prefetch queue
cannot be kept full under all conditions from an 8-bit The HOLD is sampled on phase 1, or when CLKOUT
bus. Also, word reads and writes to external memory is low.
will take an extra bus cycle for the extra byte.
When the 80C196KB acknowledges the hold request,
the output buffers for the addr/data bus, RD, WR,
15.4 HOLD/HLDA Protocol BHE and INST are floated. Although the strong pullup
and pulldown on ALE/ADV are disabled, a weak pull-
The 80C196KB supports a bus exchange protocol, al- down is turned on. This provides the option to wire OR
lowing other devices to gain control of the bus. The ALE with other bus masters. The request to hold laten-
cy is dependent on the state of the bus controller.

270651 – 63

Figure 15-10. HOLD/HLDA Timings

76
80C196KB USER’S GUIDE

MAXIMUM HOLD LATENCY REGAINING BUS CONTROL

The time between HOLD being asserted and HLDA There is no delay from the time the 80C196KB re-
being driven is known as Hold Latency. After recogniz- moves HLDA to the time it takes control of the bus.
ing HOLD, the 80C196KB waits for any current bus After HOLD is removed, the 80C196KB drops HLDA
cycle to finish, and then asserts HLDA. There are 3 in the following state and resumes control of the bus.
types bus cycles; 8-bit external cycle, 16-bit external
cycle, and an idle bus. Accessing on-chip BREQ is asserted when the part is in hold and needs to
ROM/EPROM is an idle bus. perform an external memory cycle. An external memo-
ry cycle can be a data access or a request from the
HOLD is an asynchronous input. There are two differ- prefetch queue for a code request. A request comes
ent system configurations for asserting HOLD. The from the queue when it contains two bytes or less. Once
80C196KB will recognize HOLD internally on the next asserted, it remains asserted until HOLD is removed.
clock edge if the system meets Thvch (HOLD valid to At the earliest, BREQ can be asserted with HLDA.
CLKOUT high). If Thvch is not met (HOLD applied
asynchronously), HOLD may be recognized one clock Hold requests do not freeze the 80C196KB when exe-
later (see Figure 15-12). Consult the latest 80C196KB cuting out of internal memory. The part continues exe-
data sheet for the Thvch specification. cuting as long as the resources it needs are located in-
ternal to the 80C196KB. As soon as the part needs to
Figure 15-12 shows the 80C196KB entering HOLD access external memory, it asserts BREQ and waits for
when the bus is idle. This is the minimum hold latency the HOLD to be removed. At this time, the part cannot
for both the synchronous and asynchronous cases. If respond to any interrupt requests until HOLD is re-
Thvch is met, HLDA is asserted about on the next moved.
falling edge of CLKOUT. See the data sheet for Tclhal
(CLKOUT low to HLDA low) specification. For this When executing out of external memory during a
case, the minimum hold latency e Thvcl a 0.5 states HOLD, the 80C196KB keeps running until the queue
a Tclhal. is empty or it needs to perform an external data cycle.
The 80C196KB cannot service any interrupts until
If HOLD is asserted asynchronously, the minimum HOLD is removed.
hold latency increases by one state time and e Thvcl
a 1.5 states a Tclhal. The 80C196KB will also respond to hold requests in
the Idle Mode. The latency for entering bus hold from
Figure 15-11 summarizes the additional hold latency the Idle Mode is the same as when executing out of
added to the minimum latency for the 3 types of bus internal memory.
cycles. When accessing external memory, add one state
for each waitstate inserted into the bus cycle. For an Special consideration must be given to the bus arbiter
8-bit bus, worst case hold latency is for word reads or design if the 80C196KB can be reset while in HOLD.
writes. For this case, the bus controller must access the For example, a CPU part would try and fetch the CCR
bus twice, which increases latency by two states. from external memory after RESET is brought high.
Now there would be two parts attempting to access
For exiting Hold, the minimum hold latency times ap- 80C196KB memory. Also, if another bus master is di-
ply for when the 80C196KB will deassert HLDA in rectly driving ALE, RD, and INST, the ONCE mode
response to HOLD being removed. or another test mode could be entered. The simplest
solution is to make the RESET pin of the 80C196KB a
Idle Bus Min system reset. This way the other bus master would also
16-bit External Access Min a 1 state be reset. Examples of system reset circuits are given in
Section 13.
8-bit External Access Min a 3 states
Min e Thvcl a 0.5 states a Tclhal if Thvcl is met
e Thvcl a 1.5 states a Tclhal for asynchronous HOLD
Figure 15-11. Maximum Hold Latency

77
80C196KB USER’S GUIDE

Case 1. Meeting Thvcl

270651 – 82

Case 2. Asserting HOLD Asynchronously

270651 – 83

Figure 15-12. HOLD Applied Asynchronously

DISABLING HOLD REQUESTS The safest way is to add a JBC instruction to check the
status of the HLDA pin after the code that clears the
Clearing the HLDEN bit (WSR.7), can disable HOLD HLDEN bit. Figure 15-13 is an example of code that
requests when consecutive memory cycles are required. prevents the part from executing a new instruction until
Clearing the HDLEN bit, however, does not cause the both current HOLD requests are serviced and the hold
80C196KB to take over the bus immediately. The feature is disabled.
80C196KB waits for the current HOLD request to fin-
ish. Then it disables the bus hold feature, causing any
new requests to be ignored until the HLDEN bit is set
again. Since there is a delay from the time the code for
15.5 AC Timing Explanations
clearing this bit is fetched to the time it is actually exe- Figure 15-14 shows the timing of the ADDR/DATA
cuted, the code that clears HLDEN needs to be a few bus and control signals. Refer to the latest data sheet
instructions ahead of the block that needs to be protect- for the AC timings to make sure your system meets
ed from HOLD requests. specifications. The major timing specifications are ex-
plained in Figure 15-15.

DI ; disable interrupts
ANDB WSR, #OEFH ; disable hold request
WAIT: JBC PORT1, 6, WAIT; Check the HLDA pin
# ; If set, execute
# ; protected instructions
#
ORB WSR,#80h ; enable HOLD requests
EI ; enable interrupts
NOTE:
Interrupts should be disabled to prevent code interruption

Figure 15-13. HOLD code

78
80C196KB USER’S GUIDE

270651 – 80

Figure 15-14. AC Timing Diagrams

79
80C196KB USER’S GUIDE

270651 – 81

270651 – 84

Figure 15-14. AC Timing Diagrams (Continued)

80
80C196KB USER’S GUIDE

TIMINGS THE MEMORY SYSTEM MUST MEET: TCLDV Ð CLKOUT Low to Input Data Valid:
Maximum time the memory system has
TAVYV Ð ADDRESS Valid to READY Setup: to output valid data after the CLKOUT
Maximum time the memory system has falls.
to decode READY after ADDRESS is TRHDZ Ð RD High to Input Data Float: Time af-
output by the 80C196KB to guarantee at ter RD is inactive until the memory sys-
least one-wait state will occur. tem must float the bus. If this timing is
TLLYV Ð ALE Low to READY Setup: Maximum not met, bus contention will occur.
time the memory system has to decode TRXDX Ð Data Hold after RD Inactive: Time after
READY after ALE falls to guarantee at RD is inactive that the memory system
least one wait state will occur. must hold Data on the bus. Always 0 ns
TYLYH Ð READY Low to READY HIGH: Maxi- on the 80C196KB.
mum amount of nonREADY time or
the maximum number of wait states that
can be inserted into a bus cycle. Since TIMINGS THE 80C196KB WILL PROVIDE:
the 80C196KB is a completely static FXTAL Ð Frequency on XTAL1: Frequency of sig-
part, TYLYH is unbounded. nal input into the 80C196KB. The
80C196KB runs internally at (/2 FXTAL.
TCLYX Ð READY Hold after CLKOUT Low:
Minimum time the level on the READY TOSC Ð 1/FXTAL: All A.C. Timings are refer-
pin must be valid after CLKOUT falls. enced to TOSC.
The minimum hold time is always 0 ns. TXHCH Ð XTAL1 High to CLKOUT High or
If maximum value is exceeded, addition- Low: Needed in systems where the sig-
al wait states will occur. nal driving XTAL1 is also a clock for
TLLYX Ð READY Hold AFTER ALE Low: Mini- external devices.
mum time the level on the READY pin TCLCL Ð CLKOUT Cycle Time: Nominally 2
must be valid after ALE falls. If maxi- TOSC.
mum value is exceeded, additional wait
TCHCL Ð CLKOUT High Period: Needed in sys-
states will occur.
tems which use CLKOUT as clock for
TAVGV Ð ADDRESS Valid to BUSWIDTH Val- external devices.
id: Maximum time the memory system
TCLLH Ð CLKOUT Falling Edge to ALE/ADV
has to decode BUSWIDTH after AD-
Rising: A help in deriving other timings.
DRESS is output by the 80C196KB. If
exceeded, it is not guaranteed the TLLCH Ð ALE/ADV Falling Edge to CLKOUT
80C196KB will respond with an 8- or Rising: A help in deriving other timings.
16-bit bus cycle. TLHLH Ð ALE Cycle Time: Time between ALE
TLLGV Ð ALE Low to BUSWIDTH Valid: Maxi- pulses.
mum time after ALE/ADV falls until TLHLL Ð ALE/ADV High Period: Useful in de-
BUSWIDTH must be valid. If exceeded, termining ALE/ADV rising edge to
it is not guaranteed the 80C196KB will ADDRESS valid. External latches must
respond with an 8- or 16-bit bus cycle. also meet this spec.
TCLGX Ð BUSWIDTH Hold after CLKOUT TAVLL Ð ADDRESS Setup to ALE/ADV Falling
Low: Minimum time BUSWIDTH must Edge: Length of time ADDRESS is val-
be held valid after CLKOUT falls. Al- id before ALE/ADV falls. External
ways 0 ns of the 80C196KB. latches must meet this spec.
TAVDV Ð ADDRESS Valid to Input Data Valid: TLLAX Ð ADDRESS Hold after ALE/ADV Fall-
Maximum time the memory system has ing Edge: Length of Time ADDRESS is
to output valid data after the 80C196KB valid after ALE/ADV falls. External
outputs a valid address. latches must meet this spec.
TRLDV Ð RD Low to Input Data Valid: Maximum TLLRL Ð ALE/ADV Low to RD Low: Length of
time the memory system has to output time after ALE/ADV falls before RD is
valid data after the 80C196KB asserts asserted. Could be needed to insure
RD. proper memory decoding takes place be-
fore a device is enabled.

Figure 15-15. AC Timing Explanations

81
80C196KB USER’S GUIDE

TRLCL Ð RD Low to CLKOUT Falling Edge: TWLWH Ð WR Low to WR High: WR pulse width.
Length of time from RD asserted to Memory devices must meet this spec.
CLKOUT falling edge: Useful for sys- TWHQX Ð Data Hold after WR Rising Edge:
tems based on CLKOUT. Amount of time data is valid on the bus
TRLRH Ð RD Low to RD High: RD pulse width. after WR going inactive. Memory devic-
TRHLH Ð RD High to ALE/ADV Asserted: Time es must meet this spec.
between RD going inactive and next TWHLH Ð WR Rising Edge to ALE/ADV Rising
ALE/ADV, also used to calculate time Edge: Time between WR going inactive
between inactive and next ADDRESS and next ALE/ADV. Also used to cal-
valid. culate WR inactive and next ADDRESS
TRLAZ Ð RD Low to ADDRESS Float: Used to valid.
calculate when the 80C196KB stops TWHBX Ð BHE, INST, Hold after WR Rising
driving ADDRESS on the bus. Edge: Minimum time these signals will
TLLWL Ð ALE/ADV Low Edge to WR Low: be valid after WR inactive.
Length of time ALE/ADV falls before TRHBX Ð BHE, INST HOLD after RD Rising
WR is asserted. Could be needed to en- Edge: Minimum time these signals will
sure proper memory decoding takes be valid after RD inactive.
place before a device is enabled. TWHAX Ð AD8 – 15 Hold after WR Rising Edge:
TCLWL Ð CLKOUT Falling Edge to WR Low: Minimum time the high byte of the ad-
Time between CLKOUT going low and dress in 8-bit mode will be valid after
WR being asserted. Useful in systems WR inactive.
based on CLKOUT. TRHAX Ð AD8 – 15 Hold after RD Rising Edge:
TQVWH Ð Data Valid to WR Rising Edge: Time Minimum time the high byte of the ad-
between data being valid on the bus and dress in 8-bit mode will be valid after
WR going inactive. Memory devices RD inactive.
must meet this spec.
TCHWH Ð CLKOUT High to WR Rising Edge:
Time between CLKOUT going high and
WR going inactive. Useful in systems
based on CLKOUT.

Figure 15-15. AC Timing Explanations (Continued)

270651 – 66

Figure 15-16. 8-Bit System with EPROM

82
80C196KB USER’S GUIDE

15.6 Memory System Examples ed in the lower half of memory,and the RAM in the
upper half.
External memory systems for the 80C196KB can be set
up in many different ways. Figure 15-16 shows a simple Figure 15-18 shows a 16 bit system with 2 EPROMs.
8 bit system with a single EPROM. The ADV Mode Again, ADV is used to chip select the memory. Figure
can be selected to provide a chip select to the memory. 15-19 shows a system with dynamic bus width. Code is
By setting bit CCR.1 to 0, the system is locked into the executed from the two EPROMs and data is stored in
eight bit mode. An eight bit system with EPROM and the single RAM. Note the Chip Select of the RAM also
RAM is shown in Figure 15-17. The EPROM is decod- is input to the BUSWIDTH pin to select an eight bit
cycle.

270651 – 67

Figure 15-17. 8-Bit System with EPROM and RAM

270651 – 68

Figure 15-18. 16-Bit System with EPROM

83
80C196KB USER’S GUIDE

270651 – 69

Figure 15-19. 16-Bit System with Dynamic Buswidth

270651 – 70

Figure 15-20. I/O Port Reconstruction

84
80C196KB USER’S GUIDE

15.7 I/O Port Reconstruction The Run-Time Programming Mode allows individu-
al EPROM locations to be programmed at run-time
When a single-chip system is being designed using a under complete software control. (Run-Time Pro-
multiple chip system as a prototype, it may be neces- gramming is done with EA e 5V.)
sary to reconstruct I/O Ports 3 and 4 using a memory
mapped I/O technique. The circuit to reconstruct the In the Programming Mode some I/O pins have new
Ports is shown in Figure 15-20. It can be attached to a functions. These pins determine the programming func-
80C196KB system which has the required address de- tion, provide programming control signals and slave ID
coding and bus demultiplexing. numbers, and pass error information. Figure 16-1
shows how the pins are renamed. Figure 16-2 describes
The output circuitry is a latch that operates when each new pin function.
1FFEH or 1FFFH are placed on the MA lines. The
inverters surrounding the latch create an open-collector PMODE selects the programming mode (see Figure
output to emulate the open-drain output found on the 16-3). The 87C196KB does not need to be in the Pro-
80C196KB. The RESET line sets the ports to all 1s gramming Mode to do run-time programming; it can be
when the chip is reset. The voltage and current specifi- done at any time.
cations of the port will be different from the
80C196KB, but the functionality will be the same. When an 87C196KB EPROM device is not being
erased the window must be covered with an opaque
The input circuitry is a bus transceiver that is addressed label. This prevents functional degradation and data
at 1FFEH and 1FFFH. If the ports are going to be loss from the array.
either inputs or outputs, but not both, some of the cir-
cuitry may be eliminated.
16.1 Power-Up and Power-Down
16.0 USING THE EPROM To avoid damaging devices during programming, fol-
low these rules:
The 87C196KB contains 8 Kbytes of ultraviolet Eras- RULE Ý1 VPP must be within 1V of VCC while VCC
able and electrically Programmable Read Only Memo- is below 4.5V.
ry (EPROM). When EA is a TTL high, the EPROM is
RULE Ý2 VPP can not be higher than 5.0V until VCC
located at memory locations 2000H through 3FFFH.
is above 4.5V.
Applying a 12.75V to EA when the chip is reset places RULE Ý3 VPP must not have a low impedance path
the 87C196KB device in the EPROM Programming to ground when VCC is above 4.5V.
Mode. The Programming Mode supports EPROM pro- RULE Ý4 EA must be brought to 12.75V before VPP
gramming and verification. The following is a brief de- is brought to 12.75V (not needed for run-
scription of each of the programming modes: time programming).
The Auto Configuration Byte Programming Mode RULE Ý5 The PMODE and SID pins must be in
programs the Programming Chip Configuration Byte their desired state before RESET rises.
and the Chip Configuration Byte. RULE Ý6 All voltages must be within tolerance and
the oscillator stable before RESET rises.
The Auto Programming Mode enables an RULE Ý7 The supplies to VCC, VPP, EA and RE-
87C196KB to program itself without using an SET must be well regulated and free of
EPROM programmer. spikes and glitches.
The Slave Programming Mode provides a standard To adhere to these rules you can use the following pow-
interface for programming any number of er-up and power-down sequences:
87C196KB’s by a master device such as an EPROM
programmer.

85
80C196KB USER’S GUIDE

POWER-UP EA e 5V
PALE e PROG e SID e PMODE e PORT3, 4 e
RESET e 0V 0V
VCC e VPP e EA e 5V VCC e VPP e EA e 0V
CLOCK on (if using an external clock instead of the CLOCK OFF
internal oscillator)
PALE e PROG e PORT3, 4 e VIH(1) NOTES:
SID and PMODE valid 1. VIH e logical ‘‘1’’ (2.4V minimum)
EA e 12.75V(2) 2. The same power supply can be used for EA and
VPP e 12.75V(3) VPP. However, the EA pin must be powered up before
WAIT (wait for supplies and clock to settle) VPP is powered up. Also, EA should be protected
RESET e 5V from noise to prevent damage to it.
WAIT Tshll (RESET high to first PALE low) 3. Exceeding the maximum limit on VPP for any
BEGIN amount of time could damage the device permanently.
The VPP source must be well regulated and free of
glitches.
POWER-DOWN
RESET e 0V
VPP e 5V 16.2 Reserved Locations
All Intel Reserved locations except address 2019H,
when mapped internally or externally, must be loaded
with 0FFH to ensure compatibility with future devices.
Address 2019H must be loaded with 20H.

270651 – 71

Figure 16-1. Programming Mode Pin Functions

86
80C196KB USER’S GUIDE

Mode Name Function

General PMODE Programming Mode Select. Determines the EPROM programming
(P0–0.4, 0.5, algorithm that is performed. PMODE is sampled after a chip reset and
0.6, 0.7) should be static while the part is operating.
Auto PCCB PVER Program Verification Output. A high signal indicates that the bytes
Programming Mode (P2.0) have programmed correctly.
PALE Programming ALE Input. Indicates that Port3 contains the data to be
(P2.1) programmed into the CCB and the PCCB.
Auto Programming PACT Programming Active Output. Indicates when programming activity is
Mode (P2.7) complete.
PVAL Program Valid Output. Indicates the success or failure of
(P3.0) programming. A zero indicates successful programming.
Ports Address/Command/Data Bus. Used in the Auto Programming Mode
3 and 4 as a regular system bus to access external memory. Should have
pullups to VCC (15 kX).
Slave Programming SID Slave ID Number. Used to assign a pin of Port 3 or 4 to each slave to
Mode (HSI–0.0, use for passing programming verification acknowledgement. For
0.1, 0.2, 0.3) example, if gang programming in the Slave Programming Mode, the
slave with SID e 001 will use Port 3.1 to signal correct or incorrect
program verification.
PALE Programming ALE Input. Indicates that Ports 3 and 4 contain a
(P2.1) command/address.
PROG Programming Input. Falling edge indicates valid data on PBUS and the
(P2.2) beginning of programming. Rising edge indicates end of programming.
PVER Program Verification Output. Low signal after rising edge of PROG
(P2.0) indicates programming was not successful.
AINC Auto Increment Input. Active low input signal indicates that the auto
(P2.4) increment mode is enabled. Auto Increment will allow reading or
writing of sequential EPROM locations without address transactions
across the PBUS for each read or write.
Ports Address/Command/Data Bus. Used to pass commands, addresses,
3 and 4 and data to and from 87C196KBs in the Slave Programming Mode.
One pin each can be assigned to up to 15 slaves to pass verification
information.
Figure 16-2. Programming Mode Pin Definitions

PMODE Programming Mode 16.3 Programming Pulse Width

0–4 Reserved
Register (PPW)
5 Slave Programming In the Auto and Run-Time Programming Modes the
width of the programming pulse is determined by the 8
6 ROM Dump bit PPW (Programming Pulse Width) register. In the
7–0BH Reserved Auto Programming Mode, the PPW is loaded from lo-
cation 4014H in external memory. In Run-time Pro-
0CH Auto Programming gramming Mode, the PPW is located in window 14 at
0DH Program Configuration Byte 04H. In order for the EPROM to properly program,
the pulse width must be set to approximately 100 uS.
0EH–0FH Reserved The pulse width is dependent on the oscillator frequen-
Figure 16-3. Programming cy and is calculated with the following formula:
Function Pmode Values
Pulse Width e PPW * (Tosc * 8)

PPW e 150 @ 12 Mhz

In the Slave Programming Mode the width of the pro-

gramming pulse is determined by the PROG signal.

87
80C196KB USER’S GUIDE

16.4 Auto Configuration Byte or WRITE lock bits are enabled, some programming
Programming Mode modes will require security key verification before exe-
cuting and some modes will not execute. See Figure
The Programming Chip Configuration Byte (PCCB) is 16-10 and the sections on each programming mode for
a non-memory mapped EPROM location. It gets load- details of the effects of enabling the lock bits.
ed into the CCR during reset for auto and slave pro-
gramming. The Auto Configuration Byte Programming If the PCCB is not programmed, the CCR will be load-
Mode programs the PCCB. ed with 0FFFH when the device is in the Programming
Mode.
The Chip Configuration Byte (CCB) is at location
2018H and can be programmed like any other EPROM
location using Auto, Slave, or Run-Time Programming. 16.5 Auto Programming Mode
However, you can also use Auto Configuration Byte
Programming to program the CCB when no other loca- The Auto Programming Mode provides the ability to
tions need to be programmed. The CCB is programmed program the 87C196KB EPROM without using an
with the same value as the PCCB. EPROM programmer. For this mode follow the power-
up sequence described in Section 16.1 with PMODE e
The Auto Configuration Byte Programming Mode is 0CH. External location 4014H must contain the PPW.
entered by following the power-up sequence described When RESET rises, the 87C196KB automatically pro-
in Section 16.1 with PMODE e 0DH, Port 4 e grams itself with the data found at external locations
0FFH, and Port 3 e the data to be programmed into 4000H through 5FFFH.
the PCCB and CCB. When a 0 is placed on PALE the
CCB and PCCB are automatically programmed with The 87C196KB begins programming by setting PACT
the data on Port 3. After programming, PVER is driv- low. Then it reads a word from external memory. The
en high if the bytes programmed correctly and low if Modified Quick-Pulse Programming Algorithm (de-
they did not. scribed later) programs the corresponding EPROM lo-
cation. Since the erased state of a byte is 0FFH, the
Once the PCCB and CCB are programmed, all pro- Auto Programming Mode will skip locations with
gramming activities and bus operations use the selected 0FFH for data. When all 8K have been programmed,
bus width, READY control, bus controls, and READ/ PACT goes high and the device outputs a 0 on PVAL
WRITE protection until you erase the device. You (P3.0) if it programmed correctly and a 1 if it failed.
must be careful when programming the READ and Figure 16-4 shows a minimum configuration using an
WRITE lock bits in the PCCB and CCB. If the READ 8K c 8 EPROM to program an 87C196KB in the
Auto Programming Mode.

AUTO PROGRAMMING MODE AND THE

CCB/PCCB

In the Auto Programming Mode the CCR is loaded

with the PCCB. The PCCB must correspond to the
memory system of the programming setup, including
the READY and bus control selections. You can pro-
gram the PCCB using the Auto Configuration Byte
Programming Mode (see Section 16.4).

The data in the PCCB takes effect upon reset. If you

enable the READ and WRITE lock bits during Auto
Programming but do not reset the device, Auto Pro-
gramming will continue. If you enable either the
270651 – 73 READ or WRITE lock bits in the CCB using Auto
NOTES: Configuration Byte Programming and then reset the
Tie Port 3 to the value desired to be programmed into 87C196KB for Auto Programming, the device does a
CCB and PCCB. security key verification. The same security keys that
Make all necessary minimum connections for power, reside at internal addresses 2020H – 202FH must reside
ground and clock. at external locations 4020H – 402FH. If the keys match,
auto programming continues. If the keys do not match,
Figure 16-5. The PCCB Programming Mode the device enters an endless loop of internal execution.

88
80C196KB USER’S GUIDE

270651 – 72

NOTES:
*Inputs must be driven high or low.
**Allow RESET to rise after the voltages to VCC, EA, and VPP are stable.

Figure 16-4. Auto Programming Mode

89
80C196KB USER’S GUIDE

16.6 Slave Programming Mode The 87C196KB receives an input signal, PALE, to in-
dicate a valid command is present. PROG causes the
Any number of 87C196KBs can be programmed by a 87C196KB to read in or output a data word. PVER
master programmer through the Slave Programming indicates if the programming was successful. AINC au-
Mode. There is no 87C196KB dependent limit to the tomatically increments the address for the Data Pro-
number of devices that can be programmed. gram and Word Dump commands.

In this mode, the 87C196KB programs like a simple

Data Program Command
EPROM device and responds to three different com-
mands: data program, data verify, and word dump. The A Data Program Command is illustrated in Figure 16-
87C196KB uses Ports 3 and 4 and five other pins to 7. Asserting PALE latches the command and address
select commands, to transfer data and addresses, and to on Ports 3 and 4. PROG is asserted to latch the data
provide handshaking. The two most significant bits on present on Ports 3 and 4. PROG also starts the actual
Ports 3 and 4 specify the command and the lower 14 programming sequence. The width of the PROG pulse
bits contain the address. The address ranges from determines the programming pulse width. Note that the
2000H-3FFFH and refers to internal memory space. PPW is not used in the Slave Programming Mode.
Figure 16-6 is a list of valid Programming Commands.
After the rising edge of PROG, the slaves automatically
P4.7 P4.6 Action verify the contents of the location just programmed.
PVER is asserted if the location programmed correctly.
0 0 Word Dump This gives verification information to programmers
0 1 Data Verify which can not use the Data Verify Command. The
1 0 Data Program AINC pin can increment to the next location or a new
1 1 Reserved Data Program Command can be issued.
Figure 16-6. Slave Programming
Mode Commands

270651 – 74

Figure 16-7. Data Program Command in Slave Mode

90
80C196KB USER’S GUIDE

PVER is a 1 if the data program was successful. PVER mand and places the value at the new address on Ports
is a 0 if the data program was unsuccessful. Figure 16-7 3 and 4. For example, when the slave receives the com-
shows the relationship of PALE, PROG, and PVER to mand 0100H, it will place the word at internal address
the Command/Data path on Ports 3 and 4 for the Data 2100H on Ports 3 and 4. PROG governs when the slave
Program Command. drives the bus. The Timings are the same as shown in
Figure 16-7.
Data Verify Command Note that the Word Dump Command only works when
a single slave is attached to the bus. Also, there is no
When the Data Verify Command is sent, the slaves in-
restriction on commands that precede or follow a Word
dicate correct or incorrect verification of the previous
Dump Command.
Data Program Command by driving one bit of Ports 3
and 4. A 1 indicates a correct verification, and a 0 indi-
cates incorrect verification. The SID (Slave I.D) of each Gang Programming With the Slave
slave determines which bit of Ports 3 and 4 will be Programming Mode
driven. For example, a SID of 0001 would drive Port
3.1. PROG governs when the slaves drive the bus. Fig- Gang Programming of 87C196KBs can be done using
ure 16-8 shows the relationship of ports 3 and 4 to the Slave Programming Mode. There is no 87C196KB
PALE and PROG. based limit on the number of devices that may be
hooked to the same Port 3 and 4 data path for gang
A Data Verify Command is always preceded by a Data programming.
Program Command in a programming system with as
many as 16 slaves. However, a Data Verify Command If more than 16 devices are being gang programmed,
does not have to follow every Data Program Com- the PVER outputs of each chip can be used for verifica-
mand. tion. The master programmer can issue a Data Pro-
gram Command, then either watch every device’s error
signal, or AND all the signals together to form a sys-
Word Dump Command tem PVER.
When the Word Dump Command is issued, the
87C196KB adds 2000H to the address field of the com-

270651 – 75

Figure 16-8. Ports 3 and 4 to PALE and PROG

91
80C196KB USER’S GUIDE

If 16 or fewer 87C196KBs are to be gang programmed 16.7 Run-Time Programming

at once, a more flexible form of verification is available
by giving each device a unique SID. The master pro- The 87C196KB can program itself under software con-
grammer can issue a Data Verify Command after the trol. One byte or word can be programmed instead of
Data Program Command. When a verify command is the entire array. The only additional requirement is
seen by the slaves, each will drive a bit of Ports 3 or 4 that you apply a programming voltage to VPP and have
corresponding to its unique SID. A 1 indicates the ad- the ambient temperature at 25§ C. Run-time program-
dress verified, while a 0 means it failed. ming is done with EA at a TTL high (internal memory
enabled).
SLAVE PROGRAMMING MODE AND THE
To Run-Time Program, the user writes to the location
CCB/PCCB
to be programmed. The value of the PPW register de-
Devices in the Slave Programming Mode use Ports 3 termines the programming pulse. To ensure 87C196KC
and 4 as the command/data path. The data bus is not compatibility, the Idle Mode should be used for Run-
used. Therefore, you do not need to program either the Time Programming. Figure 16-9 is the recommended
CCB or the PCCB before starting slave programming. code sequence for Run-Time Programming. The Modi-
fied Quick Pulse algorithm guarantees the programmed
You can program the CCB like any other location in EPROM cell for the life of the part.
slave mode. Data programmed into the CCB takes ef-
fect upon reset. If you enable either the READ or the RUN-TIME PROGRAMMING AND THE
WRITE lock bits in the CCB during slave program- CCB/PCCB
ming and do not reset the device, slave programming
will continue. If you do reset the device, the device first For run-time programming, the CCR is loaded with the
does a security key verification. The same security keys CCB. Run-time programming is done with EA equal to
that reside at internal addresses 2020H–202FH must a TTL-high (internal execution) so the internal CCB
reside at external addresses 4020H–402FH. If the keys must correspond to the memory system of the applica-
match, slave programming continues. If the keys do not tion setup. You can use Auto Configuration Byte Pro-
match, the device enters an endless loop of internal exe- gramming or a generic programmer to program the
cution. CCB before using Run-Time Programming.

LD WSR,#14 ;Initialize programmable

LD PPW,#VALUE ;pulse width

PROGRAM: POP ADDRESS TEMP ;Load program data

POP DATA TEMP ;and address
PUSHF
LD COUNT, #25T

LOOP: ST DATA TEMP,[ADDR TEMP] ;begin programming

;enter idle mode
DJNZ COUNT, L00P ;loop 25 times
POPF
RET
NOTE:
*Not Really Needed on Current 87C196KB Part

Figure 16-9. Future Run-Time Programming Algorithm

92
80C196KB USER’S GUIDE

The CCB can also be programmed during Run-Time

Programming like any other EPROM location. CCB.1 CCB.0
RD WR Protection
Data programmed into the CCB takes effect immedi- Lock Lock
ately. If the WRITE lock bit of the CCB is enabled, the 1 1 Array is unprotected. ROM
array can no longer be programmed. You should only
Dump Mode and all
program the WRITE lock bit when no further pro-
gramming will be done to the array. If the READ lock programming modes are
bit is programmed the array can still be programmed allowed.
using run-time programming but a data access will only 0 1 Array is READ protected. Run-
be performed when the program counter is between time programming is allowed.
2000H and 3FFFH.
Auto, Slave, and ROM Dump
Mode are allowed after security
key verification.
16.8 ROM/EPROM Memory Protection
Options 1 0 Array is WRITE protected. Auto,
Slave, and ROM Dump Mode
Write protection is available for EPROM parts, and are allowed after security key
read protection is provided for both ROM and
verification. Run-time
EPROM parts.
programming is not allowed.
Write protection is enabled by clearing the LOC0 bit in 0 0 Array is READ and WRITE
the CCR. When write protection is enabled, the bus protected. Auto, Slave, and
controller will cycle through the write sequence but will
ROM Dump Mode are allowed
not actually drive data to the EPROM or enable VPP to
the EPROM. This protects the entire EPROM (loca- after security key verification.
tions 2000H–3FFFH) from inadvertent or unautho- Run-time programming is not
rized programming. allowed.
Figure 16-10
Read protection is enabled by clearing the LOC1 bit of
the CCR. When read protection is selected, the bus
controller will only perform a data read from the ad- ROM DUMP MODE
dress range 2020H-202FH (Security Key) and 2040H-
3FFFH if the Slave Program Counter is in the range You can use the security key and ROM Dump Mode to
2000H-3FFFH. Since the Slave PC can be as many as 4 dump the internal ROM/EPROM for testing purposes.
bytes ahead of the CPU program counter, an instruc-
tion after address 3FFAH may not access protected The security key is a 16 byte number. The internal
memory. Also note the interrupt vectors and CCB are ROM/EPROM must contain the security key at loca-
not read protected. tions 2020H – 202FH. The user must place the same
security key at external address 4020H – 402FH. Before
EA is latched on reset so the device cannot be switched doing a ROM dump, the device checks that the keys
from internal to external memory by toggling EA. match.

If the CCR has any protection enabled, the security key

is write protected to keep unauthorized users from ov-
erwriting the key with a known security key.

NOTE:
Substantial effort has been made to provide an excel-
lent program protection scheme. However, Intel can-
not and does not guarantee that these protection
methods will always prevent unauthorized access.

93
80C196KB USER’S GUIDE

For the 87C196KB, the ROM dump mode is entered

like the other programming modes described in Section Description Location Value
16.1 with PMODE equal to 6H. For the 83C196KB, Signature Word 2070H 897CH
the ROM Dump Mode is entered by placing EA at a Programming VCC 2072H 040H
TTL high, holding ALE low and holding INST and (5.0V)
RD high on the rising edge of RESET. The device first Programming VPP 2073H 0A3H
verifies the security key. If the security keys do not
(12.75V)
match, the device puts itself into an endless loop of
internal execution. If the keys match, the device dumps Figure 16-10. Signature Word and Voltage Levels
internal locations 2000H-3FFFH to external locations
4000H–5FFFH.
Erasing the 87C196KB

After each erasure, all bits of the 87C196KB are logical

16.9 Algorithms 1s. Data is introduced by selectively programming 0s.
The only way to change a 0 to a 1 is by exposure to
The Modified Quick-Pulse Algorithm ultraviolet light.

The Modified Quick-Pulse Algorithm must be used to Erasing begins upon exposure to light with wavelengths
guarantee programming over the life of the EPROM in shorter than approximately 4000 Angstroms. It should
Run-time and Slave Programming Modes. be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000 Angstrom
The Modified Quick-Pulse Algorithm calls for each range. Constant exposure to room level fluorescent
EPROM location to receive 25 separate 100 uS ( g 5 lighting could erase an 87C196KB in about 3 years. It
ms) programming cycles. Verification is done after the would take about 1 week in direct sunlight to erase an
25th pulse. If the location verifies, the next location is 87C196KB.
programmed. If the location fails to verify, the location
fails the programming sequence. Opaque labels should always be placed over the win-
dow to prevent unintentional erasure. In the Power-
Once all locations are programmed and verified, the down Mode, the part will draw more current than nor-
entire EPROM is again verified. mal if the EPROM window is exposed to light.

Programming of 87C196KB EPROMs is done with The recommended erasure procedure for the
VPP e 12.75V g 0.25V and VCC e 5.0V g 0.5V. 87C196KB is exposure to ultraviolet light which has a
wavelength of 2537 Angstroms. The integrated dose
(UV intensity * exposure time) should be a minimum of
Signature Word
15 Wsec/cm2. The total time for erasure is about 15 to
The 87C196KB contains a signature word at location 20 minutes at this level of exposure. The 87C196KB
2070H. The word can be accessed in the Slave Mode by should be placed within 1 inch of the lamp during expo-
executing a Word Dump Command. The programming sure. The maximum integrated dose an 87C196KB can
voltages are determined by reading the test ROM at be exposed to without damage is 7258 Wsec/cm2 (1
locations 2072H and 2073H. The voltages are calculat- week @ 12000 uW/cm2). Exposure to UV light greater
ed by using the following equation. than this can cause permanent damage.

Voltage e 20/256 * (test ROM data)

The values for the signature word and voltage levels are
shown in Figure 16-10.

94