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CSE231 - Lecture 5

This document provides an overview of a lecture on combinational logic circuits. The key outcomes are listed as implementing circuits like adders, decoders, multiplexers; converting between binary and Gray code; and using parity generators and checkers. It then goes on to provide examples and explanations of various combinational logic components like adders, subtractors, comparators, decoders, encoders, multiplexers and how to implement them using logic gates. Conversion between number systems like binary to Gray code and error detection using parity bits are also discussed.
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0% found this document useful (0 votes)
117 views

CSE231 - Lecture 5

This document provides an overview of a lecture on combinational logic circuits. The key outcomes are listed as implementing circuits like adders, decoders, multiplexers; converting between binary and Gray code; and using parity generators and checkers. It then goes on to provide examples and explanations of various combinational logic components like adders, subtractors, comparators, decoders, encoders, multiplexers and how to implement them using logic gates. Conversion between number systems like binary to Gray code and error detection using parity bits are also discussed.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 33

CSE231 – Digital Logic Design

Lecture – 5 Lesson Outcomes

After completing this lecture, students will be able to


• Implement combinational logic circuits including adder,
subtractor, comparator, encoder, decoder, multiplexer,

Combinational demultiplexers. etc.


• Convert from binary to Gray code, and Gray code to
binary by using logic devices.

Logic Circuits • Use parity generators and checkers to detect bit errors
in digital systems

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Key Terms
 Comparator A digital circuit that compares the magnitudes of two quantities and produces an output
indicating the relationship of the quantities.
 Decoder A digital circuit that converts coded information into a familiar or noncoded form.
 Demultiplexer (DEMUX) A circuit that switches digital data from one input line to several output lines
in a specified time sequence.
 Encoder A digital circuit that converts information to a coded form.
 Full-adder A digital circuit that adds two bits and an input carry to produce a sum and an output carry.
Half-adder A digital circuit that adds two bits and produces a sum and an output carry. It cannot
 handle input carries.
 Look-ahead carry A method of binary addition whereby carries from preceding adder stages are
anticipated, thus eliminating carry propagation delays.
 Multiplexer (MUX) A circuit that switches digital data from several input lines onto a single output line
in a specified time sequence.
 Parity bit A bit attached to each group of information bits to make the total number of 1s odd or even
for every group of bits.
 Ripple carry A method of binary addition in which the output carry from each adder becomes the input
carry of the next higher-order adder.

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Implementing logic circuit from Boolean expression

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Combinational logic circuit

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Combinational logic circuit

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Half Adder

Half
Adder
Logic
Symbol

Half
Adder
Logic
Diagram

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Full Adder

Full
Adder
Logic
Symbol

Full
Adder
Logic
Diagram

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3-bit parallel adder

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4-bit parallel adder

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Two 4-bit parallel adders consists 8-bit adder

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Full adder and binary adder - application

A voting system
using full adders
and binary adders

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Ripple carry adder
 A ripple carry adder is one in which
the carry output of each full-adder
is connected to the carry input of
the next higher-order stage (a stage
is one full-adder).
 The sum and the output carry of
any stage cannot be produced until
the input carry occurs; this causes a
time delay in the addition process,
as illustrated in Figure 6–14.
 The carry propagation delay for
each full-adder is the time from the
application of the input carry until
the output carry occurs, assuming
that the A and B inputs are already
present.

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Subtractors – half and full

Half Full
Subtractor Subtractor

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Comparator

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Comparator – application (temperature control)

When the measured temperature and the specified


temperature are the same, the two BCD codes are
equal and the T output is LOW (0). When the
measured temperature falls below the specified
value, there is a difference in the BCD codes and
the T output is HIGH (1), which turns on the heater.
The temperature control logic can be implemented
with exclusive-OR gates, as shown in Figure.

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Decoder: Basic binary decoder

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4-bit decoder (4-line-to-16-line or 1-of-16 decoder)

In order to decode
all possible
combinations of
four bits, sixteen
decoding gates are
required (24 = 16).
For any given code
on the inputs, one
of the sixteen
outputs is
activated. A list of
the sixteen binary
codes and their
corresponding
decoding functions
is given in Table.

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BCD-decimal decoder

 The BCD-to-decimal decoder


converts each BCD code (8421
code) into one of ten possible
decimal digit indications. It is
frequently referred as a 4-line-
to-10-line decoder or a 1-of-10
decoder.
 A list of the ten BCD codes and
their corresponding decoding
functions is given in Table 6–5.
 Each of these decoding functions
is implemented with NAND gates
to provide active-LOW outputs.
If an active-HIGH output is
required, AND gates are used for
decoding.

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Encoder: Decimal to BCD encoder

Can be implemented by
OR gates

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Code converter: BCD to binary conversion

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BCD to binary conversion

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Gray codes

 The Gray code is unweighted and is not an arithmetic code; that is, there are no
specific weights assigned to the bit positions. The important feature of the Gray code is
that it exhibits only a single bit change from one code word to the next in sequence.

 Gray code is used in in


many applications, such
as shaft position
encoders, where error
susceptibility increases
with the number of bit
changes between
adjacent numbers in a
sequence.

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Binary to gray code conversion and vice versa

Binary-to-Gray Code Conversion Gray-to-Binary Code Conversion


1. The most significant bit (left-most) in the 1. The most significant bit (left-most) in
Gray code is the same as the the binary code is the same as the
corresponding MSB in the binary number. corresponding bit in the Gray code.
2. Going from left to right, add each 2. Add each binary code bit generated to
adjacent pair of binary code bits to get the Gray code bit in the next adjacent
the next Gray code bit. Discard carries. position. Discard carries.

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Binary to gray code conversion and vice versa

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Binary to gray code conversion and vice versa

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Parity method for error detection

 Many systems use a parity bit as a means for bit error


detection. Any group of bits contain either an even or an odd
number of 1s. A parity bit is attached to a group of bits to
make the total number of 1s in a group always even or always
odd. An even parity bit makes the total number of 1s even,
and an odd parity bit makes the total odd.
 A given system operates with even or odd parity, but not
both. For instance, if a system operates with even parity, a
check is made on each group of bits received to make sure the
total number of 1s in that group is even. If there is an odd
number of 1s, an error has occurred.

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Parity checker

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Multiplexer

 A multiplexer (MUX) is a device that allows digital information from several sources to
be routed onto a single line for transmission over that line to a common destination.

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Multiplexer application – A 7-segment display multiplexer

 Figure 6–49 shows a simplified method of multiplexing BCD


numbers to a 7-segment display. In this example, 2-digit
numbers are displayed on the 7-segment readout by the use of a
single BCD-to-7-segment decoder.
 The basic operation is as follows. Two BCD digits (A3A2A1A0 and
B3B2B1B0) are applied to the multiplexer inputs. A square wave
is applied to the data-select line, and when it is LOW, the A bits
(A3A2A1A0) are passed through to the inputs of the 74HC47
BCD-to-7-segment decoder. The LOW on the data-select also
puts a LOW on the A1 input of the 74HC139 2-line-to-4-line
decoder, thus activating its 0 output and enabling the A-digit
display by effectively connecting its common terminal to ground.
The A digit is now on and the B digit is off.
 When the data-select line goes HIGH, the B bits (B3B2B1B0) are
passed through to the inputs of the BCD-to-7-segment decoder.
Also, the 74HC139 decoder’s 1 output is activated, thus enabling
the B-digit display. The B digit is now on and the A digit is off.

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Demultiplexer

 A demultiplexer (DEMUX) basically reverses the multiplexing function. It takes digital


information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. As you will learn, decoders
can also be used as demultiplexers.
 Figure 6–52 shows a 1-line-to-4-
line demultiplexer (DEMUX)
circuit. The data-input line goes to
all of the AND gates. The two
data-select lines enable only one
gate at a time, and the data
appearing on the data-input line
will pass through the selected gate
to the associated data-output line.

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Demultiplexer

PROBLEM. The serial data-input waveform


(Data in) and data-select inputs (S0 and S1)
are shown in Figure 6–53. Determine the
data-output waveforms on D0 through D3 for
the demultiplexer in Figure 6–52.

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References

1. Digital Fundamentals by Thomas Floyd, Pearson International Edition,


11th Edition, Chapter 6, Page 313-386.

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Next class

Latches,
Flip-Flops
and Timers
CSE231 Lecture 5 Page 33/33

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