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Sample Testplan-AXI DRIVER

The document provides a test plan for verifying the functionality of an AXI protocol. It describes the verification strategy, testbench architecture, functional coverage, assertions, and test scenarios. The testbench architecture includes AXI sequence libraries, a testbench top module, agent classes for the master and slave, and a scoreboard. It aims to achieve 100% code coverage to fully verify the AXI protocol.

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venkata prashanth
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209 views

Sample Testplan-AXI DRIVER

The document provides a test plan for verifying the functionality of an AXI protocol. It describes the verification strategy, testbench architecture, functional coverage, assertions, and test scenarios. The testbench architecture includes AXI sequence libraries, a testbench top module, agent classes for the master and slave, and a scoreboard. It aims to achieve 100% code coverage to fully verify the AXI protocol.

Uploaded by

venkata prashanth
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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AXI UVM VERIFICATION TESTPLAN

DOCUMENTATION
Version <1.0>
<17/09/2023>
2

VERSION HISTORY

Version Implemented Revision Approved Approval Reason


# By Date By Date
1.0 ARUNA M 17/09/2023 Initial
Documentation
draft
1.0 Review by Review Date
name: Ms.
Geethanjali
1.1
3
4

1 INTRODUCTION

1.1 OBJECTIVE OF THE VERIFICATION PLAN DOCUMENT


The objective of the verification strategy described herein is to verify the functionality of
the AXI protocol. The main verification concerns for this unit are functional completeness
and correctness, data integrity, and performance. Testplan document explains the
functional coverage and assertion of the AXI Protocol(v1.0).
1.2 UNIT SIMULATION
Unit level verification of these will be completed by the core team. System Verilog
simulation environments described below will be used for the simulation.
The primary simulation environment for the AXI slave unit will be the system verilog
random constraint simulation environment at the chip level. This environment is being
developed from scratch to ensure high verification coverage/assertion. The scope of the
testing in this environment is all mainline data flows, error detection, error recovery

1.3 VERIFICATION TOOLS


SYNOPSYS VCS - For Simulation , code coverage and functional coverage.
VCS Version : T-2022.06

2 VERIFICATION STRATEGY

2.1 ASSUMPTIONS / CONSTRAINTS / STANDARDS


1. Slave address: only one slave device is active and connected to AXI Master.
2. The test bench acts as a AXI Master and it will verify AXI Slave

Add any other assumption’s:


5

3 TESTBENCH ARCHITECTURE
6

3.1 AXI SEQUENCE LIBRARY


Define test suites, read and write operation to check memory read/ write is supported.

File (axi_based_sequence_lib.sv) defines base sequence


class AXI_base_seq extends uvm_sequence #(AXI_transfer);
function new(string name="axi_base_seq");
super.new(name);
endfunction
`uvm_object_utils_begin(AXI_base_seq)
`uvm_object_utils_end

File (axi_master_based_seq_lib.sv) uses a base sequence to raise/drop objections if base


sequence is a default sequence.
virtual task pre_body();
if (starting_phase != null)
starting_phase.raise_objection(this, {"Running sequence '",
get_full_name(), "'"});
endtask

virtual task post_body();


if (starting_phase != null)
starting_phase.drop_objection(this, {"Completed sequence '",
get_full_name(), "'"});
endtask

File (axi_master_read_seq_lib.sv) created read transaction.


File (axi_master_write_seq_lib.sv) created write transaction.
File (axi_seq_lib_pkg.sv) imports the UVM class library and UVM automation macros.
`include "axi_based_seq_lib.sv"
`include "axi_master_based_seq_lib.sv"
`include "axi_slave_based_seq_lib.sv"
`include "axi_master_read_seq_lib.sv"
7

`include "axi_master_write_seq_lib.sv"
File (axi_slave_based_seq_lib.sv) use a base sequence to raise/drop objections if base
sequence is a default sequence

3.2 TESTBENCH TOP


The testbench top class (demo_top.sv) for AXI protocol consists of:
 Clock and reset signals
reg clk;
reg reset;
Design clock (5 ns) is generated.
Active low reset is asserted for 20 ns.

 Interface instantiation
AXI_vif axi_vif_0(
.AXI_ACLK(clock),
.AXI_ARESET_N(reset)
);

3.3 AXI_COMMON

AXI common methods: function calls, queue, hast table are defined in this file
(axi_common.sv).

3.4 AXI CONFIGUATION


AXI configuration for master, slave, environment configuration, default AXI bus
parameter set are defined in the file (axi_conf.sv).

3.5 AXI_ENV
The environment class of AXI defines how many master/slave and connections are
implemented in file (axi_env.sv).

3.6 AXI_MASTER_AGENT
The master agent, contain monitor or sequencer checks if the ACTIVE is on

3.7 AXI_MASTER_DRIVER
Defines master driver, transfer TLM level info to pin level info in file
(axi_master_driver.sv)
8

3.8 AXI_MASTER_MONITOR
The following two bits are used to control whether checks and coverage are done in the
monitor
. bit checks_enable = 1;
bit coverage_enable = 1;

TLM port is used to connect the monitor to the scoreboard


uvm_analysis_port #(AXI_transfer) item_collected_port;

// Create the covergroup


master_transfer_cg = new();
master_transfer_cg.set_inst_name("master_transfer_cg");

// Create the TLM port


item_collected_port = new("item_collected_port", this);

3.9 AXI_MASTER_SEQUENCE
It's a driver bridge

3.10 AXI PACKAGE


Import the UVM class library and UVM automation macros
`include "uvm_macros.svh"

`include "axi_type.sv"
`include "axi_conf.sv"
`include "axi_transfer.sv"
`include "axi_common.sv"

`include "axi_master_monitor.sv"
`include "axi_master_driver.sv"
`include "axi_master_sequencer.sv"
//`include "axi_master_recorder.sv"
`include "axi_master_agent.sv"
9

`include "axi_slave_monitor.sv"
`include "axi_slave_driver.sv"
`include "axi_slave_sequencer.sv"
`include "axi_slave_agent.sv"

`include "axi_env.sv"

3.11 AXI SLAVE AGENT


Slave agent, contain monitor or sequencer if the ACTIVE is on

3.12 AXI SLAVE DRIVER


Slave driver, transfer TLM level info to pin level info
3.13 AXI SLAVE MONITOR
The following two bits are used to control whether checks and coverage are done in the
monitor
bit checks_enable = 1;
bit coverage_enable = 1;
This TLM port is used to connect the monitor to the scoreboard
uvm_analysis_port #(AXI_transfer) item_collected_port;
TLM port is used to connect the monitor to driver, that can help driver to identify
// the trx mapping table based on trx's ID...
uvm_analysis_port #(AXI_transfer) item_write_port;
uvm_analysis_port #(AXI_transfer) item_read_port;

3.14 AXI SLAVE SEQUENCER


It's a driver bridge

3.15 AXI TRANSFER


Defines AXI transfer type
10

3.16 AXI VIRTUAL INTERFACE


Defines AXI virtual interface which is a connection pool interface for DUT and Virtual
test

3.17 AXI SCOREBOARD

// TLM write() implementation


function void Demo_scoreboard::write(AXI_transfer trx);
if(!disable_scoreboard) begin
`uvm_info(get_type_name(), $psprintf("Scoreboard \n%s", trx.sprint()), UVM_HIGH)
memory_verify(trx);
connect_verify(trx);
end
endfunction : write

// connect verify
function void Demo_scoreboard::connect_verify(AXI_transfer trx);
endfunction : connect_verify

// memory verify
function void Demo_scoreboard::memory_verify(AXI_transfer trx);

endtask
3.3 FUNCTIONAL COVERAGE
Cover group Cover point Coverage Remarks
status (%)
Cg1_axi Ex: Based on
the coverage
percentage,
remarks will
11

be updated

3.4 ASSERTIONS
Name of the Name of the Assertion Assertion
assertion property rule Status
12

3.5 CODE COVERAGE

Expecting a code coverage of 100 percent for the verification to be complete.

3.6 TEST SCENARIOS

NO Name of the testcase


1
2
3
4
5

3.7 TEST SCENARIOS DESCRIPTIONS


3.7.1 TEST SCENARIOS
13

Appendix A: References
The following table summarizes the documents referenced in this document.
Document Description Location
Name and
Version
<Document [Provide description of the <URL or Network path where
Name and document] document is located>
Version
Number>

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