DEPARTMENT OF

COMPUTER SCIENCE
Nutan College Of Engineering & Research, & ENGINEERING
Talegaon Dabhade, Pune- 410507
Computer Architecture And Organization
Unit I: Introduction
Introduction:
1. Concept of Computer Organization and Architecture.
2. Fundamental Unit.
3 .Computer Function and Interconnection.
4. CPU Structure and Function.

I. Concept of Computer Organization and Architecture

Computers Organization and Architecture is the study of internal working, structuring and implementation
of a computer system. Architecture in computer system, same as anywhere else, refers to the externally
visual attributes of the system. Externally visual attributes, here in computer science, mean the way a system
is visible to the logic of programs (not the human eyes!). Organization of computer system is the way of
practical implementation which results in realization of architectural specifications of a computer system. In
more general language, Architecture of computer system can be considered as a catalog of tools available
for any operator using the system, while Organization will be the way the system is structured so that all
those cataloged tools can be used, and that in an efficient fashion.

 Computer Architecture
Computer Architecture is an abstract model and are those attributes that are visible to programmer
like instruction sets, number of bits used for data, addressing technique.

 Computer Organization
Expresses the realization of architecture or how features are implemented like these registers, data
paths or connection to memory. Organizational attributes include those hardware details transparent
to the programmer, such as control signals; interfaces between the computer and peripherals; and
the memory technology used.

Example:
Both Intel and AMD processors have the same X86 architecture, but how the two companies
implement that architecture (their computer organizations) is usually very different. The same
programs run correctly on both, because the architecture is the same, but they may run at different
speeds, because the organizations are different.

Von Neumann Architecture

Von Neumann architecture was first published by John von Neumann in 1945.

His computer architecture design consists of a Control Unit, Arithmetic and Logic Unit (ALU), Memory
Unit, Registers and Inputs/Outputs.

Von Neumann architecture is based on the stored-program computer concept, where instruction data and
program data are stored in the same memory.

This design is still used in most computers produced today.

Architecture Diagram

Central Processing Unit (CPU)

The Central Processing Unit (CPU) is the electronic circuit responsible for executing the instructions of a
computer program.

It is sometimes referred to as the microprocessor or processor.

The CPU contains the ALU, CU and a variety of registers.

Registers

Registers are high speed storage areas in the CPU. All data must be stored in a register before it can be
processed.

MAR Memory Address Register Holds the memory location of data that needs to be accessed
MDR Memory Data Register Holds data that is being transferred to or from memory

AC Accumulator Where intermediate arithmetic and logic results are stored

PC Program Counter Contains the address of the next instruction to be executed

CIR Current Instruction Register Contains the current instruction during processing

Arithmetic and Logic Unit (ALU)

The ALU allows arithmetic (add, subtract etc) and logic (AND, OR, NOT etc) operations to be carried out.

Control Unit (CU)

The control unit controls the operation of the computer’s ALU, memory and input/output devices, telling them
how to respond to the program instructions it has just read and interpreted from the memory unit.

The control unit also provides the timing and control signals required by other computer components.

Buses

Buses are the means by which data is transmitted from one part of a computer to another, connecting all major
internal components to the CPU and memory.

A standard CPU system bus is comprised of a control bus, data bus and address bus.

Address
Carries the addresses of data (but not the data) between the processor and memory
Bus
DataBus Carries data between the processor, the memory unit and the input/output devices

Control Carries control signals/commands from the CPU (and status signals from other devices) in
Bus order to control and coordinate all the activities within the computer

Memory Unit

The memory unit consists of RAM, sometimes referred to as primary or main memory. Unlike a hard drive
(secondary memory), this memory is fast and also directly accessible by the CPU.

RAM is split into partitions. Each partition consists of an address and its contents (both in binary form).

The address will uniquely identify every location in the memory.

Loading data from permanent memory (hard drive), into the faster and directly accessible temporary memory
(RAM), allows the CPU to operate much quicker.

II. Fundamental unit

A computer consists of five functionally independent main parts input, memory, arithmetic logic
unit (ALU), output and control unit.

Fig.1.1 Computer System

Input device accepts the coded information as source program i.e. high level language. This
is either stored in the memory or immediately used by the processor to perform the desired
operations.

The program stored in the memory determines the processing steps. Basically the computer
converts one source program to an object program. i.e. into machine language.
Finally the results are sent to the outside world through output device. All of these actions are
coordinated by the control unit.

1. Input unit: -The source program/high level language program/coded information/simply data
is fed to a computer through input devices keyboard is a most common type. Whenever a key is
pressed, one corresponding word or number is translated into its equivalent binary code over a
cable & fed either to memory or processor.
Example: Joysticks, trackballs, mouse, scanners, etc are other input devices

2. Memory unit:-Its function into store programs and data. It is basically to two types

1 Primary memory
2 Secondary memory

1. Primary memory: - Is the one exclusively associated with the processor and operates at the
electronics speeds programs must be stored in this memory while they are being executed.
Memory contains a large number of semiconductors storage cells capable of storing one bit of
information. These are processed in a group of fixed site called word.
To provide easy access to a word in memory, a distinct address is associated with each
word location. Addresses are numbers that identify memory location.

Number of bits in each word is called word length of the computer. Programs must reside
in the memory during execution. Instructions and data can be written into the memory or
read out under the control of processor.

Memory in which any location can be reached in a short and fixed amount of time after
specifying its address is called random-access memory (RAM).

The time required to access one word in called memory access time. Memory which is
only readable by the user and contents of which can’t be altered is called read only
memory (ROM) it contains operating system.

Caches are the small fast RAM units, which are coupled with the processor and are often
contained on the same IC chip to achieve high performance. Although primary storage is
essential it tends to be expensive.
2. Secondary memory: - Is used where large amounts of data & programs have to be
stored, particularly information that is accessed infrequently.
Examples: - Magnetic disks & tapes, optical disks (ie CD-ROM’s), floppies etc.,

3. Arithmetic logic Unit (ALU):-

Most of the computer operators are executed in ALU of the processor like addition,
subtraction, division, multiplication, etc. the operands are brought into the ALU from
memory and stored in high speed storage elements called register. Then according to the
instructions the operation is performed in the required sequence.

The control and the ALU are may times faster than other devices connected to a computer
system. This enables a single processor to control a number of external devices such as
key boards, displays, magnetic and optical disks, sensors and other mechanical controllers.

4. Output unit:

These actually are the counterparts of input unit. Its basic function is to send the processed
results to the outside world.
Examples:- Printer, speakers, monitor etc.

5. Control unit:

It effectively is the nerve center that sends signals to other units and senses their states. The actual
timing signals that govern the transfer of data between input unit, processor, memory and output
unit are generated by the control unit.

III. Computer Function and Interconnection

 The basic function performed by a computer is execution of a program, which
consists of a set of instructions stored in memory. The processor does the actual
work by executing instructions specified in the program
 Instruction processing consists of two steps: The processor reads (fetches) instructions
from memory one ata time and executes each instruction. Program execution consists
of repeating the process of instruction fetch and instruction execution.
 Basic Instruction Cycle:
i. Fetch Cycle
ii. Execution Cycle
Fig.1.2 Basic Instruction Cycle
 At the beginning of each instruction cycle, the processor fetches an instruction
from memory. In a typical processor, a register called the program counter (PC)
holds the address of the instruction to be fetched next. The processor always
increments the PC after each instruction fetch so that it will fetch the next
instruction in sequence.
 The fetched instruction is loaded into a register in the processor known as the
instruction register (IR). The instruction contains bits that specify the action the
processor is to take. The processor interprets the instruction and performs
the required action. In general, these actions fall into four categories
1Processor-memory: Data may be transferred from processor to memory or from
memory to processor.
2Processor-I/O: Data may be transferred to or from a peripheral device by
transferring between the processor and an I/O module.
3Data processing: The processor may perform some arithmetic or logic operation on
data.
4Control: An instruction may specify that the sequence of execution be altered. For
example, the processor may fetch an instruction from location 149, which specifies
that the next instruction be from location 182. The processor will remember this fact
by setting the program counter to 182.Thus, on the next fetch cycle, the instruction
will be fetched from location 182 rather than 150.
Consider a simple example using a hypothetical machine that includes the
characteristics listed in Figure 3.4. The processor contains a single data register,
called an accumulator (AC).
Fig 1.3 Example of Program Execution
Three instructions, which can be described as three fetch and three execute cycles, are
required:
The PC contains 300, the address of the first instruction. This instruction (the value 1940
in hexadecimal) is loaded into the instruction register IR and the PC is incremented. Note
that this process involves the use of a memory address register

(MAR) and a memory buffer register (MBR). For simplicity, these intermediate registers
are ignored.
The first 4 bits (first hexadecimal digit) in the IR indicate that the AC is to be loaded. The
remaining 12 bits (three hexadecimal digits) specify the address (940) from which data
are to be loaded.

i. The next instruction (5941) is fetched from location 301 and the PC is incremented.
ii. The old contents of the AC and the contents of location 941 are added and the
result is stored in the AC.
iii. The next instruction (2941) is fetched from location 302 and the PC is incremented.
iv. The contents of the AC are stored in location 941.

 A single instruction cycle with the following steps occurs:

i. Fetch the ADD instruction.
ii. Read the contents of memory location A into the processor.
iii. Read the contents of memory location B into the processor. In order that the
iv. contents of A are not lost, the processor must have at least two registers for
v. Storing memory values, rather than a single accumulator.
vi. Add the two values.
vii. Write the result from the processor to memory location A.

 The Instruction Cycle State Diagram states can be described as follows:

i. Instruction fetch (if): Read instruction from its memory location into the processor.
ii. Instruction operation decoding (iod): Analyze instruction to determine
type of operation to be performed and operand(s) to be used.
iii. Operand address calculation (oac): If the operation involves reference to an
operand in memory or available via I/O, then determine the address of the
operand.
iv. Operand fetch (of): Fetch the operand from memory or read it in from I/O.
v. Data operation (do): Perform the operation indicated in the instruction.
vi. Operand store (os): Write the result into memory or out to I/O.
Instruction address calculation (iac): Determine the address of the next I
instruction to be executed. Usually, this involves adding a fixed number to
vii. the address of the previous instruction. For example, if each instruction is 16
bits long and memory is organized into 16-bit words, then add 1 to the previous
address. If, instead, memory is organized as individually addressable 8-bit
bytes, then add 2 to the previous address.
Fig.1.4 Instruction Cycle State Diagram
 States in the upper part of Figure 3.6 involve an exchange between the processor and
either memory or an I/O module. States in the lower part of the diagram involve only
internal processor operations.
 The oac state appears twice, because an instruction may involve a read, a write, or both.
 Also note that the diagram allows for multiple operands and multiple results, because
some instructions on some machines require this. For example, the PDP-11 instruction
ADD A, B results in the following sequence of states: iac, if, iod, oac, of, oac, of, do,
oac, os.

 Interrupts
 Virtually all computers provide a mechanism by which other modules (I/O, memory)
may interrupt the normal processing of the processor.
 The most common classes of interrupts

1. Program-Generated by some condition that occurs as a result of an instruction

execution, such as arithmetic overflow, division by zero.
2. Timer-Generated by a timer within the processor. This allows the operating
system to perform certain functions on a regular basis.
3. I/O-Generated by an I/O controller.
4. Hardware failure- Generated by a failure such as power failure or memory
parity error. Interrupts are provided primarily as a way to improve processing
efficiency.
Fig.1.5 Program Flow of Control without and with Interrupts
 Interrupts and Instruction cycle

1. With interrupts, the processor can be engaged in executing other instructions while an I/O
operation is in progress. Consider the flow of control in Figure 3.7b.As before, the user program
reaches a point at which it makes a system call in the form of a WRITE call. The I/O program
that is invoked in this case consists only of the preparation code and the actual I/O command.
After these few instructions have been executed, control returns to the user program. Meanwhile,
the external device is busy accepting data from computer memory and printing it. This I/O
operation is conducted concurrently with the execution of instructions in the user program.
2. When the external device becomes ready to be serviced—that is, when it is ready to accept more
data from the processor,—the I/O module for that external device sends an interrupt request signal
to the processor. The processor responds by suspending operation of the current program,
branching off to a program to service that particular I/O device, known as an interrupt handler,
and resuming the original execution after the device is serviced. The points at which such
interrupts occur are indicated by an asterisk in Figure 3.7b.
3. From the point of view of the user program, an interrupt is just that: an interruption of the normal
sequence of execution. When the interrupt processing is completed, execution resumes (Figure
3.8). Thus, the user program does not have to contain any special code to accommodate interrupts;
the processor and the operating system are responsible for suspending the user program and then
resuming it at the same point.
To accommodate interrupts, an interrupt cycle is added to the instruction cycle, as shown in Figure 3.9.
In the interrupt cycle, the processor checks to see if any interrupts have occurred, indicated by the
presence of an interrupt signal. If no interrupts are pending, the processor proceeds to the fetch cycle
and fetches the next instruction of the current program. If an interrupt is pending, the processor does the
following:
It suspends execution of the current program being executed and saves its context.
It sets the program counter to the starting address of an interrupt handler routine.

Fig.1.6 Transfer of Control via Interrupts

The processor now proceeds to the fetch cycle and fetches the first instruction in the interrupt handler
program, which will service the interrupt. The interrupt handler program is generally part of the
operating system. Typically, this program determines the nature of the interrupt and performs whatever
actions are needed.

When the interrupt handler routine is completed, the processor can resume execution of the user
program at the point of interruption.

 Multiple Interrupts
Fig.1.7.Sequential and nested interrupt processing

 Interconnection
The collection of paths connecting the various modules is called the interconnection structure. The
design of this structure will depend on the exchanges that must be made among modules.
Figure (3.15) 1.9 suggests the types of exchanges that are needed by indicating the major forms of
input and output for each module type:
Memory: Typically, a memory module will consist of N words of equal length. Each word is assigned
a unique numerical address (0,1,...,N – 1).A word of data can be read from or written into the memory.
The nature of the operation is indicated by read and write control signals. The location for the
operation is specified by an address.
I/O module: From an internal (to the computer system) point of view, I/O is functionally similar to
memory. There are two operations, read and write. Further, an I/O module may control more than one
external device. We can refer to each of the interfaces to an external device as a port and give each a
unique address (e.g.,0,1,...,M – 1).In addition, there are external data paths for the input and output of
data with an external device. Finally, an I/O module may be able to send interrupt signals to the
processor.
Processor: The processor reads in instructions and data, writes out data after processing, and uses
control signals to control the overall operation of the system. It also receives interrupt signals.
The interconnection structure must support the following types of transfers:
Memory to processor: The processor reads an instruction or a unit of data from memory.
Processor to memory: The processor writes a unit of data to memory.
I/O to processor: The processor reads data from an I/O device via an I/O module.
Processor to I/O: The processor sends data to the I/O device.
I/O to or from memory: For these two cases, an I/O module is allowed to exchange data directly with
memory, without going through the processor, using direct memory access (DMA).

Fig.1.9 Computer Modules

 Bus Interconnection
Bus is a communication pathway connecting two or more devices. A key characteristic of a bus is that
it is a shared transmission medium. Multiple devices connect to the bus, and a signal transmitted by
any one device is available for reception by all other devices attached to the bus. If two devices
transmit during the same time period, their signals will overlap and become garbled. Thus, only one
device at a time can successfully transmit.
Typically, a bus consists of multiple communication pathways, or lines. Each line is capable of
transmitting signals representing binary 1 and binary 0.
A bus that connects major computer components (processor, memory, I/O) is called a system bus.

Fig.1.10.Bus Interconnection Scheme

 Bus Structure
The data lines provide a path for moving data among system modules.
These lines, collectively, are called the data bus. The data bus may consist of 32,64,128, or even more
separate lines, the number of lines being referred to as the width of the data bus. Because each line can
carry only 1 bit at a time, the number of lines determines how many bits can be transferred at a time.
The width of the data bus is a key factor in determining overall system performance.
The address lines are used to designate the source or destination of the data on the data bus.
The control lines are used to control the access to and the use of the data and address lines. Because
the data and address lines are shared by all components, there must be a means of controlling their use.
Control signals transmit both command and timing information among
system modules. Timing signals indicate the validity of data and address information. Command
signals specify operations to be performed. Typical control lines include
 Memory write: Causes data on the bus to be written into the addressed location
 Memory read: Causes data from the addressed location to be placed on the bus
 I/O write: Causes data on the bus to be output to the addressed I/O port
 I/O read: Causes data from the addressed I/O port to be placed on the bus
 Transfer ACK: Indicates that data have been accepted from or placed on the bus
 Bus request: Indicates that a module needs to gain control of the bus
 Bus grant: Indicates that a requesting module has been granted control of the bus
 Interrupt request: Indicates that an interrupt is pending
 Interrupt ACK: Acknowledges that the pending interrupt has been recognized
 Clock: Is used to Synchronize operations
 Reset: Initializes all modules.

IV.CPU Structure and Function

 Structure: The way in which the components are interrelated

 Function: The operation of each individual component as part of the structure

Function
The basic functions that a computer can perform. In general terms, there are only four:
 Data processing
 Data storage
 Data movement
 Control
.

Fig.1.11 Possible Computer Operations

Structure
There are four main structural components:
Central processing unit (CPU)-Controls the operation of the computer and performs its data
processing functions; often simply referred to as processor.
Main memory-Stores data
I/O- Moves data between the computer and I/O
System interconnection-mechanism that provides communication among CPU, main
memory, and I/O. A common example of system interconnection is by means of a system
bus, consisting of a number of conducting wires to which all the other components attach.

Fig.1.12.Computer Top Level Structure

Its major structural components are as follows:

Control unit: Controls the operation of the CPU and hence the computer
Arithmetic and logic unit (ALU): Performs the computer’s data processing functions
Registers: Provides storage internal to the CPU
CPU interconnection: Some mechanism that provides for communication among the control
unit, ALU, and registers
IAS( Von Neumann Architecture)
Key Feature: Stored program Concept

Reference:
Computer Organization and Architecture by – William Stallings 8th edition

Ms. Shital P. Shinde

(Subject Co-ordinator)

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