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The document is a resume for Jenifer Nisha Jacob, who has over 7 years of experience in technical project management, post-silicon validation, and customer engagement at Intel Corporation. Her experience includes product ownership of validation tools, customer interactions, hardware and software engineering, and research assistant work. She holds a Master's degree in Computer Engineering from Northwestern University.

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47 views

Profile

The document is a resume for Jenifer Nisha Jacob, who has over 7 years of experience in technical project management, post-silicon validation, and customer engagement at Intel Corporation. Her experience includes product ownership of validation tools, customer interactions, hardware and software engineering, and research assistant work. She holds a Master's degree in Computer Engineering from Northwestern University.

Uploaded by

Jenifer Nisha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Contact

[email protected]
JENIFER NISHA JACOB
tern.edu Technical Project Management | Post-Silicon Validation | Customer
Engagement
www.linkedin.com/in/jenifer-nisha-
Hillsboro, Oregon, United States
jacob (LinkedIn)

Top Skills Summary


Customer Satisfaction Experienced technical professional with a cross functional
Continuous Integration and background spanning across hardware engineering, software
Continuous Delivery (CI/CD)
development and project management. Direct customer engagement
MacOS X
experience with Customer First mindset and stakeholder
management.
Languages
Tamil (Native or Bilingual)
Technical expertise in Silicon Validation with 7+ years of experience
English (Full Professional)
in tool development & validation, debugging, Project Management
Hindi (Elementary)
and Agile methodologies.

Honors-Awards
Second prize in the World Science
Day Project Expo
Experience
Division Recognition Award
Intel Corporation
Division Recognition Award
7 years 10 months
Division Recognition Award
Technical Product Owner - Post Silicon Validation Tools
December 2016 - Present (6 years)
Hillsboro, Oregon, United States

Product Owner – IO Margin Tool (IOMT)

• Successfully delivered Intel IO Margin Tool (IOMT) for System Marginality


Validation of PEG, DMI, USB4, PCIe, USB3, SATA and UFS on Windows,
Chrome OS, Ubuntu and OS X through 5+ generations of Intel Client
processors across Mobile, Desktop and Workstation segments on time, with
aggressive project schedules

• Collaborated across multidisciplinary teams including Silicon Architecture,


BIOS, PHY Design, Electrical Validation, Functional Validation and Customer
Enabling teams to guide features from conception to launch

• Guided development/validation teams in sprint activities, introducing new


features/requirements, explaining business impact, defining & prioritizing user
stories and demystifying complex challenges / roadblocks

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• Established clear processes for OxMs to use the software solution across
various stages of product development & manufacturing

• Division Recognition Award Q3'22 for Delivering BOM cost optimization by


implementing UFS on Intel 13th Generation Mobile platforms

Product Owner - Impedance Spectrum Tool (IST)

• Collaborated with FIVR design and Debug Architects to enable DFx with
security policy in Intel Client processors to allow OxMs to measure PDN
Impedance on their platforms

• Defined the roadmap for IST by establishing integration plan, validation plan
and future support model

• Hands-on experience with Oscilloscopes, DMMs and good understanding of


Power Integrity concepts

Apple/Chrome EV Tools Lead


December 2017 - July 2021 (3 years 8 months)
Santa Clara, California, United States

• Responsible for customer interaction, making commitments, managing


schedule, commitments and driving issue resolution of all EV Tools delivered
to Apple and Google

• Liaison between the Tier 1 OEMs and internal engineering teams. Good
stakeholder management resulting in zero escalations from customers

• Chaired weekly Key Customer EV Tools Forum to update roadmap, review


progress against goals, raise potential roadblocks/delays and discuss new
customer requests

• Led the implementation of IO Tuning Tool to provide OEM the capability to


tune Integrated TBT that was newly introduced 10th Gen Intel Core processors

• Provided on-site PDN Impedance Measurement service for Tier 1 OEM


designs while the external version was under development

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• Division Recognition Award Q4'18 for First Release of Ubuntu IO Margining
Tool to Apple in Record Time

• Division Recognition Award Q2'21 for Shift-left & streamline release of


Electrical Validation/Compliance Tools for Intel 11th Gen Chrome Platforms

Hardware/Software Engineer - Customer Co-engineering


February 2015 - December 2016 (1 year 11 months)
Hillsboro, Oregon, United States

• Owned enhancement, validation, release and debug of Intel Electrical Margin


Tool (IEMT) (Python based OS application) for a Tier 1 OEM for two client
processor generations

• Enhancements included - enabling OS specific Power Management


requirements/benchmarks, GUI modifications (Javascript), Auto-detection of
devices, reporting Equalization parameters

• Created a CI/CD pipeline for IEMT using TeamCity to allow regular


integration of ingredients and nightly build and deployment of installer, thus
leading to early detection of bugs

• Comprehended schematics/board files for customer designs, identified corner


cases, defined exhaustive test plan, procured platforms/devices/dependencies
and automated execution of test cases

• Hands-on expertise in Intel Reference Validation Platforms and Customer


Prototypes, flashing OS & BIOS and enabling interfaces including memory,
external graphics, display port, PCIe & SATA

• Good understanding of system software stack comprising of low level


registers access methods (MSRs, MMIO, Port IO etc), firmware interfaces(SPI
and UEFI), development and debugging on kernel mode drivers(Win), shared
libraries and application software.

Intel Corporation
Graduate Intern
June 2014 - December 2014 (7 months)
Hillsboro, Oregon

• Was part of a team that developed Intel Brand Verification Tools that perform
series of hardware/software checks on OEM/ODM systems for compliance
with Intel branding programs(vPro, Ultrabook, etc.).
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• Owned the implementation of verification tests for 6th generation Intel®
Core™ processor family

• Engineered test cases for the nightly automation to ensure compliance with
Intel Architecture requirements.

• Coordinated and collaborated with the team in an Agile Software


development methodology.

Northwestern University, McCormick School of Engineering and


Applied Sciences
Research Assistant
March 2014 - June 2014 (4 months)
Evanston

• Designed Multi-speculative Adders (Brent-Kung, Kogge-Stone, Ripple Carry)


using VHDL
• Examined the working of these adders by introducing 1-bit carry predictors
between different fragments of the adders.
• Inspected the behavior of these adders at reduced voltage levels using
Synopsys VCS.
• Evaluated several FPGA based Soft Error Injection techniques that introduce
SEUs, trace output and observe effects.

Northwestern University, McCormick School of Engineering and


Applied Sciences
Java Tutor
October 2013 - December 2013 (3 months)
Evanston, Illinois, United States

• Assisted graduate (in Analytics) students to understand object oriented


concepts through java.
• Clarified their doubts and taught them to trace and debug code snippets in
java.
• Helped them to outline their projects and code efficiently using Eclipse IDE.

Infosys
Systems Engineer
October 2012 - August 2013 (11 months)
Chennai, Tamil Nadu, India

Developed and enhanced web applications for a fortune 500 client.

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Education
Northwestern University
Master of Science (MS), Computer Engineering · (2013 - 2014)

Panimalar Engineering College, Anna University


Bachelor of Engineering, Electronics And Instrumentation · (2008 - 2012)

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