Scribd
Upload
20 views

Siddhi_DV_Engineer.pdf

Design verification Role

Uploaded by

passioncool.india
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
20 views

Siddhi_DV_Engineer.pdf

Design verification Role

Uploaded by

passioncool.india
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Education

Siddhi Kadam Master’s in Technology (Electronics)


VJTI, Mumbai
9.14 CGPI
2018 - 2020

Bachelors in Engineering (Electronics) 2013 - 2017


Shah & Anchor Kutchhi Engg. College
8.01 CGPI

Employment
Design & Verification Engineer Dec 2022 - Present
Truechip Solutions Pvt. Ltd., Pune

1) Project Name: NOC Verification IP – SV, UVM, Perl scripting

 Developing the top-level test bench architectures for verification


of multiple NOC IP structures.
 Understanding NOC Scoreboard used for verification of multi-
protocol (AXI 3/4/5/4lite, AHB 3lite/5, and APB 4/5) and multi-

Personal Details 
width IPs.
Implementation of features of AMBA5 protocol in NOC
Scoreboard.
[email protected]  Perl scripting used to run the commands and regression.
 Test plan generation & Debugging test scenarios.
8879055223  NOC VIP Presentations to the clients.
Dombivli, Mumbai
2) Project Name: AXI VIP
www.linkedin.com/in/siddhi9519

 Understanding the top level architecture for Single-Master &


Skills 
Single-Slave architecture, Multi-environment architectures.
Writing Assertions.
 Test plan generation. Debugging test failures & fixing the
 SV implementation for corner case scenarios.

 UVM
 SVA Associate Engineer - Trainee May 2022 - Nov 2022
Sevitech (UST Global), Bangalore
 Perl Scripting
 Computer Architecture 1) Project Name: ARM SoC – AMBA AHB / APB 4.0 BFM Developments
 Circuit Design & AXI Master & Slave UVC – AMBA AXI4 Protocol Language:
System Verilog, UVM
 EDA Tools - Questa
 Understand AHB / APB VIP architecture document Specifications
Hobbies 
& done Feature Extraction.
Developed Reusable Test Bench Architecture having AHB Master
& APB slave that supports all the burst WR/RD transactions.
 Listening Music Assertions to cover multiple Burst scenarios. Debugging test
failures & generated functional and code coverage
 Cooking
 Singing 2) Project Name: BLE-5 Protocol Verification- Language used: System
Verilog, UVM, Perl Scripting

Qualities  Understand BLE5 Specifications & created V-plan


 Understand different BLE states & packet structures.
 Good Listener  Verification using multiple test cases to verify BLE configuration
(VIP-VIP) using Advertising, Scanning, and Initiating Packets.
 Good Communication Skills  Writing constraints for various parameters in BLE packet
 Team-Player structure.

 Self-Motivated
SAP MM Consultant Dec 2020 - May 2022
IBM India Pvt. Ltd., Ahmedabad

Achievements Project: Worked on two technologies – SAP ECC and SAP Ariba.

 To provide technical support to the client-facing challenges in


 Awarded for giving high work SAP ECC and to deliver as per the client’s requirements.
throughput from IBM Employer.  To configure solution requirements on the products; understand
 Publication in IJRASET for Computer if any issues and diagnose the root cause of such issues. To work
Architecture-based topic – with the client and other SAP teams to meet a common goal.
Performance Improvement of  Logical thinking and problem-solving skills along with an ability
Existing Cache Replacement Policies to collaborate were keen points for this role.

Internships
 Received Scholarship from VJTI
Alumni Association during MTech,
2019
 Appointed as Alumni Representative
in Departmental Advisory Board in Engineering Intern July 2019 – Nov 2019
BE College, 2022 Cummins India Pvt. Ltd. , Pune

1) Project - ECU Failure due to welding - Analysis


Analysis of ECU damage during welding - Which sub-components of ECU
are getting affected, the reason to cause ECU failure, and designing a
circuit to prevent this damage, was done during the project.
Tools used - NI circuit design, LT Spice
Assigned work - Analyse the problem statement and design a circuit,
design DFMEA, and DVPnR

2) Project - Battery monitoring algorithm without using battery


sensor
Battery's state of charge is a critical index in BMS. Usually, the coulomb
counting method is used to estimate the SOC. But since the module
associated with the CC method is expensive an attempt was made to
estimate the SOC of the battery using OCV with a reverse-engineering
concept.
Tools Used - Arduino, NI circuit design, Fritzing tool.

Intern June 2020 – July 2020


Technoventor Solutions Pvt. Ltd., Nagpur

Project - Automatic Hand Sanitizer Dispenser (Hobby Project)


The challenge was to create the dispenser without using a
microcontroller. This way the module will be very cost-effective and
easy to design.

Course
Maven Silicon – Bangalore

Project Name: Router 1x3 – RTL Design and Verification. Language


Used: Verilog, System Verilog, UVM.

 Architected the block-level structure for the design. Implemented


RTL using Verilog HDL
 Architected the class-based verification environment using System
Verilog.
 Verified the RTL model using various test cases such as packets of
different sizes, erroneous packets, etc.
 Generated functional and code coverage for the RTL verification sign-
off.

You might also like