Setting up ASAP7 PDK

Copy the folder asap7 into your home directory, this will be your work directory for 7nm:

cp -r /home/eng/v/vks160030/asap7/ ~

cd asap7

Running Virtuoso

Every time you quit, before starting Virtuoso or Innovus, type in the following commands.

. /home/eng/v/vks160030/profile.ic-adv_asap7

virtuoso
Create New Library

File -> New -> Library

In Library give the name of the library (can be any other name too)
In Technology File select Attach to an existing an existing technology library
Click OK
Select asap7_TechLib

Click OK

Create New Cell View

For Layout

File -> New -> Cellview

In File,
Library: Select the name of the library which you created in the previous step
Cell: Give the name of the standard cell you will be designing
Type: select layout

Click OK

If you get this warning, click Yes and proceed

An empty layout view should open

Before starting inverter layout, 3 things should be done:

1) On the le side of the screen, in layers click on AV and check if you have layers such as
n drw, Gate drw, LISD drw.
2) On top of the screen, in the tool bar look for Calibre. If you do not nd Calibre, it means
that you haven’t setup environment properly. Go back to Se ng up ASAP7 PDK and
repeat.
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3) Go to Op ons -> Display
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In Grid Controls, X Snap Spacing = 0.001, Y Snap Spacing = 0.001

Now you can proceed to layout drawing

Inverter Layout Tutorial
Layout Rules:
▪ Gate width = 0.02um
▪ Gate pitch = 0.054um
▪ Fin width = 0.007um
▪ Fin pitch = 0.027um
▪ Cell height = 0.288um
▪ SDT width = 0.024um
▪ Minimum width M1, M2, M3 = 0.018um
▪ V0, V1, V2 = 0.018um x 0.018um

i) Select Gate drawing layer and Press R to draw the layer. Draw the layer with a width of
0.02u and a height of 0.288u. Place the Gate at a distance of 0.17u from the reference y-
axis as shown in the picture below.
Place 2 more gates beside this gate, the distance between each gate should be 0.034um
and gate pitch = 0.054um

Gate pitch

The outer two gates are dummy gates.

ii) Select n drawing layer. Draw the rst n as shown in the picture below, it should be
touching the y-axis and distance from the x-axis is 0.019um. The width of n must be
0.007um.
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Similarly place 9 ns above this n, the distance between each n should be 0.02um and
n pitch = 0.027um
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Fin pitch

iii) Draw the BOUNDARY drawing layer as shown in picture, it should cover all gates and
ns.
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iv) Draw well drawing (0.162um x 0.144um)
v) Draw GCut drawing. It is drawn at the center of dummy gates (0.054um x 0.044um) and
also at the top and bo om (0.162um x 0.037um). Please refer the below image. At the
bo om GCut layer is 0.006um below the x-axis and at the top its 0.006 above the
BOUNDARY layer.
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vi) Draw Ac ve drawing for pfet and nfet (0.07um x 0.081um)
Wp = Wn = 0.081um. On le and right, distance between the dummy gate and Ac ve
layer is 0.009um. On top and bo om, distance between the GCut layer and Ac ve layer
is 0.005um.
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vii) Draw SDT drawing on Ac ve (0.024 um x 0.081 um). The distance between Gate and SDT
is 0.005um. SDT is drawn on Ac ve layer wherever connec ons are to be made. If a
source or drain has no connec ons, then SDT layer should not be drawn.
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viii) Draw LISD drawing on top on SDT drawing, wherever VDD and GND connec ons are to
be made, extend the LISD layer above the Ac ve layer by 0.027um as shown in the
below picture.

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ix) Draw LIG drawing. ChangeOn top and bottom for connecting the LISD layer to VDD
and GND (0.162um x 0.016um). One for gate connection (0.022um x 0.024um).

Note: The distance GCut layer and LIG layer is 0.014um

LIG for gate connection: (0.022um x 0.024um)

Refer the below shown picture. Distance from GCut (left and right): 0.016um, Distance from
Active (top and bottom): 0.015um
x) Draw V0 drawing (via0: similar to contact in 65nm) for the all gates, nets and VDD, GND
(place V0 on LIG layer).
V0: 0.018um x 0.018um.
7 V0s drawn are marked in the layout

1 2

6 7
xi) Draw M1 to connect the nets and for VDD and GND

In the below figure, all other layers are disabled so that only M1 and V0 are visible
In the picture below all drawn layers are visible
xii) Draw Pselect on top on pfet and Nselect on top of nfet (0.162um x 0.135um).
Only V0, LISD, LIG, Pselect, Nselect
The picture below has all drawn layers are visible
xiii) VDD and GND are brought to M2.
Input and output pins are brought up to M3.

For VDD and GND, draw M2 on top of M1, place V1 (0.018um x 0.018um) to connect M1
to M2
In the below picture only M1, M2, V1 are made visible
All drawn layers are visible below
Now create labels for VDD and GND as VDD! and GND! using M2 pin layer
On the top tool bar, Create -> Label

Place the labels on M2 drawing layer

Input and output pins should be brought up to M3,
Place M2 and V1 (0.018um x 0.018um) on top of M1.

Only M1, M2, V1 are enabled in the below picture

Below is the picture with all drawn layers

Now place M3 and V2 (0.018um x 0.018um) on top of M2.

Only M1, M2, M3, V2 are enabled in the picture below

All drawn layers are visible in the next picture

Now create label for Input and Output pins
Create -> Label
Place them on M3 pins.
Inverter layout is now completed.

Schema c
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Go to Virtuoso main window
File -> New -> Cellview

Click OK

i) In the tool bar on topTo create nfet: Create -> Instance

Library: asap7_TechLib
Cell: nmos_rvt
View: symbol
Fins: 3 (Width sets to 81nm)

ii) Similarly, to create pfet: Create -> Instance

Library: asap7_TechLib
Cell: pmos_rvt
View: symbol
Fins: 3 (Width sets to 81nm)
iii) Press W and draw wires.

iv) Create Input and Output Pins

Create -> Pin

Create -> Pin

v) Add VDD and GND
Create -> Instance

Create -> Instance

Final Schematic should like this:

Check and Save the design

Inverter schematic is now completed.

Design Rule Check

In the layout view, on the tool bar at the top

Calibre -> Run nmDRC

Rules: In DRC Rules File, browse and select the Calibre_DRC_Rules le which is in your work
directory (asap7)

In DRC Run Directory, if you are unable to edit in the interac ve window, go to les and create a
new directory and browse that directory in the interac ve window.

Inputs:
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Outputs:

Run Control:
Click on the Run DRC tab

You will get 1 error as shown in picture below:

If you get any other errors, you have to x them before proceeding.
If you have only 1 error, proceed ahead
In order to get a DRC clean inverter, you need to add a Tap Cell

Go to Library Manager -> In Library column, select asap7_TechLib -> Tap_Cell -> Open layout

Copy the en re Tap_Cell and paste it beside the inverter as shown below
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Make sure all the layers of Tap_Cell align with your inverter layout

Note: When you draw layouts manually and place them one beside another, you just need to
have 1 Tap_Cell in entire row. Tap cells help pfets and nfets to tie to VDD and GND levels
so that they don't drift too much.

This means that in the nal stages of your project 1 when you perform DRC of all standard
cell, only 1 Tap cell needs to be placed at the right corner.
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Run DRC again, you should have no errors
Layout vs Schema c

In the layout view, Calibre -> Run nmLVS

Rules: In LVS Rules File, browse and select the Calibre_LVS_Rules le which is in your work
directory (asap7)

In LVS Run Directory, if you are unable to edit in the interac ve window, go to les and create a
new directory and browse that directory in the interac ve window.

Inputs:

Layout tab: Select the op on Export from layout viewer

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Netlist tab: Select the op on Export from schema c viewer, Format: SPICE

Outputs:
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Run Control:
Click on Run LVS

Parasi c Extrac on

Rules: In the layout view, Calibre -> Run PEX

Rules: In PEX Rules File, browse and select the Calibre_RCX_Rules le which is in your work
directory (asap7)

In PEX Run Directory, if you are unable to edit in the interac ve window, go to les and create a
new directory and browse that directory in the interac ve window.
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Inputs:
Layout tab: Select the op on Export from layout viewer

Netlist tab: Select the op on Export from schema c viewer, Format: SPICE
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Outputs: Fomat -> HSPICE, Use Names From -> SCHEMATIC

Run Control
Click on Run PEX

Ignore the 6 warnings.

Parasi c extrac on of inverter is now completed.

Go to the loca on where you saved inverter.pex.netlist le and use this le to run HSPICE.
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HSPICE

Make a new directory for HSPICE simula ons in your work directory
mkdir ~/asap7/hspice
cd ~/asap7/hspice

Make another directory for inverter les

mkdir inverter
cd inverter

Copy the parasi c extracted les into this directory: 3 les should be copied into this loca on
⇒ inverter.pex.netlist
⇒ inverter.pex.netlist.pex
⇒ inverter.pex.netlist.INVERTER.pxi

Create a hspice file:

gedit inverter_hspice.sp

Transistor Model file 7nm_TT.pm is already available in your work directory

Save this file and run HSPICE

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. /proj/cad/startup/profile.synopsys_2016
hspice inverter_hspice.sp
Run Waveview and analyze the results
wv&

For more details about analyzing results: https://personal.utdallas.edu/~Xiangyu.Xu/wv/