CHAPTER 2

The Microprocessor and its Architecture

‫رابط الكورس كامل لهندسة حاسب | جامعة الطائف‬

https://si-manual.com/courses/micro-processors

‫رابط الكورس كامل لعلوم حاسب | جامعة الطائف‬

https://si-manual.com/courses/micro-processors-and-assembly-language

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Chapter Content

▪ Intel Core2 and 8086 Microprocessors

▪ Core2 Microprocessor and 8086 registers
▪ Multipurpose Registers
▪ Special-Purpose Registers

▪ Intel 8086 Microprocessor

▪ BIU and EU of 8086 Microprocessor
▪ Pipelining
▪ 8086 Microprocessor Registers

▪ Introduction to Assembly Language

▪ MOV instruction
▪ ADD Instruction

▪ Program Segments
▪ Code Segment Code Segment
▪ Data Segment
▪ Little Endian Convention
▪ Stack Segment
▪ Flag Register

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Intel Microprocessor from 8086 → Core 2

Intel 8086 16-bit

Intel 80286 16-bit
Intel 80386 32-bit
Intel core 2 32-bit with 64-bit extension

8086 through Core2 consider two types of registers:

Core2 ‫ و الي معالجات‬8086 ‫ في معالجات‬registers ‫هناك نوعين من ال‬
▪ Program visible registers: ‫مرئية للبرنامج‬
registers are used during programming and are specified by the instructions.
▪ Program invisible registers: ‫غير مرئية للبرنامج‬
not addressable directly during applications programming

▪ 80286 and above contain program-invisible registers to control and operate protected memory and other features of the microprocessor
▪ 80386 through Core2 microprocessors contain full 32-bit internal architectures.
▪ 8086 through the 80286 are fully upward-compatible to the 80386 through Core2.

The programming model 8086 through Core2 microprocessor including the 64-bit extensions.

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Registers of 8086 and Core2 microprocessor

Multi-purpose Registers Special -purpose Registers

RAX RIP addresses the next instruction in a section of memory.
▪ a 64-bit register (RAX) ▪ defined as (instruction pointer) a code segment.
▪ a 32-bit register (accumulator) (EAX)
▪ 16-bit register (AX) RSP addresses an area of memory called the stack.
▪ or as either of two 8-bit registers AH and AL
▪ the (stack pointer) stores data through this pointer
The accumulator is used for instructions such as multiplication, division, and
some of the adjustment instructions. RFLAGS indicate the condition of the microprocessor and control its
operation.
▪ Flags are upward-compatible from the 8086/8088 through Core2.
RBX ▪ The rightmost five and the overflow flag are changed by most
▪ addressable as RBX, EBX, BX, BH, BL. arithmetic and logic operations.
▪ BX register (Base Index) sometimes holds offset address of a location in ▪ although data transfers do not affect them
the memory system in all versions of the microprocessor.

RCX
▪ RCX, ECX, CX, CH, or CL.
▪ a (Count) general-purpose register that also holds the count for various
▪ Flags never change for any data transfer or program control
instructions
operation.
▪ Some of the flags are also used to control features found in the
RDX microprocessor.
▪ RDX, EDX, DX, DH, or DL.
▪ a (Data) general-purpose register holds a part of the result from a
multiplication or part of dividend before a division.
Segment Registers
Generate memory addresses when combined with other registers in the
RBP microprocessor.
▪ RBP, EBP, or BP.
▪ points to a memory (Base Pointer) location for memory data transfers
1. CS (Code Segment) holds code (programs and procedures)
used by the microprocessor.

RDI 2. DS (Data Segment) contains most data used by a program.

▪ RDI, EDI, or DI.
Data are accessed by a content of other registers that hold.
▪ often addresses (destination index) string destination data for the string
instructions.
3. SS (Stack Segment) defines the area of memory used for the
RSI used as RSI, ESI, or SI. stack.
- stack entry point is determined by the stack segment and stack
▪ the (source index) register addresses source string data for the string
pointer registers.
instructions
▪ Like RDI, RSI also functions as a general-purpose register. - The BP register also addresses data within the stack segment.

4. ES (Extra Segment) an additional data segment used by

some instructions to hold destination data.
R8 - R15
▪ found in the Pentium 4 and Core2 if 64-bit extensions are enabled.
▪ data are addressed as 64-, 32-, 16-, or 8-bit sizes and are of general
purpose.

HL AL

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BIU and EU of 8086 Microprocessor

8086 CPU

:‫تم تقسيمه الي‬

BIU EU
(Bus Interface Unit) (Execution Unit)

‫ مع ال الذاكرة و مع‬BIU ‫تتعامل ال‬ ‫ بتنفيذ التعليمات‬EU ‫تقوم ال‬

‫ و تأخذ منها تعليمات‬I/O ‫ال‬
‫األسمبلي و البينات و ترسلها الي ال‬ BIU ‫المرسلة لها من ال‬
EU

The 8086 CPU logic has been partitioned into two functional units:
▪ Bus Interface Unit (BIU)
▪ Execution Unit (EU)

The major reason for this separation is to increase the processing speed of the processor.
‫السبب الرئيسي لهذا التقسيم هو زيادة سرعة المعالج‬

Bus Interface Unit (BIU) Execution Unit (EU)

The BIU must interact with memory and input and output devices in fetching the The EU unit is responsible for executing the instructions of the programs and to carry out
instructions and data required by the EU. the required processing.

EU ‫ و تأخذ منها تعليمات األسمبلي و البينات و ترسلها الي ال‬I/O ‫ مع ال الذاكرة و مع ال‬BIU ‫تتعامل ال‬ BIU ‫ بتنفيذ التعليمات المرسلة لها من ال‬EU ‫تقوم ال‬

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Pipelining
:‫ مراحل‬3 ‫ يتم تنفيذها على‬Assembly ‫أي عملية‬

Fetch Decode execute

❖ Fetch:
registers ‫نقل تعليمة األسمبلي من الذاكرة الي المعالج واخزنها في واحدة من ال‬
❖ Decode
‫ الخ‬.‫فهم نوع ال تعليمة األسمبلي هل هي جمع ام طرح‬
❖ execute
registers ‫تنفيذ تعليمة األسمبلي وكتابة الناتج في واحد من ال‬

There are two ways to make the CPU process information faster:
:‫هناك طريقتين لتحسين أداء المعالج‬

▪ increase the working frequency.

‫زيادة التردد‬ ▪
▪ Pipelining (change the internal architecture of the CPU)
‫ وذلك يتطلب تغيير تركيب المعالج الداخلي‬Pipelining ‫استخدام فكرة ال‬ ▪

Pipelining allows the CPU to fetch and execute at the same time.
‫ تجعل المعالج يستطيع تجهيز لتعليمات و تنفيذها في نفس الوقت‬Pipelining ‫إضافة فكرة ال‬
Pipelining in the 8088/86 by splitting the internal structure of the microprocessor into two sections:

:‫ عن طريق تقسيم الهيكل الداخلي للمعالج الدقيق إلى قسمين‬8088/86 ‫ في معالج‬Pipelining ‫يمكن اضافة ال‬

▪ Bus Interface Unit (BIU)

▪ Execution Unit (EU).

8086 CPU

BIU EU

These two sections work simultaneously.

The BIU accesses memory and peripherals while the EU executes instructions previously fetched.
This works only if the BIU keeps ahead of the EU; thus, the BIU of the 8088/86 has a buffer, or queue.
‫ بشكل دائم‬EU ‫ سابقة لوحدة ال‬BIU ‫ بشكل صحيح فقط عندما تكون وحدة ال‬pipelining ‫تعمل فكرة ال‬
buffer ‫ولذاك تم إضافة‬
The buffer(queue) size is:
▪ 4 bytes long in the 8088
▪ 6 bytes in the 8086.
If any instruction takes too long to execute, the queue is filled to its maximum capacity and the buses will sit idle.
The BIU fetches a new instruction whenever the queue has room for 2 bytes in the 6-byte 8086 queue, and for 1 byte.

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Registers in 8086/8088 microprocessors
▪ The general-purpose registers in 8088/86 microprocessors can be accessed as either 16-bit or 8-bit registers.
▪ All other registers can be accessed only as 16-bit registers.

Multi-purpose Registers Special -purpose Registers

AX addressable as AH, AL IP instruction pointer
▪ The accumulator is used for instructions such as multiplication, division, ▪ addresses the next instruction in a section of memory.
and some of the adjustment instructions.
BX addressable as BH, BL. SP stack pointer
▪ BX register (base index) sometimes holds offset address of a location in ▪ addresses an area of memory called the stack.
the memory system in all versions of the microprocessor. ▪ the (stack pointer) stores data through this pointer.

CX addressable as CH, or CL FLAGS indicate the condition of the microprocessor and control its
▪ a (count) general-purpose register that also holds the count for various
instructions Segment Registers
DX CS (Code Segment) holds code (programs and procedures) used by the
addressable as DH, or DL. microprocessor.
▪ a (data) general-purpose register holds a part of the result from a
multiplication or part of dividend before a division
DS (Data Segment) contains most data used by a program.
BP Base Pointer ▪ Data are accessed by a content of other registers that hold.
▪ points to a memory (base pointer) location for memory data transfers
SS (Stack Segment) defines the area of memory used for the stack.
▪ stack entry point is determined by the stack segment and stack pointer
DI Destination Index registers.
▪ often addresses (destination index) string destination data for the string ▪ The BP register also addresses data within the stack segment.
instructions.
ES (Extra Segment) an additional data segment used by some
instructions to hold destination data.
SI Source Index
▪ The (source index) register addresses source string data for the string
instructions.

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General-purpose Registers Control and Status Registers
AX addressable as AH, AL
▪ The accumulator is used for instructions such as multiplication, division,
and some of the adjustment instructions. IP instruction pointer
▪ addresses the next instruction in a section of memory.
BX addressable as BH, BL.
▪ BX register (base index) sometimes holds offset address of a location in
FLAGS indicate the condition of the microprocessor and control its
the memory system in all versions of the microprocessor.

CX addressable as CH, or CL
▪ a (count) general-purpose register that also holds the count for various
instructions

DX
addressable as DH, or DL.
▪ a (data) general-purpose register holds a part of the result from a
multiplication or part of dividend before a division

Pointer and Index Registers Segment Registers

SP stack pointer CS (Code Segment) holds code (programs and procedures) used by the
▪ addresses an area of memory called the stack. microprocessor.
▪ the (stack pointer) stores data through this pointer.
DS (Data Segment) contains most data used by a program.
BP Base Pointer ▪ Data are accessed by a content of other registers that hold.
▪ points to a memory (base pointer) location for memory data transfers
SS (Stack Segment) defines the area of memory used for the stack.
DI Destination Index ▪ stack entry point is determined by the stack segment and stack pointer
▪ often addresses (destination index) string destination data for the string registers.
instructions. ▪ The BP register also addresses data within the stack segment.

ES (Extra Segment) an additional data segment used by some

SI Source Index instructions to hold destination data.
▪ The (source index) register addresses source string data for the string
instructions.

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The accumulator is used for instructions such as multiplication, division, and some of the
AX, addressable as AH, AL
adjustment instructions.

BX register (base index) sometimes holds offset address of a location in the memory system
BX, addressable as BH, BL.
General-Purpose (Data) Registers in all versions of the microprocessor.
.

a (count) general-purpose register that also holds the count for various instructions
CX, addressable as CH, or CL

a (data) general-purpose register holds a part of the result from a multiplication or part of
DX, addressable as DH, or DL.
dividend before a division.

points to a memory (base pointer) location for memory data transfers.

BP Base Pointer
Pointer Registers
addresses an area of memory called the stack.
SP stack pointer
the (stack pointer) stores data through this pointer.

often addresses (destination index) string destination data for the string instructions.
Index Registers DI Destination Index.

The (source index) register addresses source string data for the string instructions.
SI Source Index

addresses the next instruction in a section of memory.

instruction Registers IP instruction pointer

holds code (programs and procedures) used by the microprocessor.

CS (Code Segment)

Segment Registers contains most data used by a program.

DS (Data Segment)
Data are accessed by an contents of other registers that hold the offset address offset address.

defines the area of memory used for the stack.

SS (Stack Segment)
stack entry point is determined by the stack segment and stack pointer registers.
the BP register also addresses data within the stack segment.

an additional data segment used by some instructions to hold destination data.

ES (Extra Segment)

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Introduction to Assembly Language

Assembly
Instuctions

Program Control Data Movement Arithmetic and

Instructions Instructions Logic Instructions
[Chapter 5] [Chapter 6] [Chapter 7]

instruction syntax Example

MOV destination, source MOV RegA, RegB RegA = RegB

MOV

ADD destination, source ADD RegA, RegB RegA = RegA + RegB

ADD

MOV instruction rules

‫القاعدة‬ Examples
Data can be moved among all the register as long as the source MOV AL, DX ; Error
and destination registers match in size. MOV BX, AH ; Error
Rule 1 ‫ الي اخر طالما متساوين في الحجم‬register ‫ينفع انقل بينات من أي‬

Data cannot be moved directly into segment registers. MOV DS, 2459H ; Error
segment register ‫مينفعش أنقل قيمة ثابته في أي واحد من ال‬
MOV AX, 2345H ; load 2345H into AX
Rule 2 (To load a value into a segment register, first load it to a non- MOV DS, AX ; load the value of AX into DS
segment register and then move it to the segment register.)
‫ و بعدين انقله لل‬segment ‫ غير‬register ‫ ممكن انقل القيمة الثابتة في أي‬:‫(الحل‬
) segment

Rule 3 If a value less than FFH is moved into a 16-bit register, the rest of MOV BX, 5 ; the result will be BX = 0005H;
the bits are assumed to be all zeros. MOV BL, 5 ; the result will be BL = 05H;

Moving a value that is too large into a register will cause an MOV BL, 7F2H ; ILLEGAL: 7F2H is larger than 8 bits
error. MOV AX, 2FE456H ; ILLEGAL: the value is larger than AX
Rule 4 ‫ اللي هخزن فيه‬Register ‫مينفعش أنقل بيانات حجمها اكبر من ال‬

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Program Segments

▪ CS (Code Segment)
holds code (programs and procedures) used by the microprocessor.

▪ DS (Data Segment)
contains most data used by a program.

▪ SS (Stack Segment)
defines the area of memory used for the stack.

▪ ES (Extra Segment)
an additional data segment used by some instructions to hold destination data.

Segment Segment register Offset Register

Code Segment CS IP
Data Segment DS BX, SI, DI
Stack Segment SS SP, BP
Extra Segment ES SI, DI, BX

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Logical address and physical address

address

physical address logical address

offset address
is the 20-bit address
a location within a 64K-byte logical Address=
This is an actual physical location
This address can have a range of segment range. segment value + offset
00000H to FFFFFH address

Physical Address Offset Address Logical Address

▪ 20-bit address. ▪ 16-bit address
▪ This address can have a range of 00000H to FFFFFH ▪ a location within a 64K-byte segment range. logical address = segment value: offset value
▪ This is an actual physical location in RAM or ROM ▪ an offset address can range from 0000H to FFFFH.
within the 1-Megabyte memory range.

Address Code segment Data segment

offset value offset value
𝐎𝐟𝐟𝐬𝐞𝐭 𝐚𝐝𝐝𝐫𝐞𝐬𝐬. IP register value BX or SI or DI register value

CS: IP DS: offset

𝐋𝐨𝐠𝐢𝐜𝐚𝐥 𝐚𝐝𝐝𝐫𝐞𝐬𝐬

CS ≪ left + IP DS ≪ left + offset

𝐏𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐚𝐝𝐝𝐫𝐞𝐬𝐬

CS ≪ left + 0000 DS ≪ left + 0000

𝐓𝐡𝐞 𝐥𝐨𝐰𝐞𝐫 𝐩𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐫𝐚𝐧𝐠𝐞
(𝑺𝒕𝒂𝒓𝒕 𝒂𝒅𝒅𝒓𝒆𝒔𝒔 𝒐𝒇 𝒂 𝒔𝒆𝒈𝒎𝒆𝒏𝒕)

CS ≪ left + FFFF DS ≪ left + FFFF

𝐓𝐡𝐞 𝐮𝐩𝐩𝐞𝐫 𝐩𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐫𝐚𝐧𝐠𝐞
(𝑬𝒏𝒅 𝒂𝒅𝒅𝒓𝒆𝒔𝒔 𝒐𝒇 𝒂 𝒔𝒆𝒈𝒎𝒆𝒏𝒕)

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Code Segment

▪ To execute a program, the 8086 fetches the instructions from the code segment.

▪ The logical address of an instruction always consists of a CS (code segment) and an IP (instruction pointer), shown in 𝐂𝐒: 𝐈𝐏
format.

▪ The physical address for the location of the instruction is generated by shifting the CS left one hex digit and then adding it to
the IP.

▪ IP contains the offset address.

▪ The resulting 20-bit address is called the physical address.

Address Code segment Data segment

offset value offset value
𝐎𝐟𝐟𝐬𝐞𝐭 𝐚𝐝𝐝𝐫𝐞𝐬𝐬. IP register value BX or SI or DI register value

CS: IP DS: offset

𝐋𝐨𝐠𝐢𝐜𝐚𝐥 𝐚𝐝𝐝𝐫𝐞𝐬𝐬

CS ≪ left + IP DS ≪ left + offset

𝐏𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐚𝐝𝐝𝐫𝐞𝐬𝐬

CS ≪ left + 0000 DS ≪ left + 0000

𝐓𝐡𝐞 𝐥𝐨𝐰𝐞𝐫 𝐩𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐫𝐚𝐧𝐠𝐞
(𝑺𝒕𝒂𝒓𝒕 𝒂𝒅𝒅𝒓𝒆𝒔𝒔 𝒐𝒇 𝒂 𝒔𝒆𝒈𝒎𝒆𝒏𝒕)

CS ≪ left + FFFF DS ≪ left + FFFF

𝐓𝐡𝐞 𝐮𝐩𝐩𝐞𝐫 𝐩𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐫𝐚𝐧𝐠𝐞
(𝑬𝒏𝒅 𝒂𝒅𝒅𝒓𝒆𝒔𝒔 𝒐𝒇 𝒂 𝒔𝒆𝒈𝒎𝒆𝒏𝒕)

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Data Segment

Address Code segment Data segment

offset value offset value
𝐎𝐟𝐟𝐬𝐞𝐭 𝐚𝐝𝐝𝐫𝐞𝐬𝐬. IP register value BX or SI or DI register value

CS: IP DS: offset

𝐋𝐨𝐠𝐢𝐜𝐚𝐥 𝐚𝐝𝐝𝐫𝐞𝐬𝐬

CS ≪ left + IP DS ≪ left + offset

𝐏𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐚𝐝𝐝𝐫𝐞𝐬𝐬

CS ≪ left + 0000 DS ≪ left + 0000

𝐓𝐡𝐞 𝐥𝐨𝐰𝐞𝐫 𝐩𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐫𝐚𝐧𝐠𝐞
(𝑺𝒕𝒂𝒓𝒕 𝒂𝒅𝒅𝒓𝒆𝒔𝒔 𝒐𝒇 𝒂 𝒔𝒆𝒈𝒎𝒆𝒏𝒕)

CS ≪ left + FFFF DS ≪ left + FFFF

𝐓𝐡𝐞 𝐮𝐩𝐩𝐞𝐫 𝐩𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐫𝐚𝐧𝐠𝐞
(𝑬𝒏𝒅 𝒂𝒅𝒅𝒓𝒆𝒔𝒔 𝒐𝒇 𝒂 𝒔𝒆𝒈𝒎𝒆𝒏𝒕)

In 8086 microprocessors, the area of memory set aside for data is called the data segment.

Code segment is associated with CS and IP, the data segment uses register DS and an offset value.
Assume that the offset for the data segment begins at 200H. The data is placed in memory locations:

𝐃𝐒: 𝟎𝟐𝟎𝟎 = 𝟐𝟓
𝐃𝐒: 𝟎𝟐𝟎𝟏 = 𝟏𝟐
𝐃𝐒: 𝟎𝟐𝟎𝟐 = 𝟏𝟓
𝐃𝐒: 𝟎𝟐𝟎𝟑 = 𝟏𝐅
𝐃𝐒: 𝟎𝟐𝟎𝟒 = 𝟐𝐁

and the program can be rewritten as follows:

𝐌𝐎𝐕 𝐀𝐋, 𝟎 ; 𝐜𝐥𝐞𝐚𝐫 𝐀𝐋

𝐀𝐃𝐃 𝐀𝐋, [𝟎𝟐𝟎𝟎] ; 𝐚𝐝𝐝 𝐭𝐡𝐞 𝐜𝐨𝐧𝐭𝐞𝐧𝐭𝐬 𝐨𝐟 𝐃𝐒: 𝟐𝟎𝟎 𝐭𝐨 𝐀𝐋
𝐀𝐃𝐃 𝐀𝐋, [𝟎𝟐𝟎𝟏] ; 𝐚𝐝𝐝 𝐭𝐡𝐞 𝐜𝐨𝐧𝐭𝐞𝐧𝐭𝐬 𝐨𝐟 𝐃𝐒: 𝟐𝟎𝟏 𝐭𝐨 𝐀𝐋
𝐀𝐃𝐃 𝐀𝐋, [𝟎𝟐𝟎𝟐] ; 𝐚𝐝𝐝 𝐭𝐡𝐞 𝐜𝐨𝐧𝐭𝐞𝐧𝐭𝐬 𝐨𝐟 𝐃𝐒: 𝟐𝟎𝟐 𝐭𝐨 𝐀𝐋
𝐀𝐃𝐃 𝐀𝐋, [𝟎𝟐𝟎𝟑] ; 𝐚𝐝𝐝 𝐭𝐡𝐞 𝐜𝐨𝐧𝐭𝐞𝐧𝐭𝐬 𝐨𝐟 𝐃𝐒: 𝟐𝟎𝟑 𝐭𝐨 𝐀𝐋
𝐀𝐃𝐃 𝐀𝐋, [𝟎𝟐𝟎𝟒] ; 𝐚𝐝𝐝 𝐭𝐡𝐞 𝐜𝐨𝐧𝐭𝐞𝐧𝐭𝐬 𝐨𝐟 𝐃𝐒: 𝟐𝟎𝟒 𝐭𝐨 𝐀𝐋

By Eng. Emad Mahdy

WhatsApp: +20 12 7148 2006
https://www.youtube.com/@eng.emadmahdy
https://si-manual.com
This program will run with any set of data. Changing the data has no effect on the code.

If the data had to be stored at a different offset address, say 450H, the program would have to be rewritten.
One way to solve this problem would be to use a register to hold the offset address.

The 8086/88 allows only the use of registers BX, SI, and DI as offset registers for the data segment.

In the following example, BX is used as a pointer:

𝐌𝐎𝐕 𝐀𝐋, 𝟎 ; 𝐢𝐧𝐢𝐭𝐢𝐚𝐥𝐢𝐳𝐞 𝐀𝐋

𝐌𝐎𝐕 𝐁𝐗, 𝟎𝟐𝟎𝟎𝐇 ; 𝐁𝐗 𝐩𝐨𝐢𝐧𝐭𝐬 𝐭𝐨 𝐭𝐡𝐞 𝐨𝐟𝐟𝐬𝐞𝐭 𝐚𝐝𝐝𝐫𝐞𝐬𝐬 𝐨𝐟 𝐟𝐢𝐫𝐬𝐭 𝐛𝐲𝐭𝐞
𝐀𝐃𝐃 𝐀𝐋, [𝐁𝐗] ; 𝐚𝐝𝐝 𝐭𝐡𝐞 𝐟𝐢𝐫𝐬𝐭 𝐛𝐲𝐭𝐞 𝐭𝐨 𝐀𝐋
𝐈𝐍𝐂𝐁𝐗 ; 𝐢𝐧𝐜𝐫𝐞𝐦𝐞𝐧𝐭 𝐁𝐗 𝐭𝐨 𝐩𝐨𝐢𝐧𝐭 𝐭𝐨 𝐭𝐡𝐞 𝐧𝐞𝐱𝐭 𝐛𝐲𝐭𝐞
𝐀𝐃𝐃 𝐀𝐋, [𝐁𝐗] ; 𝐚𝐝𝐝 𝐭𝐡𝐞 𝐧𝐞𝐱𝐭 𝐛𝐲𝐭𝐞 𝐭𝐨 𝐀𝐋
𝐈𝐍𝐂𝐁𝐗 ; 𝐢𝐧𝐜𝐫𝐞𝐦𝐞𝐧𝐭 𝐭𝐡𝐞 𝐩𝐨𝐢𝐧𝐭𝐞𝐫
𝐀𝐃𝐃 𝐀𝐋, [𝐁𝐗] ∶ 𝐚𝐝𝐝 𝐭𝐡𝐞 𝐧𝐞𝐱𝐭 𝐛𝐲𝐭𝐞 𝐭𝐨 𝐀𝐋
𝐈𝐍𝐂𝐁𝐗 ; 𝐢𝐧𝐜𝐫𝐞𝐦𝐞𝐧𝐭 𝐭𝐡𝐞 𝐩𝐨𝐢𝐧𝐭𝐞𝐫

By Eng. Emad Mahdy

WhatsApp: +20 12 7148 2006
https://www.youtube.com/@eng.emadmahdy
https://si-manual.com
Little Endian Convention

What happens when 16-bit data is used?

For example:

MOV AX, 35F3H ; load 35F3H into AX

MOV [1500], AX ; copy the contents of AX to offset 1500H

In cases like this, the low byte goes to the low memory location and the high byte goes to the high memory address.

In example above, memory location DS:1500 contains F3H and memory location DS:1501 contains 35H.

DS: 1500 = F3
DS: 1501 = 35

This convention is called little endian versus big endian.

In the big-endian method, the high byte goes to the low address.

In the little-endian method, the high byte goes to the high address and the low byte to the low address.

All Intel microprocessors and many mini-computers use the little-endian convention

By Eng. Emad Mahdy

WhatsApp: +20 12 7148 2006
https://www.youtube.com/@eng.emadmahdy
https://si-manual.com
Stack Segment

Pushing onto the stack popping from the stack

Notice as each PUSH is executed, the contents of the register are saved on the stack and Popping the contents of the stack back into the 80x86 CPU is the opposite process of
SP is decremented by 2. pushing.

For every byte of data saved on the stack, SP is decremented once, and since push is With every pop, the top 2 by1es of the stack are copied to the register specified by the
saving the contents of a 16-bit register, it is decremented twice. instruction and the stack pointer is incremented twice.

By Eng. Emad Mahdy

WhatsApp: +20 12 7148 2006
https://www.youtube.com/@eng.emadmahdy
https://si-manual.com
Flag Register

d8 (carry) d7 (sign) d6 d5 d4 d3 d2 d1 d0

SF (sign Flag) 0, if positive number

SF = {
1, if negative number

ZF (Zero Flag) 0, if result ≠ 0

ZF = {
1, if result = 0

AF (Auxiliary Carry Flag) 0, if there is No carry from d3 to d4

AF = {
1, if there is a carry from d3 to d4

PF (Parity Flag) 0, if number of 1′s is odd

PF = {
1, if number of 1′s is even

CF (Carry Flag) 0, if no carry

CF = {
1, if there is a carry

By Eng. Emad Mahdy

WhatsApp: +20 12 7148 2006
https://www.youtube.com/@eng.emadmahdy
https://si-manual.com