CHAPTER 2

Architecture of 8086 microprocessor

Chapter objective
• Be familiar with the 8086
microprocessors architecture
– Its general features
– Its register architecture
– Its memory segmentation
– Addressing Modes

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Feature of 8086
• This is the photo of the microprocessor

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Introduction to 8086 microprocessor

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General Feature of 8086
• 8086 was introduced in 1978 G.C. by Intel.
• It is 40 pin dual in line packaged
• Use high-performance metal-oxide
semiconductor (HMOS) technology
• It has approximately 29,000 transistors

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Internal architecture of 8086
• It is a 16 bit microprocessor (16 bit word length)
– The ALU work 16 bit at a time
– Has 16 bit register sets
• Has16 bit internal and external data bus
– Memory
– Ports
• Address space
– 20 bit address bus (can access 22oor 1mb)
– 16 bit Input and output address space (can access 216
location of ports)
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Architecture of 8086(conti…)
• It has 14, 16 bit register sets
• Memory is byte addressable - Every byte has a separate
address.
• Can operate in two modes
– Minimum mode(single processor application)
– Maximum mode(multiple processor application)
• Has different addressing modes
– Register addressing mode
– Immediate addressing modes
– Direct addressing modes
– Etc

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Architecture of 8086(conti…)
• It has two functional units
– The bus interface unit(BIU)
– The execution unit
• These functional unit can work simultaneously
increasing the number of instruction executed per
unit time (Pipelining)
• The BIU has to interact with memory and input and
output devices in fetching the instructions and data
required by the EU
• EU is responsible for executing the instructions of the
programs and to carry out the required processing
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The bus interfacing unit(BIU)
• Function of the BIU
– 8086 interface to the outside world through the BIU
– It provides 16 bit data bus and 20 bit address bus
– Some of its functions includes
• Fetching instruction from memory
• Reading and writing data to memory or IO ports
• It queue (pre-fetch) instruction for the 8086 the purpose
of pipeline
• It calculate the physical or effective address of a memory

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The bus Interfacing Unit(BIU)
• Component of the BIU
– The instruction queues
• Speed up program execution
• Pre-fetch 6 byte of instruction in queue
registers
– Segment registers
– Instruction pointer
– Bus control logic
– Address summer

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BIU – Instruction Byte Queue
• 8086 instructions vary from 1 to 6 bytes
• Therefore fetch and execution are taking place
concurrently in order to improve the
performance of the microprocessor
• The BIU feeds the instruction stream to the
execution unit through a 6 byte prefetch queue
• This prefetch queue can be considered as a form
of loosely coupled pipelining

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BIU – Instruction Byte Queue
• Execution and decoding of certain instructions do
not require the use of buses
• While such instructions are executed, the BIU
fetches up to six instruction bytes for the
following instructions (the subsequent
instructions)
• The BIU store these prefetched bytes in a first-in-
first out register by name instruction byte queue
• When the EU is ready for its next instruction, it
simply reads the instruction byte(s) for the
instruction from the queue in BIU

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Segmentation
• The address bus width is 20 bit wide
• But all its registers are 16 bit width
• For these reason it partition its 1mb memory into many
64kb memory segment and access them individually
• 8086 allow only 4 active segments at a time
• For the selection of the four active segments we use
segment register
– Code segment register
– Data segment registers
– Stack segment register
– Extra segment registers
• Used to hold the starting address of segments
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Physical Memory

Segmented Memory 00000

The memory in an 8086 based

system is organized as segmented Code segment (64KB)
memory.
Data segment (64KB)

1 MB
The CPU 8086 is able to address Extra segment (64KB)
1Mbyte of memory.
Stack segment (64KB)

The Complete physically available

memory may be divided into a
number of logical segments.
FFFFF

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• The size of each segment is 64 KB
• A segment is an area that begins at any location
which is divisible by 16.
• A segment may be located any where in the
memory
• Each of these segments can be used for a
specific function.
– Code segment is used for storing the instructions.
– The stack segment is used as a stack and it is used to
store the return addresses.
– The data and extra segments are used for storing
data byte.
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• Advantage of segmentation
– It expands the addressing capacity of 8086 from
16 bit to 20 bit
– It allow the segments to have more than 16kb
memory size by having more than one segments
– It facilitate the separate memory area for
program, data, stack and extra segment
– Allow dynamic relocation

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Use of Segment registers
• Code segment Register:
– Contains initial address of the code segment
– This address plus the offset value contained in
instruction pointer (IP) gives the address from
which the instruction has to be fetched.
• Stack segment Register:
– Contains initial address of the Stack segment .
– This address plus the offset value contained in
Stack pointer (SP)is used for stack operations.

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Use of Segment registers
• Data segment Register:
– Contains initial address of the current data segment
– This address plus the offset value contained in
instruction gives the specific location of data segment.
• Extra segment Register :
– Contains initial address of the extra segment which is
used by some string operations.
– This address plus the offset value contained in
Destination index (DI) gives the specific location of
destination in string operations.
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MEMORY
00000

BIU
Segment Registers 34BA0
CODE (64k)
44B9F
CSR 34BA
44EB0
DATA (64K)

MB
1
44EB 54EAF
DSR
54EB0
ESR 54EB EXTRA (64K)
64EAF
695E 695E0
SSR
STACK (64K)
795DF

Each segment register store the upper

16 bit of the starting address of the
segments 21
Instruction pointer & summing block
• The instruction pointer register contains a 16-bit
offset address of instruction that is to be executed
next.
• The IP always references the Code segment register
(CS).
• The value contained in the instruction pointer is
called as an offset because this value must be
added to the base address of the code segment,
which is available in the CS register to find the 20-
bit physical address.
• The value of the instruction pointer is incremented
after executing every instruction. 22
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• The following examples shows the CS:IP scheme
of address formation:
CS 34BA IP 8AB4 Code segment
34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D645

34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F

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The execution unit(EU)
• Tells the address of the instruction and data that it
want to access to the BIU
• It decode and execute instructions
• Part of the EU includes
– Control unit
– Arithmetic and logic unit (ALU)
– Set of registers
• General purpose registers
• Pointers and index registers
• Special purpose register
– Flag registers

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Register organization

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General purpose register
• The are 4 general purpose register
• The are AX, BX, CX, DX
• Each can be split into two 8 bit register
– AL and AH, BL and BH, CL and CH and DH and
DL
• They can be used to holding data variables and
immediate results

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General purpose registers

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Execution Unit - Flags

• Overflow Flag (OF) - set if the result is too large

positive number, or is too small negative
number to fit into destination operand
• Direction Flag (DF) - if DF=0, SI and DI will auto-
incremented during the execution; otherwise,
SI and DI will auto-decrement
• Interrupt-enable Flag (IF) - setting this bit
enables maskable interrupts otherwise ignored
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Execution Unit - Flags
• Single-step Flag (TF) - if set then single-step interrupt
will occur after the next instruction
– Trap flag
• Sign Flag (SF) - set if the most significant bit of
the result is set. (negative)
• Zero Flag (ZF) - set if the result is zero.
• Auxiliary carry Flag (AF) - set if there was a carry
from or borrow in nibble of AL register.
• Parity Flag (PF) - set if parity (the number of "1"
bits) in the low-order byte of the result is even.
• Carry Flag (CF) - set if there was a carry from or
borrow to the most significant bit during last
result calculation 30
Execution Unit - Pointers
• Stack Pointer (SP) is a 16-bit register pointing to program
stack
• Base Pointer (BP) is a 16-bit register pointing to data in
stack segment. BP register is usually used for based, based
indexed or register indirect addressing.
• Source Index (SI) is a 16-bit register.
– SI is used for indexed, based indexed and register indirect
addressing,
– To hold offset of data in data segment
– 20 bit address is calculated from SI and DS
• Destination Index (DI) is a 16-bit register.
– DI is used for indexed, based indexed and register indirect
addressing,
– String instructions use ES and DI to determine the 20 bit physical
address
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Execution Unit - Pointers

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Registers and pointers
Segment register Pointer

CS (code segment) IP (instruction pointer)

DS (data segment) DI, SI

SS (Stack segment) SP (stack pointer)

BP (base pointer)

ES (Extra segment) DI

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Flag registers example

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Addressing mode
• What is addressing mode?
– Addressing mode is how a processor bring operand for its
operation
• Generally in 8086 µP, there are many types of
addressing modes such as
– Data addressing mode
– Program memory addressing mode
– Stack memory addressing mode
– String addressing mode
– I/O addressing mode
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DATA ADDRESSING MODE
•In order to illustrate data addressing mode we
use the mov instruction set of of 8086
processors e.g.
Register Addressing
• It is the most common form of data addressing.
• Use the content of the registers as an operand
– As a Source or destination
• Note:- never mix an 8-bit \with a 16-bit register,
Immediate addressing mode
• Use immediate data (literal data) as a source

• No segment register as destination

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Direct addressing modes
– Address is formed by adding the displacement to the
default data segment address or an alternate
segment address.
Direct addressing mode

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Register Indirect Addressing
• Allows data to be addressed at any memory
location through an offset address held in any of
the following registers: BP, BX, DI, and SI.
Register indirect

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Base-Plus-Index Addressing
• Similar to indirect addressing
• Uses one base register (BX or BP) and one index
register (DI or SI) to indirectly address the
memory.
 Are mostly used to access array element
– The base register often holds the beginning location of
a memory array.
– the index register holds the relative position
of an element in the array
Base-Plus-Index Addressing

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Register Relative Addressing
• Similar to base-plus-index addressing
– Data in a segment of memory are addressed by adding
the displacement to the contents of a base or an index
register (BP, BX, DI, or SI)
• Example MOV AX,[BX+1000H]
Register Relative Addressing
Base Relative-Plus-Index Addressing
• Similar to base-plus-index addressing.
– adds a displacement
– uses a base register and an index register to
form the memory address
• This type of addressing mode often addresses a
two-dimensional array of memory data.
• Example
– MOV AX,[BX + SI + 100H].
– displacement of 100H adds to BX and SI to form the
offset address within the data segment
Base Relative-Plus-Index addressing
Types of data addressing modes

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Other addressing modes
• String Addressing modes
– Uses movs instead of mov instruction
• Addressing mode for accessing I/O ports
– Use in and out instruction
• Program control addressing modes
– Use jmp and call instruction
• Stack memory addressing modes (push and
pop)

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