A Verilog BFM Methodology

Rodney Pesavento
[email protected]
Michael Privett
[email protected]

SNUG’99 Rodney Pesavento 1

Outline

• Model Overview
• Test Bench Overview
• Clocking Suggestions
• Adding Timing to a Model
• A State Machine BFM
• A Task BFM
• Conclusion
SNUG’99 Rodney Pesavento 2
Types of Models

• Two Types of Models

• Hard Model
– A full RTL Representation
– A Gate Level Implementation
• Bus Functional Model (BFM)
– Models only the Bus Interface
– Models Bus Cycles

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Test Bench Overview

• Verilog can have multiple top levels

– One top level is for the Test Bench
• The BFM
• The Clocking unit
• The Device Under Test
– Another one is for the Test Code
• Calls to the BFM
• Signal timing control
• test flow control

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Test Environment Diagram

module tc1;
Clock reg [15:0] adr, dat;
integer j;
BFM initial begin : tc_blk
for(j=0;j<8;j=j+1) begin
adr = j; dat = j;
Unit tb.bfm.wr(adr,dat,ws0);
Under tb.bfm.rd(adr,dat,ws1);
end //for
Other Test end //initial
endmodule
Model
Test Bench Test Code

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Speed Up A Single Clock

• Use a forever loop in the always block

• Use Blocking assignment
• Improves clock speed by 25%
// Normal Clock Block // Improved Clock Block
always begin : clk_blk always begin : clk_blk
clk <= 0; clk = 0;
#10 clk <= 1; forever #10 clk = ~clk;
#10; end
end

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Speed Up Multiple Clocks

• Create a parameterized clock module

• Instance it for each clock
• Use keyword macromodule
macromodule clk_mod (clk); module test_bench;
output clk; wire clk0, clk1, clk2;
parameter hper = 5; ebfm eb1 (…,…);
reg clk; xcntr u1 (…,…);
always begin clk_mod #(7) c0 (clk0);
clk = 0; clk_mod #(20) c1 (clk1);
forever #hper clk = ~clk; clk_mod #(100) c2 (clk2);
end endmodule
endmodule

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Adding Timing to a Model

• In-line Delays: sig_a <= #10 sig_b.

– Distributed throughout model
– Works for wires or regs
– Slightly faster than Specify…
• Specify Block Delays
– Concisely located in one place
– Easy to enable or disable
– Require ports to connect to wires
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Specify Block Example
specify
specparam data_rise 1:2:3;
specparam data_fall 2:3:4;
specparam data_float 3:4:5;

(clk => data) = (data_rise, data_fall,data_float);

specparam data_setup = 2:3:4;

specparam data_hold = 0:1:2;

$setup(data, posedge clk, data_setup);

$hold(posedge clk, data, data_hold);
endspecify
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•BFM Overview

• A BFM Generates Bus Cycles

– Either with a State Machine
– Or a Task
– But, a Task is always used to call the cycle
• A Bus Cycle can be any type of cycle
– Memory or IO, Read or Write
– A Hold Cycle
– An Interrupt Cycle
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State Machine BFM

• Tasks are used to initiate the SM

• The SM creates the Bus Cycle
• The SM and Tasks use handshaking
– Tasks assert a request for a bus cycle
– The SM asserts a busy flag when active
– This allows a task to return before the SM
completes the bus cycle
• The BFM SM executes idle cycles
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Partial SM BFM Example
// sm bfm body An initial block would
always @(posedge clk or posedge rst) set up local signal values
begin
if (rst) // initialize SM signals IDLE: initiates cycles
else case (state) based on the req signals
`IDLE : // assert idle state values
busy <= 0; RD_CYC: drives the bus
if (rd_req) state = `RD_CYC; ...
`RD_CYC : // assert read values
to a read cycle
busy <= 1; ...
`RD_RDY : // capture data on rdy RD_RDY: Captures data
if (rdy) begin on rdy. check_data errors
check_data; ...
endcase
on ws timeout; compares
end // always actual data to expected.
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Partial SM BFM Example
The mrd task initiates a // read task
memory read cycle task mrd;
begin
It waits if the SM is busy, if (busy) @(negedge busy);
before asserting a request rd_req = 1;
ldat = tdat;
ladr = tadr;
Task inputs are assigned to
lws = tws;
local signals for SM use if (!busy) @(posedge busy);
end // task
The task does not terminate
until the SM asserts busy module test_code;
tb.bfm.rst;
Test code references tasks via tb.bfm.mwr(adr,dat,ws1);
the Verilog hierarchy tb.bfm.mrd(adr,dat,ws3);
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Task BFM

• Is only made up of tasks, no SM

• Each task creates its own Bus cycle
• The task is active for the entire cycle
• The BFM does not execute when idle
• Good for compute intensive block
• Hard to use with another BFM
– Because the task does not return quickly

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Partial Task BFM Example
Module has only one statement. module ibfm(clk,rst,adr,dat,…);
assign dat = wr ? ldat : 8’hz;
The control is entirely in tasks.
task mwr; // tadr, tdat, tws
A task BFM for an internal bus while (busy) @(posedge clk);
might contain block selects. busy = 1;
sel0=tadr[15]; sel1=~tadr[15];
adr = tadr[14:0];
Generate wait states for (ii=1:ii<=tws;ii=ii+1)
@(posedge clk);
Drive local data with task data wr = 1;
ldat = tdat;
All Signals need to be set to @(posedge clk);
// assign signals to idle values
Idle value at the end of a task endtask
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Conclusion

• Task BFMs are good for Unit Tests

– Faster Simulation Speeds
• SM BFMs are good for Chip Tests
– Greater Functionality
• Use Specify blocks for Timing
• Use Blocking assignments
– For Temporary Variables
– For Clocks in forever loops
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