BASICS OF DDR

PROTOCOL
Jose Thomas Vellara

www.linkedin.com/in/josethomasvellara
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CONTENTS

1. Introduction to DDR
2. Pin Description
3. Functional Block Diagram
4. Functional Description
5. Initialization
6. Register Definition
7. Command Table and Commands
8. Simplified State Diagram
9. Operations - Bank/Row Activation, Reads, Writes, Precharge, Powerdown

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INTRODUCTION TO DDR

● The DDR SDRAM is a high-speed CMOS, dynamic random-access memory internally configured as a quad-bank

DRAM.

● The DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.

● The double data rate architecture is essentially a 2n prefetch

architecture with an interface designed to transfer two data words

per clock cycle at the I/O pins.

● A single read or write access for the DDR SDRAM effectively

consists of a single 2n-bit wide, one clock cycle data transfer at

the internal DRAM core and two corresponding n-bit wide, one-

half-clock-cycle data transfers at the I/O pins.

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INTRODUCTION TO DDR CONTD

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PIN DESCRIPTION
SYMBOL TYPE DESC

CK, CK’ Input Clock, differential s/g

CKE Input Clock Enable

CS’ Input Chip Select

RAS’ Input Row Address Strobe

CAS’ Input Column Address Strobe

WE’ Input Write Enable

DM Input Input Data Mask

BA0 - BA1 Input Bank Address

A0 - A13 Input Address inputs

DQS I/O Data Strobe

DQ I/O Data Bus 5

FUNCTIONAL BLOCK DIAGRAM

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FUNCTIONAL DESCRIPTION

● Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
● Address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed.
● The address bits registered coincident with the READ or WRITE command are used to select the starting column location
for the burst access.
● Prior to normal operation, the DDR SDRAM must be initialized.

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INITIALIZATION

● DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation.

● Except for CKE, inputs are not recognized as valid until after VREF is applied.

● After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200 μs

delay prior to applying an executable command.

● Once the 200 μs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be

brought HIGH.

● Following the NOP command, a PRECHARGE ALL command should be applied.

● Next a MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL.

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INITIALIZATION

● Then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the

operating parameters.

● 200 clock cycles are required between the DLL reset and any executable command. A PRECHARGE ALL command

should be applied, placing the device in the ”all banks idle” state.

● Once in the idle state, two AUTO refresh cycles must be performed. Additionally, a MODE REGISTER SET command for

the Mode Register, with the reset DLL bit deactivated.

● Following these cycles, the DDR SDRAM is ready for normal operation.

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REGISTER DEFINITION
MODE REGISTER

● The Mode Register is used to define the specific mode of operation of the DDR SDRAM.

● Includes the selection of a burst length, a burst type, a CAS latency, and an operating mode.

● The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain

the stored information until it is programmed again or the device loses power (except for bit A8, which may be self-

clearing).

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REGISTER DEFINITION CONTD

● Mode Register bits A0-A2 specify the burst length

● A3 specifies the type of burst (sequential or interleaved)

● A4-A6 specify the CAS latency

● A7-A13 or (A12 on 256Mb/512Mb, A13 on 1Gb, refer below

table) specify the operating mode.

● Burst length, Burst type, CAS latency and operating mode

subfields are explained in the following slides.

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MODE REGISTER CONTD: SUBFIELDS 0 1 2 3 4 5 6 7 8 9
1. BURST LENGTH

● Read and write accesses to the DDR SDRAM are burst oriented.
● The burst length determines the maximum number of column
locations that can be accessed for a given READ or WRITE
command.
● Burst lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types.
● When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected.
● Burst will wrap within the block if a boundary is reached.
● The block is uniquely selected by A1-Ai when the burst length is set to
two, by A2-Ai when the burst length is set to four and by A3-Ai when the
burst length is set to eight (where Ai is the most significant column
address bit for a given configuration).
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● The remaining (least significant) address bit(s) is (are) used to select the
MODE REGISTER CONTD: SUBFIELDS
2. BURST TYPE

● Accesses within a given burst may be programmed to be either

sequential or interleaved.
● The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address.
3. READ LATENCY (CAS LATENCY)

● The READ latency is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data.
● If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
coincident with clock edge n + m.

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MODE REGISTER CONTD: SUBFIELDS
4. OPERATING MODE

● The normal operating mode is selected by issuing a Mode Register Set command with bits A7-A13
each set to zero, and bits A0-A6 set to the desired values.
● A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A13 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired values.
● A Mode Register Set command issued to reset the DLL must always be followed by a Mode Register
Set command to select normal operating mode (i.e., with A8=0).
● All other combinations of values for A7-A13 are reserved for future use and/or test modes.

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Q&A

1. What are the memory clock frequencies of DDR266, DDR400?

2. 3.

4.
What are the
CAS/Read latencies?

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REGISTER DEFINITION CONTD

EXTENDED MODE REGISTER

● The Extended Mode Register controls functions beyond those

controlled by the Mode Register.
● Extended Mode Register is programmed via the MODE
REGISTER SET command (with BA0 = 1 and BA1 = 0)
● These additional functions include DLL enable/disable, output
drive strength selection (optional).
● It will retain the stored information until it is programmed again or
the device loses power.
● Extended Mode Register must be loaded when all banks are idle The delay-locked loop (DLL) is a circuit
fed by a reference clock that attempts to
and no bursts are in progress, and the controller must wait the
find the period of that reference clock by
specified time before initiating any subsequent operation. adjusting the delay of a variable delay
buffer in a feedback loop. The loop is
Output Drive Strength: The normal drive strength for all outputs is specified to locked when the delayed clock signal 16
be SSTL_2, Class II. Some vendors might also support a weak driver strength matches the incoming clock signal.
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COMMAND TABLE

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1. DESELECT COMMAND

● CS’ is high
● prevents new commands from being executed by the DDR SDRAM
● DDR SDRAM is effectively deselected
● operations already in progress are not affected

2. NO OPERATION (NOP) COMMAND

● command is used to perform a NOP to a DDR SDRAM which is selected

● this prevents unwanted commands from being registered during idle or wait states
● operations already in progress are not affected

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3. ACTIVE COMMAND

● ACTIVE command is used to open (or activate) a row in a particular bank for
a subsequent access.

● Values on the BA0, BA1 inputs selects the bank, and the address provided on
inputs A0-A13 selects the row.

● Row remains active (or open) for accesses until a precharge (or READ or
WRITE with AUTOPRECHARGE) is issued to that bank.

● PRECHARGE (or READ or WRITE with AUTOPRECHARGE) command must

be issued before opening a different row in the same bank.

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4. READ COMMAND

● The READ command is used to initiate a burst read access to an active row.

● The value on the BA0, BA1 inputs selects the bank, and the address provided on
inputs A0-Ai (shown in below table) selects the starting column location.

● The value on input A10 determines whether or not auto precharge is used.

● If auto precharge is selected, the row being accessed will be precharged at the
end of the read burst; if auto precharge is not selected, the row will remain open for
subsequent accesses.

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5. WRITE COMMAND

● The WRITE command is used to initiate a burst write access to an active row.

● The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs
A0-Ai (shown in previous table), selects the starting column location.

● The value on input A10 determines whether or not auto precharge is used.

● Input data appearing on the DQs is written to the memory array subject to the DM input
logic level appearing coincident with the data.

● If a given DM signal is registered LOW, the corresponding data will be written to

memory.

● If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and 22
a write will not be executed to that byte/ column location.
6. BURST TERMINATE COMMAND

● The BURST TERMINATE command is used to truncate read bursts (with autoprecharge disabled).

● The most recently registered READ command prior to the BURST TERMINATE command will be truncated.

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7. PRECHARGE COMMAND

● The PRECHARGE command is used to deactivate the open row in a particular

bank or the open row in all banks.

● The bank(s) will be available for a subsequent row access a specified time (tRP)
after the precharge command is issued.

● Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank.

● A PRECHARGE command will be treated as a NOP if there is no open row in

that bank, or if the previously open row is already in the process of precharging.

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AUTO PRECHARGE

● AUTO PRECHARGE is a feature which performs the same individual-bank precharge function described above, but

without requiring an explicit command.

● A10 is to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command.

● A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon

completion of the READ or WRITE burst.

● AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual Read or Write

command.

● AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst.

● The user must not issue another command to the same bank until the precharge time (tRP) is completed.

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REFRESH REQUIREMENTS

● DDR SDRAMs require a refresh of all rows in any rolling 64ms interval.

● 2 ways, explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode.

● Dividing the number of device rows into the rolling 64 ms interval defines the average refresh interval, tREFI, which is a

guideline to controllers for distributed refresh timing.

● To avoid excessive interruptions to the memory controller, higher density DDR SDRAMs maintain the 7.8 μs average

refresh time and perform multiple internal refresh bursts.

● For example, a 256 Mb DDR SDRAM has 8192 rows resulting in a tREFI of 7.8 μs.

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REFRESH REQUIREMENTS CONTD

AUTO REFRESH COMMAND

● AUTO REFRESH is used during normal operation of the DDR SDRAM.

● This command is nonpersistent, so it must be issued each time a refresh is required.

● The refresh addressing is generated by the internal refresh controller. This makes the address bits ”Don’t Care”

during an AUTO REFRESH command.

● The DDR SDRAM requires AUTO REFRESH cycles at an average periodic interval of tREFI.

● A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM

● The maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 *

tREFI.

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REFRESH REQUIREMENTS CONTD

SELF REFRESH MODE

● The SELF REFRESH mode can be used to retain data in the DDR SDRAM, even if the rest of the system is powered
down.
● When in the self refresh mode, the DDR SDRAM retains data without external clocking.
● The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled.
● The DLL is automatically disabled upon entering SELF REFRESH, and is automatically enabled upon exiting SELF RE-
FRESH.
● Input signals except CKE are ”Don’t Care” during SELF REFRESH.
● The procedure for exiting self refresh requires a sequence of commands.
● First, CK must be stable prior to CKE going back HIGH.
● Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the
completion of any internal refresh in progress.
● A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying
any other command. 28
Q&A

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SIMPLIFIED STATE DIAGRAM

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OPERATIONS

1. Bank/Row Activation

2. Reads

3. Writes

4. Precharge

5. Powerdown

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OPERATIONS CONTD
1. BANK/ROW ACTIVATION

● Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be
”opened.”
● This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated.
● After opening a row, a READ or WRITE command may be issued to that row, subject to the tRCD specification.
● A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row
has been ”closed” (precharged).
● The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
● A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a
reduction of total row access overhead.
● The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.

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OPERATIONS CONTD
2.0. READS

● READ bursts are initiated with a READ command.

● The starting column and bank addresses are provided with the READ command
and AUTO PRECHARGE is either enabled or disabled
● If AUTO PRECHARGE is enabled, the row that is accessed will start precharge at
the completion of the burst.
● During READ bursts, the valid data-out element from the starting column address
will be available following the CAS latency after the READ command.
● DQS is driven by the DDR SDRAM along with output data. The initial LOW state
on DQS is known as the read preamble; the LOW state coincident with the last
data-out element is known as the read postamble.
● Upon completion of a burst, assuming no other commands have been initiated,
the DQs will go High-Z.

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OPERATIONS CONTD
2.1. READS CONTD

● Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command.
● In either case, a continuous flow of data can be maintained.
● The first data element from the new burst follows either the last element of a completed burst or the last desired data
element of a longer burst which is being truncated.
● The new READ command should be issued X cycles after the first READ command, where X equals the number of
desired data element pairs (2n prefetch architecture).
● A READ command can be initiated on any clock cycle following a previous READ command.

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OPERATIONS CONTD
2.2. READS CONTD

● Data from any READ burst may be truncated with a BURST TERMINATE command.
● The BURST TERMINATE latency is equal to the read (CAS) latency.
● Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued.
● If truncation is necessary, the BURST TERMINATE command must be used.
● A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO
PRECHARGE was not activated).

● Following the PRECHARGE command, a

subsequent command to the same bank cannot be
issued until tRP is met.
● The PRECHARGE command can be used to
truncate bursts.
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OPERATIONS CONTD
2.3. READS CONTD

Read burst, consecutive with burst length 4/8

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OPERATIONS CONTD
2.4. READS CONTD

Read burst, non consecutive with burst length 4

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OPERATIONS CONTD
2.5. READS CONTD

Random Read access, with burst length 2/4/8

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OPERATIONS CONTD
2.6. READS CONTD

Read with Burst Terminate, burst length 4/8.

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OPERATIONS CONTD
2.7. READS CONTD

● Read to Write, with

burst length 2/4/8.
● If burst length is 2,
BST is same as
NOP.

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OPERATIONS CONTD
2.8. READS CONTD

● Read to Precharge
● After precharge, we can issue new command to the same bank only after tRP.

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OPERATIONS CONTD
3.0. WRITES

● WRITE bursts are initiated with a WRITE command.

● The starting column and bank addresses are provided with the WRITE command, and

AUTO PRECHARGE is either enabled or disabled for that access.

● The first valid data-in element will be registered on the first rising edge of DQS

following the write command, and subsequent data elements will be registered on

successive edges of DQS.

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OPERATIONS CONTD
3.1. WRITES CONTD

● The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the
LOW state on DQS following the last data-in element is known as the write postamble.
● The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS).
● Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any
additional input data will be ignored.

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OPERATIONS CONTD
3.2. WRITES CONTD

● Simple write burst, with burst length 4.

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OPERATIONS CONTD
3.3. WRITES CONTD

● Write to write commands, with burst length 4.

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OPERATIONS CONTD
3.4. WRITES CONTD

● Write to write non consecutive commands, with burst length 4.

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OPERATIONS CONTD
3.5. WRITES CONTD

● Random write commands.

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OPERATIONS CONTD
3.6. WRITES CONTD

● Write to Read, non interrupting.

● A non-interrupted burst of 4 is shown.

● tWTR is referenced from the first positive

CK edge after the last Data-In pair
(importance comes in odd no of data,
explained in following slides).
● tWTR = 2tCK for optional CL = 1.5
(otherwise tWTR = 1tCK).
● The READ and WRITE commands are to
the same device but not necessarily to the
same bank.

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OPERATIONS CONTD
3.7. WRITES CONTD

● Write to Read, interrupting, even

no of data written.

● An interrupted burst of 8 is shown, 4

data elements (even) are written.

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OPERATIONS CONTD
3.8. WRITES CONTD

● Write to Read, interrupting, odd

no of data written.

● An interrupted burst of 8 is shown,

3 data elements (odd)are written.

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OPERATIONS CONTD
3.9. WRITES CONTD

● Write to Precharge, non interrupting.

● A non-interrupted burst of 4 is shown, 4

data elements (even) are written.

● tWR is referenced from the first positive
CK edge after the last Data In pair.

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OPERATIONS CONTD
3.10. WRITES CONTD

● Write to Precharge, interrupting,

even no of data written.

● An interrupted burst of 4 or 8 is
shown, 2 data elements (even)
are written.

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OPERATIONS CONTD
3.11. WRITES CONTD

● Write to Precharge, interrupting,

odd no of data written.

● An interrupted burst of 4 or 8 is
shown, 1 data element (odd) is
written.

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OPERATIONS CONTD
4.0. PRECHARGE

● The PRECHARGE command is used to deactivate the open row in a particular

bank or the open row in all banks.
● The bank(s) will be available for a subsequent row access some specified time
(tRP) after the precharge command is issued.
● Input A10 determines whether one or all banks are to be precharged.
● Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank.

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OPERATIONS CONTD
5.0. POWER DOWN

● Powerdown is entered when CKE is registered low.

● If powerdown occurs when all banks are idle, this mode is referred to as precharge powerdown.

● If powerdown occurs when there is a row active in any bank, this mode is referred to as active powerdown.

● Entering powerdown deactivates the input and output buffers, excluding CK, CK and CKE.

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OPERATIONS CONTD
5.1. POWER DOWN CONTD

● For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that
case, the DLL must be enabled after exiting powerdown, and 200 clock cycles must occur before a READ command
can be issued.
● However, powerdown duration is limited by the refresh requirements of the device, so in most applications, the
self-refresh mode is preferred over the DLL-disabled powerdown mode.
● The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT
command).

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THANK YOU

http://www.linkedin.com/in/josethomasvellara

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