Group Format Name Pseudocode F E DCBA9 8 7 6 5 4 3 2 1 0 F E DCBA9 8 7 6 5 4 3 2 1 0

U RV32I LUI rd,imm Load Upper Immediate (Top 20 bits of rd)rd ← imm Imm [31:12] rd 0010111
U RV32I AUIPC rd,offset Add Upper Immediate to PC rd ← pc + offset Imm [31:12] rd 0010111
UJ RV32I JAL rd,offset Jump and Link rd ← pc + len(inst)… pc ← pc + off [20][10:1] [11][19:12] rd 1101111
I RV32I JALR rd,rs1,offset Jump and Link Register (return to rs1 when off=0) rd ← pc + len(inst)…pc ← (rs1+off)∧-2 Imm [11:0] Rs1 000 rd 1100111
SB RV32I BEQ rs1,rs2,offset Branch Equal if rs1 = rs2 then pc ← pc + offset Imm [12][10:0] Rs2 Rs1 000 Im [11][4:1] 1100011
SB RV32I BNE rs1,rs2,offset Branch Not Equal if rs1 ≠ rs2 then pc ← pc + offset Imm [12][10:1] Rs2 Rs1 001 Im [11][4:1] 1100011
SB RV32I BLT rs1,rs2,offset Branch Less Than if rs1 < rs2 then pc ← pc + offset Imm [12][10:2] Rs2 Rs1 100 Im [11][4:1] 1100011
SB RV32I BGE rs1,rs2,offset Branch Greater than Equal if rs1 ≥ rs2 then pc ← pc + offset Imm [12][10:3] Rs2 Rs1 101 Im [11][4:1] 1100011
SB RV32I BLTU rs1,rs2,offset Branch Less Than Unsigned if rs1 < rs2 then pc ← pc + offset Imm [12][10:4] Rs2 Rs1 110 Im [11][4:1] 1100011
SB RV32I BGEU rs1,rs2,offset Branch Greater than Equal Unsigned if rs1 ≥ rs2 then pc ← pc + offset Imm [12][10:5] Rs2 Rs1 111 Im [11][4:1] 1100011
I RV32I LB rd,offset(rs1) Load Byte rd ← s8[rs1 + offset] Imm [11:0] Rs1 000 rd 0000011
I RV32I LH rd,offset(rs1) Load Half rd ← s16[rs1 + offset] Imm [11:0] Rs1 001 rd 0000011
I RV32I LW rd,offset(rs1) Load Word rd ← s32[rs1 + offset] Imm [11:0] Rs1 010 rd 0000011
I RV32I LBU rd,offset(rs1) Load Byte Unsigned rd ← u8[rs1 + offset] Imm [11:0] Rs1 100 rd 0000011
I RV32I LHU rd,offset(rs1) Load Half Unsigned rd ← u16[rs1 + offset] Imm [11:0] Rs1 101 rd 0000011
S RV32I SB rs2,offset(rs1) Store Byte u8[rs1 + offset] ← rs2 Imm [11:5] Rs2 Rs1 000 Imm [4:0] 0100011
S RV32I SH rs2,offset(rs1) Store Half u16[rs1 + offset] ← rs2 Imm [11:5] Rs2 Rs1 001 Imm [4:0] 0100011
S RV32I SW rs2,offset(rs1) Store Word u32[rs1 + offset] ← rs2 Imm [11:5] Rs2 Rs1 010 Imm [4:0] 0100011
I RV32I ADDI rd,rs1,imm Add Immediate rd ← rs1 + sx(imm) Imm [11:0] Rs1 000 rd 0010011
I RV32I SLTI rd,rs1,imm Set Less Than Immediate rd ← sx(rs1) < sx(imm) Imm [11:0] Rs1 010 rd 0010011
I RV32I SLTIU rd,rs1,imm Set Less Than Immediate Unsigned rd ← ux(rs1) < ux(imm) Imm [11:0] Rs1 011 rd 0010011
I RV32I XORI rd,rs1,imm Xor Immediate rd ← ux(rs1) ⊕ ux(imm) Imm [11:0] Rs1 100 rd 0010011
I RV32I ORI rd,rs1,imm Or Immediate rd ← ux(rs1) ∨ ux(imm) Imm [11:0] Rs1 110 rd 0010011
I RV32I ANDI rd,rs1,imm And Immediate rd ← ux(rs1) ∧ ux(imm) Imm [11:0] Rs1 111 rd 0010011
R RV32I SLLI rd,rs1,imm Shift Left Logical Immediate rd ← ux(rs1) « ux(imm) 0000000 shamt Rs1 001 rd 0010011
R RV32I SRLI rd,rs1,imm Shift Right Logical Immediate rd ← ux(rs1) » ux(imm) 0000000 shamt Rs1 101 rd 0010011
R RV32I SRAI rd,rs1,imm Shift Right Arithmetic Immediate rd ← sx(rs1) » ux(imm) 0100000 shamt Rs1 101 rd 0010011
S RV32I ADD rd,rs1,rs2 Add rd ← sx(rs1) + sx(rs2) 0000000 shamt Rs1 000 rd 0110011
S RV32I SUB rd,rs1,rs2 Subtract rd ← sx(rs1) - sx(rs2) 0100000 shamt Rs1 000 rd 0110011
S RV32I SLL rd,rs1,rs2 Shift Left Logical rd ← ux(rs1) « rs2 0000000 shamt Rs1 001 rd 0110011
S RV32I SLT rd,rs1,rs2 Set Less Than rd ← sx(rs1) < sx(rs2) 0000000 shamt Rs1 010 rd 0110011
S RV32I SLTU rd,rs1,rs2 Set Less Than Unsigned rd ← ux(rs1) < ux(rs2) 0000000 shamt Rs1 011 rd 0110011
S RV32I XOR rd,rs1,rs2 Xor rd ← ux(rs1) ⊕ ux(rs2) 0000000 shamt Rs1 100 rd 0110011
S RV32I SRL rd,rs1,rs2 Shift Right Logical rd ← ux(rs1) » rs2 0000000 shamt Rs1 101 rd 0110011
S RV32I SRA rd,rs1,rs2 Shift Right Arithmetic rd ← sx(rs1) » rs2 0100000 shamt Rs1 101 rd 0110011
S RV32I OR rd,rs1,rs2 Or rd ← ux(rs1) ∨ ux(rs2) 0000000 shamt Rs1 110 rd 0110011
S RV32I AND rd,rs1,rs2 And rd ← ux(rs1) ∧ ux(rs2) 0000000 shamt Rs1 111 rd 0110011
I RV32I FENCE pred,succ Fence Fm Pred Suc Rs1 000 rd 1110011
I RV32I FENCE.I Fence Instruction Imm Rs1 001 rd 0001111
I RV64I LWU rd,offset(rs1) Load Word Unsigned rd ← u32[rs1 + offset] Imm [11:0] Rs1 110 rd 0000011
RV64I LD rd,offset(rs1) Load Double rd ← u64[rs1 + offset] Imm [11:0] Rs1 011 rd 0000011
RV64I SD rs2,offset(rs1) Store Double u64[rs1 + offset] ← rs2 Imm [11:5] Rs2 Rs1 011 Imm [4:0] 0100011
RV64I SLLI rd,rs1,imm Shift Left Logical Immediate rd ← ux(rs1) « sx(imm) 000000 shamt Rs1 001 rd 0010011
RV64I SRLI rd,rs1,imm Shift Right Logical Immediate rd ← ux(rs1) » sx(imm) 000000 shamt Rs1 101 rd 0010011
RV64I SRAI rd,rs1,imm Shift Right Arithmetic Immediate rd ← sx(rs1) » sx(imm) 010000 shamt Rs1 101 rd 0010011
RV64I ADDIW rd,rs1,imm Add Immediate Word rd ← s32(rs1) + imm Imm [11:0] Rs1 000 rd 0011011
RV64I SLLIW rd,rs1,imm Shift Left Logical Immediate Word rd ← s32(u32(rs1) « imm) 000000 shamt Rs1 001 rd 0011011
RV64I SRLIW rd,rs1,imm Shift Right Logical Immediate Word rd ← s32(u32(rs1) » imm) 000000 shamt Rs1 101 rd 0011011
RV64I SRAIW rd,rs1,imm Shift Right Arithmetic Immediate Word rd ← s32(rs1) » imm 010000 shamt Rs1 101 rd 0011011
RV64I ADDW rd,rs1,rs2 Add Word rd ← s32(rs1) + s32(rs2) 000000 Rs2 Rs1 000 rd 0111011
RV64I SUBW rd,rs1,rs2 Subtract Word rd ← s32(rs1) - s32(rs2) 010000 Rs2 Rs1 000 rd 0111011
RV64I SLLW rd,rs1,rs2 Shift Left Logical Word rd ← s32(u32(rs1) « rs2) 000000 Rs2 Rs1 001 rd 0111011
RV64I SRLW rd,rs1,rs2 Shift Right Logical Word rd ← s32(u32(rs1) » rs2) 000000 Rs2 Rs1 101 rd 0111011
RV64I SRAW rd,rs1,rs2 Shift Right Arithmetic Word rd ← s32(rs1) » rs2 010000 Rs2 Rs1 101 rd 0111011
S RV32M MUL rd,rs1,rs2 Multiply rd ← ux(rs1) × ux(rs2) 0000001 Rs2 Rs1 000 Rd 0110011
S RV32M MULH rd,rs1,rs2 Multiply High Signed Signed rd ← (sx(rs1) × sx(rs2)) » xlen 0000001 Rs2 Rs1 001 Rd 0110011
S RV32M MULHSU rd,rs1,rs2 Multiply High Signed Unsigned rd ← (sx(rs1) × ux(rs2)) » xlen 0000001 Rs2 Rs1 010 Rd 0110011
S RV32M MULHU rd,rs1,rs2 Multiply High Unsigned Unsigned rd ← (ux(rs1) × ux(rs2)) » xlen 0000001 Rs2 Rs1 011 Rd 0110011
S RV32M DIV rd,rs1,rs2 Divide Signed rd ← sx(rs1) ÷ sx(rs2) 0000001 Rs2 Rs1 100 Rd 0110011
S RV32M DIVU rd,rs1,rs2 Divide Unsigned rd ← ux(rs1) ÷ ux(rs2) 0000001 Rs2 Rs1 101 Rd 0110011
S RV32M REM rd,rs1,rs2 Remainder Signed rd ← sx(rs1) mod sx(rs2) 0000001 Rs2 Rs1 110 Rd 0110011
S RV32M REMU rd,rs1,rs2 Remainder Unsigned rd ← ux(rs1) mod ux(rs2) 0000001 Rs2 Rs1 111 Rd 0111011
S RV64M MULW rd,rs1,rs2 Multiple Word rd ← u32(rs1) × u32(rs2) 0000001 Rs2 Rs1 000 Rd 0111011
S RV64M DIVW rd,rs1,rs2 Divide Signed Word rd ← s32(rs1) ÷ s32(rs2) 0000001 Rs2 Rs1 100 Rd 0111011
S RV64M DIVUW rd,rs1,rs2 Divide Unsigned Word rd ← u32(rs1) ÷ u32(rs2) 0000001 Rs2 Rs1 101 Rd 0111011
S RV64M REMW rd,rs1,rs2 Remainder Signed Word rd ← s32(rs1) mod s32(rs2) 0000001 Rs2 Rs1 110 Rd 0111011
S RV64M REMUW rd,rs1,rs2 Remainder Unsigned Word rd ← u32(rs1) mod u32(rs2) 0000001 Rs2 Rs1 111 Rd 0111011
Directive .2byte 16-bit comma separated words (unaligned)
Directive .4byte 32-bit comma separated words (unaligned) http://www.chibiakumas.com/asm
Directive .8byte 64-bit comma separated words (unaligned)
Directive .half 16-bit comma separated words (naturally aligned)
Directive .word 32-bit comma separated words (naturally aligned)
Directive .dword 64-bit comma separated words (naturally aligned)
Directive .byte 8-bit comma separated words
Directive .dtpreldword 64-bit thread local word
Directive .dtprelword 32-bit thread local word
Directive .sleb128 expression signed little endian base 128, DWARF
Directive .uleb128 expression unsigned little endian base 128, DWARF
Directive .asciz “string” emit string (alias for .string)
Directive .string emit string
Directive .incbin “filename” emit the included file as a binary sequence of octets
Directive .zero integer zero bytes
Directive .align integer align to power of 2 (alias for .p2align)
Directive .balign b,[pad_val=0] byte align
Directive .p2align p2,[pad_val=0],max align to power of 2
Directive .globl symbol_name emit symbol_name to symbol table (scope GLOBAL)
Directive .local symbol_name emit symbol_name to symbol table (scope LOCAL)
Directive .equ name, value constant definition
Directive .text emit .text section (if not present) and make current
Directive .data emit .data section (if not present) and make current
Directive .rodata emit .rodata section (if not present) and make current
Directive .bss emit .bss section (if not present) and make current
Directive .comm sym_nam,sz,aln emit common object to .bss section
.common sym_name,sz,aln emit common object to .bss section
Directive

.section sect emit section (if not present, default .text [{.text,.data,.rodata,.bss}]
Directive

.option opt RISC-V options {rvc,norvc,pic,nopic,push,pop}

Directive

.macro name arg1 [, argn] begin macro definition \argname to substitute

Directive
Directive .endm end macro definition
Directive .file“filename” emit filename FILE LOCAL symbol table
Directive .ident “string” accepted for source compatibility
.size symbol, symbol accepted for source compatibility
Directive

.type symbol, @function accepted for source compatibility

Directive
Psuedo NOP No operation addi zero,zero,0
Psuedo LIrd, expression Load immediate (several expansions)
Psuedo LA rd, symbol Load address (several expansions)
MV rd, rs1 Copy register addi rd, rs, 0
Psuedo

NOT rd, rs1 One’s complement xori rd, rs, -1

Psuedo

NEG rd, rs1 Two’s complement sub rd, x0, rs

Psuedo

NEGW rd, rs1 Two’s complement Word subw rd, x0, rs

Psuedo

SEXT.W rd, rs1 Sign extend Word addiw rd, rs, 0

Psuedo

SEQZ rd, rs1 Set if = zero sltiu rd, rs, 1

Psuedo

SNEZ rd, rs1 Set if ≠ zero sltu rd, x0, rs

Psuedo

SLTZ rd, rs1 Set if < zero slt rd, rs, x0

Psuedo

SGTZ rd, rs1 Set if > zero slt rd, x0, rs

Psuedo

FMV.S frd, frs1 Single-precision move fsgnj.s frd, frs, frs

Psuedo

FAB.S frd, frs1 Single-precision absolute value fsgnjx.s frd, frs, frs
Psuedo

FNEG.S frd, frs1 Single-precision negate fsgnjn.s frd, frs, frs

Psuedo

FMV.D frd, frs1 Double-precision move fsgnj.d frd, frs, frs

Psuedo

FABS.D frd, frs1 Double-precision absolute value fsgnjx.d frd, frs, frs
Psuedo

FNEG.D frd, frs1 Double-precision negate fsgnjn.d frd, frs, frs

Psuedo
Psuedo BEQZ rs1, offset Branch if = zero beq rs, x0, offset
BNEZ rs1, offset Branch if ≠ zero bne rs, x0, offset
Psuedo

BLEZ rs1, offset Branch if ≤ zero bge x0, rs, offset

Psuedo

BGEZ rs1, offset Branch if ≥ zero bge rs, x0, offset

Psuedo

BLTZ rs1, offset Branch if < zero blt rs, x0, offset
Psuedo

BGTZ rs1, offset Branch if > zero blt x0, rs, offset
Psuedo

BGT rs, rt, offset Branch if > blt rt, rs, offset
Psuedo

BLE rs, rt, offset Branch if ≤ bge rt, rs, offset

Psuedo
Psuedo BGTU rs, rt, offset Branch if >, unsigned bltu rt, rs, offset
BLEU rs, rt, offset Branch if ≤, unsigned bltu rt, rs, offset
Psuedo

J offset Jump jal x0, offset

Psuedo

JR offset Jump register jal x1, offset

Psuedo
Psuedo RET Return from subroutine jalr x0, x1, 0

Syntax: Imm [12][10:5] = Bits 12 & 10-5 of immediate (other bits in other part)