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/ 9
COMBINATIONAL CIRCUITS
Digital circuits are broadly classified into following two categories: Combinational Circuits and
‘Sequential Circuits.
A digital cicuit is said to be combinational if the output of the circuit at any instant of time
depends only on the present inputs. Examples of combinational circuits are: Adder, Multiplexer,
Decoder etc. On the other hand, a digital circuit is termed as sequential ifthe output ofthe circuit
at any instant of time depends not only on the present inputs but also on the past state stored in
the memory elements. Flip flop, counter, register eto. are the examples of sequential circuits. A
sequential circuit may have two parts: combinational circuit and memory element.
Arithmetic Circuits
Addition and subtraction are the two most fundamental arithmetic operations performed on
binary numbers. Half adder and full adder are basically used to perform addition operation on
binary data. Similarly, subtraction operation is often accomplished with the help of half
subtractorand full subtractor circuits.
Half Adder
A half adder is an arithmetic circuit which performs addition operation on two input bits and
produces result as sum and carry in the output. It has two input and two output lines. It is usually
used to add the first column of two binary numbers. The block diagram and truth table of the half
adder circuit is shown in Figure 2.12.
Era
¥— ate s SET
ADD
y—{ADDER| — ¢ +
10 )1o
(@) Block diagram Toe
(b) Truth table
Figure 2.12 Block diagram and truth table of half adder
From the truth table, the Boolean expression for Sum (S) and Carry (C) can be written as.
S=X@Y;C=XY
The implementation of the expressions for $ and C using gates give the circut of half adder as
shown in Figure 2.13
Figure 2.13 Logic diagram of half adderFull Adder
‘Afull adder is an arithmetic circuit which performs addition operation on three input bits and
produces result as sum and carry. Ithas three input and two output lines. Unlike, half adder, it
can be used for addition of any column of two binary numbers. The block diagram and truth table
ofthe fulladderciroutis shown in Figure 2.14
x
y—| Fut |— s
ADDER| — ¢
z—
(b) Block diagram
(b) Truth table
Figure 2.14 Block diagram and truth table of full adder
From the truth table, the Boolean expression for Sand Ccan be written as:
S=KYZ+KYZ+XYZ+ XYZ
(XY + RV) (RY EXYIZ
= (KBY)Z+ (XEY)Z
=(X@Y)@Z
=X@Y@Z
and
C=XYZ+XY¥Z+XYZ+XYZ
=XVZ+RYZ+XVZ+XVZ+XYZ+ XYZ (“AS AHA=A)
= XY (Z+2) + YZ (K+ K)+XZ(V+ 9)
=XV+YZ+XZ,
The Implementation of expressions for S and C completes the design of full adder.
Figure 2.15 Logie diagram of half adderHalfSubtractor
—
Ahalf subtractor is an arithmetic circuit which performs subtraction operation on two input bits
and produces resultas difference and borrow in the output. Ithas two input and two output lines.
Itis usually used to subtract the first column of two binary numbers. The block diagram and
truth table of the half subtractor circuit is shown in Figure 2.16. Treat X as minuend and Y as
‘subtrahend and the subtraction operation is designated by X - Y. During subtraction, ifa borrow
istaken, the output signal, B becomes 1’.
x
HALF D =a
0 oo 0
|SUBTRACTOR |
c 2 o fit
, a a)
(2) Block diagram [tio o
(b) Truth table
Figure 2.16 Block diagram and truth table of half subtractor
From the truth table, the Boolean expression for D and Bcan be written as
D=X@Y;B=XY
The implementation of the expressions for D and B using gates gives the circuit of half
subtractor.
Figure 2.17 Logic diagram of half subtractor
Full Subtractor
A full subtractoris an arithmetic circuit which performs subtraction operation between two input
bits with consideration that a borrow has been taken by a column lower to it and produces result
as difference and borrow. Ithas threeinputand two output lines. Unlike, half subtractor,itcan be
used for subtraction of any column of two binary numbers. The block diagram and truth table of
the ull subtractor circuitis shown in Figure 2.18, Treat X as minuend, ¥ as subtrahend and Zas
previous borrow. The subtraction operation is designated by X -Y -Z.x—f
_| ru
¥ | suBTRACTOR
z—
(a)Block diagram
(b) Truth table
Figure 2.18 Block diagram and truth table of full subtractor
From the truth table, the Boolean expression for Dand B can be writtenas
D=XYZ+XYZ+XYZ+XYZ
= (XV + RV)Z+ (RV +XY)Z
= (RBV)Z+ (KBY)Z
= (KOY)@Z
=X@Y@Z
and
B=XYZ+XVZ+XVZ+XVZ
= RYZ+X¥Z4XYZ+ RYZ+RYZ4 XYZ (-.A+A+A=A)
RZ (V+ ¥) +RY (2+Z)+XV (X+R)
=RV4YZ4XZ
The Implementation of expressions for D and B completes the design of full subtractor.
—=D-
Figure 2.19 Logic diagram of full subtractorData Processing Gircuits
‘The combinational circuits that are used to process the binary data in various manners and for
different purposes are called data processing circults. Encoders, decoders, multiplexers, de-
‘multiplexers, code converters, comparators etc. are the example of data processing circuit
Encoder
‘An encoder isa combinational circuit which generates a coded output signal in response to an
active input signal. fan encoder has n number of output lines, ican have2" or lesser number of
‘input lines. Encoders are typically used to convert a decimal Keyboard, tke that ofa calculator
into abinary or 860 output. Figure 2.20 shows the block diagram and truth table ofan 8 line to
line encoder whichis also known.as octal to binary encoder.
D—
a1
Dy} 8 Line to3 Line
Di—| Encoder
Ds
a—
Do
() Block diagram (©) Truth table
Figure 2.20 Block diagram and truth table of fll subtractor
The Boolean expressions forthe encoder canbe determined by careful examintion ofthe truth
table. Output tne Y, is at logic" when D, oF Dor D, or D, i at logic 1. Similarly we can
‘determine the expressions for Y,and Yas welland canbe writen as
Y=D40,400,
¥ =D,1D,0,0,
YoxD D400,
Implementation of expression forY, Y,and Y is shown in Figure 2.20 which basically describes
the octal tobinary encoder
Other popular encoders are 10 ine to 4 line encoder (ie. decimal to BCD encoder) and 16 ine to
Aline encoder (.e, hexadecimalto binary encoder),
%oo% Yo
Figure 2.21 Logie diagram of 8:3 EncoderDecoder
‘Adacoderis a combinational circuit which generates 2 or lesser unique output lines from coded
Information received on n-bit input lines. It is used to decode the binary state contained in a
piece of coded information. Decoders can be used in chip select logic of memory ICs, making
one of the output ine active ata time etc. Figure 2.24 shows the block diagram and truth table of
line to 8 line decoder (also known as binary to octal decoder).
p —| 3line to 8 Line |— Ys
ec
(b) Block diagram (b) Truth table
Figure 2.24 Block
.gram and truth table of 3 line to 8 line decoder
The Boolean expression for each output can be derived fromm the truth and can be writen as
ic Y,= ABC
¥,= ABC
{In order to implement the above expressions, we need the hardware shown in Figure 2.25 and is
termedas binary to octal decoder.
TSA ot
% Yy MW Wy Ye
Figure 2.25 Logie diagram of binary to octal decoder‘Multiplexer (MUX)
‘A Multiplexer, abbreviated as MUX has many data input lines, few select lines and one output
line, I there are n numbers of select lines, the MUX can have 2° or lesser number of input data
lines. A MUX is also known as data selector or data router. It is usually used for many to one
conversion. The block diagram and truth of an 8 line to 1 line (or 8:1) MUX is shown in Figure
2.27.
Ss 5 Sy
Y
(@) Block diagram (0) Truth table
Figure 2.27 Block diagram and truth table of 8:1 MUX
‘The Boolean expression for the output variable Y can be written as
Y=DSSS, + 0555, + DSSS, + 0,55, + 0.5.55, + 0,8,55, + 05,55, +
088.8,
‘When this expression is implemented by digital logic gates we get structure as shown in Figure
2.28,
y
Figure 2.28 Logie diagram of 8: | MUXDe-multiplexer (DEMU)
A de-multiplexer (DEMUX) is a
conversion. The block diagram
shown in Figure 2.30,
x)
combinational logic circuit, which has one data input line, few
select lines and many output lines. If there are n numbers of select lines, the de-multiplexer can
have 2 or lesser number of output lines. A de-multiplexer is also known as data distributor and
performs the inverse function of that of a multiplexer. By applying appropriate value on the select
line, the input signal can be steered into one of the output lines. Itis usually used for one to many
and truth of a simple 4 line to 8 line (or 1:8) de-multiplexer is
t-2
ts
Deemlplener
(© Block dap
Figore 2301
(Trt e
lek gram and tna ele of deminer
‘The Boolean expression for the four output ine can be written from the truth tableas follows:
¥,=855,0 — Y,=5,85,0
Y,=55,5,0 — ¥,=5,8,5,.0
Implementation of the above expression using logic gates depicts the hardware required for 1:8
dde-multiplexe andis shown in Fi
¥,=8,8,8,0
Y,=8,5,8,D
igure2.31.
D
%
uh bw % hh
Figure 231 Logie diagram of 1:8 de-multiplexerComparator
A comparator or magnitude comparator is a combinational logic circuit which compares two
binary numbers, e.g. Aand B, and produces result as A> B, A=BorAB,thenweconclude that A> B
It A,B,thenwe conclude that A> B
It A= ByandA,
