Release Notes For ModelSim Intel FPGA 2019.

Oct 15 2019
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_______________________________________________________________________

* How to Get Support

ModelSim Intel FPGA is supported by Intel
+ World-Wide-Web Support
[1]http://www.altera.com/mySupport
_______________________________________________________________________

Index to Release Notes

* [2]Key Information
* [3]Release Announcements in 2019.4
* [4]Base Product Specifications in 2019.4
* [5]Compatibility Issues with Release 2019.4
* [6]General Defects Repaired in 2019.4
* [7]SystemVerilog Defects Repaired in 2019.4
* [8]VHDL Defects Repaired in 2019.4
* [9]Document Revision History in 2019.4
_______________________________________________________________________

Key Information
* There is no licensing change between 10.7 and 2019.1 or 2019.2 or
2019.3 or 2019.4. However, if you are migrating to 2019.4 from a
release like 10.6 and older, please note that release 2019.4 uses
FLEXnet v11.14.1.3.
For floating licenses, it will be necessary to verify that the
vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd)
have FLEXnet versions equal to or greater than 11.14.1.3. If the
current FLEXnet version of your vendor daemon and lmgrd are less
than 11.14.1.3 then it will be necessary to stop your license
server and restart it using the vendor daemon and lmgrd contained
in this release.
If you use node locked licenses you don't need to do anything. This
release will update licensing to MSL v2017_1_patch2 with MGLS
v9.17_10.2.4 and PCLS v9.17.10.2.0
In summary, this release uses the following license versions:
+ FLEXnet v11.14.1.3
+ MSL v2017_1_patch2
+ MGLS v9.17_10.2.4
+ PCLS v9.17.10.2.0
_______________________________________________________________________

Release Announcements in 2019.4

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_______________________________________________________________________

Base Product Specifications in 2019.4

*
[Supported Platforms]
Linux RHEL 6 x86/x86-64
Linux RHEL 7 x86/x86-64
Linux SLES 11 x86/x86-64
Linux SLES 12 x86/x86-64
Windows 10 x86/x64
[Supported GCC Compilers (for SystemC)]
gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64
gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64
gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
gcc-4.2.1-mingw32vc12
[OVL (shipped with product)]
v2.8.1
[VHDL OSVVM (shipped with product)]
v2014.07
[Licensing]
FLEXnet v11.14.1.3
MSL v2017_1_patch2
MGLS v9.17_10.2.4
PCLS v9.17.10.2.0
_______________________________________________________________________

Compatibility Issues with Release 2019.4

VHDL Compatibility
* QSIM-58539 - (results) The attributes INSTANCE_NAME and PATH_NAME,
were not considered globally static. If the prefix of the attribute
is a signal and this expression appears in a wait statement with an
on clause or in a concurrent statement other than a process, a
change in signal value would trigger a evaluation of the wait or
concurrent statement. This currently results in extra statement
executions. The attributes are now considered globally static, so
the wait or concurrent statement is no longer sensitized to that
prefix. This change can cause simulation results to be different
from previous versions.
_______________________________________________________________________

General Defects Repaired in 2019.4

* [nodvtid] - vmake many now consume less memory.
* QSIM-55252 - The vdir command can now be given the name of an
already-existing directory; it will transform the directory into a
Questa library. The directory must be empty for this to succeed.
_______________________________________________________________________

SystemVerilog Defects Repaired in 2019.4

* [nodvtid] - Vlog would crash when parsing certain syntax
constructs.
* QSIM-58023 - Using a wire type with a struct containing a field of
an enum type could generate an error like<br>
<code># ** Fatal: (vsim-3355) Variable 'struct1.enum1' cannot be
converted to a net.</code>
* [nodvtid] - SystemVerilog macros undefining and subsequently
redefining a macro of the same name repeatedly during macro
expansion would generate incorrect results.
* QSIM-58670 - Vsim incorrectly reported a vsim-3837 error for
multiple continuous assignments to a variable when using a
bit-select expression with a complex index expression
_______________________________________________________________________

VHDL Defects Repaired in 2019.4

* QSIM-57546 - If a package contains a package instance within a USE
clause, static array constraints within the package instance may
not be compiled correctly, possible causing a fatal internal error
during elaboration of the design by the simulator.
* QSIM-57795 - The compiler could report a fatal internal error if it
encountered a generic declaration list with an index constraint
within a generic vector preceding an interface package.
* QSIM-58539 - (results) The attributes INSTANCE_NAME and PATH_NAME,
were not considered globally static. If the prefix of the attribute
is a signal and this expression appears in a wait statement with an
on clause or in a concurrent statement other than a process, a
change in signal value would trigger a evaluation of the wait or
concurrent statement. This currently results in extra statement
executions. The attributes are now considered globally static, so
the wait or concurrent statement is no longer sensitized to that
prefix. This change can cause simulation results to be different
from previous versions.
* QSIM-60023 - Use of the -mixedsvvh switch could result in the
compiler erroneously emitting error vcom-1995, which states that a
package cannot be imported into SystemVerilog designs. This can
occur when at least two VHDL packages are compiled on a single
command-line with the -mixedsvvh switch; and, one package contains
a constant declaration initialized by a function defined in the
other package, and the name of the first package comes lexically
before the name of the second package.
* QSIM-57712 - If an entity has a generic whose type depends on a
previously declared generic and that entity is directly
instantiated, then vsim could crash when loading the design. The
work around was to use a component instantiation.
* QSIM-60153 - If a component had a port that is a multi-dimensional
array whose bounds depended on the component's generics and the
port's actual was an expression, vcom could generate an internal
error.
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Document Revision History in 2019.4

* Revision - Changes - Status/Date
+ 4.3 - Modifications to improve the readability and
comprehension of the content. Approved by Tim Peeke. All
technical enhancements, changes, and fixes are listed in this
document for all products in this release. Approved by Bryan
Ramirez. - Released/October 2019
+ 4.2 - Modifications to improve the readability and
comprehension of the content. Approved by Tim Peeke. All
technical enhancements, changes, and fixes are listed in this
document for all products in this release. Approved by Bryan
Ramirez. - Released/August 2019
+ 4.1 - Modifications to improve the readability and
comprehension of the content. Approved by Tim Peeke. All
technical enhancements, changes, and fixes are listed in this
document for all products in this release. Approved by Bryan
Ramirez. - Released/April 2019
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