Release Notes For ModelSim Intel FPGA 2019.

Jan 01 2019
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_______________________________________________________________________

Index to Release Notes

* [2]Key Information
* [3]Release Announcements in 2019.1
* [4]Base Product Specifications in 2019.1
* [5]Compatibility Issues with Release 2019.1
* [6]General Defects Repaired in 2019.1
* [7]User Interface Defects Repaired in 2019.1
* [8]SystemVerilog Defects Repaired in 2019.1
* [9]VHDL Defects Repaired in 2019.1
* [10]SystemC Defects Repaired in 2019.1
* [11]Mixed Language Defects Repaired in 2019.1
* [12]User Interface Enhancements in 2019.1
* [13]SystemVerilog Enhancements in 2019.1
* [14]VHDL Enhancements in 2019.1
* [15]SystemC Enhancements in 2019.1
* [16]Mixed Language Enhancements in 2019.1
* [17]Document Revision History in 2019.1
_______________________________________________________________________

Key Information
* The following lists the supported platforms:
+ win32aloem - Windows 7, Windows 8.1, Windows 10
+ linuxaloem - RedHat Enterprise Linux 6,7 SUSE Linux Enterprise
Server 11,12
_______________________________________________________________________

Release Announcements in 2019.1

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_______________________________________________________________________

Base Product Specifications in 2019.1

*
[Supported Platforms]
Linux RHEL 6 x86/x86-64
Linux RHEL 7 x86/x86-64
Linux SLES 11 x86/x86-64
Linux SLES 12 x86/x86-64
Windows 10 x86/x64
[Supported GCC Compilers (for SystemC)]
gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64
gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64
gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
gcc-4.2.1-mingw32vc12
[OVL (shipped with product)]
v2.8.1
[VHDL OSVVM (shipped with product)]
v2014.07
[Licensing]
FLEXnet v11.14.1.3
MSL v2017_1_patch2
MGLS v9.17_10.2.4
PCLS v9.17.10.2.0
_______________________________________________________________________
Compatibility Issues with Release 2019.1

Key Information Compatibility

* QSIM-140 - (results) The compiler +protect flow is in process of
deprecation. This affects the vlog and vcom compilers. The
recommended flow is to use vencrypt (Verilog/SV) or vhencrypt
(VHDL) followed by vlog or vcom compilation. The deprecation
process starts with a warning if this option is used, which will
become an error in later releases. The reason for this change is to
remove the source ambiguities referenced by the compilation
libraries. An encrypted compilation is a compilation of the
post-encryption sources and must not retain any association with
pre-encryption sources. This principle is reinforced by maintaining
a two-step flow.

SystemVerilog Compatibility
* [nodvtid] - (source) An issue with incorrect precedence in the &&&
and "matches" operations in SV has been fixed. This may cause SV
HDL code to be compiled differently than with previous versions.
Any differences will be flagged by the compiler with an error.
* [nodvtid] - (results) The SystemVerilog 'iff' property operator now
associates to the right. IEEE 1800-2017 table 16-3.
* QSIM-17634 - (results) Optimized cell path delays could be
incorrectly shortened when used with negative timing checks.
* QSIM-8147 - (results) Restart with designs having negative timing
check limits could effect simulation timing checks and functional
evaluation behavior.

Mixed Language Compatibility

* QSIM-53075 - (results) When passing a Verilog unpacked array to a
VHDL array generic, values were mapped from the, Verilog value at
the low index was mapped to the VHDL position with the left index.
parameter int val[3:0] when passed to generic g1 :
integer_array(3:0) would map val[0] => g1(3), val[1] => g1(2),
val[2] => g1(1), val[3]=>g1(0). Now the values are passed like
val[0] => g1[0], val[1] => g1(1), val[2] => g1(2), and val[3] =>
g1(3).

SystemC Compatibility
* QSIM-498 - (source, results) SystemC support has been upgraded to
SystemC-2.3.2 from SystemC-2.3.1. Please refer to the SystemC
Simulation chapter in the user's manual for SystemC-2.3.2
incompatibilities with SystemC-2.3.1.

User Interface Compatibility

* QSIM-53110 - (source) The behavior of the vsim command "profile
option " has been made consistent for all options. Issuing this
command will display the status of the specified option -- this
command will no longer toggle the value of the specified option
(use "profile option on|off" to set the value of the option).
_______________________________________________________________________

General Defects Repaired in 2019.1

* QSIM-41547 - An issue related to licensing is fixed. The issue
caused a hang if the checked-out license feature is about to expire
(default is 15 days before expiration). A workaround was to set the
'MGLS_EXP_WARN_DAYS' variable to '1'. Now, the workaround is not
needed. This issue was not applicable to Windows platform.
_______________________________________________________________________
User Interface Defects Repaired in 2019.1
* QSIM-53662 - For certain signal widths the column width was being
miscalculated which resulted in '*' being displayed in place of an
actual value. The correct width is now being calculated.
_______________________________________________________________________

SystemVerilog Defects Repaired in 2019.1

* [nodvtid] - In some cases where a fork..join block contained a
nested fork..join_any sub-block, disabling the outer block would
not immediately disable the inner block.
* [nodvtid] - Vopt would sometimes crash in designs with interfaces
that imported complex types from packages.
* [nodvtid] - (results) The SystemVerilog 'iff' property operator now
associates to the right. IEEE 1800-2017 table 16-3.
* [nodvtid] - (source) An issue with incorrect precedence in the &&&
and "matches" operations in SV has been fixed. This may cause SV
HDL code to be compiled differently than with previous versions.
Any differences will be flagged by the compiler with an error.
* QSIM-50272 - The vencrypt feature "-auto3protect" could not
properly handle macro call syntax in the port list of a module.
* QSIM-17634 - (results) Optimized cell path delays could be
incorrectly shortened when used with negative timing checks.
* QSIM-8147 - (results) Restart with designs having negative timing
check limits could effect simulation timing checks and functional
evaluation behavior.
* QSIM-51616 - Intertial delay was not working properly for
tranif/rtranif primitives with delay when the control/enable input
had multiple transitions within the delay period.
_______________________________________________________________________

VHDL Defects Repaired in 2019.1

* QSIM-27418 - Special characters in a comment that was inside an
encrypted region could cause a parsing error.
* QSIM-2261 - An internal error was report in some cases in vcom or
vopt if an array signal is indexed or sliced. The index expression
or slice expression contains a locally static expression that has a
primary is a record or array. For example:
constant C : integer_vector(0 to 1) := ( 3, 6);
signal S : std_logic_vector(15 downto 0);
....
o <= S(C(0)); -- The use of C(0) can cause an internal error

* QSIM-16902 - If a package contains a generic of the same name as a

generic of an entity, and the package is instantiated within the
entity, the compiler may incorrectly use the static value of the
entity's generic rather than the package's generic when producing
code for the package instantiation.
* QSIM-39177 - A simulator crash could occur if an object was
declared with an initial expression that was the name of another
object whose initial value was a function call whose return type
mark was the predefined attribute SUBTYPE with a prefix that was
one of the function input parameters (when that parameter is of an
unconstrained composite type).
* QSIM-42988 - Reference to a package constant defined within a
package instance that is itself defined within a simple package
could cause the compiler to produce an internal error.
* QSIM-6762 - The compiler could crash when encountering a composite
assignment, where the left-hand side contains a variable whose type
is an interface type.
* QSIM-15169 - The vcom compiler "-just" and "-skip" options now
allow the specification 'x', which means VHDL 2008 "context"
declarations.
* QSIM-43580 - A port association that is an aggregate with an OTHERS
choice, for a constrained port that is an array-of-array, and where
those constraints are globally static, could result in either a
compiler internal error or a run-time simulator error about
mismatched array lengths.
* QSIM-50516 - In some case vopt generate an internal error or bad
code for a configuration. This would occur if a generic or port of
a component being configuration was used anywhere other than the
port/generic map.
* QSIM-53077 - In a protected type body, if there was a data member
whose subtype involved another data member's value, then bad code,
which would crash the simulator, would result.
_______________________________________________________________________

SystemC Defects Repaired in 2019.1

* QSIM-1380 - vopt crashes caused due to linking in
libsystemc_gccXX.a into the intermediate shared library during the
'sccom -linkshared' step has been fixed.
* QSIM-51654 - scparse compilation failures with the nlohmann JSON
c++ code has been fixed
_______________________________________________________________________

Mixed Language Defects Repaired in 2019.1

* QSIM-53075 - (results) When passing a Verilog unpacked array to a
VHDL array generic, values were mapped from the, Verilog value at
the low index was mapped to the VHDL position with the left index.
parameter int val[3:0] when passed to generic g1 :
integer_array(3:0) would map val[0] => g1(3), val[1] => g1(2),
val[2] => g1(1), val[3]=>g1(0). Now the values are passed like
val[0] => g1[0], val[1] => g1(1), val[2] => g1(2), and val[3] =>
g1(3).
* QSIM-2330 - A "force -deposit" on a VHDL signal connected to an SV
inout port immediately reverted back to its original value even
though there were no subsequent driver events.
_______________________________________________________________________

User Interface Enhancements in 2019.1

* QSIM-53110 - (source) The behavior of the vsim command "profile
option " has been made consistent for all options. Issuing this
command will display the status of the specified option -- this
command will no longer toggle the value of the specified option
(use "profile option on|off" to set the value of the option).
_______________________________________________________________________

SystemVerilog Enhancements in 2019.1

* QSIM-10245 - For C/C++ auto compile, modelsim.ini variable
"DpiCppInstall" has been added which is the equivalent of the
'-dpicppinstall' command line option.
* QSIM-10245 -
The '-cppinstall' and '-cpppath' options will be honored for C/C++ auto compile
in the absence of '-dpicppinstall' and '-dpicpppath' options.
For SystemC compile, the order of precedence in determining the compiler path is
the following:
- -cppinstall
- -cpppath
For C/C++ auto compile, the order of precedence in determining the compiler path
is the following:
- -dpicppinstall
- -dpicpppath
- -cppinstall
- -cpppath

* QSIM-23017 -
Warning numbers 7076 and 7077 for vlog and vsim have been upgraded to suppressi
ble errors. They will now appear as:
** Error (suppressible): (<TOOL>-7076) The gcc/g++ path '<path specified>' via -
dpicppinstall swicth is not qualified and is ignored.
** Error (suppressible): (<TOOL>-7077) the path '<path specified>' via -dpicpppa
th switch not a valid gcc/g++ full path and is ignored.
vlog/vsim -suppress 7076 | 7077 to suppress the error.

* QSIM-30463 - Add vlog/vopt -svinputport=compat option to default an

input port declared with a type but without the "var" keyword to
"wire", as required by the LRM, but only if the type is compatible
with a net declaration. The fully LRM compliant option
-svinputport=net will default to "wire" even if the type is not
compatible with a net declaration ("bit", for example), potentially
resulting in compilation errors. The default behavior remains
unchanged, which is -svinputport=relaxed, where only a a type that
is a 4-state scalar or 4-state single dimension vector type
defaults to "wire".
_______________________________________________________________________

VHDL Enhancements in 2019.1

* QSIM-43418 - Designs that have a very large number of signals that
are either multidimensional arrays or arrays whose elements are
arrays or records will now load faster at simulation time.
_______________________________________________________________________

SystemC Enhancements in 2019.1

* QSIM-498 - (source, results) SystemC support has been upgraded to
SystemC-2.3.2 from SystemC-2.3.1. Please refer to the SystemC
Simulation chapter in the user's manual for SystemC-2.3.2
incompatibilities with SystemC-2.3.1.
_______________________________________________________________________

Mixed Language Enhancements in 2019.1

* QSIM-53671 - VHDL can now instantiate a Verilog module that has a
multi-dimensional packed array-of-array-of-reg array port, when the
actual connected to that port is a VHDL array port (as long as the
number of scalar subelements matches).
_______________________________________________________________________

Document Revision History in 2019.1

* Revision - Changes - Status/Date
+ 4.0 - Modifications to improve the readability and
comprehension of the content. Approved by Tim Peeke. All
technical enhancements, changes, and fixes are listed in this
document for all products in this release. Approved by Bryan
Ramirez. - Released/January 2019
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