UNIT IV

4.1 Addition and Subtraction of Signed-Magnitude Numbers:

The representation of numbers in signed magnitude is familiar because it
is used in everyday arithmetic calculations. Here we designate of the two
numbers by A and B. Where the Signed numbers are added or subtracted,
we find that there eight different conditions to consider, depending on the
sign of the numbers and the operations performed. If the two numbers are
equal then they are subtracted, result may be either +0 or -0. Addition or
subtraction may be illustrated below.

Table 4.1 Addition and Subtraction of Signed-Magnitude Numbers

4.2 Hardware Implementation of Addition and Subtraction

To implement the two arithmetic operations with hardware, it is first
necessary two numbers stored in registers A and B respectively. As and Bs
hold the sign bits. After the completion result to be transferred to the third
register, to save the register the result is transferred to the A and A s
together to form as an Accumulator. First Parallel Adder is used to perform
the operation A+B and comparator circuit is to perform the operation
A>B,A=B or A<B. Third two parallel subtractor circuit need to perform the
micro-operation A-B and B-A. The output carry is transferred to the flip-
flop E. The AVF flag is the addition overflow flag. The M specifies the mode
of the Operation, when M=0 the output of B is transferred to the adder, the
input carry is 0, and the output of adder is equal to the sum A+B. When
M=1, the 1’s complement of B is applied to the adder, the input carry is 1,
and output S= A+B’+1. This is equal to A Plus the 2’s Complement of B,
Which is equivalent to the subtraction to the A-B.
Fig 4.1 Hardware for Signed-Magnitude Addition and Subtraction

4.3 Hardware Algorithm for Signed Magnitude Addition and

Subtraction:
The two signs A, and B, are compared by an exclusive-OR gate. If the
output of the gate is 0 the signs are identical; If it is 1, the signs are
different. For an add operation, identical signs dictate that the
magnitudes be added. For a subtract operation, different signs dictate
that the magnitudes be added. The magnitudes are added with a
microoperation EA ← A + B, where EA is a register that combines E and
A. The carry in E after the addition constitutes an overflow if it is equal
to 1. The value of E is transferred into the add-overflow flip-flop AVF. The
two magnitudes are subtracted if the signs are different for an add
operation or identical for a subtract operation. The magnitudes are
subtracted by adding A to the 2's complemented B. No overflow can occur
if the numbers are subtracted so AVF is cleared to 0. 1 in E indicates that
A >= B and the number in A is the correct result. If this numbs is zero,
the sign A must be made positive to avoid a negative zero. 0 in E indicates
that A < B. For this case it is necessary to take the 2's complement of the
value in A. The operation can be done with one microoperation A ← A' +1.
However, we assume that the A register has circuits for microoperations
complement and increment, so the 2's complement is obtained from
these two microoperations. In other paths of the flowchart, the sign of
the result is the same as the sign of A. so no change in A is required.
However, when A < B, the sign of the result is the complement of the
original sign of A. It is then necessary to complement A, to obtain the
correct sign. The final result is found in register A and its sign in As. The
value in AVF provides an overflow indication. The final value of E is
immaterial. It consists of registers A and B and sign flip-flops As and Bs.
Subtraction is done by adding A to the 2's complement of B. The output
carry is transferred to flip-flop E , where it can be checked to determine
the relative magnitudes of two numbers. The add-overflow flip-flop AVF
holds the overflow bit when A and B are added. The A register provides
other microoperations that may be needed when we specify the sequence
of steps in the algorithm.

Subtract Operation Addition Operation

Minuend in A Augend in A

=0 =1 =1 =0
A s ⊕ Bs As ⊕ Bs

EA ← A+ B’ + 1
EA ← A+ B
As ≠ Bs
As ≠ Bs As = Bs
=0 =1
E AVF ←
A≥B
E
≠0 =0
A← A
A’

A←A+ AS ← 0
1

END

Fig 4.2 Flowchart for Addition and Subtraction Algorithm

4.3 Multiplication Algorithm:
Multiplication of two fixed-point binary number is the Signed Magnitude
representation is done by successive shift operation and add operations

Fig 4.3 Fixed Point Binary Multiplication

4.3.1 Hardware Implementation:
The Hardware for multiplication consists with A ,B and Q Register. In which
B holds the Multiplicand , Q holds the Multiplier. Apart from this Sequence
Counter (SC) initially sets to 0 will be raised to no bits in the Multiplier. The
EAQ holds the effective result on performing the operation.

Fig 4.4 Hardware the Multiply Operation

4.3.2 Hardware Algorithm:
The flowchart shows the multiply algorithm AS holds the sign bit with the
Ex-or operation of the multiplicand and multiplier. Initially SC holds the n
value( no of bits of the multiplier ). If Qn=1 the EA ← A+B then perform
the shift operation of EAQ and decrement the sequence Counter. Repeat
the entire process until SC is equals to zero.
Fig 4.5 Flowchart for the Multiply Operation
4.4 Multiplication Algorithm (Booth’s):
Booth algorithm gives a procedure for multiplying binary integers in signed-
2’s complement representation. It operates on the fact that strings of 0’s
in the multiplier require no addition but just shifting, and a string of 1’s in
the multiplier from bit weight 2k to weight 2m can be treated as 2k+1 – 2m.
For example, the binary number 001110 (+14) has a string 1’s from 2 3 to
21 (k=3, m=1). The number can be represented as 2k+1 – 2m. = 24 – 21 =
16 – 2 = 14.Therefore, the multiplication M X 14, where M is the
multiplicand and 14 the multiplier, can be done as M X 2 4 – M X 21. As in
all multiplication schemes, booth algorithm requires examination of the

multiplier bits and shifting of partial product.F

Fig 4.6 Hardware for Booth’s Multiplication Algorithm

Prior to the shifting, the multiplicand may be added to the partial product,
subtracted from the partial, or left unchanged according to the following
rules:

1. The multiplicand is subtracted from the partial product upon

encountering the first least significant 1 in a string of 1’s in the
multiplier.
2. The multiplicand is added to the partial product upon encountering
the first 0 in a string of 0’s in the multiplier.
3. The partial product does not change when multiplier bit is identical to
the previous multiplier bit.

The algorithm works for positive or negative multipliers in 2’s complement

representation. This is because a negative multiplier ends with a string of 1’s
and the last operation will be a subtraction of the appropriate weight. The
two bits of the multiplier in Qn and Qn+1 are inspected. If the two bits are
equal to 10, it means that the first 1 in a string of 1 's has been

encountered. This requires a subtraction of the multiplicand from the partial

product in AC. If the two bits are equal to 01, it means that the first 0 in a
string of 0's has been encountered. This requires the addition of the
multiplicand to the partial product in AC. When the two bits are equal, the
partial product does not change.

Fig 4.7 Flowchart for the Booth’s Multiplication Algorithm

4.4 Division Algorithm:

Division of the two fixed-point binary numbers in the signed magnitude
representation is a combination of Addition and Shift operation ( left shift )

operation. The Dividend in AQ Register, Divisor in the B Register and SC

Fig 4.8 Binary Divison

with the no operations to be performed. The Partial Remainder will be

stored in the EAQ Register.

Fig 4.9 Flowchart for Signed Magnitude division

4.5 Floating Point Addition and Subtraction:

A Floating-Point Number in computer registers consists of two parts

Mantissa m, exponent e and radix r is represented as follows

m X re

Floating-Point Addition or subtraction consists of the following steps

1. Check for Zero’s

2. Align the Mantissa
3. Add/Subtract the Mantissa
4. Normalize the Result

Here we use the Registers A and B to hold the mantissa , a and b registers
to hold the exponent. Parallel Adder for Mantissa and Parallel Adder and
comparator for the exponents.
Fig 4.10 Flowchart for Floating Point Addition and Subtraction
4.6 Floating Point Multiplication:

Multiplication of Floating-Point Numbers requires that we multiply the

mantissa and add the exponents. The Multiplication of the mantissa is
performed as the same the way to provide double-precision Product.
Floating Point Multiplication involves the following steps:

1. Check for Zero’s

2. Add the Exponents.
3. Multiply the Mantissa
4. Normalize the Product

Fig 4.11 Flowchart Floating Point Multiplication

In the Floating-Point Multiplication uses the Register BR and QR to hold the
Multiplicand and Multiplier successively. Register a and b to hold the
exponents of multiplicand and multiplier respectively.

4.7 Floating Point Division:

In the Floating-Point Division, the exponents are subtracted and the

mantissa division is similar fixed-point. The floating point division involves
the following the steps:

1. Check for Zero’s

2. Initialize registers and evaluate the sign
3. Align the Dividend
4. Subtract the Exponents.
5. Divide the Mantissa.
Fig 4.12 Floating Point Division

4.8 BCD Adder:

BCD representation is a class of binary encodings of decimal numbers

where each decimal digit is represented by a fixed number of bits. BCD
adder is a circuit that adds two BCD digits in parallel and produces a sum
digit in BCD form. Since each input digit does not exceed 9, the output
sum cannot be greater than 19(9+9+1). For example: suppose we apply
two BCD digits to 4-bit binary adder. The adder will form the sum in binary
and produce a result that may range from 0 to 19. These binary numbers
are represented by K, Z8, Z4, Z2, and Z1. K is the carry and subscripts
under the Z represent the weights 8, 4, 2, and 1 that can be assigned to
the four bits in the BCD code. When binary sum is equal to or less than or
equal to 9, corresponding BCD number is identical and therefore no
conversion is needed. The condition for correction and output carry can be
expressed by the Boolean function:
C= K + Z8Z4 + Z8 Z2

Fig 4.13 BCD Adder

When it is greater than 9, we obtain non valid BCD representation, then
additional binary 6 to binary sum converts it to correct BCD representation.
The two decimal digits, together with the input-carry, are first added in the
top 4-bit binary adder to produce the binary sum. When the output-carry is
equal to 0, nothing is added to the binary sum. When C is equal to 1, binary
0110 is added to the binary sum using bottom 4-bit binary adder. The
output carry generated from the bottom binary-adder may be ignored.