COMPUTER ARITHMETIC

1. Addition and Subtraction of Unsigned Numbers

The subtraction of two n digit unsigned numbers M – N ( N ≠ 0) in base r can be done as follows:
1. Add the minuend M to the r’s complement of the
subtrahend N. This performs M + (rn– N) = M – N +
rn.
2. If M ≥ N, the sum will produce an end carries rn, which is discarded, and what is left
is the result M – N.
3. If M < N, the sum does not produce an end carry and is equal to r n–(N – M), which is
the r’s complement of (N – M). To obtain the answer in a familiar form, take the r’s
complement of the sum and place a negative sign in front.
For Example:
Using the two binary numbers X = 1010100 and Y = 1000011, we perform the
subtraction X – Y and Y – X using 2’s complements:
X = 1010100. 2’s complement of Y = +0111101,
Sum = 10010001,
Discard end carry.
Answer: X – Y = 0010001
Y = 1000011
2’s complement of X = +0101100
Sum = 1101111
There is no end carry. Answer is negative 0010001 = 2’s complement of 1101111.

2. Addition and Subtraction With Signed –Magnitude Data:

We designate the magnitude of the two numbers by A and B. Where the signed numbers are
added or subtracted, we find that there are eight different conditions to consider, depending on
the sign of the numbers and the operation performed. These conditions are listed in the first
column of Table. The other columns in the table show the actual operation to be performed
with the magnitude of the numbers. The last column is needed to present a negative zero. In
other words, when two equal numbers are subtracted, the result should be +0 not -0.

The algorithms for addition and subtraction are derived from the table and can be stated as
follows (the words parentheses should be used for the subtraction algorithm)
Operation Add Magnitudes Subtract Magnitudes

When A > B When A < B When A = B

(+A) + (+B) +(A + B)

(+A) + (– B) + (A – B) – (B – A) + (A – B)

(– A) + (+ B) – (A – B) + (B – A) + (A – B)

(– A) + (– B) – (A + B)

(+ A) – (+ B) + (A - B) – (B – A) + (A – B)

(+ A) – (– B) + (A + B)

(–A) – (+B) – (A + B)

(–A) – (–B) – (A – B) + (B – A) + (A – B)

Table: Addition and Subtraction of Signed-Magnitude Numbers

If the output of the gate is 0 the signs are identical; If it is 1, the signs are different.

For an add operation, identical signs dictate that the magnitudes be added. For a subtract
operation, different signs dictate that the magnitudes be added.
The magnitudes are added with a microoperation EA ←A + B, where EA is a register that
combines E and A. The carry in E after the addition constitutes an overflow if it is equal to 1.
The value of E is transferred into the add-overflow flip-flop AVF.

The two magnitudes are subtracted if the signs are different for an add operation or identical
for a subtract operation. The magnitudes are subtracted by adding A to the 2's complemented
B. No overflow can occur if the numbers are subtracted so AVF is cleared to 0.

1 in E indicates that A >= B and the number in A is the correct result. If this numbs is zero, the
sign A must be made positive to avoid a negative zero.

0 in E indicates that A < B. For this case it is necessary to take the 2's complement of the value
in A. The operation can be done with one microoperation A ← A' +1.
However, we assume that the A register has circuits for microoperations complement and
increment, so the 2's complement is obtained from these two microoperations.

In other paths of the flowchart, the sign of the result is the same as the sign of A. so no change
in A is required. However, when A < B, the sign of the result is the complement of the original
sign of A. It is then necessary to complement A, to obtain the correct sign.

The final result is found in register A and its sign in As. The value in AVF provides an
overflow indication. The final value of E is immaterial.

Figure below shows a block diagram of the hardware for implementing the addition and
subtraction operations.
It consists of registers A and B and sign flip-flops As and Bs. Subtraction is done by adding A
to the 2's complement of B.

The output carry is transferred to flip-flop E , where it can be checked to determine the relative
magnitudes of two numbers.

The add-overflow flip-flop AVF holds the overflow bit when A and B are added.

The A register provides other micro operations that may be needed when we specify the
sequence of steps in the algorithm.
Figure: Hardware Architecture for Addition and Subtraction of Signed-Magnitude Numbers
Figure: Flowchart

2. Multiplication
UNIT-IV COMPUTER ARCHITECTURE AND ORGANIZATION
With Signed –2’s Complement Data:

l Arithmetic Division

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