Printed pages: 02 Sub Code: RCS 302 Paperld: [G]o[o]3 Roll No. B.Tech. (SEM II) THEORY EXAMINATION 2017-18 COMPUTER ORGANIZATION & ARCHITECTURE Time: 3 Hours Total Marks: 70 Note: 1. Attempt all Sections. If require any missing data; then choose suitably. SECTION A 1. Attempt all questions in brief. 2x7=14 a. Draw the circuit diagram of D Flip Flop. b. Write the difference between RAM & ROM. ¢. Write short note on pipelining process. d. Write the difference between serial & parallel communication. e. Perform the following operation on signed numbers using 2’s compliment method: (56)10 + (-27)10 f, Write speed up performance laws. g. Differentiate between Horizontal & Vertical microprogramming. SECTION B 2. Attempt any three of the followin; 7Tx3=21 a. What is programmable logic device? List various techniques to program PLD. Explain any one technique with example. b. (i) Draw the block diagram for a small Accumulator based CPU (ii) How floating point numbers are represented in computer, also give IEEE 754 standard 32-bit floating point number format. c. Draw the data path of sequential n bit binary divider. Give the non restoring division algorithm for unsigned integers, Also illustrate algorithm for unsigned integer with ble example. d. What is micro programmed control unit? Give the basic structure of micro programmed control unit. Also discuss the microinstruction format and the control unit organization for a typical micro programmed controllers using suitable diagram. e. What do you mean by locality of reference? Explain with s fable example SECTION C 3. Attempt any one part of the following: Tx1=7 (a) Differentiate between RISC & CISC based microprocessor. (b) Explain Booths multiplication algorithm in detail. 4. Attempt any one part of the following: 7x (a) Draw the Data path of 2's compliment multiplier. Give the Robertson multiplication algorithm for 2's compliment fractions. Also illustrate the algorithm for 2's compliment fraction by a suitable example. (b) Describe Sequential Arithmetic & Logic unit (ALU) using proper diagram 5. Attempt any one part of the following: Tx1=7 (a) Give the structure of commercial 8MX 8 bit DRAM chip. (>) Explain the working of DMA controller with help of suitable diagrams.6. Attempt any one part of the following: 7x1=7 (a) What is hardwired control? List various design methods for hardwired control. Discuss in detail using diagram any one of the method for designing GCD processor. (b) How pipeline performance can he measured? Discuss. Give a space time diagram for visualizing the pipeline behavior for a four stage pipeline 7. Attempt any one part of the following: Tx1=7 (a) Discuss the various types of address mapping used in cache memory. (b) A moving arm disc storage device has the following specifications: Number of Tracks per recording surface 200 Disc rotation speed 2400 revolution/minute ‘Track-storage capacity 62500 bits Estimate the average latency and data transfer rate of this device.1 a b. cs d. e f 8 2 es Sub Co“ RCS302 o[3[o]2} Roll No. ] BTECH (SEM II) THEORY EXAMINATION 2018-19 COMPUTER ORGANIZATION AND ARCHITECTURE 2: 3 Hours Total Marks: 70 : 1. Attempt all Sections. If require any missing data; then choose suitably SECTION A Attempt all questions in brief. 2x7=14 What do you understand by Locality of Reference? Which of the following architecture is/are not suitable for realizing SIMD? What is the difference between RAM and DRAM? ‘What are the difference between Horizontal and vertical micro codes? Describe cycle stealing in DMA. List three types of contro! signals Define the role of MIMD in computer architecture SECTIO! Attempt any three of the following: Tx3=21, Evaluate the arithmetic statement X = (A*B)*(C+D) using a general register coniputer with three address, two address wh one address instruction format a piogram to evaluate the expression Perform the division processf00001111 by 001 l(use a dividend of 8 bits) A two way set associative cathe memory uses blocks of 4 words. The cache can accommodate a total o£ 2048 words from memory. The main memory size is 128K X 32 i Formulate all pertinent information required to constrict the cache memory. ii, What is the size of cache memory? What is associative memory? Explain with the help of ’block diagram, Also mention the situation in which associative memory can be €fféctive utilized. A Computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of “The instruction has four parts: an indirect bit, an operation code, a register cole'part to specify one of 64 registers and an address part (i) How many bits are there in the operation code, the register code part and the address ‘i g (i) Draw the instruction word farrfiit and indicate the number of bits in each part. (ii) How many bits are there inthe data and address inputs of the memory?SECTION C Attempt any one part of the following: 7x1=10 (a) Write short notes on (i) Instruction pipeline (ii) DMA based data transfer. (b) Explain the difference between vectored and non-vectored interrupt. Explain stating examples of each. Attempt any one part of the following: m1= (a) Draw the flow chart of Booth’s Algorithm for multiplication and show the multiplication process using Booth’s Algorithm for (-7) X (+3) (b) Write short notes on: (i) Amdahl’s Law Gi) Pipelining Attempt any one part of the following: Tx1=10 (a) What is a microprogram sequencer? With block diagram, explain the working, of microprogram sequencer. (b) Draw a flowchart for adding and subtracting two fixed point binary numbers where negative numbers are signed I's complement presentation, Attempt any one part of the following: ? 7x1=10 (a) Give the block diagram of DMA controller; Why are the read and write control lines in a DMA controller bidiféctional” (b) Explain all the phases of instruction’ pyele Attempt any one part of the followings 7x1 = (a) Explain the basic concept of Mardwired and Software control unit way edt diagrams, (b) 85 x For the following Reservation table i Calculate the set of the forbidden latencies and collision vector. ii Draw a state diagram, showing afl;possible initial sequences (cycles) without a collision in the pipelines iii Simple cycles (SC) 7 W. Greedy cycles among single the cycles vy. MAL (minimum average latency) vi, What is the minim allowed constant cycles vii. Maxi Throughput viii, ‘Throughput if the minimum constant cycle is usedPrinted Page 1 of 2 Sub Code:KCS302 Paper Id: 110322 Roll No: I B. TECH. (SEM-II1) THEORY EXAMINATION 2019-20 COMPUTER ORGANIZATION AND ARCHITECTURE Time: 3 Hours Total Marks: 100 Note: 1. Attempt all Sections. Ifrequire any missing data; then choose suitably. SECTION A 1. Attempt all questions in brief. 2x10=20 Quo. Question Marks | C 0 | Define the term Computer Architecture. 21 | Draw the basic functional units of a computer. 2 [1 ©. | Perform the 2's complement subtraction of smaller number (T0011) from [2 [2 Jarger qumber (111001). | Whats the role of Multiplexer and Decoder? z (2 e.__| Write the differences between RISC and CISC. 2) £__| What are the types of microinstructions available? RNa 2.3 &___| What is SRAM and DRAM? 2 |e], h ‘What is the difference between 2D and 2""D mex(gky organization? 2 aA i. | What is 10 control method? z | What is bus arbitration? 2 sl NB 2. Attempt any three of the fase xX Marks Quo. Cc oO a. | Convert the followin, fic expressions from infix to i a5 d om xB i A*BHC*D+ESF ii__A*[B+C*CD+EVF(G+H) we b. Design a 4-bit Carry-Look ahead Adder and expl ‘operation with an| 10 |2 example. © i. Draw the timing diagram for a instruct a5 [3 L ii____Give a note on subroutine. © | What do you mean by virtual mem cuss how paging helps in[ 10 |4 implementing virtual memory. © _| What is DMA? Deseribe how pauagfeta to transfer data from peripherals._|' | * Syecrton c 3. Attempt any one part of the folowing: Quo. Question Marks | C oO ‘a, | Describe in detail the different kinds of addressing modes with an example. | 10 __|1 b. Discuss stack Organization. Explain the following in details- 10 1 @ Register stack Gi) _ Memory stack a oo 1[Page ‘MANISH KUMAR JHA | 10-Dec-2019. 3 | 117.55.242.131Printed Page 2 of2 ‘Sub Code:KCS302 Paper td: [110322 Roll No: L 4. Attempt any one part of the followii Quo. Question Marks | C _ 0 a. | Represent the following decimal number in IEEE standard floating-point as [2 format in a single precision method (32-bit) representation method. (65.175)0 ii, 307.1875)0 b. | Using Booth algorithm perform the multiplication on the following 6-bit | 10 | 2 unsigned integer 10110011 * 11010101 5. Attempt any one part of the following: Qno. Question Marks | C ° | What is parallelism and pipelining in computer Architecture? 103 b.__| Explain the organization of Microprogrammed control unit in detail 0 [3 ail 6. Attempt any one part of the following: ‘ > Qno. ‘Question ‘Marks | Ci}. @ a. | Discuss the different mapping techniqueswused in cache memories and their | 10 [4 relative merits and demerits. Be af b. RAM chip 4096 x 8 bits has two enable lines. How many pins are needed for [| 545, | 4 the integrated circuits package? Draw a block diagram and label all input and }’ ‘outputs of the RAM. What is main feature of random-access memory? 7. Attempt any one part of the following: , Qno. y Question } ‘Marks | C y oO ‘a. | Write down the difference between isolated 1/0 and memory mapped VO. Also | 10 [3 discuss advantages and disadvantages of isolated I/O and jremory mapped I/O. “ b i. Discuss the design of a typical input or output interface. 0 {5 ii,___What are interrupts? How are they handled? 2|Page ‘MANISH KUMAR JHA | 10-Dec-2019 09:02:23 | 117.55.242.131Time: 3 Hours Printed Page: 1 of 2 VANE A Suhject Code: K 02 PAPER 1D-311337 Roll N BTECH (SEM-IIl) THEORY EXAMINATION 2020-21 COMPUTER ORGANIZATION AND ARCHITECTURE, Note: 1. Attempt all Sections. If require any missing data; then choose suitably SECTION A Total Marks: 100 1, ___Attempt aif questions in brief. 2x10=20 Qno. Question Marks | CO a Define the term Computer architecture and Computer organization. 2 I b What is mean by bus arbitration? List different types of bus arbitration 2 1 e Discuss biasing with reference to floating point representation 2 2 d What is restoring method in division algorithm? 2 2 e. Define micro operation and micro code 2 3 if Write short note on RISC. z 3 z Define hit ratio 2 4 h What do you mean by page fault? 2 4 i Explain the term cycle stealing 2 3 What do you mean by vector interrupt? Explain 2 3 SECTION B 2, Attempt any three of the followin; Qno. Question Marks | CO a i, Draw a diagram of bus system using MUXCwhich has four registers of size 4 bits | 10. 1 each ii, Evaluate the arithmetic statement X=A+B*(C*D+E*(F+G)} using a stack organized computer with zero address operation instructions. b Explain in detail the principle oP earry look ahead adder and design 4-bit OLAudder_[10 [2 a Draw the flowchart for instrubtion cycle with neat diagram and explain. aE} d Discuss 2 D RAM and 2.5D)RAM with suitable diagram. 10 4 € Draw and explain the block diagram of typical DMA controller. 0 ‘(5 SECTION C 3.___Attempt any one part of the following: Qno. Question Marks | CO a An instruction is stored at location 400 with i{& address field at location 401 The | 10 1 address field has the value 500.A processor register RI contains the number 200 Evaluate the effective address if the addressing mode of the instruction is (i) direct (ii) immediate (iii) relative (iv) register indireet(v) index with R1 as index register b What do you mean by processor ofganization? Explain various types of processor | 10 7 organization 4. Attempt any one part of the following: Qno. Question Marks | CO a Show the systemic multiplication process of (20) X (-19) using Booth’s algorithm: 10 2 b Explain IEEE standard for floating point representation, Represent the number © [10 [2 1460.125)io in single precision and double precision format 1|Page5: Printed Page: 2 of 2 VANE A Suhject Code: K 02 PAPER 1D-311337 Roll No: Attempt any one part of the following: Qno. Question Marks | CO a What is a micro program sequencer? With block diagram, explain the working of [10 [3 micro program sequencer. b Differentiate between hardwired and micro programmed control unit Explain each [10 [3 component of hardwired control unit organization 6.___Attempt any one part of the following: Qno. Question Marks | CO a Calculate the page fault for a given string with the help of LRU & FIFO page[10 [4 replacement algorithm, Size of frames = 4 and string 12 342156212376321 236 b. ‘A computer uses RAM chips of 1024*1 capacity 10 4 i) How many chips are needed & how should their address lines be connected to provide a memory capacity of 1024*8? ii) How many chips are needed to provide a memory capacity of 16 KB? 7.____Attempt any one part of the following: Qno. Question Marks | '€O a What do you mean by asynchronous data transfer? Explain strobe control and hand [10 \ }3 shaking mechanism. b. Discuss the different modes of data transfer. 10: 2|Page4 000000 oat Roll BTECH (SEM II) THEORY EXAMINATION 2021-22 COMPUTER ORGANIZATION AND ARCHITECTURE Time: 3 Hours Total Marks: 100 Note: Attempt all Sections. If you require any missing data, then choose suitably SECTION A L Attempt all question: brief. 2x10 = 20 Qno ‘Questions CO; (a)_| List and briefly define the main structural components ofa computer. | COT (b)_| Differentiate between horizontal and vertical microprogramming. C03 (©) [Represent the following conditional control statements by two register | COT transfer statements with control functions. If{P=1) then (RI €R2) else if (Q=1) then (RIER3) (@ [Design a 4-bit combinational incremental circuit using four full adder | CO2 circuits. (@) J Differentiate between Daisy chaining and centralized parallel [ COS arbitration. (8 | What is the transfer rate of an eight-track magnetic tape whose speed is | COS 120 inches per second and whose density is 1600 bits per inch? (| Register A holds the binary values 1001101. What is the register value | CO2 after arithmetic shift right? Starting-frdm the initial number 10011101, determine the register value after arithmetic shift lef, and state whether there is an overflow. (h) [What is an Associative memory? What are its advantages and [CO4 disadvantages? (@_[ Differentiate between'static RAM and Dynamic RAM. cor (@_[What are the differénttypes of instruction formats? C03 SECTION B 2. Attempt any three of the following: 10x3 = 30 Qno ‘Questions co (@)_|A digital computer has a common bus system for 8 registers of 16 bit | COI each. The bus is constructed using multiplexers. I How many select input are there in each multiplexer? IL What is the size of multipléxets needed? I1__How many multiplexers.afe there in the bus? (6) __[ Explain destination-initiated transfer using handshaking method COS, (©)_| Explain 2-bit by 2-bit Arraycmultiplier. Draw the flowchart for divide | CO2 operation of two numbers in’signed magnitude form @ [A digital computer tias-a memory unit of 64K X 16 and a cache | CO4 memory of 1K words.The cache uses direct mapping with a block size of four words. 1 How many bits are there in the tag, index, block, and word fields of the address format? IL How many bits are there in each word of cache, and how they are divided into funetions? Include a valid bit. Ii__How many blocks can the cache accommodate? (©)_[ Explain with neat diagram, the address selection for control memory. | CO3UOTE A subjeet Codes KESSI2 PAPER ID-411907 Roll Noz BIECH (SEM II) THEORY EXAMINATION 2021-22 COMPUTER ORGANIZATION AND ARCHITECTURE SECTION C 3. Attempt any one part of the following: 10x1 = 10 Qno Questions co (a) [A Binary floating-point number has seven bits for a biased exponent | CO2 The constant used for the bias is 64 1. List the biased representation of all exponents from -64 to +63 II. Show that after addition of two biased exponents, itis necessary to subtract 64 in order to have a biased exponent’s sum. IIL. Show that after subtraction of two biased exponents, it is necessary to add 64 in order to have a biased exponent’s difference (b) [Show the multiplication process using Booth algorithm, when the | CO2 following binary numbers, (+13) x (-15) are multiplied 4. Attempt any one part of the following: 10x1 = 10 Qno Questions CO (@)_| Draw a diagram of @ Bus system in which it uses 3 state buffers and a [ COT decoder instead of the multiplexers. ()_[ Explain in detail multiple bus organization with the help of a diagram [COT 5. Attempt any one part of the following: 10x10 Qno ‘Questions CO (a) |The logical address spate“in a computer system consists of 128 | CO4 segments. Each segment can have up to 32 pages of 4K words each. Physical memory consists of 4K blocks of 4K words each, Formulate the logical and physical address formats (b)_| How is the Virtual address mapped into physical address? What are the | CO4 different methods of writing into cache? 6. Attempt any one part of the following: 10x1 = 10 Qno Questions co (@) [Explain how the computer buses canbe used to communicate with | COS memory and 1/0. Also draw the) block diagram for CPU-IOP communication (b)_| What are the different methods of @synchronous data transfer? Explain | COS in detail 7. Attempt any one part of the following: 10x1 = 10 Qno Questions co (@) [Write a program Yo evaluate arithmetic expression using stack | CO3 organized computer with 0-address instructions X=(A-B)* (C-D*E)/F)/G) (b)_| List the differences between hardwired and micro programmed control | CO3 in tabular format. Write the sequence of control steps for the following instruction for single bus architecture REE R24 (R3)Printed Pages:02 Sub Code: KCS.302 Paper ld: [233687 Roll No. [ B. TECH. (SEM Ill) THEORY EXAMINATION 2022-23 COMPUTER ORGANIZATION AND ARCHITECTURE, Time: 3 Hours Total Marks: 100 Note: Attempt all Sections. If require any missing data; then choose suitably SECTION A 1. Attempt all questions in brief. 2x10=20 (a) _List the steps involved in an instruction eycle. (b) How memory read and write operations are performed in computer system? (©) Define bus and memory transfer? ()_ Define HIT and MISS ratio in memory with an example. (©) Define instruction cycle (f) Differentiate between RISC and CISC. (g) List the difference between static RAM and dynamic RAM. (h) Define Virtual memory i) List down the functions performed by an InpuOutput unit, (i) Why does the DMA get priority over CPU when both request memory transfer? SECTION B 2. Attempt any ¢hrce of the falta 10x3=30 (a) Explain functional units of computer system in detail (b)_ Explain IEEE-754 standard for floating point representation, Express (314.175)10 in all the IEEE-754 models. (©) Explain the concept of pipelining and also explain types OP pipelining (d) Consider a cache consisting of 256 blocks of 16 words each for a total of 4096 words and assume that the main memory is addressable by a 16 bits address and it consists of 4K blocks. How many bits are there in each of TAG, SET, WORD field for 2-way set associative technique? (e) Define interrupt. Also discuss different-typés of interrupt. SECTION C 3. Attempt any one part of the following: 10x1=10 (a) Explain about stack organization used in processors. What do you understand by register stack? (b) What is an effective address? How it is calculated in different types of addressing modes? Explain4. Attempt any one part of the following: 10x1=10 (a) Describe the derivation procedure of look ahead carry adder by an example with the help of block diagram. (b) Show the systematic multiplication process of (-15) * (-16) using Booth’s Algorithm, Attempt any one part of the following: 10x (a) Write a program to evaluate the arithmetic statement, P=((X-¥+Z)*(A* B)(C*D*B) By using (i) Two address instructions (ii) One address instructions (iii) Zero address instructions (b) What are the differences between hardwired and micro-programmed control unit? Attempt any one part of the following: 10x1=10 (a) Discuss the Memory Hierarchy in computer system with regard to Speed, Size and Cost (b) Write a short notes on magnetic disk, magneti¢ tape and optical disk Attempt any one part of the following 10x! 0 (a) With a neat schematic diagram,.explain about DMA controller and its mod® Of data transfer (b)_ Discuss the design of a typical input or output interfaceTIME: 3HRS. Printed Page: Subject Code: BCS302 of? PAPER ID-311725 Roll No: BTECH (SEM IL) THEORY EXAMINATION 2023-24 COMPUTER ORGANIZATION AND ARCHITECTURE Note: 1. Attempt all sections. If require any missing data; then choose suitably. SECTION A Attempt all questions in brief. M.MARKS: 70 Question Marks ‘What are the different types of Buses used in computer architecture? Name the different types of multipliers ‘What ate the different phases of an instruction eycle? How does control unit of a computer works? ‘Write a short not on locality of reference. Define 2 % D memory organization =] =]° |= 16) Tn what way synchronous and asynchronous serial modes of data transfer differ? D[P]e]e|epofo| x SECTION B Attempt any three of the following: a What is meant by the term BUS arbitration? Why is it needed? How can bus arbitration be implemented in Daisy changing scheme? Show the multiplication process using Booth’s algorithm when the following numbers are multiplied: - (-12) *(18). ‘What is pipelining? What are the(Uifferent stages of pipelining? Explain in detail Give classification of memory/based on the method of access. Also~discuss construction and working of magnetic disk and various componentsiof disk access time. What are the basic differences between interrupt initiated /O-and programmed 1/0? Explain in detail SECTION C Attempt any one part of the followin; ‘What do you mean by processor organization? Explain various types of processor organization with suitable example. Differentiate between Memory stack andiregister stack. ‘Attempt any one part of the following? Explain in detail the principle offearry looks ahead adder and design 4-bit CLA adder. Represent the following decimal humber in IEEE standard floating-point format in a single precision method (32 bit) representation method @)— (85.125)0 (ii)__(-307.1875)0 ‘Attempt any one part of the following: Explain the different cycles of an instruction execution. aI => Differentiate between hardwired and micro programmed control unit. Explain each component of hardwired control unit organization, 1[PageMAU 1 0 Subject Code: BCS302 PAPER ID-311725 Roll No: BTECH (SEM IL) THEORY EXAMINATION 2023-24 COMPUTER ORGANIZATION AND ARCHITECTURE TIME: 3HRS. M.MARKS: 70 6. Attempt any one part of the following: ‘a | Consider a cache (MT) and memory (M2) hierarchy with following characteristics: | 7 M1 : 16K word, 50 ns Access time M2: IM word, 400 ns Access time Assume 8-word cache blocks and set size 256 words with set associative mapping. (i) Show and explain the mapping between M2 and MI (ii) Calculate the effective memory access time with cache hit ratio=0.95 b. __ | Explain the direct mapping technique. Consider a digital computer has a memory | 7 unit of 64k*16 and cache memory of Ik words, The cache uses direct mapping with 4 block size of four words. (i) How many bits are there in the tag, block and word fields of the address format? (ii)__How many blocks can the cache accommodate? “Attempt any one part of the following: 7Tx1=7 ‘a | What do you mean by asynchronous data tahsier? Explain strobe control and [7 handshaking mechanism. b Explain the various modes of data transfer and discuss direct memory access mode} 7. in detail_Also explain how DMA is supetior to other modes.