Microprogramming

Alternative way of specifying control

FSM
• State -- bubble
• control signals in bubble
• next state given by signals on arc
• not a great language to specify when things are complex

Treat as a programming problem

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 1

Microprogramming
Datapath remains the same
Only control is specified differently but does the same

Each cycle specify required control signal via microprogram field

label alu src1 src2 reg memory pcwrite next?

fetch add pc 4 read pc alu alu +1
add pc extshft read dispatch 1
mem1 add A extend dispatch 2
lw2 read alu +1
write mdr fetch

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 2

FSM (left) & Microprogramming (right)

Combinational
control logic Datapath control outputs

Microcode
Outputs storage

Datapath
Outputs control
outputs
Inputs

Input
Next state
1
State register
Inputs from instruction
register opcode field Sequencing
Microprogram counter
control
Adder

Address select logic

Inputs from instruction

register opcode field

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 3

Potential Benefits of Microprogramming

More disciplined control logic - easier to debug
Enables family of machines with same ISA (IBM 360/370)

Enables more complex instruction set

Writable control-store allows in-the-field fixes

But in the 1990s:

CAD tools and PLAs offer similar discipline

Caches make memory almost as fast as control store

Complex ISA - hardwired+micro-ops (e.g., Pentium Pro)

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 4

State of the Art
Specify control
• FSM - does not scale
• microprogram - works
• vhdl/verilog - preferred

Implement control
• random logic - only if CAD tools generate
• PLAs - mostly generated by CAD tools
• Control store + update - why accept this contraint?

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 5

State of the Art

Specify control in verilog/vhdl
CAD compile to PLA, but could used ROM or RAM

Microprogramming implementation seems dead

• because it unnecessarily constrains CAD’s targets

But what if technology makes control store faster than caches?

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 6

Horizontal vs. Vertical microcode
Horizontal
• fewer and wider micro-instructions
• less encoding
• larger control store - may waste space (control lines)

Vertical
• more and narrower micro-instructions
• dense encoding
• smaller control store - but may need more steps

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 7

Exceptions: Background
What happens:
• instruction fetch page fault
• illegal opcode
• privileged opcode
• arithmetic overflow
• data page fault
• I/O device statuc change
• power-on/reset

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 8

Exceptions: Background
For some, we could test for the condition
• arithmetic overflow
• I/O device ready

But most tests for other conditions uselessly say “no”

Solution: Generate “surprise procedure calls” called exception

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 9

Exceptions: Big Picture

Interrupt (asynchronous) or trap (synchronous) triggers exception
Hardware handles initial reaction

Then invokes a software exception handler

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 10

Exceptions: Hardware
• Sets state giving cause of exception
• (MIPS: in exception_code field of Cause register -
• a coprocessor 0 register)
• Changes to Kernel mode for dangerous work ahead
• Disables interrupts (to prevent infinite looping)
• (MIPS: both the above in Status register -
• another coprocessor 0 register)
• saves current PC (MIPS: exception PC (EPC)
• jumps to specific address (MIPS: PC = 0x80000080)
• (like a surprise jal - so can’t clobber $31)
© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 11

Exceptions: Software
• Exception handler (MIPS: .ktext beginning at 0x80000080)
• Set flag to detect incorrect entry -exception while in handler
• Save some registers
• Find exception type (MIPS: exception_code in Cause reg)
• E.g., I/O interrupt or syscall
• Jump to specific exception handler ...

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 12

Exceptions: Software, cont.
• Handle specific exception
• Jump to clean-up to resume user program
• restore registers
• Reset flag that detects incorrect entry
• Atomically
• restore previous mode
• enable interrupts
• jump back to program (using EPC)

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 13

Implementing Exceptions
We worry only about hardware, not software handler
IntCause
• 0 undef instruction
• 1 arithmetic overflow

Changes to the datapath

New states in FSM to deal with exceptions

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 14

FSM with Exceptions (Fig. 5.50)
Instruction decode/
Instruction fetch Register fetch
0
MemRead 1
ALUSrcA = 0
IorD = 0 ALUSrcA = 0
IRWrite ALUSrcB = 11
Start ALUSrcB = 01
ALUOp = 00 ALUOp = 00
PCWrite
PCSource = 00

(Op = 'J')
')
)

(O
pe

EQ
ty

p
R-

'B
SW ') =

=
= ' p

=
(O

ot
(Op

p
Memory address Branch

(O
Jump

he
or
') Execution

r)
computation LW completion completion
= '
2 (Op 6 8 9
ALUSrcA = 1
ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00
ALUSrcB = 00 ALUSrcB = 00 PCWrite
ALUOp = 01
ALUOp = 00 ALUOp = 10 PCSource = 10
PCWriteCond
PCSource = 01
(Op = 'LW')

(O
p
=
'S
W'

Memory Memory
)

access access R-type completion IntCause = 0

IntCause = 1
3 5 7 11 10 CauseWrite
CauseWrite
RegDst = 1 ALUSrcA = 0 ALUSrcA = 0
MemRead MemWrite Overflow ALUSrcB = 01 ALUSrcB = 01
RegWrite
IorD = 1 IorD = 1 ALUOp = 01 ALUOp = 01
MemtoReg = 0
EPCWrite EPCWrite
PCWrite PCWrite
PCSource = 11 PCSource = 11

Write-back step
4 Overflow

RegWrite
MemtoReg = 1
RegDst = 0

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 15

Implementing Exceptions
New arcs in the FSM just like regular arcs
FSM more complex if must add many arcs

Critical path may be worsened

Alternative: vectored interrupts
• PC = base + f(Cause)
• e.g., PC = 0x80 + IntCause << 7 # 32 instructions
+ faster
– more hardware, more space

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 16

Review
Type Control Datapath Time (CPI, cycle time)
Single- comb + end No reuse 1 cycle, (imem + reg +
cycle update ALU + dmem)
Multi- comb + Reuse [3,5] cycles, Max(imem,
cycle FSM update reg, ALU, dmem)
We ? ? ~1 cycle, Max(imem , reg,
want ALU, dmem)

We will use pipelining (lunch buffet!) to achieve last row

© 2000 by Mark D. Hill CS/ECE 552 Lecture Notes: Chapter 5 17