Name : Handout-5,6 11/1/17 FN

INTRODUCTION
The Vi Microsystems Spartan-3E Trainer Kit is a demonstration platform intended for you to
become familiar with the new features and availability of the Spartan-3E FPGA family. This Kit
provides a easy-to-use development and evaluation platform for Spartan-3E FPGA designs.
KEY COMPONENTS AND FEATURES
Figure 1 shows the Spartan-3E Trainer Kit block diagram, which includes the following
components and features:
* Xilinx XC3S500E – FT256 Spartan 3E FPGA
* 500K gates & 10,476 Logic cells
* 16 Nos of digital input using slide switches
* 16 Nos of digital outputs using discrete LEDs
* One Reset switch
* FPGA configuration through
# JTAG port
# Slave serial
# Onboard Flash Prom XCFO4S
* Total 190 I/O pins : 80 pins used for integrating peripheral like LED, Switches etc.,
balance 110 pins available to user
* 3 Nos of 20 pin header to interface VLSI based experiment modules (3.3V compatible).
* 1 No of 26 pin header to interface VLIM cards like TLC (5V compatible)
* On board programmable oscillator from 3MHz to 200 MHZ
* 6 Nos of 7 segment LED display (to display Hr, Min, Sec of RTC VHDL
implementation)
* 2 Nos of 100 pin header with 110 I/O pins terminations provided to plug in daughter
boards.

Additional Add-on Features

* Header is provided to interface with the VSK-Spartan 3E
* 16 × 2 LCD interface.
* 4 × 4 matrix keyboard.
* Relay interface.
* Stepper motor interface.
* ADC & DAC interface.
# 2 ADCs of 3 MSPS each, 12 bit resolution
# Anti aliasing filters at ADC input
# 8 Channel, 12 Bit DACs
# Reconstruction filters at the DAC output
* RS232 / SPI Serial Port
* Temperature sensor interface
* USB 2.0 Complaint interface (480 Mbits/sec)
VSK-Spartan 3E model is shown below (Figure 2).

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Familiarisation of FPGA Kit

CLOCK SOURCE
Spartan3E FPGA works in different Clock frequencies. User can use any frequencies as given
below,
CLOCK INPUT FPGA PIN
CLK is A8

SWITCHES & LEDS

3.1. Power Switch
The Spartan-3E Trainer Kit has a slide power switch. Moving the power switch Up for Power
On and down for power off.
3.2. Configuration Switch
The Spartan-3E Trainer Kit has a push button Switch to Configure the FPGA from Xilinx
Serial Flash PROM.
3.3. Reset Switch

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The Spartan-3E Trainer Kit has a push button Switch to reset the FPGA. The Reset switch is
connected to “J6" of the Spartan 3E pin.
3.4. Input Switches
The Spartan-3E Trainer Kit has 16 way slide switches for giving inputs to the FPGA i/o lines.
Slide Switch connections with FPGA
SWITCHES FPGA PINS
SW4 T14
SW5 T12
SW6 T9
SW7 T7
SW8 T2
SW9 G12
SW10 H1
SW11 R3
SW12 N11
SW13 N3
SW14 M13
SW15 M7
SW16 M3
SW17 K4
SW18 J12
SW19 J11
3.5. Output LEDs
The Spartan-3E Trainer Kit has 16 individual surface-mount LEDs. The LEDs are Labeled L2
to L17. The cathode of each LED connects to ground. To light an individual LED, drive the
associated FPGA control signal High.
LED connections with FPGA
LEDS FPGA PINS
L16 R1
L15 R2
L14 K3
L13 T4
L12 T5
L11 R6
L10 T8
L9 R10
L8 N10
L7 P12
L6 N9
L5 N12
L4 P13
L3 R13
L2 T13
L1 P14
SEVEN SEGMENT LED DISPLAY
The Spartan-3E Trainer Kit has a six-character, seven segment LED display controlled by FPGA
user-I/O pins. Each digit shares eight common control signals to light individual LED segments.
Each individual character has a separate anode control input.

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FPGA Connections to Seven-Segment Display

SEGMENT FPGA PIN
A P8
B P10
C P9
D P6
E P4
F P5
G P3
DP P11
Digit Enable Signals
DISPLAY DISP1 DISP2 DISP3 DISP4 DISP5 DISP6
FPGA
PIN P1 P2 P7 R4 R11 N14
The LED control signals are time-multiplexed to display data on all four characters, as shown
in Figure below. Present the value to be displayed on the segment control inputs and select the
specified character by driving the associated anode control signal Low. Through persistence of
vision, the human brain perceives that all four characters appear simultaneously, similar to the
way the brain perceives a TV display.

Display Characters and Resulting LED Segment Control Values

CHARACTER A B C D E F G
0 1 1 1 1 1 1 0
1 0 1 1 0 0 0 0
2 1 1 0 1 1 0 0
3 1 1 1 1 0 0 1
4 0 1 1 0 0 1 1
5 1 0 1 1 0 1 1
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Familiarisation of FPGA Kit

6 1 0 1 1 1 1 1
7 1 1 1 0 0 0 0
8 1 1 1 1 1 1 1
9 1 1 1 1 0 1 1
A 1 1 1 0 1 1 1
B 0 0 1 1 1 1 1
C 1 0 0 1 1 1 1
D 0 1 1 1 1 0 1
E 1 0 0 1 1 1 1
F 1 0 0 0 1 1 1
Programs
Switch & Led
Verilog Program
module io(sw, led);
input [15:0] sw;
output [15:0] led;
assign led = sw;
endmodule
UCF
NET "sw<0>" LOC = "t14" ;
NET "sw<1>" LOC = "t12" ;
NET "sw<2>" LOC = "t9" ;
NET "sw<3>" LOC = "t7" ;
NET "sw<4>" LOC = "t2" ;
NET "sw<5>" LOC = "g12" ;
NET "sw<6>" LOC = "h1" ;
NET "sw<7>" LOC = "r3" ;
NET "sw<8>" LOC = "n11" ;
NET "sw<9>" LOC = "n3" ;
NET "sw<10>" LOC = "m13" ;
NET "sw<11>" LOC = "m7" ;
NET "sw<12>" LOC = "m3" ;
NET "sw<13>" LOC = "k4" ;
NET "sw<14>" LOC = "j12" ;
NET "sw<15>" LOC = "j11" ;
NET "led<0>" LOC = "r1" ;
NET "led<1>" LOC = "r2" ;
NET "led<2>" LOC = "k3" ;
NET "led<3>" LOC = "t4" ;
NET "led<4>" LOC = "t5" ;
NET "led<5>" LOC = "r6" ;
NET "led<6>" LOC = "t8" ;
NET "led<7>" LOC = "r10" ;
NET "led<8>" LOC = "n10" ;
NET "led<9>" LOC = "p12" ;
NET "led<10>" LOC = "n9" ;
NET "led<11>" LOC = "n12" ;
NET "led<12>" LOC = "p13" ;
NET "led<13>" LOC = "r13" ;
NET "led<14>" LOC = "t13" ;
NET "led<15>" LOC = "p14" ;
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Check the Output

1. Download the program into the FPGA.
2. Depending upon the switch position led will changed.
8.2 Simple Gate
Verilog Program
module gates(i1,i2,o2);
input i1;
input i2;
output o2;
assign o2 = i1 & i2;
endmodule
UCF
NET "i1" LOC = "t14" ;
NET "i2" LOC = "t12" ;
NET "o2" LOC = "r1" ;
Check the Output
1. Download the program into the FPGA.
2. Check the result, if both the switch is high the output is high and any one of the input is low
the output is low.

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