Address/data bus on 8086/88 is multiplexed i.e.

same bus is shared for address and data, this

Intel 8282 is a latch, which can be used todemultiplex address/data bus.

The 8282 is 8-bit latch, hence total three 8282 latches are required for 20-bit address.

As shown in fig. ALE (Address latch enable signal) of 8086 is connected to STB (Strobe) of
8282 latch.

When ALE goes high during earlier part of bus cycle the latch becomes transparent and Q
output follows the input.The input is address bit at that time.

When ALE goes low, at the negative edge of the signal,latch stores the output (address bit) and
it will hold this address till next ALE comes.

Thus A0-A15 is separated out from D0-D15 and A-16-A19is separated out from S3-S6, using
three 8282 latches.
OE pin of 8282 is grounded to enable latch’s output.

The 8282 latch also provides buffering of address lines.

Intel 8286 transceiver provides buffering for data lines of 8086/8088.

The 8286 transceiver contains eight receivers and eight drivers, so it can be used for
bidirectional data transfer. Total two 8286 are required for 16 data lines.

As shown in fig. OE pin of 8286 is connected to DEN pin of 8086.when uP is ready for data
transfer it makes
DEN
low, this will enable 8286 transceiver.

The direction of data transfer is decided by T pin of 8286, which is connected to DT/R pin of
8086. During the transmission of data, this pin is asserted high by 8086 and data is transferred
from uP through transceiver to memory or I/O device.

When T pin of 8086 is driven high, A0-A7 lines act as input lines andB0-B7 lines act as output
lines.

During reception of data DT/R pin is made low and data is received from memory or I/O device
through transceiver to uP. When T pin is driven low, B0-B7 lines act as input lines and A0- A7
lines act as output lines.

This mechanism allows bidirectional datatransfer through 8286 transceiver.

8284 Clock Generator

Intel 8284 clock generator provides clock pulse train with above specifications

Other than this it also synchronizes READY signal(which indicates peripheral is ready to
complete data transfer) and RESET signal (which is used to initialise the system) with clock
pulses.
As shown in the block diagram clock source can becrystal oscillator or external frequency input.
1.
If crystal oscillator is used as clock source, it should beconnected to X1 and X2. and F/C pin
should begrounded.
2.
If external frequency input is used as clock source then,it should be connected to EFI pin and
F/C pin should beconnected to +5V(Vcc).

The clock coming from any one of this source is given to divide by 3 counter through logic gate
circuit. It provides33% duty cycle

CLK: it is output of divide by 3 counter, which is a clock pulse train with frequency equal to one
third of crystal frequency and33% duty cycle. This signal is passed through buffer.
2.
PCLK: It is output of divide by 2 counter, which is a clock pulsetrain with frequency equal to one
half of CLK frequency 50% dutycycle or on other words it has frequency equal to one sixth(1/6)
of crystal frequency. This can be used to provide clock signal to peripheral equipment in the
system
3.
OSC: This oscillator output is TTL level signal with frequencyequal to crystal frequency. This
signal can be used to provideclock frequency to EFI pin of other 8284 clock Generators in
multiprocessor systems.

The CSYNC (Clock Synchronization) input allows the system clock to be synchronized to an
external event. It can also be used to synchronize more than one 8284s to provide clock signal
that are in phase for multiprocessor systems. This pin must begrounded to set all the counters.

8288 Bus Controller

Input signals:1. Status inputs:

MRDC: Memory Read control pin. It instructs memory to put data form addressed memory
location on the data bus.

MWTC: Memory Write control pin. It instructs memory to accept data form data bus and put the
data in addressed memory location.

IOWC: I/O Write control pin. It instructs I/O to accept data from data bus and put the data in
addressed I/O port.

IORC:I/O Read control pin. It instructs I/O to put data from addressed I/O port on the data bus.

AMWC: Advanced memory Write command. This output is enable one clock pulse earlier than
normal write commands.

AIOWC: Advanced I/O Write command. This output is enable one clock pulse earlier than
normal write commands.

INTA: interrupt acknowledge output. The output is generated infrom of two negative pulses, in
response to interrupt applied to the INTR pin.
CLK : The clock input provides internal timing.The CLK output pin of the 8284 signal generator
is connected to CLK pin of IC 8288. ALE : The address latch enable output is used to
demultiplex the address/data bus and address/status bus by using Latch IC 8288. DEN : The
data bus enable pin is used to enable the transreceiver IC 8286 which controls the bidirectional
data bus in the system. DT/R : Data transmit/receive signal output to control direction of the
bidirectional data bus buffers available in IC 8286.
AEN’: If logic 0 is applied to this pin (address enable) then all the control signals gets enabled.
CEN : If logic 1 is applied on this pin (control enable) then all the command signals gets
enabled along with control signals with AEN = 0 .
IOB : The I/O bus mode input selects either I/O bus mode or system bus mode operation. If
IOB = 1 then I/O bus mode is selected that enables the I/O bus transceivers (MCE/PDEN =0).
If IOB = 0 then system bus mode is selected, that enable cascade operation for IC 8259
(peripheral Interface controller) .