Microprocessor - I/O Interfacing Overview

Interface is the path for communication between two components. Interfacing is of two types,
memory interfacing and I/O interfacing.

Memory Interfacing
When we are executing any instruction, we need the microprocessor to access the memory for
reading instruction codes and the data stored in the memory. For this, both the memory and the
microprocessor require some signals to read from and write to registers.
The interfacing process includes some key factors to match with the memory requirements and
microprocessor signals. The interfacing circuit therefore should be designed in such a way that it
matches the memory signal requirements with the signals of the microprocessor.

IO Interfacing
There are various communication devices like the keyboard, mouse, printer, etc. So, we need to
interface the keyboard and other devices with the microprocessor by using latches and buffers.
This type of interfacing is known as I/O interfacing.

Block Diagram of Memory and I/O Interfacing

8085 Interfacing Pins
Following is the list of 8085 pins used for interfacing with other devices −
● A15 - A8 (Higher Address Bus)
● AD7 - AD0(Lower Address/Data Bus)
● ALE
● RD
● WR
● READY
Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.
Control and status signals
These signals are used to identify the nature of the operation. There are 3 control signals.
Three control signals are RD, WR & ALE.
RD − This signal indicates that the selected IO or memory device is to be read and is ready for
accepting data available on the data bus.
WR − This signal indicates that the data on the data bus is to be written into a selected memory or
IO location.
ALE (Address Latch Enable) − It is a positive going pulse generated when a new operation is
started by the microprocessor. When the pulse goes high, it indicates the address. When the pulse
goes down it indicates data.
READY − This signal indicates that the device is ready to send or receive data. If READY is low,
then the CPU has to wait for READY to go high.

Ways of Communication − Microprocessor with the Outside World?

There are two ways of communication in which the microprocessor can connect with the outside
world.
● Serial Communication Interface
● Parallel Communication interface
Serial Communication Interface − In this type of communication, the interface gets a single byte
of data from the microprocessor and sends it bit by bit to the other system serially and vice-versa.
Parallel Communication Interface − In this type of communication, the interface gets a byte of
data from the microprocessor and sends it bit by bit to the other systems in a simultaneous (or)
parallel fashion and vice-versa.
8279 programmable keyboard/display controller is designed by Intel that interfaces a keyboard
with the CPU. The keyboard first scans the keyboard and identifies if any key has been pressed. It
then sends the relative response of the pressed key to the CPU and vice-versa.

How Many Ways the Keyboard is Interfaced with the CPU?

The Keyboard can be interfaced either in the interrupt or the polled mode. In the Interrupt mode,
the processor requests service only if any key is pressed, otherwise the CPU will continue with its
main task.
In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether any key
is pressed or not with key pressure.

How Does 8279 Keyboard Work?

The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using the key
codes. These key codes are de-bounced and stored in an 8-byte FIFO RAM, which the CPU can
access. If more than 8 characters are entered in the FIFO, then it means more than eight keys are
pressed at a time. This is when the overrun status is set.
If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode else the CPU
checks the status in polling to read the entry. Once the CPU reads a key entry, then FIFO is updated,
and the key entry is pushed out of the FIFO to generate space for new entries.

Architecture and Description

I/O Control and Data Buffer
This unit controls the flow of data through the microprocessor. It is enabled only when CS is low.
Its data buffer interfaces the external bus of the system with the internal bus of the microprocessor.
The pins A0, RD, and WR are used for command, status or data read/write operations.

Control and Timing Register and Timing and Control

This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the operation of the
circuit.

Scan Counter
It has two modes i.e., Encoded mode and Decoded mode. In the encoded mode, the counter
provides the binary count that is to be externally decoded to provide the scan lines for the keyboard
and display.
In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides
a decoded 1 out of 4 scans on SL0-SL3.

Return Buffers, Keyboard Debounce, and Control

This unit first scans the key closure row-wise, if found then the keyboard debounce unit debounces
the key entry. In case, the same key is detected, then the code of that key is directly transferred to
the sensor RAM along with the SHIFT & CONTROL key status.

FIFO/Sensor RAM and Status Logic

This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed key is
entered into the RAM as per their sequence. The status logic generates an interrupt request after
each FIFO read operation till the FIFO gets empty.
In the scanned sensor matrix mode, this unit acts as sensor RAM where every row is loaded with
the status of their corresponding row of sensors into the matrix. When the sensor changes its state,
the IRQ line changes to high and interrupts the CPU.

Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word currently
read/written by the CPU to/from the display RAM.

8279 − Pin Description

The following figure shows the pin diagram of 8279 −
Data Bus Lines, DB0 - DB7
These are 8 bidirectional data bus lines used to transfer the data to/from the CPU.
CLK
The clock input is used to generate internal timings required by the microprocessor.
RESET
As the name suggests this pin is used to reset the microprocessor.
CS Chip Select
When this pin is set to low, it allows read/write operations, else this pin should be set to high.
A0
This pin indicates the transfer of command/status information. When it is low, it indicates the
transfer of data.
RD, WR
This Read/Write pin enables the data buffer to send/receive data over the data bus.
IRQ
This interrupt output line goes high when there is data in the FIFO sensor RAM. The interrupt line
goes low with each FIFO RAM read operation. However, if the FIFO RAM further contains any
key-code entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU.
Vss, Vcc
These are the ground and power supply lines of the microprocessor.
SL0 − SL3
These are the scan lines used to scan the keyboard matrix and display the digits. These lines can
be programmed as encoded or decoded, using the mode control register.
RL0 − RL7
These are the Return Lines that are connected to one terminal of keys, while the other terminal of
the keys is connected to the decoded scan lines. These lines are set to 0 when any key is pressed.
SHIFT
The Shift input line status is stored along with every key code in FIFO in the scanned keyboard
mode. Till it is pulled low with a key closure, it is pulled up internally to keep it high
CNTL/STB - CONTROL/STROBED I/P Mode
In the keyboard mode, this line is used as a control input and stored in FIFO on a key closure. The
line is a strobe line that enters the data into FIFO RAM, in the strobed input mode. It has an internal
pull up. The line is pulled down with a key closure.
BD
It stands for blank display. It is used to blank the display during digit switching.
OUTA0 – OUTA3 and OUTB0 – OUTB3
These are the output ports for two 16x4 or one 16x8 internal display refresh registers. The data
from these lines is synchronized with the scan lines to scan the display and the keyboard.

Operational Modes of 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.
Input Mode
This mode deals with the input given by the keyboard and this mode is further classified into 3
modes.
● Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using either
encoded or decoded scans. In the encoded scan, an 8×8 keyboard or in the decoded scan, a
4×8 keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL
status is stored into the FIFO RAM.
● Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the processor
using either encoder or decoder scans. In the encoder scan, 8×8 sensor matrix or with
decoder scan 4×8 sensor matrix can be interfaced.
● Strobed Input − In this mode, when the control line is set to 0, the data on the return lines
is stored in the FIFO byte by byte.
Output Mode
This mode deals with display-related operations. This mode is further classified into two output
modes.
● Display Scan − This mode allows 8/16-character multiplexed displays to be organized as
dual 4-bit/single 8-bit display units.
● Display Entry − This mode allows the data to be entered for display either from the right
side/left side

Difference between Memory Mapped I/O and I/O Mapped I/O with
reference to 8085 microprocessors
The microprocessor cannot do anything by itself therefore, it needs to be linked with memory,
extra peripherals, or IO devices. This linking is called Interfacing.
The interfacing of the I/O devices in 8085 can be done in two ways:
1. Memory-Mapped I/O Interfacing:
In this kind of interfacing, we assign a memory address that can be used in the same manner as we
use a normal memory location.
2. I/O Mapped I/O Interfacing:
A kind of interfacing in which we assign an 8-bit address value to the input/output devices which
can be accessed using IN and OUT instruction is called I/O Mapped I/O Interfacing.

ROM stands for Read Only Memory. The memory from which we can only read but cannot
write on it. This type of memory is non-volatile. The information is stored permanently in such
memories during manufacture. A ROM stores such instructions that are required to start a
computer. This operation is referred to as bootstrap. ROM chips are not only used in the computer
but also in other electronic items like washing machine and microwave oven.
ROM
Let us now discuss the various types of ROMs and their characteristics.
MROM (Masked ROM)
The very first ROMs were hard-wired devices that contained a pre-programmed set of data or
instructions. These kind of ROMs are known as masked ROMs, which are inexpensive.
PROM (Programmable Read Only Memory)
PROM is read-only memory that can be modified only once by a user. The user buys a blank
PROM and enters the desired contents using a PROM program. Inside the PROM chip, there are
small fuses which are burnt open during programming. It can be programmed only once and is not
erasable.
EPROM (Erasable and Programmable Read Only Memory)
EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40 minutes.
Usually, an EPROM eraser achieves this function. During programming, an electrical charge is
trapped in an insulated gate region. The charge is retained for more than 10 years because the
charge has no leakage path. For erasing this charge, ultra-violet light is passed through a quartz
crystal window (lid). This exposure to ultra-violet light dissipates the charge. During normal use,
the quartz lid is sealed with a sticker.
EEPROM (Electrically Erasable and Programmable Read Only Memory)
EEPROM is programmed and erased electrically. It can be erased and reprogrammed about ten
thousand times. Both erasing and programming take about 4 to 10 ms (millisecond). In EEPROM,
any location can be selectively erased and programmed. EEPROMs can be erased one byte at a
time, rather than erasing the entire chip. Hence, the process of reprogramming is flexible but slow.
Advantages of ROM
The advantages of ROM are as follows −
● Non-volatile in nature
● Cannot be accidentally changed
● Cheaper than RAMs
● Easy to test
● More reliable than RAMs
● Static and do not require refreshing
● Contents are always known and can be verified

8284 Clock Generator

8284 clock generator is an IC developed by Intel to provide clock frequency, ready and reset signal
to the 8086/8088 microprocessor. It is an 18-pin chip.
8284 produces the clock signal, synchronizes it with the ready and reset signal and provides it to
the microprocessor.
Functions of 8284
● It provides a stable clock to the processor.
● Operates on a single +5V supply.
● In the case of a multiprocessor system, it facilitates synchronization of multiple clock
signals.
● Provides resetting to the processor along with the clock signal. (Generates system reset
output)
● Available 18-pin package
● Provides synchronization local ready and microprocessor ready.
The figure below shows the block diagram of 8284 Clock Generator

As we can see that the 8284 is composed of 3 sections, reset section, clock section and ready
section.

OSC, CLOCK and PCLK are the three outputs generated by the clock section. The crystal
oscillator present in this section generates a square wave signal as its output when the crystal is
attached between its two inputs X1 and X2.
The frequency of the generated square wave signal is equal to the frequency of the crystal.
Further, the square wave signal is fed to AND gate and NOT gate (inverted buffer) simultaneously.
This inverted buffer gives the OSC signal.
F/C’ is frequency/crystal selection pin used to select the input of the oscillator.
When its input is high then the operating frequency is determined by the external frequency input
(EFI), while in the other case it is determined by the crystal oscillator.
Through AND gate, the output of the oscillator is fed to the divided by 3 counters when F/C’ is
low. While when F/C’ is high, EFI is fed to the counter. Timing signals for ready and reset pins
are produced by the counter.
For the operation with EFI input, synchronization between multiple processor system is necessary,
for which CSYNC is used. Whereas when the crystal oscillator decides the operating frequency
then, in that case, this signal is subjected to ground.
CSYNC allows synchronization among multiple 8284s. In the case of single 8284, this pin is
grounded.
It is to be noted that the generated output clock frequency in both cases will be one-third of the
applied input frequency.
The clock signal for peripheral devices is generated by dividing the clock frequency by 2.
Basically, the devices like 8254 timers require PCLK as they need lower operating frequency.
The reset section of 8284 is composed of a Schmitt trigger and a D flip-flop. On each negative
edge of the clock signal, the circuit applies a reset signal to the processor.
Initially when the power is first applied then the RC circuit gives logic 0 as input to the RES pin
as shown in the figure below. But soon the capacitor gets charged to +5 V through the resistor.
Also, the operator can anytime reset the processor by making use of the push button.
The ready signals for the processor are produced by the ready section. This gives information
regarding whether the processor is ready for operation or not. If the ready signal is low, then this
shows the wait state of the processor.
The figure below represents the interfacing of 8284 clock generator with 8086 microprocessors:
Pin Description of 8284

CSYNC – pin number 1 – Stands for clock synchronization. It is an active high signal that
synchronizes the clock signal of various 8284 chips present in a single system. As this pin shows
the significance of EFI based operation, thus it is grounded when the crystal is present between
the inputs X1 and X2.
PCLK– pin number 2 – Stands for peripheral clock. An active high signal at this pin provides
clock signal of one-sixth frequency of the EFI or crystal frequency to the peripheral devices like
8254.
AEN1’ and AEN2’ – pin number 3 and 7 – Stands for address enable and are active low pins. It
qualifies the bus ready signals i.e., RDY1 and RDY 2.
RDY1 and RDY 2 – pin number 4 and 6 – These are active high pins and these signals are provided
by devices present on the data bus showing the availability or reception of the data.
READY – pin number 5 – This pin holds the READY signal of 8086 microprocessor.
CLK – pin number 8 – Stands for clock. The signal frequency at this pin will be one-third to the
EFI/crystal frequency having a duty cycle of 33%. It is connected to the clock input of the
processor.
RESET – Pin number 10 – This pin provides the reset signal to the processor and peripheral
devices, it is an active-high pin.
RES’ – Pin number 11 – It is an active low pin that produces a reset signal for 8284. The pin is
connected to the RC network for providing power on reset.
OSC – pin number 12 – It is the output signal of the oscillator with a frequency equal to the applied
EFI or crystal frequency.
F/C’ – pin number 13 – This pin is used to select whether the input used is EFI or crystal for clock
generation. For EFI input the pin is connected to VCC i.e., logic high, while for crystal input, the
pin is connected to GND.
EFI – pin number 14 – Stands for external frequency input. This pin provides external input
frequency to 8284 when F/C’ is high. The external signal provided at this pin must have frequency
thrice that of required clock frequency.
ASYNC’ – pin number 15 – This pin gives the information regarding the synchronization provided
to the inputs. It is an active low pin then two-stage synchronization is provided, otherwise for
active high signal, single-stage synchronization is provided.
X1, X2 – pin number 16 and 17 – These two are the input pins of 8284 and is required while
connecting quartz crystal. When EFI is provided then X1 is connected with VCC or GND.
VCC – pin number 18 – The supply input of +5 V is provided at this pin.
GND – pin number 9 – This pin is used for the ground connection.
A noteworthy point over here is that, whether the input signal frequency to be given is EFI or
crystal, the applied frequency must be three times the required clock frequency at the output.