UNIT II

PERIPHERAL INTERFACING
8086
Microprocessor Memory organization in 8086

Memory IC’s : Byte oriented

8086 : 16-bit

Word : Stored by two

consecutive memory locations;
for LSB and MSB

Address of word : Address of

LSB

Bank 0 : A0 = 0 
Even addressed memory
bank

Bank 1 : 𝑩𝑯𝑬 = 0
 Odd addressed
memory bank

106
8086
Microprocessor Memory organization in 8086

𝑩𝑯
𝑬
Operation A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation

byte from odd bank is
transferred
1 0 D7 – D0 in first operation
byte from odd bank is
transferred 107
Memory Interfacing

• While executing a program, the microprocessor

needs to access memory frequently to read
instruction code and data stored in memory; the
interfacing circuit enables that access.
• Memory has some signal requirements to
write into and read from its registers.
• Similary, the microprocessor initiates a set of
signals when it wants to read from and write into
memory.
Memory interfacing to 8086
Memory interface
Memory is divided into two banks ODD and EVEN.
The data bus is 16-bits wide.
The IO/ M pin is replaced with M/ IO (8086).

BHE , Bus High Enable, control signal is added.

Address pin A 0 (or BLE , Bus Low Enable ) is used differently.
The 16-bit data bus presents a new problem:
The microprocessor must be able to read and write data to any 16-bit location in
addition to any 8-bit location.
The data bus and memory are divided into banks:
Memory interfacing
Memory interface

BHE and BLE are used to select one or both:

BHE BLE(A0) Function

0 0 Both banks enabled for 16-bit transfer
0 1 High bank enabled for an 8-bit transfer
1 0 Low bank enabled for an 8-bit transfer
1 1 No banks selected Bank selection can be accomplished in two ways:

Separate write decoders for each bank (which drive CS ).

A separate write signal (strobe) to each bank (which drive WE ).

Note that 8-bit read requests in this scheme are handled by the microprocessor (it
selects the bits it wants to read from the 16-bits on the bus).
Memory interfacing

Fig . Schematic diagram of a memory

Memory interfacing

Fig. Memory map

Fig. Memory chip selection

Memory interfacing with 8086
I/O INTERFACING
• The Input/Output devices such as keyboards and
displays are the communication channels to the
outside world.
• Latches and buffers are used for I/O interfacing.
They once hardwired, perform only one function
(either as input device if it is buffer and as output
device if it is a latch). Thus limiting their
capabilities.
• To improve the overall system performance the
Intel has designed various programmable I/O
devices.
• Some of the peripheral devices developed
by Intel for 8085/8086/8088 based system are:
• 8255 - Parallel Communication Interface
• 8251 - Serial Communication Interface
• 8254 - Programmable Timer
• 8279 - Keyboard / Display Controller
• 8257 - DMA Controller
• 8259 - Programmable Interrupt Controller
• The microprocessor can communicate with
external world or other systems using
two types of communication interfaces. They
are:
• Serial Communication Interface

• Parallel Communication Interface.

PARALLEL COMMUNICATION INTERFACE OR
(8255 A - Programmable Peripheral
Interface)

• It has a bi-directional 8-bit buffer which

interfaces the 8255A to the system data bus.
• It has 24 programmable I/O Pins.
• It reduces the external logic normally
needed to interface peripheral devices.
• It has two 8 bit ports: Port A, Port B, and two
4 bit ports: CUPPER and CLOWER.
• Available in 40-Pin DIP.
OPERATING MODES

• It can be operated in two basic modes:

– Bit Set/Reset Mode
– I/O Mode
• I/O mode is further divided into 3 modes:
– Simple I/O mode (Mode 0)
– Strobed I/O mode (Mode 1)
– Bidirectional Data Transfer mode (Mode 2)
Pin diagram of 8255A
• The 8255 consists of Four sections namely
• Data Bus Buffer
• Read/Write Control Logic
• Group A Control
• Group B Control
DATA BUS BUFFER

• Used to interface the internal data bus of

8255A to the system data bus of 8085.
• Using IN or OUT instructions, CPU can read
or write the data from/to the data bus buffer.
• It can also be used to transfer control words
and status information between CPU and
8255A.
Read/Write Control Logic
• This block controls the Chip Selection ( CS ),
Read ( RD ) and Write ( WR ) operations.
• It consists of A0 and A1 signals which are
generally connected to the CPU address lines
A0 and A1 respectively.
• When CS (Chip Select) signal goes LOW,
different values of A0 and A1 select one of the
I/O ports or control register
• Group A : Port A and Most Significant Bits
(MSB) of Port C (PC4 – PC7)
• Group B : Port B and Least Significant Bits
(LSB) of Port C (PC0 – PC3)
• Port A: One 8-bit data output latch/buffer and
one 8-bit input latch buffer.
• Port B: One 8-bit data input/output latch/buffer.
• Port C: One 8-bit data output latch/buffer and
one 8-bit data input buffer. This port can be
divided into two 4-bit ports and it can be used for
the control signal outputs and status signal inputs
in conjunction with ports A and B.
BSR (Bit Set/Reset) Mode

• This mode is applicable only for Port C.

• A control word with bit D7 = 0 is
recognized as BSR control word.
• This control word can set or reset a single bit
in the Port C.
The I/O mode is divided into three modes
Mode 0, Mode 1 and Mode 2 as given below.
• Mode 0 – Basic I/O Mode
• Mode 1 – Strobed I/O Mode
• Mode 2 – Bi-directional data transfer
mode
Mode 0 – Basic I/O mode

• The features of Mode 0 are :

• Two 8-bit ports (Port A, Port B) and two 4-bit
ports (Port CU, Port CL). Any port can be input
or output.
• Outputs are latched.
• Inputs are not latched.
Mode 1 - Strobed Input/Output

• In this mode, handshake signals are exchanged between

the and peripherals prior to data transfer
The features of mode 1 are :
• Two Groups (Group A and Group B).
• Each group contains one 8-bit data port and one
4-bit control/data port. The 8-bit data port can be either
input or output
• The 4-bit port is used for control and status of the 8-bit
data port.
• If Port A is in mode 1 (input), then PC3, PC4, PC5 are
used as control signals. If Port B is in mode 1 (input), then
PC0, PC1, PC2 are used as control signals.
• Both inputs and outputs are latched.
• STB (Strobe Input) – A “low” signal on this
pin indicates that the peripheral device has
transmitted a byte of data.
• The 8255A in response to STB , generates
IBF and INTR.
• IBF (Input Buffer Full) – A “high” signal
issued by 8255A is an acknowledge to
indicate that the input latch has received
the data byte. This is reset when the CPU
reads the data.
• INTR (Interrupt Request) – This is an output
signal, used to interrupt the CPU. This will be
in active state when STB , IBF and INTE
(internal Flip-Flop) are all at logic 1. This will
be reset by the falling edge of RD signal.
• INTE (Interrupt Enable) – This is an Internal
Flip-Flop used to enable or disable
the generation of INTR signal. There are
two Flip- Flops INTEA and INTEB are
set/reset using the BSR mode.
Mode 2 – Bi-directional Data
Transfer Mode
• This mode provides a means for communicating
with a peripheral device or structure on a single 8-
bit bus for both transmitting and receiving data
(bidirectional bus I/O).
• The features of Mode 2 are :
• Used in Group A only.
• Port A only acts as bi-directional bus port
• Port C (PC3-PC7) is used for
handshaking purpose.
INTR (Interrupt Request):
• A high on this output can be used to interrupt
the CPU for input or output operations.
OBF(Output Buffer Full):
This signal will go LOW to indicate that the
CPU has written data out to Port A.
ACK(Acknowledge):
A LOW on this input enables the tri-state
output buffer of Port A to send out the
data.
• Otherwise, the output buffer will be in the high
impedance state.
KEYBOARD/DISPLAY CONTROLLER

• Intel 8279 is an LSI device.

• It simultaneously drives the display of a system
and interfaces a keyboard with the
microprocessor.
• The keyboard display interface scans the
keyboard to identify if any key has been pressed
and sends the code of the pressed key to the
microprocessor.
• It also transmits the data received from
microprocessor to the display device.
Features of 8279
• 8279 has 3 input modes for keyboard interface
– Scanned keyboard mode
– Scanned sensor matrix mode
– Strobed input mode
• 8279 has 2 output modes for display interface
– Left entry
– Right entry
• It has two key depression modes
– 2 key lockout mode
– N key rollover mode
PIN DIAGRAM
Data Bus (D7 – D0) :
• All data and commands between the
microprocessor and 8279 are transmitted on these
lines.
RD (Read) :
Microprocessor reads the data/status from 8279.
WR (Write) :
Microprocessor writes the data to 8279.
A0 :
• A HIGH signal on this line indicates that the word
is a command or status. A LOW signal indicates
the data.
RESET :
• High signal in this pin resets the 8279. After
being reset, the 8279 is placed in the following
modes
• 16 x 8-bit character display –left entry
• Two key lock out
CS (Chip Select) :
A LOW signal on this input pin enables
the communication between 8279 and the
microprocessor.
IRQ (Interrupt Request) :
• The interrupt line goes low with each
FIFO/sensor RAM reads and returns high if
there is still information in the RAM.
SL0 – SL3 :
• Scan lines which are used to scan the key
switch or sensor matrix and the display
digits.
• These lines can be either encoded (1 of 16) or
decoded (1 of 4).
RL0 – RL7 :
• Input return lines which are connected to the
scan lines through the keys or sensor switches.
• They have active internal pull-ups to keep
them high until a switch closure pull one low.
These also serve as an 8-bit input in the
strobed input mode.
SHIFT :
• It has an active internal pullup to keep it high
until a switch closure pulls it low.
CNTL/STB :
• For keyboard mode, this line is used as a control
input and stored like status on a key closure.
• The line is also the strobed line to enter the data
in to the FIFO in the strobed input mode.
OUT A0 – OUT A3, OUT B0 – OUT B3 :
• These two ports are the outputs for the 16´4
display refresh registers. These two ports may
also be considered as one 8-bit port.
• The two 4-bit ports may be blanked
independently.
BD :

This output is used to blank the display during

digit switching or by a display blanking
command.
Block Diagram of 8279
• The 8279 has the following four sections.
• CPU Interface Section
• Keyboard Section
• Scan Section
• Display Section
CPU Interface Section
• This section has bi-directional data buffer
(DB0 – DB7), I/O control lines ( RD , WR , CS ,
A0) and Interrupt Request line (IRQ).
• The A0 signal determines
whether transmit/receive control word or data
is used.
• An active high in the IRQ line is generated to
interrupt the microprocessor whenever the data
is available.
Keyboard Section
• This section has keyboard debounce and
control, 8x8 FIFO/Sensor RAM, 8 Return lines
(RL0 – RL7) and CNTL/STB and shift lines.
• In the keyboard debounce and control unit,
keys are automatically debounced and
the keyboard can be operated in two modes.
• Two key lock out
• N – key roll over
• In the two key lock out mode, if two keys are
pressed simultaneously, the first key only
recognized.
• In the N-key roll over mode, it stores the codes of
simultaneous keys pressed in the internal buffer, it
can also be setup so that no key is recognized
until only one key remains pressed.
• The 8´8 FIFO/Sensor RAM consists of 8 registers
that are used to store eight keyboard entries.
• The return lines (RL0 – RL7) are connected to
eight columns of keyboard.
• The status of shift and CNTL/STB lines are stored
along with the key closure.
Scan Section
• This section has scan counter and four
scan lines (SL0–SL3).
• These lines are decoded by 4 to16 decoder to
generate 16 scan lines.
• Generally SL0 – SL3 are connected with
the rows of a matrix keyboard.
Display Section
• This section has two groups of output lines A0
– A3 and B0–B3.
• These lines are used to send data to
display drivers.
• BD line is used blank the display.
• It also has 16 x 8 display RAM.
8254 - Timer/Counter
• It is designed to solve the common timing
control problems in microcomputer
system design.
• Compatible with all Intel and most other
microprocessors.
• It can be operated at count rates upto 10 MHz
• Six programmable counter modes and all
modes are software programmable.
• Three independent 16-bit counters
Applications of 8254

• Real time clock

• Event-counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
PIN DIAGRAM
BLOCK DIAGRAM
Data Bus Buffer
• This 3-state, bi-directional, 8-bit buffer is used
to interface the 8254 to the system bus.
Read/Write Logic
• The Read/Write logic accepts inputs from the
system bus and generates control signals for
the other functional blocks of the 8254.
• A1 and A0 select one of the three counters or
the control word register to be read
from/written into.
Control Word Register
• The control word register is selected by the
Read/Write logic when A1, A0=11.
• If the CPU then does a write operation to the
8254, the data is stored in the control word
register and is interpreted as a control word
used to define the operation of the counters.
• The control word register can only be written
to; status information is available with the
Read-Back command.
Counter 0, Counter 1, Counter 2
• Each is a 16 bit down counter
• The counters are fully independent. Each
counter may operate in a different mode.
• Each counter has a separate clock input, count
enable (gate) input lines and output line.
• The control word register is not a part of the
counter itself, but its contents determine how
the counter operates.
OPERATING MODES

• Mode 0: Interrupt On Terminal Count

• Mode 1: Hardware Retriggerable One-Shot
• Mode 2: Rate Generator
• Mode 3: Square Wave Mode
• Mode 4: Software Triggered Strobe
• Mode 5: Hardware Triggered Strobe
Mode 0: Interrupt On Terminal Count
• Mode 0 is typically used for event counting.
• After the control word is written, OUT is initially low, and will
remain low until the counter reaches zero. OUT then goes high and
remains high until a new count or a new Mode 0 control word is written into
the counter.
• GATE = 1 enables counting;

• GATE = 0 disables counting. GATE has no effect on OUT

Mode 1: Hardware Re-triggerable
One-Shot
• OUT will be initially high. OUT will go low on
the CLK pulse following a trigger to begin the
one-shot pulse, and will remain low until the
counter reaches zero.
• OUT will then go high and remain high until the
CLK pulse after the next trigger. Thus generating
a one-shot pulse.
• After writing the control word and initial
count, the counter is armed.
• A trigger results in loading the counter and
setting OUT low on the next CLK pulse, thus
starting the one-shot pulse. An initial count of N
will result in a one-shot pulse ‘N’ CLK cycles in
Mode 2: Rate Generator
• This mode functions like a divide-by-N counter.
• It is typically used to generate a real time clock
interrupt.
• OUT will initially be high. When the initial count
has decremented to 1, OUT goes low for one CLK
pulse. OUT then goes high again, the counter
reloads the initial count and the process is
repeated.
• Mode 2 is periodic; the same sequence is repeated
indefinitely.
• For an initial count of N, the sequence repeats
every N CLK cycles.
Mode 3: Square Wave Mode
• Mode 3 is typically for baud rate
used generation.
• Mode 3 is similar to Mode 2 except for the
duty cycle of OUT. OUT will initially be high.
When half the initial count has expired, OUT
goes low for the remainder of the count.
• Mode 3 is periodic; the sequence above is
repeated indefinitely. An initial count of N
results in a square wave with a period of N
CLK cycles.
METHODS TO IMPLEMENT
MODE 3
Even counts:
• OUT is initially high. The initial count is loaded
on one CLK pulse and then is decremented by
two on succeeding CLK pulses. When the count
expires OUT changes value and the counter is
reloaded with the initial count. The above process
is repeated indefinitely.
Odd counts:
• For odd counts, OUT will be high for (N +1)/2
counts and low for (N - 1)/2 counts.
Mode 4: Software Triggered Strobe

• The output goes high on setting the mode.

After terminal count, the output goes low
for one clock period and then goes high
again.

• In this mode the OUT is initially high; it goes

low for one clock period at the end of the
count. The count must be reloaded for
subsequent outputs.
Mode 5: Hardware Triggered Strobe
• This mode is similar to mode 4, but a trigger at
the gate initiates the counting.
• This mode is similar to mode 4, except that it
is triggered by the rising pulse at the gate.
• Initially the OUT is high and when the gate
pulse is triggered from low to high, the
count begins, at the end of the count, the
OUT goes low for one clock period.
Programming the 8254

Write Operations
• For each counter, the control word must be
written before the initial count is written.
• The initial count must follow the count format
specified in the control word (least
significant byte only, most significant byte
only, or least significant byte and then
most significant byte).
Read Operations
• It is often desirable to read the value of a
counter without disturbing the count
in progress. This is easily done in the 8254.

• There are three possible methods for

reading the counters:
• Simple read operation,
• Counter latch command, and
• Read-Back command.
CONTROL WORD FORMAT OF 8254
Interrupt structure of 8086

8086 Interrupt response

Interrupt structure of 8086

Interrupt is the method of creating a temporary halt during program execution and
allows peripheral devices to access the microprocessor. The microprocessor responds to
that interrupt with an ISR (Interrupt Service Routine), which is a short program to
instruct the microprocessor on how to handle the interrupt.
The are two types of interrupts in a 8086 microprocessor.
They are hardware interrupts and software interrupts.

NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR)and it is of type 2 interrupt.

When this interrupt is activated, these following actions take place

• Completes the current instruction that is in progress.
• Pushes the Flag register values on to the stack.

• Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.
• IP is loaded from the contents of the word location 00008H.
• CS is loaded from the contents of the next word location 0000AH.
• Interrupt flag and trap flag are reset to 0.
Interrupt structure of 8086

INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled
using clear interrupt Flag instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is
disabled, then the microprocessor first completes the current execution and sends ‘0’
on INTA pin twice. The first ‘0’ means INTA informs the external device to get ready
and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the
programmable interrupt controller.

These actions are taken by the microprocessor

• First completes the current instruction.

• Activates INTA output and receives the interrupt type, say X.
• Flag register value, CS value of the return address and IP value of the return address
are pushed on to the stack.
• IP value is loaded from the contents of word location X ×
4 CS is loaded from the contents of the next word location.
Interrupt flag and trap flag is reset to 0
Software Interrupts
Some instructions are inserted at the desired position into the program to create
interrupts. These interrupt instructions can be used to test the working of various
interrupt handlers.
It includes
INT- Interrupt instruction with type number like int 06
It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.

Its execution includes the following steps

• Flag register value is pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed on to the
stack.

• IP is loaded from the contents of the word location ‘type number’ × 4

• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0
Interrupt types of 8086
Interrupts of 8086
The starting address for type0 interrupt is 00000H, for type1 interrupt is 00004H
similarly for type2 is 00008H and ……so on. The first five pointers are dedicated
interrupt pointers. i.e.

• TYPE 0 interrupt represents division by zero situation.

• TYPE 1 interrupt represents single-step execution during the debugging of a

program.

• TYPE 2 interrupt represents non-maskable NMI interrupt.

• TYPE 3 interrupt represents break-point interrupt.

• TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced
microprocessors, and interrupts from 32 to Type 255 are available for hardware
and software interrupts.
Interrupts of 8086

INT 3-Break Point Interrupt Instruction

It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the
program so that when the processor reaches there, then it stops the normal execution of
program and follows the break-point procedure.

Its execution includes the following steps

• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the
stack.
• IP is loaded from the contents of the word location 3×4 = 0000CH
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0

INTO - Interrupt on overflow instruction

It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH.
As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the
overflow flag is set to 1 and branches to the interrupt handler whose interrupt type
number is 4. If the overflow flag is reset then, the execution continues to the next
instruction.
Interrupts of 8086
Its execution includes the following steps

• Flag register values are pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed
on to the stack.

• IP is loaded from the contents of word location 4×4 = 00010H

• CS is loaded from the contents of the next word location.

• Interrupt flag and Trap flag are reset to 0

8259 interrupt control
8259 interrupt controller
8259 interrupt controller
8259 interrupt controller

The Block Diagram consists of 8 blocks which are – Data Bus Buffer,
Read/Write Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver
and 3 registers- ISR, IRR, IMR.

Data bus buffer

This Block is used as a mediator between 8259 and 8086 microprocessor by
acting as a buffer. It takes the control word from the 8086 microprocessor
and transfer it to the control logic of 8259 microprocessor. Also, after
selection of Interrupt by 8259 microprocessor, it transfer the opcode of the
selected Interrupt and address of the Interrupt service sub routine to the
connected microprocessor. The data bus buffer consists of 8 bits represented
as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits data
can be transferred at a time.

Read/Write logic
This block works only when the value of pin CS is low (as this pin is active
low). This block is responsible for the flow of data depending upon the inputs
of RD and WR. These two pins are active low pins used for read and write
operations.
8259 interrupt controller
Control logic : It is the centre of the microprocessor and controls the functioning of every
block. It has pin INTR which is connected with other microprocessor for taking interrupt
request and pin INT for giving the output. If 8259 is enabled, and the other microprocessor
Interrupt flag is high then this causes the value of the output INT pin high and in this way
8259 responds to the request made by other microprocessor.

Interrupt request register (IRR) : It stores all the interrupt level which are requesting for
Interrupt services.

Interrupt service register (ISR) : It stores the interrupt level which are currently being
executed.

Interrupt mask register (IMR) : It stores the interrupt level which have to be masked by
storing the masking bits of the interrupt level.
8259 interrupt controller
Priority resolver :
It examines all the three registers and set the priority of interrupts and
according to the priority of the interrupts, interrupt with highest priority is set
in ISR register. Also, it reset the interrupt level which is already been serviced in
IRR.
Cascade buffer :
To increase the Interrupt handling capability, cascading is done for more
number of pins by using cascade buffer. So, during increment of interrupt
capability, CSA lines are used to control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master
mode else in slave mode. In Non Buffered mode, SP/EN pin is used to specify
whether 8259 work as master or slave and in Buffered mode, SP/EN pin is used
as an output to enable data bus.
8259 Interrupt Controller

Features of 8259 PIC microprocessor –

Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.

It can be programmed either in level triggered or in edge triggered interrupt level.

We can masked individual bits of interrupt request register.

We can increase interrupt handling capability upto 64 interrupt level by cascading

further 8259 PIC.

Clock cycle is not required.

8259 interrupt controller
Control words of 8259
Command word of 8259 is divided into two parts :
Initialization command words(ICW)
Operating command words(OCW)

Initialization command words(ICW) :

ICW is given during the initialization of 8259
ICW1 and ICW2 commands are compulsory for initialization.
ICW3 command is given during a cascaded configuration.
If ICW4 is needed, then it is specified in ICW1.
The sequence order of giving ICW commands is fixed i.e. ICW1 is given first and then
ICW2 and then ICW3.
Any of the ICW commands can not be repeated, but the entire initialization process can
be repeated if required.

Operating command words(OCW) :

OCW is given during the operation of 8259 i.e. microprocessor starts using 8259.
OCW commands are not compulsory for 8259.
The sequence order of giving OCW commands is not fixed.
The OCW commands can be repeated.
8259 interrupt controller
8259 interrupt controller

When the ICW1 is loaded, then the initializations performed are:

The edge sense circuit is reset because, by default, 8259 interrupt is edge triggered.
The interrupt mask register is cleared.
IR7 is assigned to priority 7.
Slave mode address is assigned as 7.
When D0 = 0, this means IC4 command is not required. Therefore, functions used in
IC4
are reset.
Special mask mode is reset and status read is assigned to IRR.

ICW2 command :
The control word is recognized as ICW2 when A0= 1.
It stores the information regarding the interrupt vector address.
In the 8085 based system, the A15 to A8 bits of control word is used for interrupt vector
addresses.
In the 8086 based system, T6 to T3 bits are inserted instead of A15 to A8 and A10 to A8 are
used for selecting interrupt level, i.e. 000 for IR0 and 111 for IR7.
8259 Operational command word
Operational command word 1

It is used to set and reset the mask bits in IMR(interrupt mask register). M7 –
M0 describes 8 mask bits
Serial communication
Serial communication is a communication method that uses one or two transmission lines
to send and receive data, and that data is continuously sent and received one bit at a time.
Since it allows for connections with few signal wires, one of its merits is its ability to hold
down on wiring material and relaying equipment costs.

Serial communication standards

RS-232C/RS-422A/RS-485 are EIA (Electronic Industries Association) communication
standards. Of these communication standards, RS-232C has been widely adopted in a
variety of applications, and it is even standard equipment on computers and is often used
to connect modems and mice. Sensors and actuators also contain these interfaces, many
of which can be controlled via serial communication.
Serial communication
Single-ended signaling is the simplest and most commonly used method of
transmitting electrical signals over wires.

One wire carries a varying voltage that represents the signal, while the
other wire is
connected to a reference voltage, usually ground.

Differential signaling is a method for electrically transmitting information

using two
complementary signals.
The technique sends the same electrical signal as a differential pair of
signals, each in
its own conductor.
The pair of conductors can be wires in a twisted-pair or ribbon cable or traces on
a printed circuit board.
Serial communication
RS-232C
This serial communication standard is widely used and is often equipped on
computers as standard.It is also called "EIA-232".The purpose and timing of the signal
lines and the connectors have been defined (D-sub 25-pin or D-sub 9-pin).Currently
the standard has been revised with the addition of signal lines and is formally called
"ANSI/EIA-232-E".However, even now it is generally referred to as "RS-232C".

RS-422A
This standard fixes problems in RS-232C such as a short transmission distance and a
slow transmission speed.It is also called "EIA-422A".The purpose and timing of the
signal lines are defined, but the connectors are not.Many compatible products
primarily adopt D-sub 25-pin and D-sub 9-pin connectors.

RS-485
This standard fixes the problem of few connected devices in RS-422A.It is also called
"EIA-485".RS-485 is forward compatible standard with RS-422A.The purpose and
timing of the signal lines are defined, but the connectors are not.Many compatible
products primarily adopt D-sub 25-pin and D-sub 9-pin connectors
In RS-232C, the connectors to use and the signal assignments have been defined
and are standardized. The figure to the right describes the D-sub 9-pin signal
assignments and signal lines.

Pin No. Signal name Description

1 DCD Data Carrier Detect Carrier detect

2 RxD Received Data Received data

3 TxD Transmitted Data Transmitted data

4 DTR Data Terminal Ready Data terminal ready

Signal ground
5 SG Signal Ground
or common
return
6 DSR Data Set Ready Data set ready

7 RTS Request To Send Request to send

8 CTS Clear To Send Clear to send

9 RI Ring Indicator Ring indicator

Maintenance ground
CASE FG Frame Ground
or earth
RS 232 Connection method

In RS-232C, the connectors and signal assignments have been standardized, so many
standard-compliant cables are available commercially. However, equipment comes in the
following types, and depending on the equipment that will be connected, a straight
cable or a crossover cable is required.
Equipment type
DCE
Data communication equipment.This term indicates equipment that passively operates
such as modems, printers, and plotters.
DTE
Data terminal equipment.This term indicates equipment that actively operates such as
computers.

Full-duplex communication
A method where send and receive both have their own transmission line so data can
be simultaneously sent and received.
Half-duplex communication
A method where communication is performed using one transmission line while
switching between send and receive. For this reason, simultaneous communication
cannot be performed.
Crossover cable connection

Full-duplex communication A method where send and receive both have their
own transmission line so data can be simultaneously sent and received. Half-
duplex communication A method where communication is performed using one
transmission line while switching between send and receive. For this reason,
simultaneous communication cannot be performed
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COURSE: DCN UNIT: 1 Pg.