Course Code: CST202

Course Name: Computer Organization and Architecture

Previous year questions.

MODULE 1:
1. Compare auto increment and auto decrement addressing modes with examples (3)
2. Outline the steps involved in the execution of an instruction. (3)
3. Identify the addressing modes that can be used for representing the following
4 . Identify the addressing modes that can be used for representing the following

higher level language constructs in machine level. Illustrate each addressing

mode using an example.
l) Anays
2) Pointers
3) Constants
4) Variables (4)
5.Illustrate the single bus organization of processor unit with the help of suitable
diagrams. Explain, listing the control signals, how the following operations are
handled in this organization.
i) Transfer contents of register R5 to Rl
ii) Move (R6), R2 (Fetch a word from memory and move it to register R2, when
the memory address is stored in register R6 ) (l0)
6. Outline the differences in instruction execution during straight line sequencing
and branching using suitable examples. (7)
7. Differentiate between big endian and little endian byte ordering.
Consider a computer that has a byte addressable memory organized as 32 bit
words' A program reads ASCII characters entered at a key board and stores
them in successive bye locations, starting at location 1000. Show the contents
of the two memory words at locations 1000 and 1004 after the name Johnson
has been entered in case:
i) Big Endian Byte ordering is used.
ii) Little Endian Byte ordering is used
(ASCII equivalent of characters in Johnson in hex will be 44, 6F. 68& 6E.
\ 73,6F,6E. You can indicate unused bye locations using XX). (7)
8. With a neat diagram explain the internal architecture of CPU? (3)
9. Enumerate the sequence of actions (control signals) involved in executing an
unconditional branch instruction? (3)
10. What do you mean by addressing modes, r#ith proper examples explain in detail
about various address modes? (10)
11.Write down the sequence of actions needed to fetch and execute instruction:
STORE Rl,[R2] (4)
12. Draw the diagram of a multi-bus organization with 3 buses, write the control
sequence for the instruction ADD [Rl],R2,R3 for the above mentioned multi-bus
organization. (9)
13. What are condition codes, list the different condition codes? (5)
14. Name the registers which are connected to both external and internal bus?
What are the signals associated with these registers? (3)
15. Compare and contrast single bus and multi-bus organization of CPU? (4)
16. Write the three-address, two-address and one-address representations of the
operation below with relevant assumptions; evaluate following:
i, (A+B) * (C+D)
ii, c<- [A] + [B] (10)

17. With the help of a neat figure, describe the data path inside the processor?(6)
18. Draw the diagram of single bus organization, write the control sequence for the
instruction ADD [R2],R3 for the above mentioned single bus organization. (8)
19. Explain how the PC, IR, MAR and MDR registers are used during the
instruction execution cycle. (3)
20. What information is conveyed by the addressing mode used in an instruction?
List any four addressing modes. (3)
21. What do you mean by byte addressable memory? Explain the two different types
of byte assignment using diagrams (7)
22. Illustrate processor organisation using a single bus with help of a diagram.
Explain how register transfers and ALU operations are carried out in the single
bus organisation. (7)
23.Describe the following addressing modes. giving an example for each:
i) Indirect Addressing mode
ii) Immediate Addressing mode
iii) Indexed Addressing mode (7)
24. Discuss how instructions are classified based on number of operands or addresses
they use. (7)

ANSWERS
1. Compare auto increment and auto decrement addressing modes with examples (3)
 Auto Increment Addressing Mode:
o The operand address is specified by a register. After the operand is
accessed, the register is automatically incremented by the size of the
operand.
o Example: If R1 = 1000, the instruction MOV R2, [R1++] transfers the
value at memory address 1000 to R2, and then increments R1 to 1004.
 Auto Decrement Addressing Mode:
o The operand address is specified by a register. Before the operand is
accessed, the register is decremented by the size of the operand.
o Example: If R1 = 1004, the instruction MOV R2, [--R1] decrements
R1 to 1000 and then moves the value from memory address 1000 to
R2.

2. Outline the steps involved in the execution of an instruction. (3)

1. Fetch: The Program Counter (PC) holds the address of the next instruction.
This address is transferred to the Memory Address Register (MAR). The
instruction is then fetched from memory and placed in the Instruction Register
(IR).
2. Decode: The instruction in the IR is decoded by the Control Unit (CU) to
understand what operation needs to be performed (e.g., arithmetic, logical,
memory access).
3. Execute: The operation is carried out by the ALU or other processor units,
based on the decoded instruction. The results are stored in registers or
memory.
4. Write-back: If necessary, the result of the operation is written back into the
appropriate memory location or register.
3. Identify the addressing modes for representing higher-level language constructs. (4)
 Arrays:
o Indexed Addressing Mode: The address of the array element is
calculated by adding an index to a base address.
o Example: MOV R1, [R2 + R3] where R2 is the base address, and R3 is
the index.
 Pointers:
o Indirect Addressing Mode: The address of the operand is stored in a
pointer (usually a register).
o Example: MOV R1, [R2] where R2 holds the address of the operand.
 Constants:
o Immediate Addressing Mode: The operand is directly embedded
within the instruction.
o Example: MOV R1, #10 where #10 is the constant.
 Variables:
o Direct Addressing Mode: The instruction directly specifies the
memory address of the variable.
o Example: MOV R1, [1000] where 1000 is the address of the variable.

4. Illustrate the single bus organization of processor unit with diagrams and control
signals. (10)
22. Processor Organization Using Single Bus (7)

In a Single Bus Organization, there is a single shared bus for transferring

data between registers, the ALU, and memory. The components involved are:
 Registers (R1, R2, etc.)
 ALU
 Memory
 Control Unit
Control Signals:
 Register Select: Decides which register will place its value onto the bus or will
receive data from the bus.
 Memory Read/Write: Controls whether data is being read from or written to
memory.
 Bus Control: Manages data flow along the bus.
Example Operations:
 Transfer contents of R5 to R1:
1. The value of R5 is placed onto the bus.
2. R1 is selected to receive data from the bus.
 Move (R6), R2:
1. The address in R6 is used to fetch data from memory.
2. Data from memory is placed on the bus and moved to R2.
5. Differences in instruction execution during straight line sequencing and branching.
(7)
 Straight Line Sequencing:
o Instructions are executed one after the other in the sequential order.
o The PC is incremented after each instruction is fetched.
o Example: MOV R1, #5, followed by ADD R2, R1.
 Branching:
o A branch instruction causes the program to jump to a different memory
address, and the PC is updated to the branch target address.
o Example: JMP 1000 causes the program to jump to address 1000.

6. Big Endian vs. Little Endian Byte Ordering. (7)

 Big Endian: Most significant byte is stored first (at the smallest address).
o Example for "Johnson" (ASCII: 44, 6F, 68, 6E, 73, 6F, 6E):
 Memory at 1000: 44 6F 68 6E
 Memory at 1004: 73 6F 6E XX
 Little Endian: Least significant byte is stored first.
o Example for "Johnson":
 Memory at 1000: 68 6F 44 6E
 Memory at 1004: 6E 73 6F XX

7. Internal Architecture of CPU (3)

The internal architecture of a CPU generally consists of:
 Control Unit (CU): Directs the operation of the processor.
 Arithmetic and Logic Unit (ALU): Performs arithmetic and logic operations.
 Registers: Small, high-speed storage locations (e.g., Accumulator (AC),
Program Counter (PC), Instruction Register (IR)).
 Memory: Holds data and instructions.
 Buses: For data transfer between components.




8. Sequence of Actions for Unconditional Branch Instruction (3)

1. Fetch: Fetch the branch instruction from memory.
2. Decode: Decode the branch instruction and identify the target address.
3. Execute: Update the Program Counter (PC) with the target address, causing a
jump.

9. Addressing Modes (10)

 Immediate Addressing: Operand is part of the instruction.
o Example: MOV R1, #10
 Direct Addressing: Operand address is explicitly given.
o Example: MOV R1, [1000]
 Indirect Addressing: Operand address is stored in a register or memory
location.
o Example: MOV R1, [R2]
 Indexed Addressing: The operand address is calculated by adding an index to a
base address.
o Example: MOV R1, [R2 + R3]
 Register Addressing: Operand is in a register.
o Example: MOV R1, R2

10. Byte Addressable Memory and Types of Byte Assignment (7)

 Byte Addressable Memory means that each memory address points to a single
byte.
 Byte Assignment Types:
o Word Aligned: Each word begins at a memory address that is a
multiple of the word size (e.g., 4-byte words start at addresses divisible
by 4).
o Byte Aligned: Data can be stored at any byte address.
11. Sequence of Actions for Instruction: STORE R1, [R2] (4)
 Fetch the Instruction:
 The instruction STORE R1, [R2] is fetched from memory. The Program
Counter (PC) holds the address of the instruction to be fetched.
 The address in PC is transferred to the Memory Address Register (MAR), and
the instruction is read from memory.
 The instruction is placed in the Instruction Register (IR).
 Decode the Instruction:
 The control unit decodes the instruction in the IR to identify that it is a STORE
instruction.
 The instruction requires the data from R1 to be stored in the memory location
whose address is stored in R2.
 Fetch the Address from R2:
 The address of the memory location where the data needs to be stored is found
in R2.
 The value from R2 is placed onto the Memory Address Register (MAR), so
that the memory knows where the data will be written.
 Place Data from R1 onto the Bus:
 The value from R1 (the data to be stored) is placed onto the Data Bus.
 The Data Bus is used to transfer the data between the registers and memory.
 Memory Write Operation:
 The Control Unit (CU) sends a signal to Memory to perform a write operation.
This is done by activating the Memory Write control signal.
 The data from R1, which is currently on the Data Bus, is written into the
memory location specified by R2 (the address in MAR).
 Update Program Counter:
 After the instruction is executed, the Program Counter (PC) is updated to point
to the next instruction, moving on to the next step in the program.

12. Multi-Bus Organization with 3 Buses

(9)
A multi-bus system has multiple buses (e.g., Data bus, Address bus, Control
bus) for simultaneous data transfer between the registers, memory, and ALU.
 Diagram: Shows 3 buses connecting the registers, ALU, and memory.

Instruction: ADD [R1], R2, R3

This instruction performs the following:

1. Fetch the data from memory using the address in R1.

2. Transfer the data to the ALU.
3. Perform the addition operation.
4. Store the result in R3.

Step 1: Fetch Data from Memory Using the Address in R1

 The Address Bus is used to transfer the memory address.
o The value of R1 is placed onto the Address Bus, which is used to
point to the memory location from which the data is to be fetched.
 The Control Bus sends a Memory Read signal, telling memory to send the
data from the location specified by R1 to the Data Bus.
 The Data Bus now holds the data from memory, which will be transferred to
the ALU.
Step 2: Transfer Data to the ALU
 The Data Bus now carries the data fetched from memory (which was pointed
to by the value in R1).
 The Control Bus sends the necessary signals to enable the ALU to receive the
data from the Data Bus.
 The ALU now stores the fetched data (let's call this Data1).
Step 3: Perform the Addition Operation
 The Data Bus also carries the value of R2 from the register R2 to the ALU.
This is done by placing the value from R2 onto the Data Bus.
 The ALU now has two operands:
o Data1 (the data from memory, fetched in Step 1).
o R2 (the value from the register R2).
 The ALU performs the addition operation on Data1 and R2, producing the
result.
Step 4: Store the Result in R3
 The Data Bus carries the result of the addition operation to R3.
 The Control Bus sends a Register Write signal to R3, enabling R3 to store
the result of the addition.
 The result is now stored in R3, completing the execution of the ADD [R1],
R2, R3 instruction.

13. Condition Codes (5)

Condition codes are flags that store the results of an operation (such as zero,
negative, carry, etc.) to control conditional execution.
 Condition Codes:
 Zero Flag (Z):
 Set if the result of an operation is zero.
 Useful for conditional branching (e.g., jump if zero).
 Negative Flag (N):
 Set if the result is negative (in signed arithmetic).
 Used to check for negative results or conditions (e.g., jump if negative).
 Carry Flag (C):
 Set if there is a carry-out or borrow during addition or subtraction.
 Used for unsigned arithmetic and multi-word operations.
 Overflow Flag (V):
 Set if a signed arithmetic overflow occurs.
 Used for detecting overflow in signed operations.

14. Registers Connected to External and Internal Bus (3)

 Registers Connected to Both Buses: Program Counter (PC), Instruction
Register (IR), Memory Address Register (MAR), Memory Data Register
(MDR).

 Signals:
o Read/Write Control: Directs whether data is being read from or written
to memory.
o Bus Control: Determines which register or memory location will drive
or receive data from the bus.

15. Single Bus vs Multi-Bus Organization

(4)
 Single Bus Organization:
o A single bus is used for all data transfers, causing potential delays as
only one transfer can occur at a time.
o Example: Simultaneous access to multiple components is not possible.
 Multi-Bus Organization:
o Multiple buses allow for parallel data transfers, improving
performance.
o Example: Separate buses for data, address, and control lines allow
simultaneous operations.
Single Bus
Feature Multi-Bus Organization
Organization

Uses only one bus for all data Uses multiple buses (e.g., data
Number of
transfers, including address, data, and bus, address bus, control bus),
Buses
control signals. allowing parallel transfers.
Data Lower efficiency because only one Higher efficiency due to parallel
Transfer transfer can happen at a time, causing data transfer, enabling simultaneous
Efficiency potential delays. operations.
No simultaneous access to multiple Simultaneous access to different
Simultaneous
components. All components must share components (e.g., CPU, memory,
Access
the single bus. ALU) through separate buses.
Complexity Lower complexity as only one bus is Higher complexity due to the need
involved. Simple design. for multiple buses, but this
complexity leads to better
performance.
Lower performance because of Higher performance as operations
Performance bottlenecks and delays in data can happen in parallel, reducing
transfer. bottlenecks.
Lower cost due to fewer Higher cost due to more buses and
Cost
components and simpler design. complex components.
Control signals are shared across the Control signals are more specialized and
Control
bus, which can introduce delays when distributed across the multiple buses,
Signals
multiple operations are needed. improving speed and flexibility.
Separate buses for data (Data Bus),
One bus handles transferring data
Example addresses (Address Bus), and control
from registers to memory or ALU.
signals (Control Bus).
More flexible, as different
Less flexible, as it can only
Flexibility operations (e.g., memory read and ALU
perform one operation at a time.
operation) can occur simultaneously.

16. Three-address, Two-address, and One-address Representations (10)

24. Instruction Classification Based on Operands (7)

Number
Format Operand(s) Typical Use
of Addresses
Three- Two source operands and Common in high-level languages
3
Address one destination operand. and systems with powerful ISAs.
One source operand and one
Two- destination operand (usually Used in simpler instruction sets
2
Address the destination is or to save instruction length.
overwritten).
One operand (typically
One- Common in accumulator-based
1 register), result stored in the
Address systems, simpler architectures.
same operand or register.

1. Three-Address Representation
Example Expression:
(A + B) * (C + D)
 Step-by-Step Translation: We break the expression into smaller operations.
First, we calculate the sum of A + B and the sum of C + D, and then multiply
the results.
Three-Address Representation:
1. ADD R1, A, B
o Operation: Add A and B and store the result in R1.
Explanation: In this instruction, A and B are the source operands, and
o
R1 is the destination where the result is stored.
2. ADD R2, C, D
o Operation: Add C and D and store the result in R2.
o Explanation: Here, C and D are the operands, and R2 stores the result
of their sum.
3. MUL R3, R1, R2
o Operation: Multiply R1 (the result of A + B) and R2 (the result of C +
D), and store the result in R3.
o Explanation: This performs the final multiplication using the results
stored in R1 and R2, storing the result in R3.
ADD R1, A, B // R1 = A + B
ADD R2, C, D // R2 = C + D
MUL R3, R1, R2 // R3 = R1 * R2

Example Expression:
C <- [A] + [B]
 Step-by-Step Translation: We first load the value from A into a register, then
add the value from B, and store the result back in C.
Two-Address Representation:
1. MOV R1, [A]
o Operation: Load the value from memory location A into register R1.
Explanation: [A] is the memory address, and R1 is the register where
o
the value is stored.
2. ADD R1, [B]
o Operation: Add the value from memory location B to R1.
Explanation: [B] is the operand (source) added to R1. The result of
o
R1 + [B] is stored back in R1, overwriting the original value.
3. MOV C, R1
o Operation: Move the value from R1 into memory location C.
o Explanation: The final result stored in R1 is transferred back to
memory location C.
Example in two-address form:
MOV R1, [A] // R1 = A
ADD R1, [B] // R1 = R1 + B
MOV C, R1 // C = R1

3. One-Address Representation
In the one-address format, there is only one operand. The operation is usually
performed on a register, with the result being stored back into the same register or
operand. This format is generally used in machines with very limited instruction sets
or simpler architectures, where operations are often done on registers, and the
operands are implicitly defined.
Example Expression:
C <- A + B
 Step-by-Step Translation: We load the value of A into a register, then add B
to it, and store the result back into C.
One-Address Representation:
1. LOAD R1, A
o Operation: Load the value of A into register R1.
o Explanation: The operand A is loaded into R1.
2. ADD R1, B
o Operation: Add the value of B to R1, and store the result in R1.
Explanation: The addition of R1 + B is stored in R1. There is no
o
separate destination operand.
3. STORE C, R1
o Operation: Store the result from R1 into memory location C.
o Explanation: The result, now in R1, is transferred to memory location
C.

17. Data Path Inside the Processor

(6)

The data path inside the processor consists of:

1. Registers (R1, R2, etc.)
 Definition: Registers are small, fast storage locations within the processor that
temporarily hold data during computation. They store intermediate results and
are used for operands and instruction data.
 Purpose: Registers are used to hold data that the processor is currently
working on. Each register is addressed with a specific name, such as R1, R2,
etc.
 Types:
o General-purpose registers: These are used for various temporary data
storage needs.
o Special-purpose registers: These include Program Counter (PC),
Instruction Register (IR), Memory Address Register (MAR), and
Memory Data Register (MDR), which are critical for instruction
execution.
2. Arithmetic Logic Unit (ALU)
 Definition: The ALU is a critical component responsible for performing all
arithmetic (e.g., addition, subtraction) and logical (e.g., AND, OR) operations.
 Purpose: The ALU processes data according to the operations specified by
instructions. It can handle operations like:
o Arithmetic operations: Addition, subtraction, multiplication, division
(if supported).
o Logical operations: AND, OR, NOT, XOR.
3. Memory
 Definition: Memory is where data and instructions are stored. It is typically
divided into RAM (Random Access Memory) and Cache Memory.
 Purpose: The memory stores program instructions, data, and results from
operations. When a program is executed, data is fetched from memory,
processed, and then the results are stored back in memory.
 Types:
o Main memory (RAM): Stores data and instructions while the
processor is running.
o Cache memory: A smaller, faster type of memory used to hold
frequently accessed data to speed up processing.
4. Buses (Data Bus, Address Bus, Control Bus)
 Definition: Buses are a set of physical pathways used to carry data, addresses,
and control signals between components like the ALU, Registers, Memory,
and other units of the processor.
 Types:
o Data Bus: Carries the actual data between components. It connects the
ALU, registers, and memory, allowing them to exchange data.
o Address Bus: Carries memory addresses that are used by the processor
to access data in memory. It connects the MAR (Memory Address
Register) to memory.
o Control Bus: Carries control signals generated by the Control Unit
(CU) to regulate the operations of various components (e.g., signaling
when to read from or write to memory, when to activate the ALU, etc.).
5. Control Unit (CU)
 Definition: The Control Unit (CU) is responsible for coordinating all
operations within the processor. It sends control signals to all parts of the
processor to manage the execution of instructions.

18. Single Bus Organization for ADD [R2], R3 (8)

In a Single Bus Organization, all components of the processor (such as
registers, ALU, memory) are connected to a single bus. The bus is used to transfer
data between different components. In the case of the instruction ADD [R2], R3, we
are performing the following operation:
 ADD [R2], R3 means that the value from R3 is added to the value stored at
the memory location pointed to by R2.
Steps Involved in Execution:
1. The value from R3 is placed on the bus:
o Explanation: The first step is that the value stored in register R3 needs
to be placed onto the bus so it can be transferred to memory (or another
register).
o Action: The Control Unit (CU) sends the signal to the bus to place the
value from R3 onto it. This is done by first sending the value of R3 to
the bus, making it available to other components that need it.
o Result: The bus now carries the value from R3, ready to be transferred
to the location specified by R2.
2. The address of R2 is transferred to the MAR:
o Explanation: In this instruction, the R2 register contains a memory
address (the location where data is to be added). The next step is to
send the value stored in R2 to the Memory Address Register (MAR).
o Action: The value of R2 (which is the address of the memory location)
is transferred to MAR via the bus. The MAR holds the address of the
memory location where data is either read from or written to.
o Result: The MAR now holds the address of the memory location, and
the processor is ready to access memory at this address.
3. R2 is selected as the destination register to receive data from the bus:
o Explanation: Once the address is set, the processor needs to perform
the operation, which in this case is addition. The value from R3 will
be added to the value stored in memory at the address pointed to by
R2.
o Action: The Control Unit (CU) selects R2 as the destination for the
result. The value from the bus (which is from R3) is then added to the
value at the memory address pointed to by R2, and the result is stored
back in the R2 register.
4. Data Transfer to R2 (Destination Register):

The data from R3 (now on the bus) is added to the value stored at the address in
MAR (which was taken from R2).

19. PC, IR, MAR, and MDR Registers in Instruction Execution Cycle (3)
 Program Counter (PC): Holds the address of the next instruction.
 Instruction Register (IR): Holds the current instruction being executed.
 Memory Address Register (MAR): Holds the address of the data or instruction
in memory.
 Memory Data Register (MDR): Holds the data read from or written to
memory.
20. Information Conveyed by Addressing Mode (3)
 Addressing modes define how the operand of an instruction is accessed.
 Examples: Immediate, Direct, Indirect, Register, Indexed addressing modes.
 Immediate Addressing: Operand is part of the instruction.
o Example: MOV R1, #10
 Direct Addressing: Operand address is explicitly given.
o Example: MOV R1, [1000]
 Indirect Addressing: Operand address is stored in a register or memory
location.
o Example: MOV R1, [R2]
 Indexed Addressing: The operand address is calculated by adding an index to a
base address.
o Example: MOV R1, [R2 + R3]
 Register Addressing: Operand is in a register.
o Example: MOV R1, R2

21. Byte Addressable Memory and Assignment Types (7)

 Byte Addressable: Each memory location points to a single byte.
 Two Types:
1. Word Aligned: Words are aligned at memory addresses that are
multiples of the word size.
2. Byte Aligned: No such restriction for words.