BCS302 | Digital Design and Computer Organization |

Module -03
Basic Structure of Computers: Basic Operational Concepts, Bus Structures,
Performance – Processor Clock, Basic Performance Equation, Clock Rate,
Performance Measurement.
Machine Instructions and Programs: Memory Location and Addresses,
Memory Operations, Instructions and Instruction Sequencing, Addressing
Modes .
Computer Organization
It describes the function of and design of the various units of digital computer that store and
process information.

1. Basic Structure of Computers:

A Computer is an electronic system capable of performing various computational tasks at a fast
rate. A computer consists of five functionally independent main parts: input unit, memory unit,
Arithmetic logic unit(ALU), output unit and control unit.

Figure 1.1 Basic functional units of a computer

• Input device accepts the coded information as source program i,e high level language. This
is either stored in the memory or immediately used by the processor to perform the desired
operations.
• The program stored in the memory determines the processing steps.
• Basically, the computer converts source program into object program (machine language).

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• Finally, the result is sent to outside world through output device. All these actions are
coordinated by the control unit.

Q. With neat diagram , Explain the basic operational concepts of a Computer

1.1 Basic operational concepts

An Instruction consists of 2 parts,
1) Operation code (Opcode) and 2)
Operands.
OPCODE OPERANDS
The data/operands are stored in memory.
The individual instruction are brought from the memory to the processor.
Then, the processor performs the specified operation.

The activity in a computer is governed by instructions.

A typical instruction may be
ADD LOCA, R0
• Add the operand at memory location LOCA to the operand in a register R0 in the processor.
• Place the sum into register R0.
• The original contents of LOCA are preserved.
• The original contents of R0 is overwritten.
• The following are the steps to execute the instruction:

Step 1: Fetch the instruction from main-memory into the processor.

Step 2: Fetch the operand at location LOCA from main-memory into the processor.
Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the contents of register
R0.
Step 4: Store the result (sum) in R0.

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Processor components

Figure shows in detail how processor and memory are connected. Processor contains several
registers along with ALU and timing unit.
The processor contains ALU, control-circuitry and many registers.

• The processor contains „n‟ general-purpose registers R0 through Rn-1.

• The IR holds the instruction that is currently being executed.
• The control-unit generates the timing-signals that determine when a given action is to take
place.
• The PC contains the memory-address of the next-instruction to be fetched & executed.
• During the execution of an instruction, the contents of PC are updated to point to next
instruction.
• The MAR holds the address of the memory-location to be accessed.
• The MDR contains the data to be written into or read out of the addressed location.
• MAR and MDR facilitates the communication with memory. The other two registers which
facilitate communication with memory are:
1. MAR – (Memory Address Register):- It holds the address of the location to be
accessed.

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2. MDR – (Memory Data Register):- It contains the data to be written into or

read out of the address location.
Typical Operating steps are as follows:
a) Programs reside in the memory through input devices
b) PC is set to point to the first instruction
c) The contents of PC are transferred to MAR
d) A Read signal is sent to the memory
e) The first instruction is read out and loaded into MDR
f) The contents of MDR are transferred to IR
g) Decode and execute the instruction

STEPS TO EXECUTE AN INSTRUCTION

1) The address of first instruction (to be executed) gets loaded into PC.
2) The contents of PC (i.e. address) are transferred to the MAR & control-unit issues Read signal
to memory.
3) After certain amount of elapsed time, the first instruction is read out of memory and placed
into MDR.
4) Next, the contents of MDR are transferred to IR. At this point, the instruction can be decoded
&executed.
5) To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As a
result ,the operand is transferred from memory into MDR, and then it is transferred from
MDR to ALU.
6) Likewise required number of operands is fetched into processor.
7) Finally, ALU performs the desired operation.
8) If the result of this operation is to be stored in the memory, then the result is sent to the MDR.
9) The address of the location where the result is to be stored is sent to the MAR and a Write
cycle is initiated.
10) At some point during execution, contents of PC are incremented to point to next instruction
in the program.

Interrupt: Normal execution of programs may be preempted if some device requires urgent
servicing. An interrupt is a request signal from an I/O device for service by the processor. The
processor provides the requested service by executing an appropriate interrupt service routine.

1.2 Bus Structures

There are many ways to connect different parts inside a computer together.
• A bus is a group of lines that serves as a connecting path for several devices.
• A bus may be lines or wires.
• The lines carry data or address or control signal.
• There are 2 types of Bus structures:

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1) Single Bus Structure and 2) Multiple Bus Structure.

Bus control lines are used to arbitrate multiple requests for use of one bus.

1) Single Bus Structure

Because the bus can be used for only one transfer at a time, only 2 units can actively use
the bus at any given time.Bus control lines are used to arbitrate multiple requests for use
of the bus.

Advantages:

1. Low cost.
2. Very flexible for attaching peripheral devices

Figure : Single Bus structure

2) Multiple Bus Structure

Systems that contain multiple buses achieve more concurrency in operations.Two or more
transfers can be carried out at the same time.

Advantage: Better performance.

Disadvantage: Increased cost.

• The devices connected to a bus vary widely in their speed of operation.

• To synchronize their operational-speed, buffer-registers can be used.

• Buffer Registers
→ are included with the devices to hold the information during transfers.
→ prevent a high-speed processor from being locked to a slow I/O device during data transfers.
Performance – Processor Clock, Basic Performance Equation, Clock Rate,
Performance Measurement.

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1.3 Performance –
• The most important measure of a computer is how quickly it can execute programs.

• Three factors affect performance: 1. Hardware design 2. Instruction set 3. Compiler

• The total time required to execute the program is elapsed time is a measure of the
performance of the entire computer system. It is affected by the speed of the processor, the
disk and the printer.
• The time needed to execute a instruction is called the processor time.
• Processor time to execute a program depends on the hardware involved in the execution
of individual machine instructions

Figure : The processor Cache

Figure shows cache memory as part of the processor unit. The processor and a relatively small
cache memory can be fabricated on a single integrated circuit chip.
o Let us examine the flow of program instructions and data between the memory and the
processor. At the start of execution, all program instructions and the required data are stored in
the main memory. o As the execution proceeds, instructions are fetched one by one over the
bus into the processor, and a copy is placed in the cache later if the same instruction or data
item is needed a second time, it is read directly from the cache.

1.3.1 Processor Clock

• Processor circuits are controlled by a timing signal called clock The clock defines the
regular time intervals called clock cycles.
• To execute a machine instruction the processor divides the action to be performed into a
sequence of basic steps that each step can be completed in one clock cycle.
• Processor used in today‟s personal computer and work station have a clock rates that range
from a few hundred million to over a billion cycles per second.
• Let P = Length of one clock cycle R = Clock rate.
• Relation between P and R is given byR= 1
𝑃

• The term “cycles per second” is called hertz

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• The term “million” is denoted by the prefix Mega(M) and “billion” is denoted by the prefix
Giga(G)

Write the basic performance equation. explain the role of each of the parameters in the equation
on the performance of the computer.
1.3.2 Basic Performance Equation
Let T = Processor time required to executed a Program.
N = Actual number of instruction executions.
S = Average number of basic steps needed to execute one machine instruction.
R = Clock rate in cycles per second.

• The program execution time is given by T= 𝑁 𝑋 𝑆 --------- (1)

𝑅

• Equ1 is referred to as the basic performance equation.

• To achieve high performance, the computer designer must reduce the value of T, which
meansreducing N and S, and increasing R.

This is often referred to as the basic performance equation.

The value of N is reduced if source program is compiled into fewer machine instructions.
The value of S is reduced if instructions have a smaller number of basic steps to perform.
The value of R can be increased by using a higher frequency clock.
Care has to be taken while modifying values since changes in one parameter may affect the other.

1.3.3 Clock Rate

There are two possibilities for increasing the clock rate, R.
• First, improving the integrated-circuit (IC) technology makes logic circuit faster,
which reduces the time needed to complete a basic step. This allows the clock rate R to
be increased.
• Second, reducing the amount of processing done in one basic step also makes it
possible to reduce the clock period, P. However, if the actions that have to be performed
by an instruction remain the same, the number of basic steps needed may increase.

1.3.4 Performance Measurement

• The performance measure is the time taken by the computer to execute a given bench
mark. Initially some attempts were made to create artificial programs that could be used
as bench mark programs
• A non-profit organization called SPEC- system performance evaluation corporation selects
and publishes bench marks

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• The program selected range from game playing, compiler, and data base applications to
numerically intensive programs in astrophysics and quantum chemistry. In each case, the
program is compiled under test, and the running time on a real computer is measured.
• The same program is also compiled and run on one computer selected as reference.
• The „SPEC‟ rating is computed as follows.

If the SPEC rating = 50 Means that the computer under test is 50 times as fast as the ultra sparc
10.
This is repeated for all the programs in the SPEC suit, and the geometric mean of the result is
computed .
Where n is the number of programs in the suite
Geometrical mean= Is defined as the nth root of the product of n numbers

Problem 1:
List the steps needed to execute the machine instruction:

Load LOCA, R0

Solution:
1. Transfer the contents of register PC to register MAR.
2. Issue a Read command to memory. And, then wait until it has transferred the requested word
into register MDR.
3. Transfer the instruction from MDR into IR and decode it.
4. Transfer the address LOCA from IR to MAR.
5. Issue a Read command and wait until MDR is loaded.
6. Transfer contents of MDR to the ALU.
7. Transfer contents of R0 to the ALU.
8. Perform addition of the two operands in the ALU and transfer result into R0.
9. Transfer contents of PC to ALU.
10. Add 1 to operand in ALU and transfer incremented address to PC.

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Problem 2:
List the steps needed to execute the machine instruction:
Add R1, R2, R3

Solution:
1. Transfer the contents of register PC to register MAR.
2. Issue a Read command to memory. And, then wait until it has transferred the requested word
into register MDR.

3. Transfer the instruction from MDR into IR and decode it.

4. Transfer contents of R1 and R2 to the ALU.
5. Perform addition of two operands in the ALU and transfer answer into R3.
6. Transfer contents of PC to ALU.
7. Add 1 to operand in ALU and transfer incremented address to PC.

Problem 3:
(a) Give a short sequence of machine instructions for the task “Add the contents of memory-
location A to those of location B, and place the answer in location C”.

Instructions:

Load Ri,
LOC and
Store Ri, LOC

are the only instructions available to transfer data between memory and the general purpose
registers.

Is it possible to use fewer instructions of these types to accomplish the task in part (a)? If
yes, give the sequence.

Solution:

(a)
Load
A, R0
Load
B, R1
Add
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R0, R1
Store R1, C

(b) Yes;
Move
B, C
Add
A, C

Problem 4:
A program contains 1000 instructions. Out of that 25% instructions requires 4 clock cycles,40%
instructions requires 5 clock cycles and remaining require 3 clock cycles for execution. Find the
total time required to execute the program running in a 1 GHz machine.
Solution:
N = 1000

25% of N= 250 instructions require 4 clock cycles.

40% of N =400 instructions require 5 clock cycles.
35% of N=350 instructions require 3 clock cycles.

T = (N*S)/R=

=(250*4+400*5+350*3)/1X109

=(1000+2000+1050)/1*109

= 4.05 μs.

Problem 5:

For the following processor, obtain the performance.

Clock rate = 800 MHz
No. of instructions executed = 1000
Average no of steps needed / machine instruction = 20

Solution:

Problem 6:
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(a) Program execution time T is to be examined for a certain high-level language program. The
program can be run on a RISC or a CISC computer. Both computers use pipelined instruction
execution, but pipelining in the RISC machine is more effective than in the CISC machine.
Specifically, the effective value of S in the T expression for the RISC machine is 1.2, bit it is only
1.5 for the CISC machine. Both machines have the same clock rate R. What is the largest
allowable value for N, the number of instructions executed on the CISC machine, expressed as a
percentage of the N value forthe RISC machine, if time for execution on the CISC machine is to
be longer than on the RISC machine?

(b) Repeat Part (a) if the clock rate R for the RISC machine is 15 percent higher than that for
the CISC machine.

Solution:
(a) Let TR = (NR X SR)/RR & TC = (NC X SC)/RC be execution times on RISC and CISC
processors.

Then Equating execution times and clock rates, we have 1.2NR = 1.5NC

NC/NR = 1.2/1.5 = 0.8

Therefore, the largest allowable value for NC is 80% of NR. (b)

In this case,

1.2NR/1.15 = 1.5NC/1.00

Then
NC/NR =1.2/(1.15 X 1.5) = 0.696

Therefore, the largest allowable value for NC is 69.6% of NR.

Machine Instructions and Programs:

1.4 Memory Locations and addresses

• Memory consists of many millions of storage cells (flip-flops).
• Each cell can store a bit of information i.e. 0 or 1 (Figure 2.1).
• Each group of n bits is referred to as a word of information, and n is called the word length.
• The word length can vary from 8 to 64 bits.
• A unit of 8 bits is called a byte.
• Accessing the memory to store or retrieve a single item of information (word/byte) requires
distinct addresses for each item location. (It is customary to use numbers from 0 through 2k-1 as
the addresses of successive-locations in the memory).
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• If 2k = no. of addressable locations; then 2k addresses constitute the address-space of the

computer.
For example, a 24-bit address generates an address-space of 224 locations (16 MB).

Figure: Memory Words

Each group of n bits is referred to as a word of information and n is called the word length. The
memory of a computer can be schematically represented as a collection of words as shown in fig.
Modern computers have word lengths that typically range from 16 to 64 bits. If the word length of
a computer is 32 bits, a signal word can store a 32 bit 2‟s complement number or four ASCII
characters, each occupying 8bits, as shown in figure.
A unit of 8bit is called a byte. To retrieve information from memory, either for one word or
one byte (8-bit), addresses for each location are needed. A k-bit address memory has 2k memory
locations, namely 0 – 2k-1, called memory space. 24-bit memory: 224 = 16,777,216 = 16M
(1M=220)
32-bit memory: 232 = 4G (1G=230) , 1K(kilo)=210 , 1T(tera)=240
32 bits

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A byte is always 8 bits, but the word length typically ranges from 16 to 64 bits.

• In byte-addressable memory, successive addresses refer to successive byte locations in the

memory.
• Byte locations have addresses 0, 1, 2. . . . .
• If the word-length is 32 bits, successive words are located at addresses 0, 4, 8. .
with each word having 4 bytes.

Discuss two ways in which byte addresses are assigned

Big-Endian and Little-Endian assignment, explain with necessary figure.

Big-Endian and Little-Endian Assignment

1) Big-Endian: lower byte addresses are used for the most significant bytes of the word
2) Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of
the word.
• In both cases, byte-addresses 0, 4, 8. ......... are taken as the addresses of successive words in the
memory.

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Consider a 32-bit integer (in hex): 0x12345678 which consists of 4 bytes: 12, 34, 56, and
78. Hence this integer will occupy 4 bytes in memory.
Assume, we store it at memory address starting
1000. On little-endian, memory will look like

Address Value
1000 78
1001 56
1002 34
1003 12
On big-endian, memory will look like

Address Value
1000 12
1001 34
1002 56
1003 78

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Word Alignment
Words are said to be aligned in memory if they begin at a byte address that is a multiple of the
number of bytes in a word.
• 16-bit word: word addresses: 0, 2, 4,….
• 32-bit word: word addresses: 0, 4, 8,….
• 64-bit word: word addresses: 0, 8,16,….

Accessing Numbers, Characters and Character Strings

A number usually occupies one word. It can be accessed in the memory by specifying its word
address. Similarity individual characters can be accessed by their byte address.
There are two ways to indicate the length of the string. A special control character with the
meaning “end of string” can be used as the character in the string, or separate memory word
location or register can contain a number indicating the length of the string in bytes.

1.5 Memory Operations

Two basic operations involving the memory are:
1) Load (Read/Fetch) & 2) Store (Write).
o The load operation transfers a copy of the contents of a specific memory location to the
processor. The memory contents remain unchanged. The memory contents remain unchanged.

• Steps for Load operation:

1) Processor sends the address of the desired location to the memory.
2) Processor issues „read‟ signal to memory to fetch the data.
3) Memory reads the data stored at that address. 4) Memory sends the read data to the processor.

o The store operations transfer an item of information from the processor to specific memory
location, destroying the former contents of that location.
• Steps for Store operation are:

1) Processor sends the address of the memory-location where it wants to store data.
2) Processor issues „write‟ signal to memory to store the data.
3) Content of register(MDR) is written into the specified memory-location.

1.6 Instructions and instruction Sequencing

A computer must have instructions capable of performing four types of operations:
1) Data transfers between the memory and the registers (MOV, PUSH, POP, XCHG).
2) Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR, NOT).
3) Program sequencing and control(CALL.RET, LOOP, INT). 4) I/0 transfers (IN, OUT).

Register Transfer Notation (RTN)

• We can Identify a location by a symbolic name standing for its hardware binary address

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(LOC, R0,…)
• Contents of a location are denoted by placing square brackets around the name of the location
(R1←[LOC], R3 ←[R1]+[R2])
Example: consider the operations that adds the contents of register R1 and R2, then places
their sum into register R3.

R3 ← [R2] + [R2]
This type of notation is known as Register Transfer Notation (RTN).
• The possible locations in which transfer of information occurs are:

1) Memory-location 2)
Processor register & 3)
Registers in I/O device.

Assembly Language Notation

Represent machine instructions and programs.

Basic Instruction Type

The operation of adding 2 numbers is a fundamental capability in any computer. The statement
C=A+B
In a high level language program is a command to the computer to add the current values of the
2 variables called A & B and to assign the sum to third variable, C.

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Same in high level language statement requires the action to takes place in the computer
C ← [A] + [B]

Instruction formats with examples:

Instruction Execution and Straight –line sequencing

The program is executed as follows:
1) Initially, the address of the first instruction is loaded into PC (Program counter is a register
which holds the address of the next instruction to be executed)
2) Then, the processor control circuits use the information in the PC to fetch and execute
instructions, one at a time, in the order of increasing addresses. This is called straight-line
sequencing (Figure)
3) During the execution of each instruction, the PC is incremented by 4 to point to the next
instruction.
4) Executing given instruction is a two-phase procedure.

i) In fetch phase, the instruction is fetched from the memory location (whose address is in the
PC) and placed in the IR (Instruction register) of the processor.
ii) In execute phase, the contents of IR(Instruction register) is examined to determine which
operation is to be performed. The specified operation is then performed by the processor.
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Program Explanation

• Consider the program for adding a list of n numbers (Figure 2.9).

• The Address of the memory-locations containing the n numbers are symbolically given as
NUM1, NUM2…..NUMn.

• Separate Add instruction is used to add each number to the contents of register R0.

• After all the numbers have been added, the result is placed in memory-location SUM.

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Branching
• Consider the task of adding a list of „n‟ numbers (Figure ).
• Number of entries in the list „n‟ is stored in memory-location N.
• Register R1 is used as a counter to determine the number of times the loop is executed.
• Content-location N is loaded into register R1 at the beginning of the program.
• The Loop is a straight line sequence of instructions executed as many times as needed.

The loop starts at location LOOP and ends at the instruction Branch>0.

• During each pass,

→ address of the next list entry is determined and
→ that entry is fetched and added to R0.

• The instruction Decrement R1 reduces the contents of R1 by 1 each time through the loop.

• Then Branch Instruction loads a new value into the program counter. As a result, the
processor fetches and executes the instruction at this new address called the Branch
Target.

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• A Conditional Branch Instruction causes a branch only if a specified condition is

satisfied. If the condition is not satisfied, the PC is incremented in the normal way, and
the next instruction in sequential address order is fetched and executed.

Fig : (a) A st-line program for adding n nos. (b) Using loop to add n Numbers.

Condition Code:

The processor keeps track of information about the results of various operations for use by
subsequent conditional branch instructions. This is accomplished by recording the required
information in individual bits, often called conditional codes flags. These flags are usually
grouped together in a special processor register called the condition code register or status
register.

Individual condition code flags are set to 1 or cleared to 0, depending on the outcome of the
operation performed. Four commonly used flags are
• N (Negative) Set to 1 if the result is –ve otherwise cleared to 0.
• Z (zero) Set to 1 if the result is 0, otherwise cleared to 0.
• V (Overflow) Set to 1 if the arithmetic overflow occurs otherwise cleared to 0.
• C (Carry) Set to 1 if a carry out results from the operations otherwise cleared to 0.
Functions of different flags are as follows
N and Z flags
i. Indicate whether the result of arithmetic or logic operations is negative or zero.
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ii. Affected by instructions that transfer data, such as Move, Load and Store. iii. To
cause a branch based on the sign and value of the operand that was moved.
iv. Test instruction that examines a value in a register to in the memory and sets or clears the
N and Z flags.
V flag
i. Indicates whether overflow has taken place.
ii. Overflow occurs when the result of an arithmetic operation is outside the range of
values that can be represented by the number of bits available for the operands
C flag
i. If it set to 1 then it indicates carry occurs from the most significant bit position during
a arithmetic operation.
ii. This flag allows to-perform arithmetic operation on operands that are longer than the
word length of the processor.

1.7 Addressing Modes

What is an addressing mode .Explain different generic addressing modes
with an
example for
each
What is the need for an addressing mode? Explain the following addressing
modes with
examples: immediate, direct, indirect, index,
relative

Programmers use organizations called data structures to represent the data in computations. These
include lists, linked lists, array, and queues and so on. Translating high-level language to assembly
language requires compiler to use constants, local global variables, pointers and arrays to facilitate
with instruction set of the computer in which the program will be run.
“The different ways in which the location of an operand is specified in an instruction are referred
to as addressing modes.”

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Table: Generic Addressing Modes

EA=Effective Address & Value= a signed Number

Implementation of Variable and Constants

1)Variable is represented by allocating a memory-location to hold its

value. Thus, the value can be changed as needed using appropriate
instructions Immediate Mode
• The operand is given explicitly in the instruction.
• For example, the instruction

Move #200, R0 ;Place the value 200 in register R0.

• Clearly, the immediate mode is only used to specify the value of a source-operand.

2) Register Mode
• The operand is the contents of a register.
• The name (or address) of the register is given in the instruction.
• Registers are used as temporary storage locations where the data in a register are accessed.
• For example, the instruction

Move R1, R2 ;Copy content of register R1 into register R2.

3) Absolute (Direct) Mode

• The operand is in a memory-location.
• The address of memory-location is given explicitly in the instruction.
• The absolute mode can represent global variables in the program.
• For example, the instruction

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Move LOC, R2 ;Copy content of memory-location LOC into register R2.

4) Indirection and Pointers
Instruction does not give the operand or its address explicitly.
• Instead, the instruction provides information from which the new address of the operand can be
determined.
• This address is called Effective Address (EA) of the operand. Indirect Mode
• The EA of the operand is the contents of a register (or memory-location).
• The register (or memory-location) that contains the address of an operand is called a Pointer.
• We denote the indirection by
→ name of the register or
→ new address given in the instruction.

E.g: Add (R1),R0 ;

The operand is in memory. Register R1 gives the effective-address (B) of the operand. The data
is read from location B and added to contents of register R0.

Figure : (a) Through General Purpose Register (b) Through memory locations

To execute the Add instruction in figure

(a). the processor uses the value which is in register R1, as the EA of the operand.
• It requests a read operation from the memory to read the contents of location B. The value read
is the desired operand, which the processor adds to the contents of register R0.
• Indirect addressing through a memory-location is also possible as shown in figure
(b). In this case, the processor first reads the contents of memory-location A, then requests a
second read operation using the value B as an address to obtain the operand.

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Figure: Use of indirect addressing in program

Program Explanation
i. In above program, Register R2 is used as a pointer to the numbers in the list, and the operands
are accessed indirectly through R2.
ii. The initialization-section of the program loads the counter-value n from memory-location N
into R1 and uses the immediate addressing-mode to place the address value NUM1, which is
the address of the first number in the list, into R2. Then it clears R0 to 0.
iii. The first two instructions in the loop implement the unspecified instruction block starting at
LOOP.
iv. The first time through the loop, the instruction Add (R2), R0 fetches the operand at location
NUM1 and adds it to R0.
v. The second Add instruction adds 4 to the contents of the pointer R2, so that it will contain the
address value NUM2 when the above instruction is executed in the second pass through the
loop.

5) Indexing and Arrays

• A different kind of flexibility for accessing operands is useful in dealing with lists and
arrays. a) Index mode
• The operation is indicated as X(Ri) , where X=the constant value which defines an
offset(also called a displacement). Ri=the name of the index register which contains
address of a new location.
• The effective-address of the operand is given by EA=X+[Ri]
• The contents of the index-register are not changed in the process of generating the
effective-address.
• The constant X may be given either
 as an explicit number or
 as a symbolic-name representing a numerical value.
• Figure illustrates two ways of using the Index mode. In fig(a), the index register, R1,
contains the address of a memory-location, and the value X defines an offset(also called
a displacement) from this address to the location where the operand is found.

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• To find EA of operand:

Eg: Add 20(R5), R2

EA=>1000+20=1020

Figure: Indexed addressing

• An alternative use is illustrated in fig(b). Here, the constant X corresponds to a memory address,
and the contents of the index register define the offset to the operand. In either case, the effective-
address is the sum of two values; one is given explicitly in the instruction, and the other is stored
in a register.

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6) Base with Index Mode

• Another version of the Index mode uses 2 registers which can be denoted as (Ri, Rj) Here,
a second register may be used to contain the offset X.
• The second register is usually called the base register.
• The effective-address of the operand is given by EA=[Ri]+[Rj]
• This form of indexed addressing provides more flexibility in accessing operands because
both components of the effective-address can be changed.

7) Base with Index & Offset Mode

Another version of the Index mode uses 2 registers plus a constant, which can be denoted as
X(Ri, Rj)
• The effective-address of the operand is given by EA=X+[Ri]+[Rj]
• This added flexibility is useful in accessing multiple components inside each item in a
record, where the beginning of an item is specified by the (Ri, Rj) part of the addressing
mode. In other words, this mode implements a 3-dimensional array.

8) Relative Mode
• This is similar to index-mode with one difference:
The effective-address is determined using the PC in place of the general purpose register Ri.

• The operation is indicated as X(PC).

• X(PC) denotes an effective-address of the operand which is X locations above or below
the current contents of PC.

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• Since the addressed-location is identified "relative" to the PC, the name Relative mode is
associated with this type of addressing.
• This mode is used commonly in conditional branch instructions. An instruction such as
Branch > 0 LOOP
;Causes program execution to go to the branch target location identified by name LOOP
if branch condition is satisfied.

1.8.5 Additional Addressing Modes

9) Auto Increment Mode
Effective-address of operand is contents of a register specified in the instruction (Fig). After
accessing the operand, the contents of this register are automatically incremented to point to the
next item in a list. Implicitly, the increment amount is 1.
This mode is denoted as
(Ri)+ ; where Ri=pointer-register.

Figure: Auto-increment addressing mode used in the program

10) Auto Decrement Mode

The contents of a register specified in the instruction are first automatically decremented
and are then used as the effective-address of the operand. This mode is denoted as -(Ri)
; where Ri=pointer-register.
These 2 modes can be used together to implement an important data structure called a stack.

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Question Paper Questions of Module -1 :

1. With the help of a neat diagram explain the basic operational concepts of the computer
2. Explain the basic operational concepts between the processor and the memory.
3. What is performance measurement? Explain the overall SPEC rating for computer
4. Draw single bus structure.Explain
5. What is addressing mode? Explain three addressing modes with example.
6. Explain Big-Endian and Little-Endian methods of byte addressing with proper example
7. Write the basic performance equation. Explain the role of each parameter in the equation
on the performance of a computer
8. What are the factors that affect the performance? Explain any four
9. A program contains 1000instrcutions. Out of that 25% instruction 4 clock cycles 40%
instructions requires 5 clock cycles and remaining requires 3 clock cycles for execution.
Find the total time required to execute the program running in 1 GHz machine.
10. Explain immediate, indirect and indexed addressing modes.

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