Chapter 4

Combinational Logic
Circuits
Combinational Circuits
A combinational circuit is a digital logic circuit composed by logic gates whose outputs at any time are
determined directly from the present combination of inputs without any regard to previous inputs. The
digital logic gates are the building block of combinational circuits. A combinational circuit performs a
specific information-processing operation fully specified logically by a set of Boolean functions. Adder,
subtractor, multiplexer, demultiplexer, encoder and decoder are the common example of combinational
logic circuit.

The basic components of a combinational circuit are: input variables, logic gates, and output variables.

The 'n' input variables come from an external source whereas the 'm' output variables go to an external
destination. In many applications, the source or destination is storage registers.

Design procedure of a Combinational Circuit

The design procedure of a combinational circuit involves the following steps:
1. The problem is stated.
2. The total number of available input variables and required output variables is determined.
3. The input and output variables are allocated with letter symbols.
4. The exact truth table that defines the required relationships between inputs and outputs is
derived.
5. The simplified Boolean function is obtained from each output. Use Karnaugh Maps or Boolean
algebra.
6. Draw the logic circuit diagram.

Half Adder
The Half Adder is a type of combinational logic circuit that adds two of the 1-bit binary digits. It
generates carry and sum of both the inputs. The Half Adder does not add the carry obtained from the
previous addition to the next one. Let A and B are the input and carry C and sum S are the output
generated by half adder. The block diagram and truth table of the half adder is shown in figure below:

Inputs Outputs
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Figure – Block diagram of the Half adder Figure – Truth table of half adder
From truth table, Boolean expression for sum and carry is as follows:
⊕
.
Figure – Logic diagram of the half adder

Full Adder
The Full Adder is also a type of combinational logic that adds three of the 1-bit binary digits for
performing an addition operation. It generates a sum of all three inputs along with a carry value. The
Full Adder, along with its current inputs A and B, also adds the previous carry.

Let inputs are A, B and Cin. Where, A & B are the two parallel significant bits and Cin is the carry bit,
which is generated from previous stage. This Full adder also produces two outputs sum S & carry Cout.
The block diagram and truth table of the half adder is shown in figure below:

Inputs Outputs
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Figure – Block diagram of the Full adder Figure – Truth table of Full adder

From K-map the Boolean expressions for sum and carry are

⊕ ⨁
⊕ ⊕

The logic circuit diagram of full adder is as follow:

Figure – Logic circuit diagram of full adder

Full Adder using half adder

The full adder can be constructed by using half adders. there are two half adder circuits that are
combined using the OR gate to form full adder.

Figure – Block diagram of Full adder by using half adder

The logic circuit diagram of the full adder by using half adder is as below:

Figure – Logic circuit diagram of Full adder by using half adder

4-bit Binary Adder
The 4-bit binary adder performs the addition of two 4-bit numbers. The 4 Full adders are cascaded to
form 4-bit binary adder. Each Full adder is getting the respective bits of two parallel inputs A & B. The
carry output of one Full adder will be the carry input of subsequent higher order Full adder. This 4-bit
binary adder produces the resultant sum having at most 5 bits. So, carry out of last stage Full adder will
be the MSB.

Figure – Block diagram of the 4-bit binary adder

Half Subtractor
The half subtractor is also a building block for subtracting two binary numbers. It has two inputs and
two outputs. This circuit is used to subtract two single bit binary numbers A and B. The 'diff' and
'borrow' are two output states of the half subtractor. The block diagram and the truth table for half
subtractor are given below:

Figure – Block diagram of the half subtractor Figure –Truth table of the half subtractor
From the truth table, Boolean expression for sum and carry is as follows:
⊕

The logic circuit for half subtractor is

Figure – Logic circuit for half subtractor

Full Subtractor
The Half Subtractor is used to subtract only two numbers. To overcome this problem, a full subtractor
was designed. The full subtractor is used to subtract three 1-bit numbers A, B, and C, which are
minuend, subtrahend, and borrow, respectively. The full subtractor has three input states and two output
states i.e., diff and borrow. The block diagram and the truth table for full subtractor are given below:

Figure – Block diagram of the full subtractor Figure –Truth table of the full subtractor

K-map for Difference K-map for Borrow out

From K-map the expression for Difference is

⊕ ⊕
⊕ ⊕
From K-map the expression for Borrow out is
. . .
The logic circuit for full subtractor is given as

Figure – Logic circuit for full subtractor

Full subtractor using half subtractor

The full subtractor can be constructed by using half subtractors. there are two half subtractor circuits that
are combined using the OR gate to form full adder. The block diagram and logic circuit is as follows:

Figure – Block diagram of Full subtractor by using half subtractor

Figure – Logic circuit diagram of Full subtractor by using half subtractor

4-bit Binary Subtractor

The 4-bit binary subtractor produces the subtraction of two 4-bit numbers. Let the 4bit binary numbers,
A=A3 A2 A1 A0 and B=B3B2B1B0. Internally, the operation of 4-bit Binary subtractor is similar to that of
4-bit Binary adder. If the normal bits of binary number A, complemented bits of binary number B and
initial carry borrow, Cin as one are applied to 4-bit Binary adder, then it becomes 4-bit Binary subtractor.
The block diagram of 4-bit binary subtractor is shown in the following figure.
Figure –4 Bit Binary Subtractor

This 4-bit binary subtractor produces an output, which is having at most 5 bits. If Binary number A is
greater than Binary number B, then MSB of the output is zero and the remaining bits hold the magnitude
of A – B. If Binary number A is less than Binary number B, then MSB of the output is one. So, take the
2’s complement of output in order to get the magnitude of A – B.

Controlled inverter
Controlled inverter is a logical circuit, which is used to invert the input. In other word the output of the
controlled inverter is 1’s complement of the input. If the controlled signal C is 1 then the output is
complement of the input. If the controlled signal C is 0 then the output is equal to the input.

The figure shows that the 3 bit controlled inverter, which invert the inputs if c is 1.

The Binary Adder / Subtractor

A Binary Adder/Subtractor is a special type of circuit that is used to perform both operations, i.e.,
Addition and Subtraction. Let us consider a 4-bit binary adder / subtractor to understand its operation.
The 4-bit binary adder / subtractor produces either the addition or the subtraction of two 4-bit numbers
based on the value of initial carry or borrow, 0. Let the 4-bit binary numbers, A = A3 A2 A1A0 and
B=B3B2B1B0. The operation of 4-bit Binary adder / subtractor is similar to that of 4-bit Binary adder and
4-bit Binary subtractor.
Apply the normal bits of binary numbers A and B & initial carry or borrow, C0 from externally to a 4-bit
binary adder.

If initial carry, 0 is zero, then each full adder gets the normal bits of binary numbers A & B. So, the 4-
bit binary adder / subtractor produces an output, which is the addition of two binary numbers A & B.

The block diagram of 4-bit binary adder / subtractor is shown in the following figure.
Figure –4 Bit Binary Adder/Subtractor

If initial borrow, 0 is one, then each full adder gets the normal bits of binary number A &
complemented bits of binary number B. So, the 4-bit binary adder / subtractor produces an output, which
is the subtraction of two binary numbers A & B.
Therefore, with the help of additional Ex-OR gates, the same circuit can be used for both addition and
subtraction of two binary numbers.

Ripple Carry Adders

A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascaded, with the carry output from each full adder connected
to the carry input of the next full adder in the chain. Therefore it is called ripple carry adder.
There are various types in ripple-carry adders. They are 4-bit ripple-carry adder, 8-bit ripple-carry adder
etc.

4-bit Ripple-Carry Adder

The figure represents the 4-bit ripple-carry adder. In this adder, four full adders are connected in
cascade. Co is the carry input bit and it is zero always. When this input carry ‘Co’ is applied to the two
input sequences A0 A1 A2 A3 and B0 B1 B2 B3 then output represented with S0 S1 S2 S3 and output
carry C4.

Figure – Block diagram of the 4-bit ripple-carry adder

Fast adder
Fast adder is also called Carry lookahead adder. A carry-lookahead adder improves speed by reducing
the amount of time required to determine carry bits. A carry-Lookahead adder is a fast parallel adder as
it reduces the propagation delay by more complex hardware, hence it is costlier.

Now consider the full adder to understand the logic of fast adder or Carry lookahead adder. Lets look on
the logic circuit and truth table of full adder as shown in figure.
If we define two variables as carry generate Gi and carry propagate Pi then,
Pi = Ai ⊕ Bi
Gi = Ai Bi
The sum output and carry output can be expressed as
Si = Pi ⊕ Ci
Ci+1 = Gi + Pi Ci
Where Gi is a carry generate which produces the carry when both Ai, Bi are one regardless of the input
carry. Pi is a carry propagate and it is associate with the propagation of carry from Ci to Ci+1.
The carry output Boolean function of each stage in a 4 stage fast adder can be expressed as
C1 = G0 + P0 Cin
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 Cin
C3 = G2 + P2 C2 = G2 + P2 G1+ P2 P1 G0 + P2 P1 P0 Cin
C4 = G3 + P3 C3= G3 + P3 G2+ P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 Cin

From the above Boolean equations we can observe that C4 does not have to wait for C3 and C2 to
propagate but actually C4 is propagated at the same time as C3 and C2. Since the Boolean expression for
each carry output is the sum of products so these can be implemented with one level of AND gates
followed by an OR gate. The logic circuit of fat adder or carry lookahead adder for 4 bit is shown in the
figure below:

Figure –Logic diagram of fast adder

The above figure is more complex so for simplicity we draw a block diagram type figure of fast adder as
shown in figure below:

In this adder, the propagation delay is reduced. The carry output at any stage is dependent only on the
initial carry bit of the beginning stage. Using this adder it is possible to calculate the intermediate
results. This adder is the fastest adder used for computation.

Multiplexer
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and single
output line. One of these data inputs will be connected to the output based on the values of selection
lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination will select only one data input. Multiplexer is also called as Mux or Data selector.

Figure- N:1 Multiplexer

Multiplexers are classified into four types:
• 2-1 multiplexer ( 1select line)
• 4-1 multiplexer (2 select lines)
• 8-1 multiplexer (3 select lines)
• 16-1 multiplexer (4 select lines)
4×1 Multiplexer (4:1 Multiplexer or 4 to 1 Multiplexer)
In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection lines, i.e.,
S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present at the
selection lines S0 and S1, one of these 4 inputs are connected to the output. The block diagram, the truth
table and the logic circuit diagram of the 4×1 multiplexer are given below.

Figure- 4x1 Multiplexer Figure- Truth table

Figure- Logic diagram of 4x1 Multiplexer

From logic circuit diagram and truth table
The output is equal to A0 if S1=0, S0=0, Y = S S A
The output is equal to A1 if S1=0, S0=1, Y = S S A
The output is equal to A2 if S1=1, S0=0, Y = S S A
The output is equal to A3 if S1=1, S0=1, Y = S S A!
The output of the all AND gates are ORed to get the final expression for 4x1 multiplexer.
Y S S A S S A S S A S S A!
The above expression is the required expression for 4x1 multiplexer.
8 x 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7, 3 selection
lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of inputs that are
present at the selection lines S0, S1 and S2, one of these 8 inputs are connected to the output. The block
diagram, the truth table and the logic circuit diagram of the 8×1 multiplexer are given below.

Figure- 8x1 Multiplexer Figure- Truth table

Figure- Logic diagram of 8x1 Multiplexer

The logical expression of the term Y is as follows:

Y S S S A S S S A S S S A S S S A! S S S A# S S S A$ S S S A%
S S S A&
Q. What is multiplexer tree?
A number of m-to-1 multiplexers can be arranged in a tree topology to obtain a bigger n-to-1
multiplexer is called Multiplexer Tree where n>m. Bigger Multiplexer can be obtained by combining
smaller Multiplexers.

16 to 1 Multiplexer using 4 to 1 multiplexer

We can implement the 16 to 1 multiplexer using 4 to 1 multiplexer. To implement the 16 to 1
multiplexer, we need five 4 to1 multiplexers. The 4 to 1 multiplexer has 2 selection lines, 4 inputs, and 1
output.
Let inputs are I0 to I15, selection bits are S0, S1, S2, S3 and Y be the output of the multiplexer.
From figure we can that the first order multiplexers take four inputs and select one input as a output
depending upon the selection bit S0 and S1. Each multiplexer produces one output so there is a four
output. We fed these output to the second order 4 to 1 multiplexer to produce single output depending
upon the higher order selection bit S2 and S3.

Implementation of the Boolean function using multiplexer

Q.1. Implement the Boolean expression F(A, B, C) = ∑ m(0, 1, 3, 5, 7) using a 8:1 multiplexer.
Solution-
The three input variables (A, B, C) are connected as three selection lines. The inputs, corresponding to
the minterms (0, 1, 3, 5, 7) are connected to logic 1 and the remaining terms to the logic 0(grounded).
Q.2. Implement the Boolean expression F(A, B, C) = ∑ m(0, 2, 5, 6) using 4 : 1 multiplexer.
Solution:
In the given Boolean expression, there are 3 variables. We should use 23:1 = 8:1 multiplexer. But as per
the question, it is to be implemented with 4:1 mux.
For 4:1 multiplexer, there should be 2 selection lines. So from the given 3 variables, the 2 least
significant variables (B, C) are used as selection line inputs and most significant variable A is used as an
input.
The minterms given in the Boolean expression is circled and analyzed. After analyzing, the input values
of 4 : 1 mux is obtained as , A, 1, 0.

Q.3. Implement F(A, B, C, D) = ∑ m(0, 1, 5, 6, 8, 10, 12, 15) using 8 : 1 multiplexer.

Solution:
In the given Boolean expression, there are 4 variables. We should use 24: 1 = 16:1 multiplexer. But as
per the question, it is to be implemented with 8:1 mux.
For 8:1 multiplexer, there should be 3 selection lines. So from the given 4 variables, the 3 least
significant variables (B, C, D) are used as selection line inputs and most significant variable A is used as
an input.

The 8 inputs are derived using the implementation table shown below

From the derived input, 8:1 multiplexer can be drawn as below

Q.4. Implement F(A, B, C, D) = ∑ m(0, 1, 2, 4, 6, 9, 12, 14) using 4 : 1 multiplexer.
Solution:
For 4:1 multiplexer, there should be 2 selection lines. So from the given 4 variables, the 2 least
significant variables (C, D) are used as selection line inputs and most significant variables (A, B) are
used as an input.
The 4 inputs are derived using the implementation table shown below

̅ ̅ ̅ ̅ ̅
̅ ̅
̅ ̅ ̅ ̅ ̅
! 0
Demultiplexer
De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It has
single input, ‘n’ selection lines and maximum of 2n outputs. The input will be connected to one of these
outputs based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination can select only one output. De-Multiplexer is also called as De-Mux or Data distributor.

Figure- Block diagram of Demultiplexer

Demultiplexers are classified into four types
1-2 demultiplexer (1 select line)
1-4 demultiplexer (2 select lines)
1-8 demultiplexer (3 select lines)
1-16 demultiplexer (4 select lines)

1×4 Demultiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2 selection lines, i.e.,
S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which are present at the
selection lines S0 and S1, the input be connected to one of the outputs. The block diagram, the truth table
and logic circuit diagram of the 1×4 multiplexer are given below.

Figure- 1x4 Demultiplexer Figure- Truth Table

Figure- Logic circuit diagram of 1x4 Demultiplexer

From truth table, it is clear that the data input is connected
-to output Y0, when S0= 0 and S1= 0.
-to output Y1, when S0= 0 and S1= 1.
-to output Y2, when S0= 1 and S1= 0.
-to output Y3, when S0= 1 and S1= 1.
The logical expression of the outputs is as follows:
Y0 = S S A
Y1 = S S A
Y2 = S S A
Y3 = S1 S0 A
Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7, 3
selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S0, S1 and S2, the input will be connected to one of these outputs.
The block diagram and the truth table of the 1×8 de-multiplexer are given below.

Figure- Block diagram and Logic circuit of 1×8 De-multiplexer

Figure- Truth table of 1×8 De-multiplexer

The logical expression of the output is as follows.

Y0 = )* )+ ), - Y1 = )* )+ ), . Y2 = )* )+ ), - Y3 = )* )+ ), -
Y4 = )* )+ ), - Y5 = )* )+ ), . Y6 = )* )+ ), - Y7 = )* )+ ), -

1 to 16 Demultiplexer by using 1 to 8 and 1 to 2 demultiplexer

For implementing 1 to 16 demultiplexer by using lower orders demultiplexer. We have to use one 1 to 2
and two 1 to 8 demultiplexer. One selection S3 line is applied to 1 to 2 demultiplexer to produce two
output and these outputs are further fed to two 1 to 8 demultiplexer to produce 16 outputs depending
upon the selection bits S0, S1, S2.

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah

Figure- Block diagram of 1 to 16 Demultiplexer by using 1 to 8 and 1 to 2 demultiplexer

Basic Encoders
The combinational circuits that change the binary information into N output lines are known as Binary
Encoder or simply Encoders. The binary information is passed in the form of 2N input lines. The output
lines define the N-bit code for the binary information. In simple words, the Encoder performs the reverse
operation of the Decoder. At a time, only one input line is activated for simplicity. The produced N-bit
output code is equivalent to the binary information.

Figure- Block diagram of Encoder

Basic Encoder can be categorized as
4 to 2 line encoder
8 to 3 line encoder or Octal to Binary encoder
Decimal to BCD encoder

4 to 2 line Encoder
In 4 to 2 line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two outputs, i.e., A0 and
A1. In 4-input lines, one input-line is set to true at a time to get the respective binary code in the output
side. Below are the block diagram and the truth table of the 4 to 2 line encoder.
Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
Figure- 4 to 2 line encoder

Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

Figure- Truth table of 4 to 2 line encoder Figure -Logical circuit of 4 to 2 line encoder

The logical expression of the output term A0 and A1 is as follows:

A1=Y3+Y2
A0=Y3+Y1
Logical circuit of the above expressions is given above.

8 to 3 line Encoder
The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder, there are total
of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2. In 8-input
lines, one input-line is set to true at a time to get the respective binary code in the output side.

Figure – Block diagram of 8 to 3 line Encoder

Inputs Outputs
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Figure – Truth table of 8 to 3 line Encoder
Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
The logical expression of the output term A0, A1, and A2 are as follows:
A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1
Logical circuit of the above expressions is given below.

Figure - Logical circuit of 8 to 3 line Encoder

Decimal to BCD Encoder
The Decimal to BCD Encoder is also known as 10 to 4 line Encoder. In 10 to 4 line encoder, there are
total of ten inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, and Y9 and four outputs, i.e., A0, A1, A2, and
A3. In 10-input lines, one input-line is set to true at a time to get the respective BCD code in the output
side. The block diagram and the truth table of the decimal to BCD encoder are given below.

Figure- Block diagram of Decimal to BCD Encoder

Figure – Truth table of Decimal to BCD Encoder

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
The logical expression of the term A0, A1, A2, and A3 is as follows:
A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
Logical circuit of the above expressions is given below:

Figure - Logical circuit of Decimal to BCD Encoder

Priority Encoder
The Priority Encoder is another type of combinational circuit similar to a binary encoder, except that it
generates an output code based on the highest prioritized input. Priority encoders are used extensively in
digital and computer systems as microprocessor interrupt controllers where they detect the highest
priority input.

A 4 to 2 priority encoder has 4 inputs: Y3, Y2, Y1 & Y0, and 2 outputs: A1 & A0. Here, the input, Y3 has
the highest priority, whereas the input, Y0 has the lowest priority. In this case, even if more than one
input is ‘1’ at the same time, the output will be the (binary) code corresponding to the input, which is
having higher priority. V is the valid bit and it is zero when priority is not set and 1 for priority. The
truth table for the priority encoder is as follows.
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0 V
0 0 0 0 X X 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
The logical expression for A1 and A0 are shown below.

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah

The above two Boolean functions can be implemented as.

Figure - Logical circuit of Priority Encoder

Decoder
The combinational circuit that change the binary information into 2N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output lines define the
2N-bit code for the binary information. In simple words, the Decoder performs the reverse operation of
the Encoder. At a time, only one input line is activated for simplicity. The produced 2N-bit output code is
equivalent to the binary information.

Figure – Block diagram of Decoder

2 to 4 line decoder
In the 2 to 4 line decoder, there are a total of three inputs, i.e., A0, and A1 and E and four outputs, i.e.,
Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of these four
outputs will be 1.

Figure – Block diagram of 2 to 4 line decoder

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah

Enable Inputs Outputs
E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Figure – Truth table of 2 to 4 line decoder
The logical expression of the output term Y0, Y1, Y2, and Y3 is as follows
/! 0. .
/ 0. .
/ 0. .
/ 0. .
Logical circuit of the above expressions is given below

Figure - Logical circuit of 2 to 4 line decoder

3 to 8 line decoder
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there are a
total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three inputs, i.e., A0, A1, and A2. This
circuit has an enable input 'E' and when enable 'E' is set to 1, one of these eight outputs will be 1.

Figure - 3 to 8 line decoder

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
Enable Inputs Outputs
E A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
Figure – Truth table of 3 to 8 line decoder

The logical expression of the output terms Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0 =E. .* . .+ . ., . Y1 =E. .* . .+ . ., Y2 =E. .* . .+ . ., Y3 =E. .* . .+ . .,
Y4 =E. .* . .+ . ., Y5 =E. .* . .+ . ., Y6 =E. .* . .+ . ., Y7 =E. .* . .+ . .,

Logical circuit of the above expressions is given below:

Figure - Logical circuit of 3 to 8 line decoder

BCD-to-Decimal Decoder
The BCD-to-decimal decoder converts each BCD code into one of ten possible decimal digit
indications. The method of implementation is the same as for the 3-of-8 decoder In a BCD to Decimal
decoder, there are a total of ten outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 and Y9 and four inputs,
i.e., A0, A1, A2 and A3. This circuit has an enable input 'E' and when enable 'E' is set to 1, one of these
ten outputs will be 1. It is frequently referred as a 4-line-to-10-line decoder or a 1-of-10 decoder.
Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
Figure – BCD to Decimal decoder

Decimal Enable Inputs Outputs

Digit E A3 A2 A1 A0 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
x 0 x x x x 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0
2 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0
3 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0
4 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0
5 1 0 1 0 1 0 0 0 0 1 0 0 0 0 0
6 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0
7 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0
8 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0
9 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0
Figure – Truth table of BCD to Decimal decoder

Figure - Logical circuit of BCD to Decimal decoder

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
The logical expression of the output terms Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 and Y9 is as follows:
Y0 =E. A! . A . A . A Y1 =E. A! . A . A . A
Y2 =E. A! . A . A . A Y3 =E. A! . A . A . A
Y4 =E. A! . A . A . A Y5 =E. A! . A . A . A
Y6 =E. A! . A . A . A Y7 =E. A! . A . A . A
Y8 =E. A! . A . A . A Y9 =E. A! . A . A . A
The logic circuit of BCD to Decimal decoder is given above.
BCD to Seven Segment decoder
In Binary Coded Decimal (BCD) encoding scheme each of the decimal numbers (0-9) is represented
by its equivalent binary pattern (which is generally of 4-bits).
Whereas, Seven segment display is an electronic device which consists of seven Light Emitting
Diodes (LEDs) arranged in some definite pattern (common cathode or common anode type), which is
used to display Hexadecimal numerals (in this case decimal numbers, as input is BCD i.e., 0-9).
Basically seven segment LED display are of two types:
1. Common Cathode Type: In this type of display all cathodes of the seven LEDs are connected
together to the ground or –Vcc (hence, common cathode) and LED displays digits when some
‘HIGH’ signal is supplied to the individual anodes.
2. Common Anode Type: In this type of display all the anodes of the seven LEDs are connected to
battery or +Vcc and LED displays digits when some ‘LOW’ signal is supplied to the individual
cathodes.

Seven segment displays does not work by directly supplying voltage to different segments of LEDs.
First, our decimal number is changed to its BCD equivalent signal then BCD to seven segment
decoder converts that signals to the form which is fed to seven segment display.
This BCD to seven segment decoder has four input lines (A, B, C and D) and 7 output lines (a, b, c, d,
e, f and g), this output is given to seven segment LED display which displays the decimal number
depending upon inputs.

Figure – BCD to Seven segment Display

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
Decimal Input Output
numbers A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
Figure – Truth table for BCD to Seven segment display
Note –
For Common Anode type seven segment LED display, we only have to interchange all ‘0s’ and
‘1s’ in the output side i.e., (for a, b, c, d, e, f, and g replace all ‘1’ by ‘0’ and vice versa) and
solve using K-map.
Output for first combination of inputs (A, B, C and D) in Truth Table corresponds to ‘0’ and
last combination corresponds to ‘9’. Similarly rest corresponds from 2 to 8 from top to bottom.
BCD numbers only range from 0 to 9, thus rest inputs from 10-F are invalid inputs.

1. For segment ‘a’:

For segment ‘a’, 0, 2, 3, 5, 6, 7, 8, 9 are high

∴2 ⨁
2. For segment ‘b’:
For segment ‘b’, 0, 1, 2, 3, 4, 7, 8, 9 are high

∴3 ⨁
3. For segment ‘c’:
For segment ‘c’, 0, 1, 3, 4, 5, 6, 7, 8, 9 are high

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah

∴4
4. For segment ‘d’:
For segment ‘d’, 0, 2, 3, 5, 6, 8, 9 are high

∴5
5. For segment ‘e’:
For segment ‘e’, 0, 2, 6, 8 are high

∴6
6. For segment ‘f’:
For segment ‘f’, 0, 4, 5, 6, 8, 9 are high

∴
Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
7. For segment ‘g’:
For segment ‘g’, 2, 3, 4, 5, 6, 8, 9 are high

∴7 ⨁
Magnitude Comparator
A magnitude Comparator is a combinational circuit that compares two digital or binary numbers in order
to find out whether one binary number is equal, less than, or greater than the other binary number.
Magnitude comparator is also called digital comparator. We logically design a circuit for which we will
have two inputs one for A and the other for B and have three output terminals, one f or A > B condition,
one for A = B condition, and one for A < B condition.

Figure – N-bit magnitude comparator

1-Bit Magnitude Comparator

A comparator used to compare two bits is called a single-bit comparator. It consists of two inputs each
for two single-bit numbers and three outputs to generate less than, equal to, and greater than between
two binary numbers.
The truth table for a 1-bit comparator is given below.
A B A<B A>B A=B
0 0 0 0 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 1
The logical expressions are
For A<B, /
For A>B, /
For A=B, /
From above expressions, we can write,
A8B A:B
Taking the complement on both side,
8 :
. ; ;

The logic circuit for 1-bit comparator is given below

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah

Figure –1-bit comparator
2-Bit Magnitude Comparator
A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to, and greater than
between two binary numbers.
The truth table for a 2-bit comparator is given below.
INPUT OUTPUT
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0

From the above truth table, K-map for each output can be drawn as follows.

K-map and logical expressions for Output A>B given below

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah

K-map and logical expressions for Output A<B given below

/
K-map and logical expressions for Output A=B given below

/
/
/
/ < ⊕ = ⊕
The logic circuit for 2-bit comparator is given below

Figure – Logic circuit for 2-bit Magnitude Comparator

Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah
4-bit magnitude comparator
A comparator used to compare two binary numbers each of four bits is called a 4-bit magnitude
comparator. It consists of eight inputs each for two four-bit numbers and three outputs to generate less
than, equal to, and greater than between two binary numbers.
The truth table for a 4-bit comparator would have 28 = 256 rows. So we will do things a bit differently
here. We will compare each bit of the two 4-bit numbers, and based on that comparison and the weight
of their positions, we will draft a truth table.
A3B3 A2B2 A1B1 A0B0 A>B A<B A=B
A3>B3 x x x 1 0 0
A3<B3 x x x 0 1 0
A3= B3 A2>B2 x x 1 0 0
A3= B3 A2<B2 x x 0 1 0
A3= B3 A2=B2 A1>B1 x 1 0 0
A3= B3 A2=B2 A1<B1 x 0 1 0
A3= B3 A2=B2 A1=B1 A0>B0 1 0 0
A3= B3 A2=B2 A1=B1 A0<B0 0 1 0
A3= B3 A2=B2 A1=B1 A0=B0 0 0 1
From the above truth table we can derive the equations for three outputs.
The equation For A=B
We know that the equation for A=B is ⊕ , let assume the output is x such that x be the four bit
number as x3 x2 x1x0 . The final equation is
/ < ! ⊕ ! =. < ⊕ =. < ⊕ =. < ⊕ = >! . > . > . >
The equation For A<B
From the above truth table we can write equation for A<B
/ 8 ! ! >! >! . > >! . > . >
The equation For A>B
Similarly, we can write equation for A>B from the above truth table
/ 8 ! ! >! >! . > >! . > . >
Now the Logic circuit can be drawn as below

OR
Figure – Logic circuit for 4-bit Magnitude Comparator
Digital Logic: Chapter 4: Combinational Logic Circuits By: MB Sah